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KVM: use jump label to optimize checking for SW enabled apic in spurious interrupt...
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
aec51dc4 49#include <trace/events/kvm.h>
2ed152af 50
229456fc
MT		 51#define CREATE_TRACE_POINTS
52#include "trace.h"
043405e1 53
24f1e32c 54#include <asm/debugreg.h>
d825ed0a 55#include <asm/msr.h>
a5f61300 56#include <asm/desc.h>
0bed3b56 57#include <asm/mtrr.h>
890ca9ae 58#include <asm/mce.h>
7cf30855 59#include <asm/i387.h>
1361b83a 60#include <asm/fpu-internal.h> /* Ugh! */
98918833 61#include <asm/xcr.h>
1d5f066e 62#include <asm/pvclock.h>
217fc9cf 63#include <asm/div64.h>
043405e1 64
313a3dc7 65#define MAX_IO_MSRS 256
890ca9ae 66#define KVM_MAX_MCE_BANKS 32
5854dbca 67#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 68
0f65dd70
AK		 69#define emul_to_vcpu(ctxt) \
70 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
71
50a37eb4
JR		 72/* EFER defaults:
73 * - enable syscall per default because its emulated by KVM
74 * - enable LME and LMA per default on 64 bit KVM
75 */
76#ifdef CONFIG_X86_64
1260edbe
LJ		 77static
78u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 79#else
1260edbe 80static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 81#endif
313a3dc7 82
ba1389b7
AK		 83#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
84#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 85
cb142eb7 86static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 87static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 88
97896d04 89struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 90EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 91
476bc001
RR		 92static bool ignore_msrs = 0;
93module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 94
92a1f12d
JR		 95bool kvm_has_tsc_control;
96EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
97u32 kvm_max_guest_tsc_khz;
98EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
99
cc578287
ZA		 100/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
101static u32 tsc_tolerance_ppm = 250;
102module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
103
18863bdd
AK		 104#define KVM_NR_SHARED_MSRS 16
105
106struct kvm_shared_msrs_global {
107 int nr;
2bf78fa7 108 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 109};
110
111struct kvm_shared_msrs {
112 struct user_return_notifier urn;
113 bool registered;
2bf78fa7
SY		 114 struct kvm_shared_msr_values {
115 u64 host;
116 u64 curr;
117 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 118};
119
120static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
121static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
122
417bc304 123struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 124 { "pf_fixed", VCPU_STAT(pf_fixed) },
125 { "pf_guest", VCPU_STAT(pf_guest) },
126 { "tlb_flush", VCPU_STAT(tlb_flush) },
127 { "invlpg", VCPU_STAT(invlpg) },
128 { "exits", VCPU_STAT(exits) },
129 { "io_exits", VCPU_STAT(io_exits) },
130 { "mmio_exits", VCPU_STAT(mmio_exits) },
131 { "signal_exits", VCPU_STAT(signal_exits) },
132 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 133 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 134 { "halt_exits", VCPU_STAT(halt_exits) },
135 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 136 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 137 { "request_irq", VCPU_STAT(request_irq_exits) },
138 { "irq_exits", VCPU_STAT(irq_exits) },
139 { "host_state_reload", VCPU_STAT(host_state_reload) },
140 { "efer_reload", VCPU_STAT(efer_reload) },
141 { "fpu_reload", VCPU_STAT(fpu_reload) },
142 { "insn_emulation", VCPU_STAT(insn_emulation) },
143 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 144 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 145 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 146 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
147 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
148 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
149 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
150 { "mmu_flooded", VM_STAT(mmu_flooded) },
151 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 152 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 153 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 154 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 155 { "largepages", VM_STAT(lpages) },
417bc304
HB		 156 { NULL }
157};
158
2acf923e
DC		 159u64 __read_mostly host_xcr0;
160
d6aa1000
AK		 161int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
162
af585b92
GN		 163static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
164{
165 int i;
166 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
167 vcpu->arch.apf.gfns[i] = ~0;
168}
169
18863bdd
AK		 170static void kvm_on_user_return(struct user_return_notifier *urn)
171{
172 unsigned slot;
18863bdd
AK		 173 struct kvm_shared_msrs *locals
174 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 175 struct kvm_shared_msr_values *values;
18863bdd
AK		 176
177 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 178 values = &locals->values[slot];
179 if (values->host != values->curr) {
180 wrmsrl(shared_msrs_global.msrs[slot], values->host);
181 values->curr = values->host;
18863bdd
AK		 182 }
183 }
184 locals->registered = false;
185 user_return_notifier_unregister(urn);
186}
187
2bf78fa7 188static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 189{
2bf78fa7 190 struct kvm_shared_msrs *smsr;
18863bdd
AK		 191 u64 value;
192
2bf78fa7
SY		 193 smsr = &__get_cpu_var(shared_msrs);
194 /* only read, and nobody should modify it at this time,
195 * so don't need lock */
196 if (slot >= shared_msrs_global.nr) {
197 printk(KERN_ERR "kvm: invalid MSR slot!");
198 return;
199 }
200 rdmsrl_safe(msr, &value);
201 smsr->values[slot].host = value;
202 smsr->values[slot].curr = value;
203}
204
205void kvm_define_shared_msr(unsigned slot, u32 msr)
206{
18863bdd
AK		 207 if (slot >= shared_msrs_global.nr)
208 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 209 shared_msrs_global.msrs[slot] = msr;
210 /* we need ensured the shared_msr_global have been updated */
211 smp_wmb();
18863bdd
AK		 212}
213EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
214
215static void kvm_shared_msr_cpu_online(void)
216{
217 unsigned i;
18863bdd
AK		 218
219 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 220 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 221}
222
d5696725 223void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 224{
225 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
226
2bf78fa7 227 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 228 return;
2bf78fa7
SY		 229 smsr->values[slot].curr = value;
230 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 231 if (!smsr->registered) {
232 smsr->urn.on_user_return = kvm_on_user_return;
233 user_return_notifier_register(&smsr->urn);
234 smsr->registered = true;
235 }
236}
237EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
238
3548bab5
AK		 239static void drop_user_return_notifiers(void *ignore)
240{
241 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
242
243 if (smsr->registered)
244 kvm_on_user_return(&smsr->urn);
245}
246
6866b83e
CO		 247u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
248{
8a5a87d9 249 return vcpu->arch.apic_base;
6866b83e
CO		 250}
251EXPORT_SYMBOL_GPL(kvm_get_apic_base);
252
253void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
254{
255 /* TODO: reserve bits check */
8a5a87d9 256 kvm_lapic_set_base(vcpu, data);
6866b83e
CO		 257}
258EXPORT_SYMBOL_GPL(kvm_set_apic_base);
259
3fd28fce
ED		 260#define EXCPT_BENIGN 0
261#define EXCPT_CONTRIBUTORY 1
262#define EXCPT_PF 2
263
264static int exception_class(int vector)
265{
266 switch (vector) {
267 case PF_VECTOR:
268 return EXCPT_PF;
269 case DE_VECTOR:
270 case TS_VECTOR:
271 case NP_VECTOR:
272 case SS_VECTOR:
273 case GP_VECTOR:
274 return EXCPT_CONTRIBUTORY;
275 default:
276 break;
277 }
278 return EXCPT_BENIGN;
279}
280
281static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 282 unsigned nr, bool has_error, u32 error_code,
283 bool reinject)
3fd28fce
ED		 284{
285 u32 prev_nr;
286 int class1, class2;
287
3842d135
AK		 288 kvm_make_request(KVM_REQ_EVENT, vcpu);
289
3fd28fce
ED		 290 if (!vcpu->arch.exception.pending) {
291 queue:
292 vcpu->arch.exception.pending = true;
293 vcpu->arch.exception.has_error_code = has_error;
294 vcpu->arch.exception.nr = nr;
295 vcpu->arch.exception.error_code = error_code;
3f0fd292 296 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 297 return;
298 }
299
300 /* to check exception */
301 prev_nr = vcpu->arch.exception.nr;
302 if (prev_nr == DF_VECTOR) {
303 /* triple fault -> shutdown */
a8eeb04a 304 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 305 return;
306 }
307 class1 = exception_class(prev_nr);
308 class2 = exception_class(nr);
309 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
310 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
311 /* generate double fault per SDM Table 5-5 */
312 vcpu->arch.exception.pending = true;
313 vcpu->arch.exception.has_error_code = true;
314 vcpu->arch.exception.nr = DF_VECTOR;
315 vcpu->arch.exception.error_code = 0;
316 } else
317 /* replace previous exception with a new one in a hope
318 that instruction re-execution will regenerate lost
319 exception */
320 goto queue;
321}
322
298101da
AK		 323void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
324{
ce7ddec4 325 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 326}
327EXPORT_SYMBOL_GPL(kvm_queue_exception);
328
ce7ddec4
JR		 329void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330{
331 kvm_multiple_exception(vcpu, nr, false, 0, true);
332}
333EXPORT_SYMBOL_GPL(kvm_requeue_exception);
334
db8fcefa 335void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 336{
db8fcefa
AP		 337 if (err)
338 kvm_inject_gp(vcpu, 0);
339 else
340 kvm_x86_ops->skip_emulated_instruction(vcpu);
341}
342EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 343
6389ee94 344void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 345{
346 ++vcpu->stat.pf_guest;
6389ee94
AK		 347 vcpu->arch.cr2 = fault->address;
348 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 349}
27d6c865 350EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 351
6389ee94 352void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 353{
6389ee94
AK		 354 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
355 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 356 else
6389ee94 357 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 358}
359
3419ffc8
SY		 360void kvm_inject_nmi(struct kvm_vcpu *vcpu)
361{
7460fb4a
AK		 362 atomic_inc(&vcpu->arch.nmi_queued);
363 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 364}
365EXPORT_SYMBOL_GPL(kvm_inject_nmi);
366
298101da
AK		 367void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
368{
ce7ddec4 369 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 370}
371EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
372
ce7ddec4
JR		 373void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
374{
375 kvm_multiple_exception(vcpu, nr, true, error_code, true);
376}
377EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
378
0a79b009
AK		 379/*
380 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
381 * a #GP and return false.
382 */
383bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 384{
0a79b009
AK		 385 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
386 return true;
387 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
388 return false;
298101da 389}
0a79b009 390EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 391
ec92fe44
JR		 392/*
393 * This function will be used to read from the physical memory of the currently
394 * running guest. The difference to kvm_read_guest_page is that this function
395 * can read from guest physical or from the guest's guest physical memory.
396 */
397int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
398 gfn_t ngfn, void *data, int offset, int len,
399 u32 access)
400{
401 gfn_t real_gfn;
402 gpa_t ngpa;
403
404 ngpa = gfn_to_gpa(ngfn);
405 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
406 if (real_gfn == UNMAPPED_GVA)
407 return -EFAULT;
408
409 real_gfn = gpa_to_gfn(real_gfn);
410
411 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
412}
413EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
414
3d06b8bf
JR		 415int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
416 void *data, int offset, int len, u32 access)
417{
418 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
419 data, offset, len, access);
420}
421
a03490ed
CO		 422/*
423 * Load the pae pdptrs. Return true is they are all valid.
424 */
ff03a073 425int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 426{
427 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
428 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
429 int i;
430 int ret;
ff03a073 431 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 432
ff03a073
JR		 433 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
434 offset * sizeof(u64), sizeof(pdpte),
435 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 436 if (ret < 0) {
437 ret = 0;
438 goto out;
439 }
440 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 441 if (is_present_gpte(pdpte[i]) &&
20c466b5 442 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 443 ret = 0;
444 goto out;
445 }
446 }
447 ret = 1;
448
ff03a073 449 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 450 __set_bit(VCPU_EXREG_PDPTR,
451 (unsigned long *)&vcpu->arch.regs_avail);
452 __set_bit(VCPU_EXREG_PDPTR,
453 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 454out:
a03490ed
CO		 455
456 return ret;
457}
cc4b6871 458EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 459
d835dfec
AK		 460static bool pdptrs_changed(struct kvm_vcpu *vcpu)
461{
ff03a073 462 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 463 bool changed = true;
3d06b8bf
JR		 464 int offset;
465 gfn_t gfn;
d835dfec
AK		 466 int r;
467
468 if (is_long_mode(vcpu) || !is_pae(vcpu))
469 return false;
470
6de4f3ad
AK		 471 if (!test_bit(VCPU_EXREG_PDPTR,
472 (unsigned long *)&vcpu->arch.regs_avail))
473 return true;
474
9f8fe504
AK		 475 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
476 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 477 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
478 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 479 if (r < 0)
480 goto out;
ff03a073 481 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 482out:
d835dfec
AK		 483
484 return changed;
485}
486
49a9b07e 487int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 488{
aad82703
SY		 489 unsigned long old_cr0 = kvm_read_cr0(vcpu);
490 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
491 X86_CR0_CD | X86_CR0_NW;
492
f9a48e6a
AK		 493 cr0 |= X86_CR0_ET;
494
ab344828 495#ifdef CONFIG_X86_64
0f12244f
GN		 496 if (cr0 & 0xffffffff00000000UL)
497 return 1;
ab344828
GN		 498#endif
499
500 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 501
0f12244f
GN		 502 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
503 return 1;
a03490ed 504
0f12244f
GN		 505 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
506 return 1;
a03490ed
CO		 507
508 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
509#ifdef CONFIG_X86_64
f6801dff 510 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 511 int cs_db, cs_l;
512
0f12244f
GN		 513 if (!is_pae(vcpu))
514 return 1;
a03490ed 515 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 516 if (cs_l)
517 return 1;
a03490ed
CO		 518 } else
519#endif
ff03a073 520 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 521 kvm_read_cr3(vcpu)))
0f12244f 522 return 1;
a03490ed
CO		 523 }
524
ad756a16
MJ		 525 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
526 return 1;
527
a03490ed 528 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 529
d170c419 530 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 531 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 532 kvm_async_pf_hash_reset(vcpu);
533 }
e5f3f027 534
aad82703
SY		 535 if ((cr0 ^ old_cr0) & update_bits)
536 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 537 return 0;
538}
2d3ad1f4 539EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 540
2d3ad1f4 541void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 542{
49a9b07e 543 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 544}
2d3ad1f4 545EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 546
2acf923e
DC		 547int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
548{
549 u64 xcr0;
550
551 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
552 if (index != XCR_XFEATURE_ENABLED_MASK)
553 return 1;
554 xcr0 = xcr;
555 if (kvm_x86_ops->get_cpl(vcpu) != 0)
556 return 1;
557 if (!(xcr0 & XSTATE_FP))
558 return 1;
559 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
560 return 1;
561 if (xcr0 & ~host_xcr0)
562 return 1;
563 vcpu->arch.xcr0 = xcr0;
564 vcpu->guest_xcr0_loaded = 0;
565 return 0;
566}
567
568int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
569{
570 if (__kvm_set_xcr(vcpu, index, xcr)) {
571 kvm_inject_gp(vcpu, 0);
572 return 1;
573 }
574 return 0;
575}
576EXPORT_SYMBOL_GPL(kvm_set_xcr);
577
a83b29c6 578int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 579{
fc78f519 580 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 581 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
582 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 583 if (cr4 & CR4_RESERVED_BITS)
584 return 1;
a03490ed 585
2acf923e
DC		 586 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
587 return 1;
588
c68b734f
YW		 589 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
590 return 1;
591
74dc2b4f
YW		 592 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
593 return 1;
594
a03490ed 595 if (is_long_mode(vcpu)) {
0f12244f
GN		 596 if (!(cr4 & X86_CR4_PAE))
597 return 1;
a2edf57f
AK		 598 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
599 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 600 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
601 kvm_read_cr3(vcpu)))
0f12244f
GN		 602 return 1;
603
ad756a16
MJ		 604 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
605 if (!guest_cpuid_has_pcid(vcpu))
606 return 1;
607
608 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
609 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
610 return 1;
611 }
612
5e1746d6 613 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 614 return 1;
a03490ed 615
ad756a16
MJ		 616 if (((cr4 ^ old_cr4) & pdptr_bits) ||
617 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 618 kvm_mmu_reset_context(vcpu);
0f12244f 619
2acf923e 620 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 621 kvm_update_cpuid(vcpu);
2acf923e 622
0f12244f
GN		 623 return 0;
624}
2d3ad1f4 625EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 626
2390218b 627int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 628{
9f8fe504 629 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 630 kvm_mmu_sync_roots(vcpu);
d835dfec 631 kvm_mmu_flush_tlb(vcpu);
0f12244f 632 return 0;
d835dfec
AK		 633 }
634
a03490ed 635 if (is_long_mode(vcpu)) {
ad756a16
MJ		 636 if (kvm_read_cr4(vcpu) & X86_CR4_PCIDE) {
637 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
638 return 1;
639 } else
640 if (cr3 & CR3_L_MODE_RESERVED_BITS)
641 return 1;
a03490ed
CO		 642 } else {
643 if (is_pae(vcpu)) {
0f12244f
GN		 644 if (cr3 & CR3_PAE_RESERVED_BITS)
645 return 1;
ff03a073
JR		 646 if (is_paging(vcpu) &&
647 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 648 return 1;
a03490ed
CO		 649 }
650 /*
651 * We don't check reserved bits in nonpae mode, because
652 * this isn't enforced, and VMware depends on this.
653 */
654 }
655
a03490ed
CO		 656 /*
657 * Does the new cr3 value map to physical memory? (Note, we
658 * catch an invalid cr3 even in real-mode, because it would
659 * cause trouble later on when we turn on paging anyway.)
660 *
661 * A real CPU would silently accept an invalid cr3 and would
662 * attempt to use it - with largely undefined (and often hard
663 * to debug) behavior on the guest side.
664 */
665 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 666 return 1;
667 vcpu->arch.cr3 = cr3;
aff48baa 668 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 669 vcpu->arch.mmu.new_cr3(vcpu);
670 return 0;
671}
2d3ad1f4 672EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 673
eea1cff9 674int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 675{
0f12244f
GN		 676 if (cr8 & CR8_RESERVED_BITS)
677 return 1;
a03490ed
CO		 678 if (irqchip_in_kernel(vcpu->kvm))
679 kvm_lapic_set_tpr(vcpu, cr8);
680 else
ad312c7c 681 vcpu->arch.cr8 = cr8;
0f12244f
GN		 682 return 0;
683}
2d3ad1f4 684EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 685
2d3ad1f4 686unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 687{
688 if (irqchip_in_kernel(vcpu->kvm))
689 return kvm_lapic_get_cr8(vcpu);
690 else
ad312c7c 691 return vcpu->arch.cr8;
a03490ed 692}
2d3ad1f4 693EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 694
338dbc97 695static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 696{
697 switch (dr) {
698 case 0 ... 3:
699 vcpu->arch.db[dr] = val;
700 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
701 vcpu->arch.eff_db[dr] = val;
702 break;
703 case 4:
338dbc97
GN		 704 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
705 return 1; /* #UD */
020df079
GN		 706 /* fall through */
707 case 6:
338dbc97
GN		 708 if (val & 0xffffffff00000000ULL)
709 return -1; /* #GP */
020df079
GN		 710 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
711 break;
712 case 5:
338dbc97
GN		 713 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
714 return 1; /* #UD */
020df079
GN		 715 /* fall through */
716 default: /* 7 */
338dbc97
GN		 717 if (val & 0xffffffff00000000ULL)
718 return -1; /* #GP */
020df079
GN		 719 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
720 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
721 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
722 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
723 }
724 break;
725 }
726
727 return 0;
728}
338dbc97
GN		 729
730int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
731{
732 int res;
733
734 res = __kvm_set_dr(vcpu, dr, val);
735 if (res > 0)
736 kvm_queue_exception(vcpu, UD_VECTOR);
737 else if (res < 0)
738 kvm_inject_gp(vcpu, 0);
739
740 return res;
741}
020df079
GN		 742EXPORT_SYMBOL_GPL(kvm_set_dr);
743
338dbc97 744static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 745{
746 switch (dr) {
747 case 0 ... 3:
748 *val = vcpu->arch.db[dr];
749 break;
750 case 4:
338dbc97 751 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 752 return 1;
020df079
GN		 753 /* fall through */
754 case 6:
755 *val = vcpu->arch.dr6;
756 break;
757 case 5:
338dbc97 758 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 759 return 1;
020df079
GN		 760 /* fall through */
761 default: /* 7 */
762 *val = vcpu->arch.dr7;
763 break;
764 }
765
766 return 0;
767}
338dbc97
GN		 768
769int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
770{
771 if (_kvm_get_dr(vcpu, dr, val)) {
772 kvm_queue_exception(vcpu, UD_VECTOR);
773 return 1;
774 }
775 return 0;
776}
020df079
GN		 777EXPORT_SYMBOL_GPL(kvm_get_dr);
778
022cd0e8
AK		 779bool kvm_rdpmc(struct kvm_vcpu *vcpu)
780{
781 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
782 u64 data;
783 int err;
784
785 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
786 if (err)
787 return err;
788 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
789 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
790 return err;
791}
792EXPORT_SYMBOL_GPL(kvm_rdpmc);
793
043405e1
CO		 794/*
795 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
796 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
797 *
798 * This list is modified at module load time to reflect the
e3267cbb
GC		 799 * capabilities of the host cpu. This capabilities test skips MSRs that are
800 * kvm-specific. Those are put in the beginning of the list.
043405e1 801 */
e3267cbb 802
e115676e 803#define KVM_SAVE_MSRS_BEGIN 10
043405e1 804static u32 msrs_to_save[] = {
e3267cbb 805 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 806 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 807 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 808 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 809 MSR_KVM_PV_EOI_EN,
043405e1 810 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 811 MSR_STAR,
043405e1
CO		 812#ifdef CONFIG_X86_64
813 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
814#endif
e90aa41e 815 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 816};
817
818static unsigned num_msrs_to_save;
819
820static u32 emulated_msrs[] = {
a3e06bbe 821 MSR_IA32_TSCDEADLINE,
043405e1 822 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 823 MSR_IA32_MCG_STATUS,
824 MSR_IA32_MCG_CTL,
043405e1
CO		 825};
826
b69e8cae 827static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 828{
aad82703
SY		 829 u64 old_efer = vcpu->arch.efer;
830
b69e8cae
RJ		 831 if (efer & efer_reserved_bits)
832 return 1;
15c4a640
CO		 833
834 if (is_paging(vcpu)
b69e8cae
RJ		 835 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
836 return 1;
15c4a640 837
1b2fd70c
AG		 838 if (efer & EFER_FFXSR) {
839 struct kvm_cpuid_entry2 *feat;
840
841 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 842 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
843 return 1;
1b2fd70c
AG		 844 }
845
d8017474
AG		 846 if (efer & EFER_SVME) {
847 struct kvm_cpuid_entry2 *feat;
848
849 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 850 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
851 return 1;
d8017474
AG		 852 }
853
15c4a640 854 efer &= ~EFER_LMA;
f6801dff 855 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 856
a3d204e2
SY		 857 kvm_x86_ops->set_efer(vcpu, efer);
858
9645bb56 859 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 860
aad82703
SY		 861 /* Update reserved bits */
862 if ((efer ^ old_efer) & EFER_NX)
863 kvm_mmu_reset_context(vcpu);
864
b69e8cae 865 return 0;
15c4a640
CO		 866}
867
f2b4b7dd
JR		 868void kvm_enable_efer_bits(u64 mask)
869{
870 efer_reserved_bits &= ~mask;
871}
872EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
873
874
15c4a640
CO		 875/*
876 * Writes msr value into into the appropriate "register".
877 * Returns 0 on success, non-0 otherwise.
878 * Assumes vcpu_load() was already called.
879 */
880int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
881{
882 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
883}
884
313a3dc7
CO		 885/*
886 * Adapt set_msr() to msr_io()'s calling convention
887 */
888static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
889{
890 return kvm_set_msr(vcpu, index, *data);
891}
892
18068523
GOC		 893static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
894{
9ed3c444
AK		 895 int version;
896 int r;
50d0a0f9 897 struct pvclock_wall_clock wc;
923de3cf 898 struct timespec boot;
18068523
GOC		 899
900 if (!wall_clock)
901 return;
902
9ed3c444
AK		 903 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
904 if (r)
905 return;
906
907 if (version & 1)
908 ++version; /* first time write, random junk */
909
910 ++version;
18068523 911
18068523
GOC		 912 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
913
50d0a0f9
GH		 914 /*
915 * The guest calculates current wall clock time by adding
34c238a1 916 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 917 * wall clock specified here. guest system time equals host
918 * system time for us, thus we must fill in host boot time here.
919 */
923de3cf 920 getboottime(&boot);
50d0a0f9 921
4b648665
BR		 922 if (kvm->arch.kvmclock_offset) {
923 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
924 boot = timespec_sub(boot, ts);
925 }
50d0a0f9
GH		 926 wc.sec = boot.tv_sec;
927 wc.nsec = boot.tv_nsec;
928 wc.version = version;
18068523
GOC		 929
930 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
931
932 version++;
933 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 934}
935
50d0a0f9
GH		 936static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
937{
938 uint32_t quotient, remainder;
939
940 /* Don't try to replace with do_div(), this one calculates
941 * "(dividend << 32) / divisor" */
942 __asm__ ( "divl %4"
943 : "=a" (quotient), "=d" (remainder)
944 : "0" (0), "1" (dividend), "r" (divisor) );
945 return quotient;
946}
947
5f4e3f88
ZA		 948static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
949 s8 *pshift, u32 *pmultiplier)
50d0a0f9 950{
5f4e3f88 951 uint64_t scaled64;
50d0a0f9
GH		 952 int32_t shift = 0;
953 uint64_t tps64;
954 uint32_t tps32;
955
5f4e3f88
ZA		 956 tps64 = base_khz * 1000LL;
957 scaled64 = scaled_khz * 1000LL;
50933623 958 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 959 tps64 >>= 1;
960 shift--;
961 }
962
963 tps32 = (uint32_t)tps64;
50933623
JK		 964 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
965 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 966 scaled64 >>= 1;
967 else
968 tps32 <<= 1;
50d0a0f9
GH		 969 shift++;
970 }
971
5f4e3f88
ZA		 972 *pshift = shift;
973 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 974
5f4e3f88
ZA		 975 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
976 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 977}
978
759379dd
ZA		 979static inline u64 get_kernel_ns(void)
980{
981 struct timespec ts;
982
983 WARN_ON(preemptible());
984 ktime_get_ts(&ts);
985 monotonic_to_bootbased(&ts);
986 return timespec_to_ns(&ts);
50d0a0f9
GH		 987}
988
c8076604 989static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 990unsigned long max_tsc_khz;
c8076604 991
cc578287 992static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 993{
cc578287
ZA		 994 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
995 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 996}
997
cc578287 998static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 999{
cc578287
ZA		 1000 u64 v = (u64)khz * (1000000 + ppm);
1001 do_div(v, 1000000);
1002 return v;
1e993611
JR		 1003}
1004
cc578287 1005static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1006{
cc578287
ZA		 1007 u32 thresh_lo, thresh_hi;
1008 int use_scaling = 0;
217fc9cf 1009
c285545f
ZA		 1010 /* Compute a scale to convert nanoseconds in TSC cycles */
1011 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1012 &vcpu->arch.virtual_tsc_shift,
1013 &vcpu->arch.virtual_tsc_mult);
1014 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1015
1016 /*
1017 * Compute the variation in TSC rate which is acceptable
1018 * within the range of tolerance and decide if the
1019 * rate being applied is within that bounds of the hardware
1020 * rate. If so, no scaling or compensation need be done.
1021 */
1022 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1023 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1024 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1025 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1026 use_scaling = 1;
1027 }
1028 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1029}
1030
1031static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1032{
e26101b1 1033 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1034 vcpu->arch.virtual_tsc_mult,
1035 vcpu->arch.virtual_tsc_shift);
e26101b1 1036 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1037 return tsc;
1038}
1039
99e3e30a
ZA		 1040void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1041{
1042 struct kvm *kvm = vcpu->kvm;
f38e098f 1043 u64 offset, ns, elapsed;
99e3e30a 1044 unsigned long flags;
02626b6a 1045 s64 usdiff;
99e3e30a 1046
038f8c11 1047 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1048 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1049 ns = get_kernel_ns();
f38e098f 1050 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6
ZA		 1051
1052 /* n.b - signed multiplication and division required */
02626b6a 1053 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1054#ifdef CONFIG_X86_64
02626b6a 1055 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6
ZA		 1056#else
1057 /* do_div() only does unsigned */
1058 asm("idivl %2; xor %%edx, %%edx"
02626b6a
MT		 1059 : "=A"(usdiff)
1060 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
5d3cb0f6 1061#endif
02626b6a
MT		 1062 do_div(elapsed, 1000);
1063 usdiff -= elapsed;
1064 if (usdiff < 0)
1065 usdiff = -usdiff;
f38e098f
ZA		 1066
1067 /*
5d3cb0f6
ZA		 1068 * Special case: TSC write with a small delta (1 second) of virtual
1069 * cycle time against real time is interpreted as an attempt to
1070 * synchronize the CPU.
1071 *
1072 * For a reliable TSC, we can match TSC offsets, and for an unstable
1073 * TSC, we add elapsed time in this computation. We could let the
1074 * compensation code attempt to catch up if we fall behind, but
1075 * it's better to try to match offsets from the beginning.
1076 */
02626b6a 1077 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1078 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1079 if (!check_tsc_unstable()) {
e26101b1 1080 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1081 pr_debug("kvm: matched tsc offset for %llu\n", data);
1082 } else {
857e4099 1083 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1084 data += delta;
1085 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1086 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1087 }
e26101b1
ZA		 1088 } else {
1089 /*
1090 * We split periods of matched TSC writes into generations.
1091 * For each generation, we track the original measured
1092 * nanosecond time, offset, and write, so if TSCs are in
1093 * sync, we can match exact offset, and if not, we can match
4a969980 1094 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1095 *
1096 * These values are tracked in kvm->arch.cur_xxx variables.
1097 */
1098 kvm->arch.cur_tsc_generation++;
1099 kvm->arch.cur_tsc_nsec = ns;
1100 kvm->arch.cur_tsc_write = data;
1101 kvm->arch.cur_tsc_offset = offset;
1102 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1103 kvm->arch.cur_tsc_generation, data);
f38e098f 1104 }
e26101b1
ZA		 1105
1106 /*
1107 * We also track th most recent recorded KHZ, write and time to
1108 * allow the matching interval to be extended at each write.
1109 */
f38e098f
ZA		 1110 kvm->arch.last_tsc_nsec = ns;
1111 kvm->arch.last_tsc_write = data;
5d3cb0f6 1112 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a
ZA		 1113
1114 /* Reset of TSC must disable overshoot protection below */
1115 vcpu->arch.hv_clock.tsc_timestamp = 0;
b183aa58 1116 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1117
1118 /* Keep track of which generation this VCPU has synchronized to */
1119 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1120 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1121 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1122
1123 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1124 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a 1125}
e26101b1 1126
99e3e30a
ZA		 1127EXPORT_SYMBOL_GPL(kvm_write_tsc);
1128
34c238a1 1129static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1130{
18068523
GOC		 1131 unsigned long flags;
1132 struct kvm_vcpu_arch *vcpu = &v->arch;
1133 void *shared_kaddr;
463656c0 1134 unsigned long this_tsc_khz;
1d5f066e
ZA		 1135 s64 kernel_ns, max_kernel_ns;
1136 u64 tsc_timestamp;
18068523 1137
18068523
GOC		 1138 /* Keep irq disabled to prevent changes to the clock */
1139 local_irq_save(flags);
d5c1785d 1140 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
759379dd 1141 kernel_ns = get_kernel_ns();
cc578287 1142 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
8cfdc000 1143 if (unlikely(this_tsc_khz == 0)) {
c285545f 1144 local_irq_restore(flags);
34c238a1 1145 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1146 return 1;
1147 }
18068523 1148
c285545f
ZA		 1149 /*
1150 * We may have to catch up the TSC to match elapsed wall clock
1151 * time for two reasons, even if kvmclock is used.
1152 * 1) CPU could have been running below the maximum TSC rate
1153 * 2) Broken TSC compensation resets the base at each VCPU
1154 * entry to avoid unknown leaps of TSC even when running
1155 * again on the same CPU. This may cause apparent elapsed
1156 * time to disappear, and the guest to stand still or run
1157 * very slowly.
1158 */
1159 if (vcpu->tsc_catchup) {
1160 u64 tsc = compute_guest_tsc(v, kernel_ns);
1161 if (tsc > tsc_timestamp) {
f1e2b260 1162 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1163 tsc_timestamp = tsc;
1164 }
50d0a0f9
GH		 1165 }
1166
18068523
GOC		 1167 local_irq_restore(flags);
1168
c285545f
ZA		 1169 if (!vcpu->time_page)
1170 return 0;
18068523 1171
1d5f066e
ZA		 1172 /*
1173 * Time as measured by the TSC may go backwards when resetting the base
1174 * tsc_timestamp. The reason for this is that the TSC resolution is
1175 * higher than the resolution of the other clock scales. Thus, many
1176 * possible measurments of the TSC correspond to one measurement of any
1177 * other clock, and so a spread of values is possible. This is not a
1178 * problem for the computation of the nanosecond clock; with TSC rates
1179 * around 1GHZ, there can only be a few cycles which correspond to one
1180 * nanosecond value, and any path through this code will inevitably
1181 * take longer than that. However, with the kernel_ns value itself,
1182 * the precision may be much lower, down to HZ granularity. If the
1183 * first sampling of TSC against kernel_ns ends in the low part of the
1184 * range, and the second in the high end of the range, we can get:
1185 *
1186 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1187 *
1188 * As the sampling errors potentially range in the thousands of cycles,
1189 * it is possible such a time value has already been observed by the
1190 * guest. To protect against this, we must compute the system time as
1191 * observed by the guest and ensure the new system time is greater.
1192 */
1193 max_kernel_ns = 0;
b183aa58 1194 if (vcpu->hv_clock.tsc_timestamp) {
1d5f066e
ZA		 1195 max_kernel_ns = vcpu->last_guest_tsc -
1196 vcpu->hv_clock.tsc_timestamp;
1197 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1198 vcpu->hv_clock.tsc_to_system_mul,
1199 vcpu->hv_clock.tsc_shift);
1200 max_kernel_ns += vcpu->last_kernel_ns;
1201 }
afbcf7ab 1202
e48672fa 1203 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1204 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1205 &vcpu->hv_clock.tsc_shift,
1206 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1207 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1208 }
1209
1d5f066e
ZA		 1210 if (max_kernel_ns > kernel_ns)
1211 kernel_ns = max_kernel_ns;
1212
8cfdc000 1213 /* With all the info we got, fill in the values */
1d5f066e 1214 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1215 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1216 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1217 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1218 vcpu->hv_clock.flags = 0;
1219
18068523
GOC		 1220 /*
1221 * The interface expects us to write an even number signaling that the
1222 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1223 * state, we just increase by 2 at the end.
18068523 1224 */
50d0a0f9 1225 vcpu->hv_clock.version += 2;
18068523 1226
8fd75e12 1227 shared_kaddr = kmap_atomic(vcpu->time_page);
18068523
GOC		 1228
1229 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1230 sizeof(vcpu->hv_clock));
18068523 1231
8fd75e12 1232 kunmap_atomic(shared_kaddr);
18068523
GOC		 1233
1234 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1235 return 0;
c8076604
GH		 1236}
1237
9ba075a6
AK		 1238static bool msr_mtrr_valid(unsigned msr)
1239{
1240 switch (msr) {
1241 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1242 case MSR_MTRRfix64K_00000:
1243 case MSR_MTRRfix16K_80000:
1244 case MSR_MTRRfix16K_A0000:
1245 case MSR_MTRRfix4K_C0000:
1246 case MSR_MTRRfix4K_C8000:
1247 case MSR_MTRRfix4K_D0000:
1248 case MSR_MTRRfix4K_D8000:
1249 case MSR_MTRRfix4K_E0000:
1250 case MSR_MTRRfix4K_E8000:
1251 case MSR_MTRRfix4K_F0000:
1252 case MSR_MTRRfix4K_F8000:
1253 case MSR_MTRRdefType:
1254 case MSR_IA32_CR_PAT:
1255 return true;
1256 case 0x2f8:
1257 return true;
1258 }
1259 return false;
1260}
1261
d6289b93
MT		 1262static bool valid_pat_type(unsigned t)
1263{
1264 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1265}
1266
1267static bool valid_mtrr_type(unsigned t)
1268{
1269 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1270}
1271
1272static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1273{
1274 int i;
1275
1276 if (!msr_mtrr_valid(msr))
1277 return false;
1278
1279 if (msr == MSR_IA32_CR_PAT) {
1280 for (i = 0; i < 8; i++)
1281 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1282 return false;
1283 return true;
1284 } else if (msr == MSR_MTRRdefType) {
1285 if (data & ~0xcff)
1286 return false;
1287 return valid_mtrr_type(data & 0xff);
1288 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1289 for (i = 0; i < 8 ; i++)
1290 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1291 return false;
1292 return true;
1293 }
1294
1295 /* variable MTRRs */
1296 return valid_mtrr_type(data & 0xff);
1297}
1298
9ba075a6
AK		 1299static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1300{
0bed3b56
SY		 1301 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1302
d6289b93 1303 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1304 return 1;
1305
0bed3b56
SY		 1306 if (msr == MSR_MTRRdefType) {
1307 vcpu->arch.mtrr_state.def_type = data;
1308 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1309 } else if (msr == MSR_MTRRfix64K_00000)
1310 p[0] = data;
1311 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1312 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1313 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1314 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1315 else if (msr == MSR_IA32_CR_PAT)
1316 vcpu->arch.pat = data;
1317 else { /* Variable MTRRs */
1318 int idx, is_mtrr_mask;
1319 u64 *pt;
1320
1321 idx = (msr - 0x200) / 2;
1322 is_mtrr_mask = msr - 0x200 - 2 * idx;
1323 if (!is_mtrr_mask)
1324 pt =
1325 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1326 else
1327 pt =
1328 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1329 *pt = data;
1330 }
1331
1332 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1333 return 0;
1334}
15c4a640 1335
890ca9ae 1336static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1337{
890ca9ae
HY		 1338 u64 mcg_cap = vcpu->arch.mcg_cap;
1339 unsigned bank_num = mcg_cap & 0xff;
1340
15c4a640 1341 switch (msr) {
15c4a640 1342 case MSR_IA32_MCG_STATUS:
890ca9ae 1343 vcpu->arch.mcg_status = data;
15c4a640 1344 break;
c7ac679c 1345 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1346 if (!(mcg_cap & MCG_CTL_P))
1347 return 1;
1348 if (data != 0 && data != ~(u64)0)
1349 return -1;
1350 vcpu->arch.mcg_ctl = data;
1351 break;
1352 default:
1353 if (msr >= MSR_IA32_MC0_CTL &&
1354 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1355 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1356 /* only 0 or all 1s can be written to IA32_MCi_CTL
1357 * some Linux kernels though clear bit 10 in bank 4 to
1358 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1359 * this to avoid an uncatched #GP in the guest
1360 */
890ca9ae 1361 if ((offset & 0x3) == 0 &&
114be429 1362 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1363 return -1;
1364 vcpu->arch.mce_banks[offset] = data;
1365 break;
1366 }
1367 return 1;
1368 }
1369 return 0;
1370}
1371
ffde22ac
ES		 1372static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1373{
1374 struct kvm *kvm = vcpu->kvm;
1375 int lm = is_long_mode(vcpu);
1376 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1377 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1378 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1379 : kvm->arch.xen_hvm_config.blob_size_32;
1380 u32 page_num = data & ~PAGE_MASK;
1381 u64 page_addr = data & PAGE_MASK;
1382 u8 *page;
1383 int r;
1384
1385 r = -E2BIG;
1386 if (page_num >= blob_size)
1387 goto out;
1388 r = -ENOMEM;
ff5c2c03
SL		 1389 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1390 if (IS_ERR(page)) {
1391 r = PTR_ERR(page);
ffde22ac 1392 goto out;
ff5c2c03 1393 }
ffde22ac
ES		 1394 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1395 goto out_free;
1396 r = 0;
1397out_free:
1398 kfree(page);
1399out:
1400 return r;
1401}
1402
55cd8e5a
GN		 1403static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1404{
1405 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1406}
1407
1408static bool kvm_hv_msr_partition_wide(u32 msr)
1409{
1410 bool r = false;
1411 switch (msr) {
1412 case HV_X64_MSR_GUEST_OS_ID:
1413 case HV_X64_MSR_HYPERCALL:
1414 r = true;
1415 break;
1416 }
1417
1418 return r;
1419}
1420
1421static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1422{
1423 struct kvm *kvm = vcpu->kvm;
1424
1425 switch (msr) {
1426 case HV_X64_MSR_GUEST_OS_ID:
1427 kvm->arch.hv_guest_os_id = data;
1428 /* setting guest os id to zero disables hypercall page */
1429 if (!kvm->arch.hv_guest_os_id)
1430 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1431 break;
1432 case HV_X64_MSR_HYPERCALL: {
1433 u64 gfn;
1434 unsigned long addr;
1435 u8 instructions[4];
1436
1437 /* if guest os id is not set hypercall should remain disabled */
1438 if (!kvm->arch.hv_guest_os_id)
1439 break;
1440 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1441 kvm->arch.hv_hypercall = data;
1442 break;
1443 }
1444 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1445 addr = gfn_to_hva(kvm, gfn);
1446 if (kvm_is_error_hva(addr))
1447 return 1;
1448 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1449 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1450 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1451 return 1;
1452 kvm->arch.hv_hypercall = data;
1453 break;
1454 }
1455 default:
a737f256
CD		 1456 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1457 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1458 return 1;
1459 }
1460 return 0;
1461}
1462
1463static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1464{
10388a07
GN		 1465 switch (msr) {
1466 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1467 unsigned long addr;
55cd8e5a 1468
10388a07
GN		 1469 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1470 vcpu->arch.hv_vapic = data;
1471 break;
1472 }
1473 addr = gfn_to_hva(vcpu->kvm, data >>
1474 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1475 if (kvm_is_error_hva(addr))
1476 return 1;
8b0cedff 1477 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1478 return 1;
1479 vcpu->arch.hv_vapic = data;
1480 break;
1481 }
1482 case HV_X64_MSR_EOI:
1483 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1484 case HV_X64_MSR_ICR:
1485 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1486 case HV_X64_MSR_TPR:
1487 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1488 default:
a737f256
CD		 1489 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1490 "data 0x%llx\n", msr, data);
10388a07
GN		 1491 return 1;
1492 }
1493
1494 return 0;
55cd8e5a
GN		 1495}
1496
344d9588
GN		 1497static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1498{
1499 gpa_t gpa = data & ~0x3f;
1500
4a969980 1501 /* Bits 2:5 are reserved, Should be zero */
6adba527 1502 if (data & 0x3c)
344d9588
GN		 1503 return 1;
1504
1505 vcpu->arch.apf.msr_val = data;
1506
1507 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1508 kvm_clear_async_pf_completion_queue(vcpu);
1509 kvm_async_pf_hash_reset(vcpu);
1510 return 0;
1511 }
1512
1513 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1514 return 1;
1515
6adba527 1516 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1517 kvm_async_pf_wakeup_all(vcpu);
1518 return 0;
1519}
1520
12f9a48f
GC		 1521static void kvmclock_reset(struct kvm_vcpu *vcpu)
1522{
1523 if (vcpu->arch.time_page) {
1524 kvm_release_page_dirty(vcpu->arch.time_page);
1525 vcpu->arch.time_page = NULL;
1526 }
1527}
1528
c9aaa895
GC		 1529static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1530{
1531 u64 delta;
1532
1533 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1534 return;
1535
1536 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1537 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1538 vcpu->arch.st.accum_steal = delta;
1539}
1540
1541static void record_steal_time(struct kvm_vcpu *vcpu)
1542{
1543 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1544 return;
1545
1546 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1547 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1548 return;
1549
1550 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1551 vcpu->arch.st.steal.version += 2;
1552 vcpu->arch.st.accum_steal = 0;
1553
1554 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1555 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1556}
1557
15c4a640
CO		 1558int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1559{
5753785f
GN		 1560 bool pr = false;
1561
15c4a640 1562 switch (msr) {
15c4a640 1563 case MSR_EFER:
b69e8cae 1564 return set_efer(vcpu, data);
8f1589d9
AP		 1565 case MSR_K7_HWCR:
1566 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1567 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1568 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1569 if (data != 0) {
a737f256
CD		 1570 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1571 data);
8f1589d9
AP		 1572 return 1;
1573 }
15c4a640 1574 break;
f7c6d140
AP		 1575 case MSR_FAM10H_MMIO_CONF_BASE:
1576 if (data != 0) {
a737f256
CD		 1577 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1578 "0x%llx\n", data);
f7c6d140
AP		 1579 return 1;
1580 }
15c4a640 1581 break;
c323c0e5 1582 case MSR_AMD64_NB_CFG:
c7ac679c 1583 break;
b5e2fec0
AG		 1584 case MSR_IA32_DEBUGCTLMSR:
1585 if (!data) {
1586 /* We support the non-activated case already */
1587 break;
1588 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1589 /* Values other than LBR and BTF are vendor-specific,
1590 thus reserved and should throw a #GP */
1591 return 1;
1592 }
a737f256
CD		 1593 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1594 __func__, data);
b5e2fec0 1595 break;
15c4a640
CO		 1596 case MSR_IA32_UCODE_REV:
1597 case MSR_IA32_UCODE_WRITE:
61a6bd67 1598 case MSR_VM_HSAVE_PA:
6098ca93 1599 case MSR_AMD64_PATCH_LOADER:
15c4a640 1600 break;
9ba075a6
AK		 1601 case 0x200 ... 0x2ff:
1602 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1603 case MSR_IA32_APICBASE:
1604 kvm_set_apic_base(vcpu, data);
1605 break;
0105d1a5
GN		 1606 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1607 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1608 case MSR_IA32_TSCDEADLINE:
1609 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1610 break;
15c4a640 1611 case MSR_IA32_MISC_ENABLE:
ad312c7c 1612 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1613 break;
11c6bffa 1614 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1615 case MSR_KVM_WALL_CLOCK:
1616 vcpu->kvm->arch.wall_clock = data;
1617 kvm_write_wall_clock(vcpu->kvm, data);
1618 break;
11c6bffa 1619 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1620 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1621 kvmclock_reset(vcpu);
18068523
GOC		 1622
1623 vcpu->arch.time = data;
c285545f 1624 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1625
1626 /* we verify if the enable bit is set... */
1627 if (!(data & 1))
1628 break;
1629
1630 /* ...but clean it before doing the actual write */
1631 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1632
18068523
GOC		 1633 vcpu->arch.time_page =
1634 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523 1635
32cad84f 1636 if (is_error_page(vcpu->arch.time_page))
18068523 1637 vcpu->arch.time_page = NULL;
32cad84f 1638
18068523
GOC		 1639 break;
1640 }
344d9588
GN		 1641 case MSR_KVM_ASYNC_PF_EN:
1642 if (kvm_pv_enable_async_pf(vcpu, data))
1643 return 1;
1644 break;
c9aaa895
GC		 1645 case MSR_KVM_STEAL_TIME:
1646
1647 if (unlikely(!sched_info_on()))
1648 return 1;
1649
1650 if (data & KVM_STEAL_RESERVED_MASK)
1651 return 1;
1652
1653 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1654 data & KVM_STEAL_VALID_BITS))
1655 return 1;
1656
1657 vcpu->arch.st.msr_val = data;
1658
1659 if (!(data & KVM_MSR_ENABLED))
1660 break;
1661
1662 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1663
1664 preempt_disable();
1665 accumulate_steal_time(vcpu);
1666 preempt_enable();
1667
1668 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1669
1670 break;
ae7a2a3f
MT		 1671 case MSR_KVM_PV_EOI_EN:
1672 if (kvm_lapic_enable_pv_eoi(vcpu, data))
1673 return 1;
1674 break;
c9aaa895 1675
890ca9ae
HY		 1676 case MSR_IA32_MCG_CTL:
1677 case MSR_IA32_MCG_STATUS:
1678 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1679 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1680
1681 /* Performance counters are not protected by a CPUID bit,
1682 * so we should check all of them in the generic path for the sake of
1683 * cross vendor migration.
1684 * Writing a zero into the event select MSRs disables them,
1685 * which we perfectly emulate ;-). Any other value should be at least
1686 * reported, some guests depend on them.
1687 */
71db6023
AP		 1688 case MSR_K7_EVNTSEL0:
1689 case MSR_K7_EVNTSEL1:
1690 case MSR_K7_EVNTSEL2:
1691 case MSR_K7_EVNTSEL3:
1692 if (data != 0)
a737f256
CD		 1693 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1694 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 1695 break;
1696 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1697 * so we ignore writes to make it happy.
1698 */
71db6023
AP		 1699 case MSR_K7_PERFCTR0:
1700 case MSR_K7_PERFCTR1:
1701 case MSR_K7_PERFCTR2:
1702 case MSR_K7_PERFCTR3:
a737f256
CD		 1703 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1704 "0x%x data 0x%llx\n", msr, data);
71db6023 1705 break;
5753785f
GN		 1706 case MSR_P6_PERFCTR0:
1707 case MSR_P6_PERFCTR1:
1708 pr = true;
1709 case MSR_P6_EVNTSEL0:
1710 case MSR_P6_EVNTSEL1:
1711 if (kvm_pmu_msr(vcpu, msr))
1712 return kvm_pmu_set_msr(vcpu, msr, data);
1713
1714 if (pr || data != 0)
a737f256
CD		 1715 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
1716 "0x%x data 0x%llx\n", msr, data);
5753785f 1717 break;
84e0cefa
JS		 1718 case MSR_K7_CLK_CTL:
1719 /*
1720 * Ignore all writes to this no longer documented MSR.
1721 * Writes are only relevant for old K7 processors,
1722 * all pre-dating SVM, but a recommended workaround from
4a969980 1723 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 1724 * affected processor models on the command line, hence
1725 * the need to ignore the workaround.
1726 */
1727 break;
55cd8e5a
GN		 1728 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1729 if (kvm_hv_msr_partition_wide(msr)) {
1730 int r;
1731 mutex_lock(&vcpu->kvm->lock);
1732 r = set_msr_hyperv_pw(vcpu, msr, data);
1733 mutex_unlock(&vcpu->kvm->lock);
1734 return r;
1735 } else
1736 return set_msr_hyperv(vcpu, msr, data);
1737 break;
91c9c3ed 1738 case MSR_IA32_BBL_CR_CTL3:
1739 /* Drop writes to this legacy MSR -- see rdmsr
1740 * counterpart for further detail.
1741 */
a737f256 1742 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 1743 break;
2b036c6b
BO		 1744 case MSR_AMD64_OSVW_ID_LENGTH:
1745 if (!guest_cpuid_has_osvw(vcpu))
1746 return 1;
1747 vcpu->arch.osvw.length = data;
1748 break;
1749 case MSR_AMD64_OSVW_STATUS:
1750 if (!guest_cpuid_has_osvw(vcpu))
1751 return 1;
1752 vcpu->arch.osvw.status = data;
1753 break;
15c4a640 1754 default:
ffde22ac
ES		 1755 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1756 return xen_hvm_config(vcpu, data);
f5132b01
GN		 1757 if (kvm_pmu_msr(vcpu, msr))
1758 return kvm_pmu_set_msr(vcpu, msr, data);
ed85c068 1759 if (!ignore_msrs) {
a737f256
CD		 1760 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1761 msr, data);
ed85c068
AP		 1762 return 1;
1763 } else {
a737f256
CD		 1764 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1765 msr, data);
ed85c068
AP		 1766 break;
1767 }
15c4a640
CO		 1768 }
1769 return 0;
1770}
1771EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1772
1773
1774/*
1775 * Reads an msr value (of 'msr_index') into 'pdata'.
1776 * Returns 0 on success, non-0 otherwise.
1777 * Assumes vcpu_load() was already called.
1778 */
1779int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1780{
1781 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1782}
1783
9ba075a6
AK		 1784static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1785{
0bed3b56
SY		 1786 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1787
9ba075a6
AK		 1788 if (!msr_mtrr_valid(msr))
1789 return 1;
1790
0bed3b56
SY		 1791 if (msr == MSR_MTRRdefType)
1792 *pdata = vcpu->arch.mtrr_state.def_type +
1793 (vcpu->arch.mtrr_state.enabled << 10);
1794 else if (msr == MSR_MTRRfix64K_00000)
1795 *pdata = p[0];
1796 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1797 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1798 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1799 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1800 else if (msr == MSR_IA32_CR_PAT)
1801 *pdata = vcpu->arch.pat;
1802 else { /* Variable MTRRs */
1803 int idx, is_mtrr_mask;
1804 u64 *pt;
1805
1806 idx = (msr - 0x200) / 2;
1807 is_mtrr_mask = msr - 0x200 - 2 * idx;
1808 if (!is_mtrr_mask)
1809 pt =
1810 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1811 else
1812 pt =
1813 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1814 *pdata = *pt;
1815 }
1816
9ba075a6
AK		 1817 return 0;
1818}
1819
890ca9ae 1820static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1821{
1822 u64 data;
890ca9ae
HY		 1823 u64 mcg_cap = vcpu->arch.mcg_cap;
1824 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1825
1826 switch (msr) {
15c4a640
CO		 1827 case MSR_IA32_P5_MC_ADDR:
1828 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1829 data = 0;
1830 break;
15c4a640 1831 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1832 data = vcpu->arch.mcg_cap;
1833 break;
c7ac679c 1834 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1835 if (!(mcg_cap & MCG_CTL_P))
1836 return 1;
1837 data = vcpu->arch.mcg_ctl;
1838 break;
1839 case MSR_IA32_MCG_STATUS:
1840 data = vcpu->arch.mcg_status;
1841 break;
1842 default:
1843 if (msr >= MSR_IA32_MC0_CTL &&
1844 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1845 u32 offset = msr - MSR_IA32_MC0_CTL;
1846 data = vcpu->arch.mce_banks[offset];
1847 break;
1848 }
1849 return 1;
1850 }
1851 *pdata = data;
1852 return 0;
1853}
1854
55cd8e5a
GN		 1855static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1856{
1857 u64 data = 0;
1858 struct kvm *kvm = vcpu->kvm;
1859
1860 switch (msr) {
1861 case HV_X64_MSR_GUEST_OS_ID:
1862 data = kvm->arch.hv_guest_os_id;
1863 break;
1864 case HV_X64_MSR_HYPERCALL:
1865 data = kvm->arch.hv_hypercall;
1866 break;
1867 default:
a737f256 1868 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 1869 return 1;
1870 }
1871
1872 *pdata = data;
1873 return 0;
1874}
1875
1876static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1877{
1878 u64 data = 0;
1879
1880 switch (msr) {
1881 case HV_X64_MSR_VP_INDEX: {
1882 int r;
1883 struct kvm_vcpu *v;
1884 kvm_for_each_vcpu(r, v, vcpu->kvm)
1885 if (v == vcpu)
1886 data = r;
1887 break;
1888 }
10388a07
GN		 1889 case HV_X64_MSR_EOI:
1890 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1891 case HV_X64_MSR_ICR:
1892 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1893 case HV_X64_MSR_TPR:
1894 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 1895 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 1896 data = vcpu->arch.hv_vapic;
1897 break;
55cd8e5a 1898 default:
a737f256 1899 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 1900 return 1;
1901 }
1902 *pdata = data;
1903 return 0;
1904}
1905
890ca9ae
HY		 1906int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1907{
1908 u64 data;
1909
1910 switch (msr) {
890ca9ae 1911 case MSR_IA32_PLATFORM_ID:
15c4a640 1912 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1913 case MSR_IA32_DEBUGCTLMSR:
1914 case MSR_IA32_LASTBRANCHFROMIP:
1915 case MSR_IA32_LASTBRANCHTOIP:
1916 case MSR_IA32_LASTINTFROMIP:
1917 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1918 case MSR_K8_SYSCFG:
1919 case MSR_K7_HWCR:
61a6bd67 1920 case MSR_VM_HSAVE_PA:
9e699624 1921 case MSR_K7_EVNTSEL0:
1f3ee616 1922 case MSR_K7_PERFCTR0:
1fdbd48c 1923 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1924 case MSR_AMD64_NB_CFG:
f7c6d140 1925 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1926 data = 0;
1927 break;
5753785f
GN		 1928 case MSR_P6_PERFCTR0:
1929 case MSR_P6_PERFCTR1:
1930 case MSR_P6_EVNTSEL0:
1931 case MSR_P6_EVNTSEL1:
1932 if (kvm_pmu_msr(vcpu, msr))
1933 return kvm_pmu_get_msr(vcpu, msr, pdata);
1934 data = 0;
1935 break;
742bc670
MT		 1936 case MSR_IA32_UCODE_REV:
1937 data = 0x100000000ULL;
1938 break;
9ba075a6
AK		 1939 case MSR_MTRRcap:
1940 data = 0x500 | KVM_NR_VAR_MTRR;
1941 break;
1942 case 0x200 ... 0x2ff:
1943 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1944 case 0xcd: /* fsb frequency */
1945 data = 3;
1946 break;
7b914098
JS		 1947 /*
1948 * MSR_EBC_FREQUENCY_ID
1949 * Conservative value valid for even the basic CPU models.
1950 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1951 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1952 * and 266MHz for model 3, or 4. Set Core Clock
1953 * Frequency to System Bus Frequency Ratio to 1 (bits
1954 * 31:24) even though these are only valid for CPU
1955 * models > 2, however guests may end up dividing or
1956 * multiplying by zero otherwise.
1957 */
1958 case MSR_EBC_FREQUENCY_ID:
1959 data = 1 << 24;
1960 break;
15c4a640
CO		 1961 case MSR_IA32_APICBASE:
1962 data = kvm_get_apic_base(vcpu);
1963 break;
0105d1a5
GN		 1964 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1965 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1966 break;
a3e06bbe
LJ		 1967 case MSR_IA32_TSCDEADLINE:
1968 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1969 break;
15c4a640 1970 case MSR_IA32_MISC_ENABLE:
ad312c7c 1971 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1972 break;
847f0ad8
AG		 1973 case MSR_IA32_PERF_STATUS:
1974 /* TSC increment by tick */
1975 data = 1000ULL;
1976 /* CPU multiplier */
1977 data |= (((uint64_t)4ULL) << 40);
1978 break;
15c4a640 1979 case MSR_EFER:
f6801dff 1980 data = vcpu->arch.efer;
15c4a640 1981 break;
18068523 1982 case MSR_KVM_WALL_CLOCK:
11c6bffa 1983 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1984 data = vcpu->kvm->arch.wall_clock;
1985 break;
1986 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1987 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1988 data = vcpu->arch.time;
1989 break;
344d9588
GN		 1990 case MSR_KVM_ASYNC_PF_EN:
1991 data = vcpu->arch.apf.msr_val;
1992 break;
c9aaa895
GC		 1993 case MSR_KVM_STEAL_TIME:
1994 data = vcpu->arch.st.msr_val;
1995 break;
890ca9ae
HY		 1996 case MSR_IA32_P5_MC_ADDR:
1997 case MSR_IA32_P5_MC_TYPE:
1998 case MSR_IA32_MCG_CAP:
1999 case MSR_IA32_MCG_CTL:
2000 case MSR_IA32_MCG_STATUS:
2001 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2002 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2003 case MSR_K7_CLK_CTL:
2004 /*
2005 * Provide expected ramp-up count for K7. All other
2006 * are set to zero, indicating minimum divisors for
2007 * every field.
2008 *
2009 * This prevents guest kernels on AMD host with CPU
2010 * type 6, model 8 and higher from exploding due to
2011 * the rdmsr failing.
2012 */
2013 data = 0x20000000;
2014 break;
55cd8e5a
GN		 2015 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2016 if (kvm_hv_msr_partition_wide(msr)) {
2017 int r;
2018 mutex_lock(&vcpu->kvm->lock);
2019 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2020 mutex_unlock(&vcpu->kvm->lock);
2021 return r;
2022 } else
2023 return get_msr_hyperv(vcpu, msr, pdata);
2024 break;
91c9c3ed 2025 case MSR_IA32_BBL_CR_CTL3:
2026 /* This legacy MSR exists but isn't fully documented in current
2027 * silicon. It is however accessed by winxp in very narrow
2028 * scenarios where it sets bit #19, itself documented as
2029 * a "reserved" bit. Best effort attempt to source coherent
2030 * read data here should the balance of the register be
2031 * interpreted by the guest:
2032 *
2033 * L2 cache control register 3: 64GB range, 256KB size,
2034 * enabled, latency 0x1, configured
2035 */
2036 data = 0xbe702111;
2037 break;
2b036c6b
BO		 2038 case MSR_AMD64_OSVW_ID_LENGTH:
2039 if (!guest_cpuid_has_osvw(vcpu))
2040 return 1;
2041 data = vcpu->arch.osvw.length;
2042 break;
2043 case MSR_AMD64_OSVW_STATUS:
2044 if (!guest_cpuid_has_osvw(vcpu))
2045 return 1;
2046 data = vcpu->arch.osvw.status;
2047 break;
15c4a640 2048 default:
f5132b01
GN		 2049 if (kvm_pmu_msr(vcpu, msr))
2050 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2051 if (!ignore_msrs) {
a737f256 2052 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2053 return 1;
2054 } else {
a737f256 2055 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2056 data = 0;
2057 }
2058 break;
15c4a640
CO		 2059 }
2060 *pdata = data;
2061 return 0;
2062}
2063EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2064
313a3dc7
CO		 2065/*
2066 * Read or write a bunch of msrs. All parameters are kernel addresses.
2067 *
2068 * @return number of msrs set successfully.
2069 */
2070static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2071 struct kvm_msr_entry *entries,
2072 int (*do_msr)(struct kvm_vcpu *vcpu,
2073 unsigned index, u64 *data))
2074{
f656ce01 2075 int i, idx;
313a3dc7 2076
f656ce01 2077 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2078 for (i = 0; i < msrs->nmsrs; ++i)
2079 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2080 break;
f656ce01 2081 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2082
313a3dc7
CO		 2083 return i;
2084}
2085
2086/*
2087 * Read or write a bunch of msrs. Parameters are user addresses.
2088 *
2089 * @return number of msrs set successfully.
2090 */
2091static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2092 int (*do_msr)(struct kvm_vcpu *vcpu,
2093 unsigned index, u64 *data),
2094 int writeback)
2095{
2096 struct kvm_msrs msrs;
2097 struct kvm_msr_entry *entries;
2098 int r, n;
2099 unsigned size;
2100
2101 r = -EFAULT;
2102 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2103 goto out;
2104
2105 r = -E2BIG;
2106 if (msrs.nmsrs >= MAX_IO_MSRS)
2107 goto out;
2108
313a3dc7 2109 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2110 entries = memdup_user(user_msrs->entries, size);
2111 if (IS_ERR(entries)) {
2112 r = PTR_ERR(entries);
313a3dc7 2113 goto out;
ff5c2c03 2114 }
313a3dc7
CO		 2115
2116 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2117 if (r < 0)
2118 goto out_free;
2119
2120 r = -EFAULT;
2121 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2122 goto out_free;
2123
2124 r = n;
2125
2126out_free:
7a73c028 2127 kfree(entries);
313a3dc7
CO		 2128out:
2129 return r;
2130}
2131
018d00d2
ZX		 2132int kvm_dev_ioctl_check_extension(long ext)
2133{
2134 int r;
2135
2136 switch (ext) {
2137 case KVM_CAP_IRQCHIP:
2138 case KVM_CAP_HLT:
2139 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2140 case KVM_CAP_SET_TSS_ADDR:
07716717 2141 case KVM_CAP_EXT_CPUID:
c8076604 2142 case KVM_CAP_CLOCKSOURCE:
7837699f 2143 case KVM_CAP_PIT:
a28e4f5a 2144 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2145 case KVM_CAP_MP_STATE:
ed848624 2146 case KVM_CAP_SYNC_MMU:
a355c85c 2147 case KVM_CAP_USER_NMI:
52d939a0 2148 case KVM_CAP_REINJECT_CONTROL:
4925663a 2149 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2150 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2151 case KVM_CAP_IRQFD:
d34e6b17 2152 case KVM_CAP_IOEVENTFD:
c5ff41ce 2153 case KVM_CAP_PIT2:
e9f42757 2154 case KVM_CAP_PIT_STATE2:
b927a3ce 2155 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2156 case KVM_CAP_XEN_HVM:
afbcf7ab 2157 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2158 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2159 case KVM_CAP_HYPERV:
10388a07 2160 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2161 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2162 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2163 case KVM_CAP_DEBUGREGS:
d2be1651 2164 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2165 case KVM_CAP_XSAVE:
344d9588 2166 case KVM_CAP_ASYNC_PF:
92a1f12d 2167 case KVM_CAP_GET_TSC_KHZ:
07700a94 2168 case KVM_CAP_PCI_2_3:
1c0b28c2 2169 case KVM_CAP_KVMCLOCK_CTRL:
018d00d2
ZX		 2170 r = 1;
2171 break;
542472b5
LV		 2172 case KVM_CAP_COALESCED_MMIO:
2173 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2174 break;
774ead3a
AK		 2175 case KVM_CAP_VAPIC:
2176 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2177 break;
f725230a 2178 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2179 r = KVM_SOFT_MAX_VCPUS;
2180 break;
2181 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2182 r = KVM_MAX_VCPUS;
2183 break;
a988b910
AK		 2184 case KVM_CAP_NR_MEMSLOTS:
2185 r = KVM_MEMORY_SLOTS;
2186 break;
a68a6a72
MT		 2187 case KVM_CAP_PV_MMU: /* obsolete */
2188 r = 0;
2f333bcb 2189 break;
62c476c7 2190 case KVM_CAP_IOMMU:
a1b60c1c 2191 r = iommu_present(&pci_bus_type);
62c476c7 2192 break;
890ca9ae
HY		 2193 case KVM_CAP_MCE:
2194 r = KVM_MAX_MCE_BANKS;
2195 break;
2d5b5a66
SY		 2196 case KVM_CAP_XCRS:
2197 r = cpu_has_xsave;
2198 break;
92a1f12d
JR		 2199 case KVM_CAP_TSC_CONTROL:
2200 r = kvm_has_tsc_control;
2201 break;
4d25a066
JK		 2202 case KVM_CAP_TSC_DEADLINE_TIMER:
2203 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2204 break;
018d00d2
ZX		 2205 default:
2206 r = 0;
2207 break;
2208 }
2209 return r;
2210
2211}
2212
043405e1
CO		 2213long kvm_arch_dev_ioctl(struct file *filp,
2214 unsigned int ioctl, unsigned long arg)
2215{
2216 void __user *argp = (void __user *)arg;
2217 long r;
2218
2219 switch (ioctl) {
2220 case KVM_GET_MSR_INDEX_LIST: {
2221 struct kvm_msr_list __user *user_msr_list = argp;
2222 struct kvm_msr_list msr_list;
2223 unsigned n;
2224
2225 r = -EFAULT;
2226 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2227 goto out;
2228 n = msr_list.nmsrs;
2229 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2230 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2231 goto out;
2232 r = -E2BIG;
e125e7b6 2233 if (n < msr_list.nmsrs)
043405e1
CO		 2234 goto out;
2235 r = -EFAULT;
2236 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2237 num_msrs_to_save * sizeof(u32)))
2238 goto out;
e125e7b6 2239 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2240 &emulated_msrs,
2241 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2242 goto out;
2243 r = 0;
2244 break;
2245 }
674eea0f
AK		 2246 case KVM_GET_SUPPORTED_CPUID: {
2247 struct kvm_cpuid2 __user *cpuid_arg = argp;
2248 struct kvm_cpuid2 cpuid;
2249
2250 r = -EFAULT;
2251 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2252 goto out;
2253 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2254 cpuid_arg->entries);
674eea0f
AK		 2255 if (r)
2256 goto out;
2257
2258 r = -EFAULT;
2259 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2260 goto out;
2261 r = 0;
2262 break;
2263 }
890ca9ae
HY		 2264 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2265 u64 mce_cap;
2266
2267 mce_cap = KVM_MCE_CAP_SUPPORTED;
2268 r = -EFAULT;
2269 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2270 goto out;
2271 r = 0;
2272 break;
2273 }
043405e1
CO		 2274 default:
2275 r = -EINVAL;
2276 }
2277out:
2278 return r;
2279}
2280
f5f48ee1
SY		 2281static void wbinvd_ipi(void *garbage)
2282{
2283 wbinvd();
2284}
2285
2286static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2287{
2288 return vcpu->kvm->arch.iommu_domain &&
2289 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2290}
2291
313a3dc7
CO		 2292void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2293{
f5f48ee1
SY		 2294 /* Address WBINVD may be executed by guest */
2295 if (need_emulate_wbinvd(vcpu)) {
2296 if (kvm_x86_ops->has_wbinvd_exit())
2297 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2298 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2299 smp_call_function_single(vcpu->cpu,
2300 wbinvd_ipi, NULL, 1);
2301 }
2302
313a3dc7 2303 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2304
0dd6a6ed
ZA		 2305 /* Apply any externally detected TSC adjustments (due to suspend) */
2306 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2307 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2308 vcpu->arch.tsc_offset_adjustment = 0;
2309 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2310 }
8f6055cb 2311
48434c20 2312 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2313 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2314 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2315 if (tsc_delta < 0)
2316 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2317 if (check_tsc_unstable()) {
b183aa58
ZA		 2318 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2319 vcpu->arch.last_guest_tsc);
2320 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2321 vcpu->arch.tsc_catchup = 1;
c285545f 2322 }
1aa8ceef 2323 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2324 if (vcpu->cpu != cpu)
2325 kvm_migrate_timers(vcpu);
e48672fa 2326 vcpu->cpu = cpu;
6b7d7e76 2327 }
c9aaa895
GC		 2328
2329 accumulate_steal_time(vcpu);
2330 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2331}
2332
2333void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2334{
02daab21 2335 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2336 kvm_put_guest_fpu(vcpu);
6f526ec5 2337 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2338}
2339
313a3dc7
CO		 2340static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2341 struct kvm_lapic_state *s)
2342{
ad312c7c 2343 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2344
2345 return 0;
2346}
2347
2348static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2349 struct kvm_lapic_state *s)
2350{
ad312c7c 2351 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2352 kvm_apic_post_state_restore(vcpu);
cb142eb7 2353 update_cr8_intercept(vcpu);
313a3dc7
CO		 2354
2355 return 0;
2356}
2357
f77bc6a4
ZX		 2358static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2359 struct kvm_interrupt *irq)
2360{
2361 if (irq->irq < 0 || irq->irq >= 256)
2362 return -EINVAL;
2363 if (irqchip_in_kernel(vcpu->kvm))
2364 return -ENXIO;
f77bc6a4 2365
66fd3f7f 2366 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2367 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2368
f77bc6a4
ZX		 2369 return 0;
2370}
2371
c4abb7c9
JK		 2372static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2373{
c4abb7c9 2374 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2375
2376 return 0;
2377}
2378
b209749f
AK		 2379static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2380 struct kvm_tpr_access_ctl *tac)
2381{
2382 if (tac->flags)
2383 return -EINVAL;
2384 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2385 return 0;
2386}
2387
890ca9ae
HY		 2388static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2389 u64 mcg_cap)
2390{
2391 int r;
2392 unsigned bank_num = mcg_cap & 0xff, bank;
2393
2394 r = -EINVAL;
a9e38c3e 2395 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2396 goto out;
2397 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2398 goto out;
2399 r = 0;
2400 vcpu->arch.mcg_cap = mcg_cap;
2401 /* Init IA32_MCG_CTL to all 1s */
2402 if (mcg_cap & MCG_CTL_P)
2403 vcpu->arch.mcg_ctl = ~(u64)0;
2404 /* Init IA32_MCi_CTL to all 1s */
2405 for (bank = 0; bank < bank_num; bank++)
2406 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2407out:
2408 return r;
2409}
2410
2411static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2412 struct kvm_x86_mce *mce)
2413{
2414 u64 mcg_cap = vcpu->arch.mcg_cap;
2415 unsigned bank_num = mcg_cap & 0xff;
2416 u64 *banks = vcpu->arch.mce_banks;
2417
2418 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2419 return -EINVAL;
2420 /*
2421 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2422 * reporting is disabled
2423 */
2424 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2425 vcpu->arch.mcg_ctl != ~(u64)0)
2426 return 0;
2427 banks += 4 * mce->bank;
2428 /*
2429 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2430 * reporting is disabled for the bank
2431 */
2432 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2433 return 0;
2434 if (mce->status & MCI_STATUS_UC) {
2435 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2436 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2437 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2438 return 0;
2439 }
2440 if (banks[1] & MCI_STATUS_VAL)
2441 mce->status |= MCI_STATUS_OVER;
2442 banks[2] = mce->addr;
2443 banks[3] = mce->misc;
2444 vcpu->arch.mcg_status = mce->mcg_status;
2445 banks[1] = mce->status;
2446 kvm_queue_exception(vcpu, MC_VECTOR);
2447 } else if (!(banks[1] & MCI_STATUS_VAL)
2448 || !(banks[1] & MCI_STATUS_UC)) {
2449 if (banks[1] & MCI_STATUS_VAL)
2450 mce->status |= MCI_STATUS_OVER;
2451 banks[2] = mce->addr;
2452 banks[3] = mce->misc;
2453 banks[1] = mce->status;
2454 } else
2455 banks[1] |= MCI_STATUS_OVER;
2456 return 0;
2457}
2458
3cfc3092
JK		 2459static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2460 struct kvm_vcpu_events *events)
2461{
7460fb4a 2462 process_nmi(vcpu);
03b82a30
JK		 2463 events->exception.injected =
2464 vcpu->arch.exception.pending &&
2465 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2466 events->exception.nr = vcpu->arch.exception.nr;
2467 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2468 events->exception.pad = 0;
3cfc3092
JK		 2469 events->exception.error_code = vcpu->arch.exception.error_code;
2470
03b82a30
JK		 2471 events->interrupt.injected =
2472 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2473 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2474 events->interrupt.soft = 0;
48005f64
JK		 2475 events->interrupt.shadow =
2476 kvm_x86_ops->get_interrupt_shadow(vcpu,
2477 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2478
2479 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2480 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2481 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2482 events->nmi.pad = 0;
3cfc3092
JK		 2483
2484 events->sipi_vector = vcpu->arch.sipi_vector;
2485
dab4b911 2486 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2487 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2488 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2489 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2490}
2491
2492static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2493 struct kvm_vcpu_events *events)
2494{
dab4b911 2495 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2496 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2497 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2498 return -EINVAL;
2499
7460fb4a 2500 process_nmi(vcpu);
3cfc3092
JK		 2501 vcpu->arch.exception.pending = events->exception.injected;
2502 vcpu->arch.exception.nr = events->exception.nr;
2503 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2504 vcpu->arch.exception.error_code = events->exception.error_code;
2505
2506 vcpu->arch.interrupt.pending = events->interrupt.injected;
2507 vcpu->arch.interrupt.nr = events->interrupt.nr;
2508 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2509 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2510 kvm_x86_ops->set_interrupt_shadow(vcpu,
2511 events->interrupt.shadow);
3cfc3092
JK		 2512
2513 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2514 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2515 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2516 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2517
dab4b911
JK		 2518 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2519 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2520
3842d135
AK		 2521 kvm_make_request(KVM_REQ_EVENT, vcpu);
2522
3cfc3092
JK		 2523 return 0;
2524}
2525
a1efbe77
JK		 2526static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2527 struct kvm_debugregs *dbgregs)
2528{
a1efbe77
JK		 2529 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2530 dbgregs->dr6 = vcpu->arch.dr6;
2531 dbgregs->dr7 = vcpu->arch.dr7;
2532 dbgregs->flags = 0;
97e69aa6 2533 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2534}
2535
2536static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2537 struct kvm_debugregs *dbgregs)
2538{
2539 if (dbgregs->flags)
2540 return -EINVAL;
2541
a1efbe77
JK		 2542 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2543 vcpu->arch.dr6 = dbgregs->dr6;
2544 vcpu->arch.dr7 = dbgregs->dr7;
2545
a1efbe77
JK		 2546 return 0;
2547}
2548
2d5b5a66
SY		 2549static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2550 struct kvm_xsave *guest_xsave)
2551{
2552 if (cpu_has_xsave)
2553 memcpy(guest_xsave->region,
2554 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2555 xstate_size);
2d5b5a66
SY		 2556 else {
2557 memcpy(guest_xsave->region,
2558 &vcpu->arch.guest_fpu.state->fxsave,
2559 sizeof(struct i387_fxsave_struct));
2560 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2561 XSTATE_FPSSE;
2562 }
2563}
2564
2565static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2566 struct kvm_xsave *guest_xsave)
2567{
2568 u64 xstate_bv =
2569 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2570
2571 if (cpu_has_xsave)
2572 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2573 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2574 else {
2575 if (xstate_bv & ~XSTATE_FPSSE)
2576 return -EINVAL;
2577 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2578 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2579 }
2580 return 0;
2581}
2582
2583static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2584 struct kvm_xcrs *guest_xcrs)
2585{
2586 if (!cpu_has_xsave) {
2587 guest_xcrs->nr_xcrs = 0;
2588 return;
2589 }
2590
2591 guest_xcrs->nr_xcrs = 1;
2592 guest_xcrs->flags = 0;
2593 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2594 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2595}
2596
2597static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2598 struct kvm_xcrs *guest_xcrs)
2599{
2600 int i, r = 0;
2601
2602 if (!cpu_has_xsave)
2603 return -EINVAL;
2604
2605 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2606 return -EINVAL;
2607
2608 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2609 /* Only support XCR0 currently */
2610 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2611 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2612 guest_xcrs->xcrs[0].value);
2613 break;
2614 }
2615 if (r)
2616 r = -EINVAL;
2617 return r;
2618}
2619
1c0b28c2
EM		 2620/*
2621 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2622 * stopped by the hypervisor. This function will be called from the host only.
2623 * EINVAL is returned when the host attempts to set the flag for a guest that
2624 * does not support pv clocks.
2625 */
2626static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2627{
2628 struct pvclock_vcpu_time_info *src = &vcpu->arch.hv_clock;
2629 if (!vcpu->arch.time_page)
2630 return -EINVAL;
2631 src->flags |= PVCLOCK_GUEST_STOPPED;
1c0b28c2
EM		 2632 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2633 return 0;
2634}
2635
313a3dc7
CO		 2636long kvm_arch_vcpu_ioctl(struct file *filp,
2637 unsigned int ioctl, unsigned long arg)
2638{
2639 struct kvm_vcpu *vcpu = filp->private_data;
2640 void __user *argp = (void __user *)arg;
2641 int r;
d1ac91d8
AK		 2642 union {
2643 struct kvm_lapic_state *lapic;
2644 struct kvm_xsave *xsave;
2645 struct kvm_xcrs *xcrs;
2646 void *buffer;
2647 } u;
2648
2649 u.buffer = NULL;
313a3dc7
CO		 2650 switch (ioctl) {
2651 case KVM_GET_LAPIC: {
2204ae3c
MT		 2652 r = -EINVAL;
2653 if (!vcpu->arch.apic)
2654 goto out;
d1ac91d8 2655 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2656
b772ff36 2657 r = -ENOMEM;
d1ac91d8 2658 if (!u.lapic)
b772ff36 2659 goto out;
d1ac91d8 2660 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2661 if (r)
2662 goto out;
2663 r = -EFAULT;
d1ac91d8 2664 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2665 goto out;
2666 r = 0;
2667 break;
2668 }
2669 case KVM_SET_LAPIC: {
2204ae3c
MT		 2670 r = -EINVAL;
2671 if (!vcpu->arch.apic)
2672 goto out;
ff5c2c03
SL		 2673 u.lapic = memdup_user(argp, sizeof(*u.lapic));
2674 if (IS_ERR(u.lapic)) {
2675 r = PTR_ERR(u.lapic);
313a3dc7 2676 goto out;
ff5c2c03
SL		 2677 }
2678
d1ac91d8 2679 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2680 if (r)
2681 goto out;
2682 r = 0;
2683 break;
2684 }
f77bc6a4
ZX		 2685 case KVM_INTERRUPT: {
2686 struct kvm_interrupt irq;
2687
2688 r = -EFAULT;
2689 if (copy_from_user(&irq, argp, sizeof irq))
2690 goto out;
2691 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2692 if (r)
2693 goto out;
2694 r = 0;
2695 break;
2696 }
c4abb7c9
JK		 2697 case KVM_NMI: {
2698 r = kvm_vcpu_ioctl_nmi(vcpu);
2699 if (r)
2700 goto out;
2701 r = 0;
2702 break;
2703 }
313a3dc7
CO		 2704 case KVM_SET_CPUID: {
2705 struct kvm_cpuid __user *cpuid_arg = argp;
2706 struct kvm_cpuid cpuid;
2707
2708 r = -EFAULT;
2709 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2710 goto out;
2711 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2712 if (r)
2713 goto out;
2714 break;
2715 }
07716717
DK		 2716 case KVM_SET_CPUID2: {
2717 struct kvm_cpuid2 __user *cpuid_arg = argp;
2718 struct kvm_cpuid2 cpuid;
2719
2720 r = -EFAULT;
2721 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2722 goto out;
2723 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2724 cpuid_arg->entries);
07716717
DK		 2725 if (r)
2726 goto out;
2727 break;
2728 }
2729 case KVM_GET_CPUID2: {
2730 struct kvm_cpuid2 __user *cpuid_arg = argp;
2731 struct kvm_cpuid2 cpuid;
2732
2733 r = -EFAULT;
2734 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2735 goto out;
2736 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2737 cpuid_arg->entries);
07716717
DK		 2738 if (r)
2739 goto out;
2740 r = -EFAULT;
2741 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2742 goto out;
2743 r = 0;
2744 break;
2745 }
313a3dc7
CO		 2746 case KVM_GET_MSRS:
2747 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2748 break;
2749 case KVM_SET_MSRS:
2750 r = msr_io(vcpu, argp, do_set_msr, 0);
2751 break;
b209749f
AK		 2752 case KVM_TPR_ACCESS_REPORTING: {
2753 struct kvm_tpr_access_ctl tac;
2754
2755 r = -EFAULT;
2756 if (copy_from_user(&tac, argp, sizeof tac))
2757 goto out;
2758 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2759 if (r)
2760 goto out;
2761 r = -EFAULT;
2762 if (copy_to_user(argp, &tac, sizeof tac))
2763 goto out;
2764 r = 0;
2765 break;
2766 };
b93463aa
AK		 2767 case KVM_SET_VAPIC_ADDR: {
2768 struct kvm_vapic_addr va;
2769
2770 r = -EINVAL;
2771 if (!irqchip_in_kernel(vcpu->kvm))
2772 goto out;
2773 r = -EFAULT;
2774 if (copy_from_user(&va, argp, sizeof va))
2775 goto out;
2776 r = 0;
2777 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2778 break;
2779 }
890ca9ae
HY		 2780 case KVM_X86_SETUP_MCE: {
2781 u64 mcg_cap;
2782
2783 r = -EFAULT;
2784 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2785 goto out;
2786 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2787 break;
2788 }
2789 case KVM_X86_SET_MCE: {
2790 struct kvm_x86_mce mce;
2791
2792 r = -EFAULT;
2793 if (copy_from_user(&mce, argp, sizeof mce))
2794 goto out;
2795 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2796 break;
2797 }
3cfc3092
JK		 2798 case KVM_GET_VCPU_EVENTS: {
2799 struct kvm_vcpu_events events;
2800
2801 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2802
2803 r = -EFAULT;
2804 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2805 break;
2806 r = 0;
2807 break;
2808 }
2809 case KVM_SET_VCPU_EVENTS: {
2810 struct kvm_vcpu_events events;
2811
2812 r = -EFAULT;
2813 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2814 break;
2815
2816 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2817 break;
2818 }
a1efbe77
JK		 2819 case KVM_GET_DEBUGREGS: {
2820 struct kvm_debugregs dbgregs;
2821
2822 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2823
2824 r = -EFAULT;
2825 if (copy_to_user(argp, &dbgregs,
2826 sizeof(struct kvm_debugregs)))
2827 break;
2828 r = 0;
2829 break;
2830 }
2831 case KVM_SET_DEBUGREGS: {
2832 struct kvm_debugregs dbgregs;
2833
2834 r = -EFAULT;
2835 if (copy_from_user(&dbgregs, argp,
2836 sizeof(struct kvm_debugregs)))
2837 break;
2838
2839 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2840 break;
2841 }
2d5b5a66 2842 case KVM_GET_XSAVE: {
d1ac91d8 2843 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2844 r = -ENOMEM;
d1ac91d8 2845 if (!u.xsave)
2d5b5a66
SY		 2846 break;
2847
d1ac91d8 2848 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2849
2850 r = -EFAULT;
d1ac91d8 2851 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2852 break;
2853 r = 0;
2854 break;
2855 }
2856 case KVM_SET_XSAVE: {
ff5c2c03
SL		 2857 u.xsave = memdup_user(argp, sizeof(*u.xsave));
2858 if (IS_ERR(u.xsave)) {
2859 r = PTR_ERR(u.xsave);
2860 goto out;
2861 }
2d5b5a66 2862
d1ac91d8 2863 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2864 break;
2865 }
2866 case KVM_GET_XCRS: {
d1ac91d8 2867 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2868 r = -ENOMEM;
d1ac91d8 2869 if (!u.xcrs)
2d5b5a66
SY		 2870 break;
2871
d1ac91d8 2872 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2873
2874 r = -EFAULT;
d1ac91d8 2875 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2876 sizeof(struct kvm_xcrs)))
2877 break;
2878 r = 0;
2879 break;
2880 }
2881 case KVM_SET_XCRS: {
ff5c2c03
SL		 2882 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
2883 if (IS_ERR(u.xcrs)) {
2884 r = PTR_ERR(u.xcrs);
2885 goto out;
2886 }
2d5b5a66 2887
d1ac91d8 2888 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2889 break;
2890 }
92a1f12d
JR		 2891 case KVM_SET_TSC_KHZ: {
2892 u32 user_tsc_khz;
2893
2894 r = -EINVAL;
92a1f12d
JR		 2895 user_tsc_khz = (u32)arg;
2896
2897 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2898 goto out;
2899
cc578287
ZA		 2900 if (user_tsc_khz == 0)
2901 user_tsc_khz = tsc_khz;
2902
2903 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 2904
2905 r = 0;
2906 goto out;
2907 }
2908 case KVM_GET_TSC_KHZ: {
cc578287 2909 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 2910 goto out;
2911 }
1c0b28c2
EM		 2912 case KVM_KVMCLOCK_CTRL: {
2913 r = kvm_set_guest_paused(vcpu);
2914 goto out;
2915 }
313a3dc7
CO		 2916 default:
2917 r = -EINVAL;
2918 }
2919out:
d1ac91d8 2920 kfree(u.buffer);
313a3dc7
CO		 2921 return r;
2922}
2923
5b1c1493
CO		 2924int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
2925{
2926 return VM_FAULT_SIGBUS;
2927}
2928
1fe779f8
CO		 2929static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2930{
2931 int ret;
2932
2933 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2934 return -1;
2935 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2936 return ret;
2937}
2938
b927a3ce
SY		 2939static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2940 u64 ident_addr)
2941{
2942 kvm->arch.ept_identity_map_addr = ident_addr;
2943 return 0;
2944}
2945
1fe779f8
CO		 2946static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2947 u32 kvm_nr_mmu_pages)
2948{
2949 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2950 return -EINVAL;
2951
79fac95e 2952 mutex_lock(&kvm->slots_lock);
7c8a83b7 2953 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2954
2955 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2956 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2957
7c8a83b7 2958 spin_unlock(&kvm->mmu_lock);
79fac95e 2959 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2960 return 0;
2961}
2962
2963static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2964{
39de71ec 2965 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2966}
2967
1fe779f8
CO		 2968static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2969{
2970 int r;
2971
2972 r = 0;
2973 switch (chip->chip_id) {
2974 case KVM_IRQCHIP_PIC_MASTER:
2975 memcpy(&chip->chip.pic,
2976 &pic_irqchip(kvm)->pics[0],
2977 sizeof(struct kvm_pic_state));
2978 break;
2979 case KVM_IRQCHIP_PIC_SLAVE:
2980 memcpy(&chip->chip.pic,
2981 &pic_irqchip(kvm)->pics[1],
2982 sizeof(struct kvm_pic_state));
2983 break;
2984 case KVM_IRQCHIP_IOAPIC:
eba0226b 2985 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2986 break;
2987 default:
2988 r = -EINVAL;
2989 break;
2990 }
2991 return r;
2992}
2993
2994static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2995{
2996 int r;
2997
2998 r = 0;
2999 switch (chip->chip_id) {
3000 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3001 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3002 memcpy(&pic_irqchip(kvm)->pics[0],
3003 &chip->chip.pic,
3004 sizeof(struct kvm_pic_state));
f4f51050 3005 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3006 break;
3007 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3008 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3009 memcpy(&pic_irqchip(kvm)->pics[1],
3010 &chip->chip.pic,
3011 sizeof(struct kvm_pic_state));
f4f51050 3012 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3013 break;
3014 case KVM_IRQCHIP_IOAPIC:
eba0226b 3015 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3016 break;
3017 default:
3018 r = -EINVAL;
3019 break;
3020 }
3021 kvm_pic_update_irq(pic_irqchip(kvm));
3022 return r;
3023}
3024
e0f63cb9
SY		 3025static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3026{
3027 int r = 0;
3028
894a9c55 3029 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3030 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3031 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3032 return r;
3033}
3034
3035static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3036{
3037 int r = 0;
3038
894a9c55 3039 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3040 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3041 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3042 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3043 return r;
3044}
3045
3046static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3047{
3048 int r = 0;
3049
3050 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3051 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3052 sizeof(ps->channels));
3053 ps->flags = kvm->arch.vpit->pit_state.flags;
3054 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3055 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3056 return r;
3057}
3058
3059static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3060{
3061 int r = 0, start = 0;
3062 u32 prev_legacy, cur_legacy;
3063 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3064 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3065 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3066 if (!prev_legacy && cur_legacy)
3067 start = 1;
3068 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3069 sizeof(kvm->arch.vpit->pit_state.channels));
3070 kvm->arch.vpit->pit_state.flags = ps->flags;
3071 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3072 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3073 return r;
3074}
3075
52d939a0
MT		 3076static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3077 struct kvm_reinject_control *control)
3078{
3079 if (!kvm->arch.vpit)
3080 return -ENXIO;
894a9c55 3081 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3082 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3083 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3084 return 0;
3085}
3086
95d4c16c 3087/**
60c34612
TY		 3088 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3089 * @kvm: kvm instance
3090 * @log: slot id and address to which we copy the log
95d4c16c 3091 *
60c34612
TY		 3092 * We need to keep it in mind that VCPU threads can write to the bitmap
3093 * concurrently. So, to avoid losing data, we keep the following order for
3094 * each bit:
95d4c16c 3095 *
60c34612
TY		 3096 * 1. Take a snapshot of the bit and clear it if needed.
3097 * 2. Write protect the corresponding page.
3098 * 3. Flush TLB's if needed.
3099 * 4. Copy the snapshot to the userspace.
95d4c16c 3100 *
60c34612
TY		 3101 * Between 2 and 3, the guest may write to the page using the remaining TLB
3102 * entry. This is not a problem because the page will be reported dirty at
3103 * step 4 using the snapshot taken before and step 3 ensures that successive
3104 * writes will be logged for the next call.
5bb064dc 3105 */
60c34612 3106int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3107{
7850ac54 3108 int r;
5bb064dc 3109 struct kvm_memory_slot *memslot;
60c34612
TY		 3110 unsigned long n, i;
3111 unsigned long *dirty_bitmap;
3112 unsigned long *dirty_bitmap_buffer;
3113 bool is_dirty = false;
5bb064dc 3114
79fac95e 3115 mutex_lock(&kvm->slots_lock);
5bb064dc 3116
b050b015
MT		 3117 r = -EINVAL;
3118 if (log->slot >= KVM_MEMORY_SLOTS)
3119 goto out;
3120
28a37544 3121 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3122
3123 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3124 r = -ENOENT;
60c34612 3125 if (!dirty_bitmap)
b050b015
MT		 3126 goto out;
3127
87bf6e7d 3128 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3129
60c34612
TY		 3130 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3131 memset(dirty_bitmap_buffer, 0, n);
b050b015 3132
60c34612 3133 spin_lock(&kvm->mmu_lock);
b050b015 3134
60c34612
TY		 3135 for (i = 0; i < n / sizeof(long); i++) {
3136 unsigned long mask;
3137 gfn_t offset;
cdfca7b3 3138
60c34612
TY		 3139 if (!dirty_bitmap[i])
3140 continue;
b050b015 3141
60c34612 3142 is_dirty = true;
914ebccd 3143
60c34612
TY		 3144 mask = xchg(&dirty_bitmap[i], 0);
3145 dirty_bitmap_buffer[i] = mask;
edde99ce 3146
60c34612
TY		 3147 offset = i * BITS_PER_LONG;
3148 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3149 }
60c34612
TY		 3150 if (is_dirty)
3151 kvm_flush_remote_tlbs(kvm);
3152
3153 spin_unlock(&kvm->mmu_lock);
3154
3155 r = -EFAULT;
3156 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3157 goto out;
b050b015 3158
5bb064dc
ZX		 3159 r = 0;
3160out:
79fac95e 3161 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3162 return r;
3163}
3164
23d43cf9
CD		 3165int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event)
3166{
3167 if (!irqchip_in_kernel(kvm))
3168 return -ENXIO;
3169
3170 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3171 irq_event->irq, irq_event->level);
3172 return 0;
3173}
3174
1fe779f8
CO		 3175long kvm_arch_vm_ioctl(struct file *filp,
3176 unsigned int ioctl, unsigned long arg)
3177{
3178 struct kvm *kvm = filp->private_data;
3179 void __user *argp = (void __user *)arg;
367e1319 3180 int r = -ENOTTY;
f0d66275
DH		 3181 /*
3182 * This union makes it completely explicit to gcc-3.x
3183 * that these two variables' stack usage should be
3184 * combined, not added together.
3185 */
3186 union {
3187 struct kvm_pit_state ps;
e9f42757 3188 struct kvm_pit_state2 ps2;
c5ff41ce 3189 struct kvm_pit_config pit_config;
f0d66275 3190 } u;
1fe779f8
CO		 3191
3192 switch (ioctl) {
3193 case KVM_SET_TSS_ADDR:
3194 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3195 if (r < 0)
3196 goto out;
3197 break;
b927a3ce
SY		 3198 case KVM_SET_IDENTITY_MAP_ADDR: {
3199 u64 ident_addr;
3200
3201 r = -EFAULT;
3202 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3203 goto out;
3204 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3205 if (r < 0)
3206 goto out;
3207 break;
3208 }
1fe779f8
CO		 3209 case KVM_SET_NR_MMU_PAGES:
3210 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3211 if (r)
3212 goto out;
3213 break;
3214 case KVM_GET_NR_MMU_PAGES:
3215 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3216 break;
3ddea128
MT		 3217 case KVM_CREATE_IRQCHIP: {
3218 struct kvm_pic *vpic;
3219
3220 mutex_lock(&kvm->lock);
3221 r = -EEXIST;
3222 if (kvm->arch.vpic)
3223 goto create_irqchip_unlock;
3e515705
AK		 3224 r = -EINVAL;
3225 if (atomic_read(&kvm->online_vcpus))
3226 goto create_irqchip_unlock;
1fe779f8 3227 r = -ENOMEM;
3ddea128
MT		 3228 vpic = kvm_create_pic(kvm);
3229 if (vpic) {
1fe779f8
CO		 3230 r = kvm_ioapic_init(kvm);
3231 if (r) {
175504cd 3232 mutex_lock(&kvm->slots_lock);
72bb2fcd 3233 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3234 &vpic->dev_master);
3235 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3236 &vpic->dev_slave);
3237 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3238 &vpic->dev_eclr);
175504cd 3239 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3240 kfree(vpic);
3241 goto create_irqchip_unlock;
1fe779f8
CO		 3242 }
3243 } else
3ddea128
MT		 3244 goto create_irqchip_unlock;
3245 smp_wmb();
3246 kvm->arch.vpic = vpic;
3247 smp_wmb();
399ec807
AK		 3248 r = kvm_setup_default_irq_routing(kvm);
3249 if (r) {
175504cd 3250 mutex_lock(&kvm->slots_lock);
3ddea128 3251 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3252 kvm_ioapic_destroy(kvm);
3253 kvm_destroy_pic(kvm);
3ddea128 3254 mutex_unlock(&kvm->irq_lock);
175504cd 3255 mutex_unlock(&kvm->slots_lock);
399ec807 3256 }
3ddea128
MT		 3257 create_irqchip_unlock:
3258 mutex_unlock(&kvm->lock);
1fe779f8 3259 break;
3ddea128 3260 }
7837699f 3261 case KVM_CREATE_PIT:
c5ff41ce
JK		 3262 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3263 goto create_pit;
3264 case KVM_CREATE_PIT2:
3265 r = -EFAULT;
3266 if (copy_from_user(&u.pit_config, argp,
3267 sizeof(struct kvm_pit_config)))
3268 goto out;
3269 create_pit:
79fac95e 3270 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3271 r = -EEXIST;
3272 if (kvm->arch.vpit)
3273 goto create_pit_unlock;
7837699f 3274 r = -ENOMEM;
c5ff41ce 3275 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3276 if (kvm->arch.vpit)
3277 r = 0;
269e05e4 3278 create_pit_unlock:
79fac95e 3279 mutex_unlock(&kvm->slots_lock);
7837699f 3280 break;
1fe779f8
CO		 3281 case KVM_GET_IRQCHIP: {
3282 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3283 struct kvm_irqchip *chip;
1fe779f8 3284
ff5c2c03
SL		 3285 chip = memdup_user(argp, sizeof(*chip));
3286 if (IS_ERR(chip)) {
3287 r = PTR_ERR(chip);
1fe779f8 3288 goto out;
ff5c2c03
SL		 3289 }
3290
1fe779f8
CO		 3291 r = -ENXIO;
3292 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3293 goto get_irqchip_out;
3294 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3295 if (r)
f0d66275 3296 goto get_irqchip_out;
1fe779f8 3297 r = -EFAULT;
f0d66275
DH		 3298 if (copy_to_user(argp, chip, sizeof *chip))
3299 goto get_irqchip_out;
1fe779f8 3300 r = 0;
f0d66275
DH		 3301 get_irqchip_out:
3302 kfree(chip);
3303 if (r)
3304 goto out;
1fe779f8
CO		 3305 break;
3306 }
3307 case KVM_SET_IRQCHIP: {
3308 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3309 struct kvm_irqchip *chip;
1fe779f8 3310
ff5c2c03
SL		 3311 chip = memdup_user(argp, sizeof(*chip));
3312 if (IS_ERR(chip)) {
3313 r = PTR_ERR(chip);
1fe779f8 3314 goto out;
ff5c2c03
SL		 3315 }
3316
1fe779f8
CO		 3317 r = -ENXIO;
3318 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3319 goto set_irqchip_out;
3320 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3321 if (r)
f0d66275 3322 goto set_irqchip_out;
1fe779f8 3323 r = 0;
f0d66275
DH		 3324 set_irqchip_out:
3325 kfree(chip);
3326 if (r)
3327 goto out;
1fe779f8
CO		 3328 break;
3329 }
e0f63cb9 3330 case KVM_GET_PIT: {
e0f63cb9 3331 r = -EFAULT;
f0d66275 3332 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3333 goto out;
3334 r = -ENXIO;
3335 if (!kvm->arch.vpit)
3336 goto out;
f0d66275 3337 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3338 if (r)
3339 goto out;
3340 r = -EFAULT;
f0d66275 3341 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3342 goto out;
3343 r = 0;
3344 break;
3345 }
3346 case KVM_SET_PIT: {
e0f63cb9 3347 r = -EFAULT;
f0d66275 3348 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3349 goto out;
3350 r = -ENXIO;
3351 if (!kvm->arch.vpit)
3352 goto out;
f0d66275 3353 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3354 if (r)
3355 goto out;
3356 r = 0;
3357 break;
3358 }
e9f42757
BK		 3359 case KVM_GET_PIT2: {
3360 r = -ENXIO;
3361 if (!kvm->arch.vpit)
3362 goto out;
3363 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3364 if (r)
3365 goto out;
3366 r = -EFAULT;
3367 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3368 goto out;
3369 r = 0;
3370 break;
3371 }
3372 case KVM_SET_PIT2: {
3373 r = -EFAULT;
3374 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3375 goto out;
3376 r = -ENXIO;
3377 if (!kvm->arch.vpit)
3378 goto out;
3379 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3380 if (r)
3381 goto out;
3382 r = 0;
3383 break;
3384 }
52d939a0
MT		 3385 case KVM_REINJECT_CONTROL: {
3386 struct kvm_reinject_control control;
3387 r = -EFAULT;
3388 if (copy_from_user(&control, argp, sizeof(control)))
3389 goto out;
3390 r = kvm_vm_ioctl_reinject(kvm, &control);
3391 if (r)
3392 goto out;
3393 r = 0;
3394 break;
3395 }
ffde22ac
ES		 3396 case KVM_XEN_HVM_CONFIG: {
3397 r = -EFAULT;
3398 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3399 sizeof(struct kvm_xen_hvm_config)))
3400 goto out;
3401 r = -EINVAL;
3402 if (kvm->arch.xen_hvm_config.flags)
3403 goto out;
3404 r = 0;
3405 break;
3406 }
afbcf7ab 3407 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3408 struct kvm_clock_data user_ns;
3409 u64 now_ns;
3410 s64 delta;
3411
3412 r = -EFAULT;
3413 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3414 goto out;
3415
3416 r = -EINVAL;
3417 if (user_ns.flags)
3418 goto out;
3419
3420 r = 0;
395c6b0a 3421 local_irq_disable();
759379dd 3422 now_ns = get_kernel_ns();
afbcf7ab 3423 delta = user_ns.clock - now_ns;
395c6b0a 3424 local_irq_enable();
afbcf7ab
GC		 3425 kvm->arch.kvmclock_offset = delta;
3426 break;
3427 }
3428 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3429 struct kvm_clock_data user_ns;
3430 u64 now_ns;
3431
395c6b0a 3432 local_irq_disable();
759379dd 3433 now_ns = get_kernel_ns();
afbcf7ab 3434 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3435 local_irq_enable();
afbcf7ab 3436 user_ns.flags = 0;
97e69aa6 3437 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3438
3439 r = -EFAULT;
3440 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3441 goto out;
3442 r = 0;
3443 break;
3444 }
3445
1fe779f8
CO		 3446 default:
3447 ;
3448 }
3449out:
3450 return r;
3451}
3452
a16b043c 3453static void kvm_init_msr_list(void)
043405e1
CO		 3454{
3455 u32 dummy[2];
3456 unsigned i, j;
3457
e3267cbb
GC		 3458 /* skip the first msrs in the list. KVM-specific */
3459 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3460 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3461 continue;
3462 if (j < i)
3463 msrs_to_save[j] = msrs_to_save[i];
3464 j++;
3465 }
3466 num_msrs_to_save = j;
3467}
3468
bda9020e
MT		 3469static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3470 const void *v)
bbd9b64e 3471{
70252a10
AK		 3472 int handled = 0;
3473 int n;
3474
3475 do {
3476 n = min(len, 8);
3477 if (!(vcpu->arch.apic &&
3478 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3479 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3480 break;
3481 handled += n;
3482 addr += n;
3483 len -= n;
3484 v += n;
3485 } while (len);
bbd9b64e 3486
70252a10 3487 return handled;
bbd9b64e
CO		 3488}
3489
bda9020e 3490static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3491{
70252a10
AK		 3492 int handled = 0;
3493 int n;
3494
3495 do {
3496 n = min(len, 8);
3497 if (!(vcpu->arch.apic &&
3498 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3499 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3500 break;
3501 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3502 handled += n;
3503 addr += n;
3504 len -= n;
3505 v += n;
3506 } while (len);
bbd9b64e 3507
70252a10 3508 return handled;
bbd9b64e
CO		 3509}
3510
2dafc6c2
GN		 3511static void kvm_set_segment(struct kvm_vcpu *vcpu,
3512 struct kvm_segment *var, int seg)
3513{
3514 kvm_x86_ops->set_segment(vcpu, var, seg);
3515}
3516
3517void kvm_get_segment(struct kvm_vcpu *vcpu,
3518 struct kvm_segment *var, int seg)
3519{
3520 kvm_x86_ops->get_segment(vcpu, var, seg);
3521}
3522
e459e322 3523gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3524{
3525 gpa_t t_gpa;
ab9ae313 3526 struct x86_exception exception;
02f59dc9
JR		 3527
3528 BUG_ON(!mmu_is_nested(vcpu));
3529
3530 /* NPT walks are always user-walks */
3531 access |= PFERR_USER_MASK;
ab9ae313 3532 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3533
3534 return t_gpa;
3535}
3536
ab9ae313
AK		 3537gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3538 struct x86_exception *exception)
1871c602
GN		 3539{
3540 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3541 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3542}
3543
ab9ae313
AK		 3544 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3545 struct x86_exception *exception)
1871c602
GN		 3546{
3547 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3548 access |= PFERR_FETCH_MASK;
ab9ae313 3549 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3550}
3551
ab9ae313
AK		 3552gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3553 struct x86_exception *exception)
1871c602
GN		 3554{
3555 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3556 access |= PFERR_WRITE_MASK;
ab9ae313 3557 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3558}
3559
3560/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3561gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3562 struct x86_exception *exception)
1871c602 3563{
ab9ae313 3564 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3565}
3566
3567static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3568 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3569 struct x86_exception *exception)
bbd9b64e
CO		 3570{
3571 void *data = val;
10589a46 3572 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3573
3574 while (bytes) {
14dfe855 3575 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3576 exception);
bbd9b64e 3577 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3578 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3579 int ret;
3580
bcc55cba 3581 if (gpa == UNMAPPED_GVA)
ab9ae313 3582 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3583 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3584 if (ret < 0) {
c3cd7ffa 3585 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3586 goto out;
3587 }
bbd9b64e 3588
77c2002e
IE		 3589 bytes -= toread;
3590 data += toread;
3591 addr += toread;
bbd9b64e 3592 }
10589a46 3593out:
10589a46 3594 return r;
bbd9b64e 3595}
77c2002e 3596
1871c602 3597/* used for instruction fetching */
0f65dd70
AK		 3598static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3599 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3600 struct x86_exception *exception)
1871c602 3601{
0f65dd70 3602 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3603 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3604
1871c602 3605 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3606 access | PFERR_FETCH_MASK,
3607 exception);
1871c602
GN		 3608}
3609
064aea77 3610int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3611 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3612 struct x86_exception *exception)
1871c602 3613{
0f65dd70 3614 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3615 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3616
1871c602 3617 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3618 exception);
1871c602 3619}
064aea77 3620EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3621
0f65dd70
AK		 3622static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3623 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3624 struct x86_exception *exception)
1871c602 3625{
0f65dd70 3626 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3627 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3628}
3629
6a4d7550 3630int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3631 gva_t addr, void *val,
2dafc6c2 3632 unsigned int bytes,
bcc55cba 3633 struct x86_exception *exception)
77c2002e 3634{
0f65dd70 3635 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3636 void *data = val;
3637 int r = X86EMUL_CONTINUE;
3638
3639 while (bytes) {
14dfe855
JR		 3640 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3641 PFERR_WRITE_MASK,
ab9ae313 3642 exception);
77c2002e
IE		 3643 unsigned offset = addr & (PAGE_SIZE-1);
3644 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3645 int ret;
3646
bcc55cba 3647 if (gpa == UNMAPPED_GVA)
ab9ae313 3648 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3649 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3650 if (ret < 0) {
c3cd7ffa 3651 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3652 goto out;
3653 }
3654
3655 bytes -= towrite;
3656 data += towrite;
3657 addr += towrite;
3658 }
3659out:
3660 return r;
3661}
6a4d7550 3662EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3663
af7cc7d1
XG		 3664static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3665 gpa_t *gpa, struct x86_exception *exception,
3666 bool write)
3667{
3668 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3669
bebb106a
XG		 3670 if (vcpu_match_mmio_gva(vcpu, gva) &&
3671 check_write_user_access(vcpu, write, access,
3672 vcpu->arch.access)) {
3673 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3674 (gva & (PAGE_SIZE - 1));
4f022648 3675 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 3676 return 1;
3677 }
3678
af7cc7d1
XG		 3679 if (write)
3680 access |= PFERR_WRITE_MASK;
3681
3682 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3683
3684 if (*gpa == UNMAPPED_GVA)
3685 return -1;
3686
3687 /* For APIC access vmexit */
3688 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3689 return 1;
3690
4f022648
XG		 3691 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3692 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 3693 return 1;
4f022648 3694 }
bebb106a 3695
af7cc7d1
XG		 3696 return 0;
3697}
3698
3200f405 3699int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3700 const void *val, int bytes)
bbd9b64e
CO		 3701{
3702 int ret;
3703
3704 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3705 if (ret < 0)
bbd9b64e 3706 return 0;
f57f2ef5 3707 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 3708 return 1;
3709}
3710
77d197b2
XG		 3711struct read_write_emulator_ops {
3712 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3713 int bytes);
3714 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3715 void *val, int bytes);
3716 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3717 int bytes, void *val);
3718 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3719 void *val, int bytes);
3720 bool write;
3721};
3722
3723static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3724{
3725 if (vcpu->mmio_read_completed) {
77d197b2 3726 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 3727 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 3728 vcpu->mmio_read_completed = 0;
3729 return 1;
3730 }
3731
3732 return 0;
3733}
3734
3735static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3736 void *val, int bytes)
3737{
3738 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3739}
3740
3741static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3742 void *val, int bytes)
3743{
3744 return emulator_write_phys(vcpu, gpa, val, bytes);
3745}
3746
3747static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3748{
3749 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3750 return vcpu_mmio_write(vcpu, gpa, bytes, val);
3751}
3752
3753static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3754 void *val, int bytes)
3755{
3756 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3757 return X86EMUL_IO_NEEDED;
3758}
3759
3760static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3761 void *val, int bytes)
3762{
f78146b0
AK		 3763 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
3764
3765 memcpy(vcpu->run->mmio.data, frag->data, frag->len);
77d197b2
XG		 3766 return X86EMUL_CONTINUE;
3767}
3768
3769static struct read_write_emulator_ops read_emultor = {
3770 .read_write_prepare = read_prepare,
3771 .read_write_emulate = read_emulate,
3772 .read_write_mmio = vcpu_mmio_read,
3773 .read_write_exit_mmio = read_exit_mmio,
3774};
3775
3776static struct read_write_emulator_ops write_emultor = {
3777 .read_write_emulate = write_emulate,
3778 .read_write_mmio = write_mmio,
3779 .read_write_exit_mmio = write_exit_mmio,
3780 .write = true,
3781};
3782
22388a3c
XG		 3783static int emulator_read_write_onepage(unsigned long addr, void *val,
3784 unsigned int bytes,
3785 struct x86_exception *exception,
3786 struct kvm_vcpu *vcpu,
3787 struct read_write_emulator_ops *ops)
bbd9b64e 3788{
af7cc7d1
XG		 3789 gpa_t gpa;
3790 int handled, ret;
22388a3c 3791 bool write = ops->write;
f78146b0 3792 struct kvm_mmio_fragment *frag;
10589a46 3793
22388a3c 3794 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 3795
af7cc7d1 3796 if (ret < 0)
bbd9b64e 3797 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3798
3799 /* For APIC access vmexit */
af7cc7d1 3800 if (ret)
bbd9b64e
CO		 3801 goto mmio;
3802
22388a3c 3803 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 3804 return X86EMUL_CONTINUE;
3805
3806mmio:
3807 /*
3808 * Is this MMIO handled locally?
3809 */
22388a3c 3810 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 3811 if (handled == bytes)
bbd9b64e 3812 return X86EMUL_CONTINUE;
bbd9b64e 3813
70252a10
AK		 3814 gpa += handled;
3815 bytes -= handled;
3816 val += handled;
3817
f78146b0
AK		 3818 while (bytes) {
3819 unsigned now = min(bytes, 8U);
bbd9b64e 3820
f78146b0
AK		 3821 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
3822 frag->gpa = gpa;
3823 frag->data = val;
3824 frag->len = now;
3825
3826 gpa += now;
3827 val += now;
3828 bytes -= now;
3829 }
3830 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3831}
3832
22388a3c
XG		 3833int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3834 void *val, unsigned int bytes,
3835 struct x86_exception *exception,
3836 struct read_write_emulator_ops *ops)
bbd9b64e 3837{
0f65dd70 3838 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 3839 gpa_t gpa;
3840 int rc;
3841
3842 if (ops->read_write_prepare &&
3843 ops->read_write_prepare(vcpu, val, bytes))
3844 return X86EMUL_CONTINUE;
3845
3846 vcpu->mmio_nr_fragments = 0;
0f65dd70 3847
bbd9b64e
CO		 3848 /* Crossing a page boundary? */
3849 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 3850 int now;
bbd9b64e
CO		 3851
3852 now = -addr & ~PAGE_MASK;
22388a3c
XG		 3853 rc = emulator_read_write_onepage(addr, val, now, exception,
3854 vcpu, ops);
3855
bbd9b64e
CO		 3856 if (rc != X86EMUL_CONTINUE)
3857 return rc;
3858 addr += now;
3859 val += now;
3860 bytes -= now;
3861 }
22388a3c 3862
f78146b0
AK		 3863 rc = emulator_read_write_onepage(addr, val, bytes, exception,
3864 vcpu, ops);
3865 if (rc != X86EMUL_CONTINUE)
3866 return rc;
3867
3868 if (!vcpu->mmio_nr_fragments)
3869 return rc;
3870
3871 gpa = vcpu->mmio_fragments[0].gpa;
3872
3873 vcpu->mmio_needed = 1;
3874 vcpu->mmio_cur_fragment = 0;
3875
3876 vcpu->run->mmio.len = vcpu->mmio_fragments[0].len;
3877 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
3878 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3879 vcpu->run->mmio.phys_addr = gpa;
3880
3881 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 3882}
3883
3884static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3885 unsigned long addr,
3886 void *val,
3887 unsigned int bytes,
3888 struct x86_exception *exception)
3889{
3890 return emulator_read_write(ctxt, addr, val, bytes,
3891 exception, &read_emultor);
3892}
3893
3894int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3895 unsigned long addr,
3896 const void *val,
3897 unsigned int bytes,
3898 struct x86_exception *exception)
3899{
3900 return emulator_read_write(ctxt, addr, (void *)val, bytes,
3901 exception, &write_emultor);
bbd9b64e 3902}
bbd9b64e 3903
daea3e73
AK		 3904#define CMPXCHG_TYPE(t, ptr, old, new) \
3905 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3906
3907#ifdef CONFIG_X86_64
3908# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3909#else
3910# define CMPXCHG64(ptr, old, new) \
9749a6c0 3911 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3912#endif
3913
0f65dd70
AK		 3914static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3915 unsigned long addr,
bbd9b64e
CO		 3916 const void *old,
3917 const void *new,
3918 unsigned int bytes,
0f65dd70 3919 struct x86_exception *exception)
bbd9b64e 3920{
0f65dd70 3921 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 3922 gpa_t gpa;
3923 struct page *page;
3924 char *kaddr;
3925 bool exchanged;
2bacc55c 3926
daea3e73
AK		 3927 /* guests cmpxchg8b have to be emulated atomically */
3928 if (bytes > 8 || (bytes & (bytes - 1)))
3929 goto emul_write;
10589a46 3930
daea3e73 3931 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3932
daea3e73
AK		 3933 if (gpa == UNMAPPED_GVA ||
3934 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3935 goto emul_write;
2bacc55c 3936
daea3e73
AK		 3937 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3938 goto emul_write;
72dc67a6 3939
daea3e73 3940 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 3941 if (is_error_page(page))
c19b8bd6 3942 goto emul_write;
72dc67a6 3943
8fd75e12 3944 kaddr = kmap_atomic(page);
daea3e73
AK		 3945 kaddr += offset_in_page(gpa);
3946 switch (bytes) {
3947 case 1:
3948 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3949 break;
3950 case 2:
3951 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3952 break;
3953 case 4:
3954 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3955 break;
3956 case 8:
3957 exchanged = CMPXCHG64(kaddr, old, new);
3958 break;
3959 default:
3960 BUG();
2bacc55c 3961 }
8fd75e12 3962 kunmap_atomic(kaddr);
daea3e73
AK		 3963 kvm_release_page_dirty(page);
3964
3965 if (!exchanged)
3966 return X86EMUL_CMPXCHG_FAILED;
3967
f57f2ef5 3968 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 3969
3970 return X86EMUL_CONTINUE;
4a5f48f6 3971
3200f405 3972emul_write:
daea3e73 3973 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3974
0f65dd70 3975 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 3976}
3977
cf8f70bf
GN		 3978static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3979{
3980 /* TODO: String I/O for in kernel device */
3981 int r;
3982
3983 if (vcpu->arch.pio.in)
3984 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3985 vcpu->arch.pio.size, pd);
3986 else
3987 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3988 vcpu->arch.pio.port, vcpu->arch.pio.size,
3989 pd);
3990 return r;
3991}
3992
6f6fbe98
XG		 3993static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
3994 unsigned short port, void *val,
3995 unsigned int count, bool in)
cf8f70bf 3996{
6f6fbe98 3997 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 3998
3999 vcpu->arch.pio.port = port;
6f6fbe98 4000 vcpu->arch.pio.in = in;
7972995b 4001 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4002 vcpu->arch.pio.size = size;
4003
4004 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4005 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4006 return 1;
4007 }
4008
4009 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4010 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4011 vcpu->run->io.size = size;
4012 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4013 vcpu->run->io.count = count;
4014 vcpu->run->io.port = port;
4015
4016 return 0;
4017}
4018
6f6fbe98
XG		 4019static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4020 int size, unsigned short port, void *val,
4021 unsigned int count)
cf8f70bf 4022{
ca1d4a9e 4023 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4024 int ret;
ca1d4a9e 4025
6f6fbe98
XG		 4026 if (vcpu->arch.pio.count)
4027 goto data_avail;
cf8f70bf 4028
6f6fbe98
XG		 4029 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4030 if (ret) {
4031data_avail:
4032 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4033 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4034 return 1;
4035 }
4036
cf8f70bf
GN		 4037 return 0;
4038}
4039
6f6fbe98
XG		 4040static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4041 int size, unsigned short port,
4042 const void *val, unsigned int count)
4043{
4044 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4045
4046 memcpy(vcpu->arch.pio_data, val, size * count);
4047 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4048}
4049
bbd9b64e
CO		 4050static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4051{
4052 return kvm_x86_ops->get_segment_base(vcpu, seg);
4053}
4054
3cb16fe7 4055static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4056{
3cb16fe7 4057 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4058}
4059
f5f48ee1
SY		 4060int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4061{
4062 if (!need_emulate_wbinvd(vcpu))
4063 return X86EMUL_CONTINUE;
4064
4065 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4066 int cpu = get_cpu();
4067
4068 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4069 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4070 wbinvd_ipi, NULL, 1);
2eec7343 4071 put_cpu();
f5f48ee1 4072 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4073 } else
4074 wbinvd();
f5f48ee1
SY		 4075 return X86EMUL_CONTINUE;
4076}
4077EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4078
bcaf5cc5
AK		 4079static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4080{
4081 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4082}
4083
717746e3 4084int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4085{
717746e3 4086 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4087}
4088
717746e3 4089int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4090{
338dbc97 4091
717746e3 4092 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4093}
4094
52a46617 4095static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4096{
52a46617 4097 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4098}
4099
717746e3 4100static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4101{
717746e3 4102 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4103 unsigned long value;
4104
4105 switch (cr) {
4106 case 0:
4107 value = kvm_read_cr0(vcpu);
4108 break;
4109 case 2:
4110 value = vcpu->arch.cr2;
4111 break;
4112 case 3:
9f8fe504 4113 value = kvm_read_cr3(vcpu);
52a46617
GN		 4114 break;
4115 case 4:
4116 value = kvm_read_cr4(vcpu);
4117 break;
4118 case 8:
4119 value = kvm_get_cr8(vcpu);
4120 break;
4121 default:
a737f256 4122 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4123 return 0;
4124 }
4125
4126 return value;
4127}
4128
717746e3 4129static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4130{
717746e3 4131 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4132 int res = 0;
4133
52a46617
GN		 4134 switch (cr) {
4135 case 0:
49a9b07e 4136 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4137 break;
4138 case 2:
4139 vcpu->arch.cr2 = val;
4140 break;
4141 case 3:
2390218b 4142 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4143 break;
4144 case 4:
a83b29c6 4145 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4146 break;
4147 case 8:
eea1cff9 4148 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4149 break;
4150 default:
a737f256 4151 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4152 res = -1;
52a46617 4153 }
0f12244f
GN		 4154
4155 return res;
52a46617
GN		 4156}
4157
4cee4798
KW		 4158static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4159{
4160 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4161}
4162
717746e3 4163static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4164{
717746e3 4165 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4166}
4167
4bff1e86 4168static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4169{
4bff1e86 4170 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4171}
4172
4bff1e86 4173static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4174{
4bff1e86 4175 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4176}
4177
1ac9d0cf
AK		 4178static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4179{
4180 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4181}
4182
4183static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4184{
4185 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4186}
4187
4bff1e86
AK		 4188static unsigned long emulator_get_cached_segment_base(
4189 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4190{
4bff1e86 4191 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4192}
4193
1aa36616
AK		 4194static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4195 struct desc_struct *desc, u32 *base3,
4196 int seg)
2dafc6c2
GN		 4197{
4198 struct kvm_segment var;
4199
4bff1e86 4200 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4201 *selector = var.selector;
2dafc6c2
GN		 4202
4203 if (var.unusable)
4204 return false;
4205
4206 if (var.g)
4207 var.limit >>= 12;
4208 set_desc_limit(desc, var.limit);
4209 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4210#ifdef CONFIG_X86_64
4211 if (base3)
4212 *base3 = var.base >> 32;
4213#endif
2dafc6c2
GN		 4214 desc->type = var.type;
4215 desc->s = var.s;
4216 desc->dpl = var.dpl;
4217 desc->p = var.present;
4218 desc->avl = var.avl;
4219 desc->l = var.l;
4220 desc->d = var.db;
4221 desc->g = var.g;
4222
4223 return true;
4224}
4225
1aa36616
AK		 4226static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4227 struct desc_struct *desc, u32 base3,
4228 int seg)
2dafc6c2 4229{
4bff1e86 4230 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4231 struct kvm_segment var;
4232
1aa36616 4233 var.selector = selector;
2dafc6c2 4234 var.base = get_desc_base(desc);
5601d05b
GN		 4235#ifdef CONFIG_X86_64
4236 var.base |= ((u64)base3) << 32;
4237#endif
2dafc6c2
GN		 4238 var.limit = get_desc_limit(desc);
4239 if (desc->g)
4240 var.limit = (var.limit << 12) | 0xfff;
4241 var.type = desc->type;
4242 var.present = desc->p;
4243 var.dpl = desc->dpl;
4244 var.db = desc->d;
4245 var.s = desc->s;
4246 var.l = desc->l;
4247 var.g = desc->g;
4248 var.avl = desc->avl;
4249 var.present = desc->p;
4250 var.unusable = !var.present;
4251 var.padding = 0;
4252
4253 kvm_set_segment(vcpu, &var, seg);
4254 return;
4255}
4256
717746e3
AK		 4257static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4258 u32 msr_index, u64 *pdata)
4259{
4260 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4261}
4262
4263static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4264 u32 msr_index, u64 data)
4265{
4266 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4267}
4268
222d21aa
AK		 4269static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4270 u32 pmc, u64 *pdata)
4271{
4272 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4273}
4274
6c3287f7
AK		 4275static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4276{
4277 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4278}
4279
5037f6f3
AK		 4280static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4281{
4282 preempt_disable();
5197b808 4283 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4284 /*
4285 * CR0.TS may reference the host fpu state, not the guest fpu state,
4286 * so it may be clear at this point.
4287 */
4288 clts();
4289}
4290
4291static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4292{
4293 preempt_enable();
4294}
4295
2953538e 4296static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4297 struct x86_instruction_info *info,
c4f035c6
AK		 4298 enum x86_intercept_stage stage)
4299{
2953538e 4300 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4301}
4302
0017f93a 4303static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4304 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4305{
0017f93a 4306 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4307}
4308
14af3f3c 4309static struct x86_emulate_ops emulate_ops = {
1871c602 4310 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4311 .write_std = kvm_write_guest_virt_system,
1871c602 4312 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4313 .read_emulated = emulator_read_emulated,
4314 .write_emulated = emulator_write_emulated,
4315 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4316 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4317 .pio_in_emulated = emulator_pio_in_emulated,
4318 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4319 .get_segment = emulator_get_segment,
4320 .set_segment = emulator_set_segment,
5951c442 4321 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4322 .get_gdt = emulator_get_gdt,
160ce1f1 4323 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4324 .set_gdt = emulator_set_gdt,
4325 .set_idt = emulator_set_idt,
52a46617
GN		 4326 .get_cr = emulator_get_cr,
4327 .set_cr = emulator_set_cr,
4cee4798 4328 .set_rflags = emulator_set_rflags,
9c537244 4329 .cpl = emulator_get_cpl,
35aa5375
GN		 4330 .get_dr = emulator_get_dr,
4331 .set_dr = emulator_set_dr,
717746e3
AK		 4332 .set_msr = emulator_set_msr,
4333 .get_msr = emulator_get_msr,
222d21aa 4334 .read_pmc = emulator_read_pmc,
6c3287f7 4335 .halt = emulator_halt,
bcaf5cc5 4336 .wbinvd = emulator_wbinvd,
d6aa1000 4337 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4338 .get_fpu = emulator_get_fpu,
4339 .put_fpu = emulator_put_fpu,
c4f035c6 4340 .intercept = emulator_intercept,
bdb42f5a 4341 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4342};
4343
5fdbf976
MT		 4344static void cache_all_regs(struct kvm_vcpu *vcpu)
4345{
4346 kvm_register_read(vcpu, VCPU_REGS_RAX);
4347 kvm_register_read(vcpu, VCPU_REGS_RSP);
4348 kvm_register_read(vcpu, VCPU_REGS_RIP);
4349 vcpu->arch.regs_dirty = ~0;
4350}
4351
95cb2295
GN		 4352static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4353{
4354 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4355 /*
4356 * an sti; sti; sequence only disable interrupts for the first
4357 * instruction. So, if the last instruction, be it emulated or
4358 * not, left the system with the INT_STI flag enabled, it
4359 * means that the last instruction is an sti. We should not
4360 * leave the flag on in this case. The same goes for mov ss
4361 */
4362 if (!(int_shadow & mask))
4363 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4364}
4365
54b8486f
GN		 4366static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4367{
4368 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4369 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4370 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4371 else if (ctxt->exception.error_code_valid)
4372 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4373 ctxt->exception.error_code);
54b8486f 4374 else
da9cb575 4375 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4376}
4377
9dac77fa 4378static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
b5c9ff73
TY		 4379 const unsigned long *regs)
4380{
9dac77fa
AK		 4381 memset(&ctxt->twobyte, 0,
4382 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4383 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
b5c9ff73 4384
9dac77fa
AK		 4385 ctxt->fetch.start = 0;
4386 ctxt->fetch.end = 0;
4387 ctxt->io_read.pos = 0;
4388 ctxt->io_read.end = 0;
4389 ctxt->mem_read.pos = 0;
4390 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4391}
4392
8ec4722d
MG		 4393static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4394{
adf52235 4395 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4396 int cs_db, cs_l;
4397
2aab2c5b
GN		 4398 /*
4399 * TODO: fix emulate.c to use guest_read/write_register
4400 * instead of direct ->regs accesses, can save hundred cycles
4401 * on Intel for instructions that don't read/change RSP, for
4402 * for example.
4403 */
8ec4722d
MG		 4404 cache_all_regs(vcpu);
4405
4406 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4407
adf52235
TY		 4408 ctxt->eflags = kvm_get_rflags(vcpu);
4409 ctxt->eip = kvm_rip_read(vcpu);
4410 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4411 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4412 cs_l ? X86EMUL_MODE_PROT64 :
4413 cs_db ? X86EMUL_MODE_PROT32 :
4414 X86EMUL_MODE_PROT16;
4415 ctxt->guest_mode = is_guest_mode(vcpu);
4416
9dac77fa 4417 init_decode_cache(ctxt, vcpu->arch.regs);
7ae441ea 4418 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4419}
4420
71f9833b 4421int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4422{
9d74191a 4423 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4424 int ret;
4425
4426 init_emulate_ctxt(vcpu);
4427
9dac77fa
AK		 4428 ctxt->op_bytes = 2;
4429 ctxt->ad_bytes = 2;
4430 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4431 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4432
4433 if (ret != X86EMUL_CONTINUE)
4434 return EMULATE_FAIL;
4435
9dac77fa
AK		 4436 ctxt->eip = ctxt->_eip;
4437 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 4438 kvm_rip_write(vcpu, ctxt->eip);
4439 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4440
4441 if (irq == NMI_VECTOR)
7460fb4a 4442 vcpu->arch.nmi_pending = 0;
63995653
MG		 4443 else
4444 vcpu->arch.interrupt.pending = false;
4445
4446 return EMULATE_DONE;
4447}
4448EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4449
6d77dbfc
GN		 4450static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4451{
fc3a9157
JR		 4452 int r = EMULATE_DONE;
4453
6d77dbfc
GN		 4454 ++vcpu->stat.insn_emulation_fail;
4455 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4456 if (!is_guest_mode(vcpu)) {
4457 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4458 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4459 vcpu->run->internal.ndata = 0;
4460 r = EMULATE_FAIL;
4461 }
6d77dbfc 4462 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4463
4464 return r;
6d77dbfc
GN		 4465}
4466
a6f177ef
GN		 4467static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4468{
4469 gpa_t gpa;
4470
68be0803
GN		 4471 if (tdp_enabled)
4472 return false;
4473
a6f177ef
GN		 4474 /*
4475 * if emulation was due to access to shadowed page table
4a969980 4476 * and it failed try to unshadow page and re-enter the
a6f177ef
GN		 4477 * guest to let CPU execute the instruction.
4478 */
4479 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4480 return true;
4481
4482 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4483
4484 if (gpa == UNMAPPED_GVA)
4485 return true; /* let cpu generate fault */
4486
4487 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4488 return true;
4489
4490 return false;
4491}
4492
1cb3f3ae
XG		 4493static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4494 unsigned long cr2, int emulation_type)
4495{
4496 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4497 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4498
4499 last_retry_eip = vcpu->arch.last_retry_eip;
4500 last_retry_addr = vcpu->arch.last_retry_addr;
4501
4502 /*
4503 * If the emulation is caused by #PF and it is non-page_table
4504 * writing instruction, it means the VM-EXIT is caused by shadow
4505 * page protected, we can zap the shadow page and retry this
4506 * instruction directly.
4507 *
4508 * Note: if the guest uses a non-page-table modifying instruction
4509 * on the PDE that points to the instruction, then we will unmap
4510 * the instruction and go to an infinite loop. So, we cache the
4511 * last retried eip and the last fault address, if we meet the eip
4512 * and the address again, we can break out of the potential infinite
4513 * loop.
4514 */
4515 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4516
4517 if (!(emulation_type & EMULTYPE_RETRY))
4518 return false;
4519
4520 if (x86_page_table_writing_insn(ctxt))
4521 return false;
4522
4523 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4524 return false;
4525
4526 vcpu->arch.last_retry_eip = ctxt->eip;
4527 vcpu->arch.last_retry_addr = cr2;
4528
4529 if (!vcpu->arch.mmu.direct_map)
4530 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4531
4532 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4533
4534 return true;
4535}
4536
51d8b661
AP		 4537int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4538 unsigned long cr2,
dc25e89e
AP		 4539 int emulation_type,
4540 void *insn,
4541 int insn_len)
bbd9b64e 4542{
95cb2295 4543 int r;
9d74191a 4544 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4545 bool writeback = true;
bbd9b64e 4546
26eef70c 4547 kvm_clear_exception_queue(vcpu);
8d7d8102 4548
571008da 4549 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4550 init_emulate_ctxt(vcpu);
9d74191a
TY		 4551 ctxt->interruptibility = 0;
4552 ctxt->have_exception = false;
4553 ctxt->perm_ok = false;
bbd9b64e 4554
9d74191a 4555 ctxt->only_vendor_specific_insn
4005996e
AK		 4556 = emulation_type & EMULTYPE_TRAP_UD;
4557
9d74191a 4558 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4559
e46479f8 4560 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4561 ++vcpu->stat.insn_emulation;
1d2887e2 4562 if (r != EMULATION_OK) {
4005996e
AK		 4563 if (emulation_type & EMULTYPE_TRAP_UD)
4564 return EMULATE_FAIL;
a6f177ef 4565 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4566 return EMULATE_DONE;
6d77dbfc
GN		 4567 if (emulation_type & EMULTYPE_SKIP)
4568 return EMULATE_FAIL;
4569 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4570 }
4571 }
4572
ba8afb6b 4573 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4574 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4575 return EMULATE_DONE;
4576 }
4577
1cb3f3ae
XG		 4578 if (retry_instruction(ctxt, cr2, emulation_type))
4579 return EMULATE_DONE;
4580
7ae441ea 4581 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4582 changes registers values during IO operation */
7ae441ea
GN		 4583 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4584 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
9dac77fa 4585 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
7ae441ea 4586 }
4d2179e1 4587
5cd21917 4588restart:
9d74191a 4589 r = x86_emulate_insn(ctxt);
bbd9b64e 4590
775fde86
JR		 4591 if (r == EMULATION_INTERCEPTED)
4592 return EMULATE_DONE;
4593
d2ddd1c4 4594 if (r == EMULATION_FAILED) {
a6f177ef 4595 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4596 return EMULATE_DONE;
4597
6d77dbfc 4598 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4599 }
4600
9d74191a 4601 if (ctxt->have_exception) {
54b8486f 4602 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4603 r = EMULATE_DONE;
4604 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4605 if (!vcpu->arch.pio.in)
4606 vcpu->arch.pio.count = 0;
7ae441ea
GN		 4607 else
4608 writeback = false;
e85d28f8 4609 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4610 } else if (vcpu->mmio_needed) {
4611 if (!vcpu->mmio_is_write)
4612 writeback = false;
e85d28f8 4613 r = EMULATE_DO_MMIO;
7ae441ea 4614 } else if (r == EMULATION_RESTART)
5cd21917 4615 goto restart;
d2ddd1c4
GN		 4616 else
4617 r = EMULATE_DONE;
f850e2e6 4618
7ae441ea 4619 if (writeback) {
9d74191a
TY		 4620 toggle_interruptibility(vcpu, ctxt->interruptibility);
4621 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4622 kvm_make_request(KVM_REQ_EVENT, vcpu);
9dac77fa 4623 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea 4624 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4625 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4626 } else
4627 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4628
4629 return r;
de7d789a 4630}
51d8b661 4631EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4632
cf8f70bf 4633int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4634{
cf8f70bf 4635 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4636 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4637 size, port, &val, 1);
cf8f70bf 4638 /* do not return to emulator after return from userspace */
7972995b 4639 vcpu->arch.pio.count = 0;
de7d789a
CO		 4640 return ret;
4641}
cf8f70bf 4642EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4643
8cfdc000
ZA		 4644static void tsc_bad(void *info)
4645{
0a3aee0d 4646 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4647}
4648
4649static void tsc_khz_changed(void *data)
c8076604 4650{
8cfdc000
ZA		 4651 struct cpufreq_freqs *freq = data;
4652 unsigned long khz = 0;
4653
4654 if (data)
4655 khz = freq->new;
4656 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4657 khz = cpufreq_quick_get(raw_smp_processor_id());
4658 if (!khz)
4659 khz = tsc_khz;
0a3aee0d 4660 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4661}
4662
c8076604
GH		 4663static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4664 void *data)
4665{
4666 struct cpufreq_freqs *freq = data;
4667 struct kvm *kvm;
4668 struct kvm_vcpu *vcpu;
4669 int i, send_ipi = 0;
4670
8cfdc000
ZA		 4671 /*
4672 * We allow guests to temporarily run on slowing clocks,
4673 * provided we notify them after, or to run on accelerating
4674 * clocks, provided we notify them before. Thus time never
4675 * goes backwards.
4676 *
4677 * However, we have a problem. We can't atomically update
4678 * the frequency of a given CPU from this function; it is
4679 * merely a notifier, which can be called from any CPU.
4680 * Changing the TSC frequency at arbitrary points in time
4681 * requires a recomputation of local variables related to
4682 * the TSC for each VCPU. We must flag these local variables
4683 * to be updated and be sure the update takes place with the
4684 * new frequency before any guests proceed.
4685 *
4686 * Unfortunately, the combination of hotplug CPU and frequency
4687 * change creates an intractable locking scenario; the order
4688 * of when these callouts happen is undefined with respect to
4689 * CPU hotplug, and they can race with each other. As such,
4690 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4691 * undefined; you can actually have a CPU frequency change take
4692 * place in between the computation of X and the setting of the
4693 * variable. To protect against this problem, all updates of
4694 * the per_cpu tsc_khz variable are done in an interrupt
4695 * protected IPI, and all callers wishing to update the value
4696 * must wait for a synchronous IPI to complete (which is trivial
4697 * if the caller is on the CPU already). This establishes the
4698 * necessary total order on variable updates.
4699 *
4700 * Note that because a guest time update may take place
4701 * anytime after the setting of the VCPU's request bit, the
4702 * correct TSC value must be set before the request. However,
4703 * to ensure the update actually makes it to any guest which
4704 * starts running in hardware virtualization between the set
4705 * and the acquisition of the spinlock, we must also ping the
4706 * CPU after setting the request bit.
4707 *
4708 */
4709
c8076604
GH		 4710 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4711 return 0;
4712 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4713 return 0;
8cfdc000
ZA		 4714
4715 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4716
e935b837 4717 raw_spin_lock(&kvm_lock);
c8076604 4718 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4719 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4720 if (vcpu->cpu != freq->cpu)
4721 continue;
c285545f 4722 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4723 if (vcpu->cpu != smp_processor_id())
8cfdc000 4724 send_ipi = 1;
c8076604
GH		 4725 }
4726 }
e935b837 4727 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4728
4729 if (freq->old < freq->new && send_ipi) {
4730 /*
4731 * We upscale the frequency. Must make the guest
4732 * doesn't see old kvmclock values while running with
4733 * the new frequency, otherwise we risk the guest sees
4734 * time go backwards.
4735 *
4736 * In case we update the frequency for another cpu
4737 * (which might be in guest context) send an interrupt
4738 * to kick the cpu out of guest context. Next time
4739 * guest context is entered kvmclock will be updated,
4740 * so the guest will not see stale values.
4741 */
8cfdc000 4742 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4743 }
4744 return 0;
4745}
4746
4747static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4748 .notifier_call = kvmclock_cpufreq_notifier
4749};
4750
4751static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4752 unsigned long action, void *hcpu)
4753{
4754 unsigned int cpu = (unsigned long)hcpu;
4755
4756 switch (action) {
4757 case CPU_ONLINE:
4758 case CPU_DOWN_FAILED:
4759 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4760 break;
4761 case CPU_DOWN_PREPARE:
4762 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4763 break;
4764 }
4765 return NOTIFY_OK;
4766}
4767
4768static struct notifier_block kvmclock_cpu_notifier_block = {
4769 .notifier_call = kvmclock_cpu_notifier,
4770 .priority = -INT_MAX
c8076604
GH		 4771};
4772
b820cc0c
ZA		 4773static void kvm_timer_init(void)
4774{
4775 int cpu;
4776
c285545f 4777 max_tsc_khz = tsc_khz;
8cfdc000 4778 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4779 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4780#ifdef CONFIG_CPU_FREQ
4781 struct cpufreq_policy policy;
4782 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4783 cpu = get_cpu();
4784 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4785 if (policy.cpuinfo.max_freq)
4786 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4787 put_cpu();
c285545f 4788#endif
b820cc0c
ZA		 4789 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4790 CPUFREQ_TRANSITION_NOTIFIER);
4791 }
c285545f 4792 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4793 for_each_online_cpu(cpu)
4794 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4795}
4796
ff9d07a0
ZY		 4797static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4798
f5132b01 4799int kvm_is_in_guest(void)
ff9d07a0 4800{
086c9855 4801 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 4802}
4803
4804static int kvm_is_user_mode(void)
4805{
4806 int user_mode = 3;
dcf46b94 4807
086c9855
AS		 4808 if (__this_cpu_read(current_vcpu))
4809 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 4810
ff9d07a0
ZY		 4811 return user_mode != 0;
4812}
4813
4814static unsigned long kvm_get_guest_ip(void)
4815{
4816 unsigned long ip = 0;
dcf46b94 4817
086c9855
AS		 4818 if (__this_cpu_read(current_vcpu))
4819 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 4820
ff9d07a0
ZY		 4821 return ip;
4822}
4823
4824static struct perf_guest_info_callbacks kvm_guest_cbs = {
4825 .is_in_guest = kvm_is_in_guest,
4826 .is_user_mode = kvm_is_user_mode,
4827 .get_guest_ip = kvm_get_guest_ip,
4828};
4829
4830void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4831{
086c9855 4832 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 4833}
4834EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4835
4836void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4837{
086c9855 4838 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 4839}
4840EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4841
ce88decf
XG		 4842static void kvm_set_mmio_spte_mask(void)
4843{
4844 u64 mask;
4845 int maxphyaddr = boot_cpu_data.x86_phys_bits;
4846
4847 /*
4848 * Set the reserved bits and the present bit of an paging-structure
4849 * entry to generate page fault with PFER.RSV = 1.
4850 */
4851 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4852 mask |= 1ull;
4853
4854#ifdef CONFIG_X86_64
4855 /*
4856 * If reserved bit is not supported, clear the present bit to disable
4857 * mmio page fault.
4858 */
4859 if (maxphyaddr == 52)
4860 mask &= ~1ull;
4861#endif
4862
4863 kvm_mmu_set_mmio_spte_mask(mask);
4864}
4865
f8c16bba 4866int kvm_arch_init(void *opaque)
043405e1 4867{
b820cc0c 4868 int r;
f8c16bba
ZX		 4869 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4870
f8c16bba
ZX		 4871 if (kvm_x86_ops) {
4872 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4873 r = -EEXIST;
4874 goto out;
f8c16bba
ZX		 4875 }
4876
4877 if (!ops->cpu_has_kvm_support()) {
4878 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4879 r = -EOPNOTSUPP;
4880 goto out;
f8c16bba
ZX		 4881 }
4882 if (ops->disabled_by_bios()) {
4883 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4884 r = -EOPNOTSUPP;
4885 goto out;
f8c16bba
ZX		 4886 }
4887
97db56ce
AK		 4888 r = kvm_mmu_module_init();
4889 if (r)
4890 goto out;
4891
ce88decf 4892 kvm_set_mmio_spte_mask();
97db56ce
AK		 4893 kvm_init_msr_list();
4894
f8c16bba 4895 kvm_x86_ops = ops;
7b52345e 4896 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4897 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4898
b820cc0c 4899 kvm_timer_init();
c8076604 4900
ff9d07a0
ZY		 4901 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4902
2acf923e
DC		 4903 if (cpu_has_xsave)
4904 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4905
c5cc421b 4906 kvm_lapic_init();
f8c16bba 4907 return 0;
56c6d28a
ZX		 4908
4909out:
56c6d28a 4910 return r;
043405e1 4911}
8776e519 4912
f8c16bba
ZX		 4913void kvm_arch_exit(void)
4914{
ff9d07a0
ZY		 4915 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4916
888d256e
JK		 4917 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4918 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4919 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4920 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4921 kvm_x86_ops = NULL;
56c6d28a
ZX		 4922 kvm_mmu_module_exit();
4923}
f8c16bba 4924
8776e519
HB		 4925int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4926{
4927 ++vcpu->stat.halt_exits;
4928 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4929 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4930 return 1;
4931 } else {
4932 vcpu->run->exit_reason = KVM_EXIT_HLT;
4933 return 0;
4934 }
4935}
4936EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4937
55cd8e5a
GN		 4938int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4939{
4940 u64 param, ingpa, outgpa, ret;
4941 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4942 bool fast, longmode;
4943 int cs_db, cs_l;
4944
4945 /*
4946 * hypercall generates UD from non zero cpl and real mode
4947 * per HYPER-V spec
4948 */
3eeb3288 4949 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4950 kvm_queue_exception(vcpu, UD_VECTOR);
4951 return 0;
4952 }
4953
4954 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4955 longmode = is_long_mode(vcpu) && cs_l == 1;
4956
4957 if (!longmode) {
ccd46936
GN		 4958 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4959 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4960 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4961 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4962 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4963 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4964 }
4965#ifdef CONFIG_X86_64
4966 else {
4967 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4968 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4969 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4970 }
4971#endif
4972
4973 code = param & 0xffff;
4974 fast = (param >> 16) & 0x1;
4975 rep_cnt = (param >> 32) & 0xfff;
4976 rep_idx = (param >> 48) & 0xfff;
4977
4978 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4979
c25bc163
GN		 4980 switch (code) {
4981 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4982 kvm_vcpu_on_spin(vcpu);
4983 break;
4984 default:
4985 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4986 break;
4987 }
55cd8e5a
GN		 4988
4989 ret = res | (((u64)rep_done & 0xfff) << 32);
4990 if (longmode) {
4991 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4992 } else {
4993 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4994 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4995 }
4996
4997 return 1;
4998}
4999
8776e519
HB		 5000int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5001{
5002 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5003 int r = 1;
8776e519 5004
55cd8e5a
GN		 5005 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5006 return kvm_hv_hypercall(vcpu);
5007
5fdbf976
MT		 5008 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5009 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5010 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5011 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5012 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5013
229456fc 5014 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5015
8776e519
HB		 5016 if (!is_long_mode(vcpu)) {
5017 nr &= 0xFFFFFFFF;
5018 a0 &= 0xFFFFFFFF;
5019 a1 &= 0xFFFFFFFF;
5020 a2 &= 0xFFFFFFFF;
5021 a3 &= 0xFFFFFFFF;
5022 }
5023
07708c4a
JK		 5024 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5025 ret = -KVM_EPERM;
5026 goto out;
5027 }
5028
8776e519 5029 switch (nr) {
b93463aa
AK		 5030 case KVM_HC_VAPIC_POLL_IRQ:
5031 ret = 0;
5032 break;
8776e519
HB		 5033 default:
5034 ret = -KVM_ENOSYS;
5035 break;
5036 }
07708c4a 5037out:
5fdbf976 5038 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5039 ++vcpu->stat.hypercalls;
2f333bcb 5040 return r;
8776e519
HB		 5041}
5042EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5043
d6aa1000 5044int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5045{
d6aa1000 5046 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5047 char instruction[3];
5fdbf976 5048 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5049
8776e519
HB		 5050 /*
5051 * Blow out the MMU to ensure that no other VCPU has an active mapping
5052 * to ensure that the updated hypercall appears atomically across all
5053 * VCPUs.
5054 */
5055 kvm_mmu_zap_all(vcpu->kvm);
5056
8776e519 5057 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5058
9d74191a 5059 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5060}
5061
b6c7a5dc
HB		 5062/*
5063 * Check if userspace requested an interrupt window, and that the
5064 * interrupt window is open.
5065 *
5066 * No need to exit to userspace if we already have an interrupt queued.
5067 */
851ba692 5068static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5069{
8061823a 5070 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5071 vcpu->run->request_interrupt_window &&
5df56646 5072 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5073}
5074
851ba692 5075static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5076{
851ba692
AK		 5077 struct kvm_run *kvm_run = vcpu->run;
5078
91586a3b 5079 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5080 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5081 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5082 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5083 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5084 else
b6c7a5dc 5085 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5086 kvm_arch_interrupt_allowed(vcpu) &&
5087 !kvm_cpu_has_interrupt(vcpu) &&
5088 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5089}
5090
b93463aa
AK		 5091static void vapic_enter(struct kvm_vcpu *vcpu)
5092{
5093 struct kvm_lapic *apic = vcpu->arch.apic;
5094 struct page *page;
5095
5096 if (!apic || !apic->vapic_addr)
5097 return;
5098
5099 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5100
5101 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5102}
5103
5104static void vapic_exit(struct kvm_vcpu *vcpu)
5105{
5106 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5107 int idx;
b93463aa
AK		 5108
5109 if (!apic || !apic->vapic_addr)
5110 return;
5111
f656ce01 5112 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5113 kvm_release_page_dirty(apic->vapic_page);
5114 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5115 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5116}
5117
95ba8273
GN		 5118static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5119{
5120 int max_irr, tpr;
5121
5122 if (!kvm_x86_ops->update_cr8_intercept)
5123 return;
5124
88c808fd
AK		 5125 if (!vcpu->arch.apic)
5126 return;
5127
8db3baa2
GN		 5128 if (!vcpu->arch.apic->vapic_addr)
5129 max_irr = kvm_lapic_find_highest_irr(vcpu);
5130 else
5131 max_irr = -1;
95ba8273
GN		 5132
5133 if (max_irr != -1)
5134 max_irr >>= 4;
5135
5136 tpr = kvm_lapic_get_cr8(vcpu);
5137
5138 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5139}
5140
851ba692 5141static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5142{
5143 /* try to reinject previous events if any */
b59bb7bd 5144 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5145 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5146 vcpu->arch.exception.has_error_code,
5147 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5148 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5149 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5150 vcpu->arch.exception.error_code,
5151 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5152 return;
5153 }
5154
95ba8273
GN		 5155 if (vcpu->arch.nmi_injected) {
5156 kvm_x86_ops->set_nmi(vcpu);
5157 return;
5158 }
5159
5160 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5161 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5162 return;
5163 }
5164
5165 /* try to inject new event if pending */
5166 if (vcpu->arch.nmi_pending) {
5167 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5168 --vcpu->arch.nmi_pending;
95ba8273
GN		 5169 vcpu->arch.nmi_injected = true;
5170 kvm_x86_ops->set_nmi(vcpu);
5171 }
5172 } else if (kvm_cpu_has_interrupt(vcpu)) {
5173 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5174 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5175 false);
5176 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5177 }
5178 }
5179}
5180
2acf923e
DC		 5181static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5182{
5183 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5184 !vcpu->guest_xcr0_loaded) {
5185 /* kvm_set_xcr() also depends on this */
5186 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5187 vcpu->guest_xcr0_loaded = 1;
5188 }
5189}
5190
5191static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5192{
5193 if (vcpu->guest_xcr0_loaded) {
5194 if (vcpu->arch.xcr0 != host_xcr0)
5195 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5196 vcpu->guest_xcr0_loaded = 0;
5197 }
5198}
5199
7460fb4a
AK		 5200static void process_nmi(struct kvm_vcpu *vcpu)
5201{
5202 unsigned limit = 2;
5203
5204 /*
5205 * x86 is limited to one NMI running, and one NMI pending after it.
5206 * If an NMI is already in progress, limit further NMIs to just one.
5207 * Otherwise, allow two (and we'll inject the first one immediately).
5208 */
5209 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5210 limit = 1;
5211
5212 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5213 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5214 kvm_make_request(KVM_REQ_EVENT, vcpu);
5215}
5216
851ba692 5217static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5218{
5219 int r;
6a8b1d13 5220 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5221 vcpu->run->request_interrupt_window;
d6185f20 5222 bool req_immediate_exit = 0;
b6c7a5dc 5223
3e007509 5224 if (vcpu->requests) {
a8eeb04a 5225 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5226 kvm_mmu_unload(vcpu);
a8eeb04a 5227 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5228 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5229 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5230 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5231 if (unlikely(r))
5232 goto out;
5233 }
a8eeb04a 5234 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5235 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5236 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5237 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5238 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5239 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5240 r = 0;
5241 goto out;
5242 }
a8eeb04a 5243 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5244 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5245 r = 0;
5246 goto out;
5247 }
a8eeb04a 5248 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5249 vcpu->fpu_active = 0;
5250 kvm_x86_ops->fpu_deactivate(vcpu);
5251 }
af585b92
GN		 5252 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5253 /* Page is swapped out. Do synthetic halt */
5254 vcpu->arch.apf.halted = true;
5255 r = 1;
5256 goto out;
5257 }
c9aaa895
GC		 5258 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5259 record_steal_time(vcpu);
7460fb4a
AK		 5260 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5261 process_nmi(vcpu);
d6185f20
NHE		 5262 req_immediate_exit =
5263 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
f5132b01
GN		 5264 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5265 kvm_handle_pmu_event(vcpu);
5266 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5267 kvm_deliver_pmi(vcpu);
2f52d58c 5268 }
b93463aa 5269
b463a6f7
AK		 5270 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5271 inject_pending_event(vcpu);
5272
5273 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5274 if (vcpu->arch.nmi_pending)
b463a6f7
AK		 5275 kvm_x86_ops->enable_nmi_window(vcpu);
5276 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5277 kvm_x86_ops->enable_irq_window(vcpu);
5278
5279 if (kvm_lapic_enabled(vcpu)) {
5280 update_cr8_intercept(vcpu);
5281 kvm_lapic_sync_to_vapic(vcpu);
5282 }
5283 }
5284
d8368af8
AK		 5285 r = kvm_mmu_reload(vcpu);
5286 if (unlikely(r)) {
d905c069 5287 goto cancel_injection;
d8368af8
AK		 5288 }
5289
b6c7a5dc
HB		 5290 preempt_disable();
5291
5292 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5293 if (vcpu->fpu_active)
5294 kvm_load_guest_fpu(vcpu);
2acf923e 5295 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5296
6b7e2d09
XG		 5297 vcpu->mode = IN_GUEST_MODE;
5298
5299 /* We should set ->mode before check ->requests,
5300 * see the comment in make_all_cpus_request.
5301 */
5302 smp_mb();
b6c7a5dc 5303
d94e1dc9 5304 local_irq_disable();
32f88400 5305
6b7e2d09 5306 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5307 || need_resched() || signal_pending(current)) {
6b7e2d09 5308 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5309 smp_wmb();
6c142801
AK		 5310 local_irq_enable();
5311 preempt_enable();
5312 r = 1;
d905c069 5313 goto cancel_injection;
6c142801
AK		 5314 }
5315
f656ce01 5316 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5317
d6185f20
NHE		 5318 if (req_immediate_exit)
5319 smp_send_reschedule(vcpu->cpu);
5320
b6c7a5dc
HB		 5321 kvm_guest_enter();
5322
42dbaa5a 5323 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5324 set_debugreg(0, 7);
5325 set_debugreg(vcpu->arch.eff_db[0], 0);
5326 set_debugreg(vcpu->arch.eff_db[1], 1);
5327 set_debugreg(vcpu->arch.eff_db[2], 2);
5328 set_debugreg(vcpu->arch.eff_db[3], 3);
5329 }
b6c7a5dc 5330
229456fc 5331 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5332 kvm_x86_ops->run(vcpu);
b6c7a5dc 5333
24f1e32c
FW		 5334 /*
5335 * If the guest has used debug registers, at least dr7
5336 * will be disabled while returning to the host.
5337 * If we don't have active breakpoints in the host, we don't
5338 * care about the messed up debug address registers. But if
5339 * we have some of them active, restore the old state.
5340 */
59d8eb53 5341 if (hw_breakpoint_active())
24f1e32c 5342 hw_breakpoint_restore();
42dbaa5a 5343
d5c1785d 5344 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
1d5f066e 5345
6b7e2d09 5346 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5347 smp_wmb();
b6c7a5dc
HB		 5348 local_irq_enable();
5349
5350 ++vcpu->stat.exits;
5351
5352 /*
5353 * We must have an instruction between local_irq_enable() and
5354 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5355 * the interrupt shadow. The stat.exits increment will do nicely.
5356 * But we need to prevent reordering, hence this barrier():
5357 */
5358 barrier();
5359
5360 kvm_guest_exit();
5361
5362 preempt_enable();
5363
f656ce01 5364 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5365
b6c7a5dc
HB		 5366 /*
5367 * Profile KVM exit RIPs:
5368 */
5369 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5370 unsigned long rip = kvm_rip_read(vcpu);
5371 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5372 }
5373
cc578287
ZA		 5374 if (unlikely(vcpu->arch.tsc_always_catchup))
5375 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 5376
5cfb1d5a
MT		 5377 if (vcpu->arch.apic_attention)
5378 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 5379
851ba692 5380 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 5381 return r;
5382
5383cancel_injection:
5384 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 5385 if (unlikely(vcpu->arch.apic_attention))
5386 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 5387out:
5388 return r;
5389}
b6c7a5dc 5390
09cec754 5391
851ba692 5392static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5393{
5394 int r;
f656ce01 5395 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5396
5397 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5398 pr_debug("vcpu %d received sipi with vector # %x\n",
5399 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5400 kvm_lapic_reset(vcpu);
5f179287 5401 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5402 if (r)
5403 return r;
5404 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5405 }
5406
f656ce01 5407 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5408 vapic_enter(vcpu);
5409
5410 r = 1;
5411 while (r > 0) {
af585b92
GN		 5412 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5413 !vcpu->arch.apf.halted)
851ba692 5414 r = vcpu_enter_guest(vcpu);
d7690175 5415 else {
f656ce01 5416 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5417 kvm_vcpu_block(vcpu);
f656ce01 5418 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5419 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5420 {
5421 switch(vcpu->arch.mp_state) {
5422 case KVM_MP_STATE_HALTED:
d7690175 5423 vcpu->arch.mp_state =
09cec754
GN		 5424 KVM_MP_STATE_RUNNABLE;
5425 case KVM_MP_STATE_RUNNABLE:
af585b92 5426 vcpu->arch.apf.halted = false;
09cec754
GN		 5427 break;
5428 case KVM_MP_STATE_SIPI_RECEIVED:
5429 default:
5430 r = -EINTR;
5431 break;
5432 }
5433 }
d7690175
MT		 5434 }
5435
09cec754
GN		 5436 if (r <= 0)
5437 break;
5438
5439 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5440 if (kvm_cpu_has_pending_timer(vcpu))
5441 kvm_inject_pending_timer_irqs(vcpu);
5442
851ba692 5443 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5444 r = -EINTR;
851ba692 5445 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5446 ++vcpu->stat.request_irq_exits;
5447 }
af585b92
GN		 5448
5449 kvm_check_async_pf_completion(vcpu);
5450
09cec754
GN		 5451 if (signal_pending(current)) {
5452 r = -EINTR;
851ba692 5453 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5454 ++vcpu->stat.signal_exits;
5455 }
5456 if (need_resched()) {
f656ce01 5457 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5458 kvm_resched(vcpu);
f656ce01 5459 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5460 }
b6c7a5dc
HB		 5461 }
5462
f656ce01 5463 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5464
b93463aa
AK		 5465 vapic_exit(vcpu);
5466
b6c7a5dc
HB		 5467 return r;
5468}
5469
f78146b0
AK		 5470/*
5471 * Implements the following, as a state machine:
5472 *
5473 * read:
5474 * for each fragment
5475 * write gpa, len
5476 * exit
5477 * copy data
5478 * execute insn
5479 *
5480 * write:
5481 * for each fragment
5482 * write gpa, len
5483 * copy data
5484 * exit
5485 */
5287f194
AK		 5486static int complete_mmio(struct kvm_vcpu *vcpu)
5487{
5488 struct kvm_run *run = vcpu->run;
f78146b0 5489 struct kvm_mmio_fragment *frag;
5287f194
AK		 5490 int r;
5491
5492 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5493 return 1;
5494
5495 if (vcpu->mmio_needed) {
f78146b0
AK		 5496 /* Complete previous fragment */
5497 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment++];
cef4dea0 5498 if (!vcpu->mmio_is_write)
f78146b0
AK		 5499 memcpy(frag->data, run->mmio.data, frag->len);
5500 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5501 vcpu->mmio_needed = 0;
5502 if (vcpu->mmio_is_write)
5503 return 1;
5504 vcpu->mmio_read_completed = 1;
5505 goto done;
cef4dea0 5506 }
f78146b0
AK		 5507 /* Initiate next fragment */
5508 ++frag;
5509 run->exit_reason = KVM_EXIT_MMIO;
5510 run->mmio.phys_addr = frag->gpa;
cef4dea0 5511 if (vcpu->mmio_is_write)
f78146b0
AK		 5512 memcpy(run->mmio.data, frag->data, frag->len);
5513 run->mmio.len = frag->len;
5514 run->mmio.is_write = vcpu->mmio_is_write;
5515 return 0;
5516
5287f194 5517 }
f78146b0 5518done:
5287f194
AK		 5519 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5520 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5521 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5522 if (r != EMULATE_DONE)
5523 return 0;
5524 return 1;
5525}
5526
b6c7a5dc
HB		 5527int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5528{
5529 int r;
5530 sigset_t sigsaved;
5531
e5c30142
AK		 5532 if (!tsk_used_math(current) && init_fpu(current))
5533 return -ENOMEM;
5534
ac9f6dc0
AK		 5535 if (vcpu->sigset_active)
5536 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5537
a4535290 5538 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5539 kvm_vcpu_block(vcpu);
d7690175 5540 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5541 r = -EAGAIN;
5542 goto out;
b6c7a5dc
HB		 5543 }
5544
b6c7a5dc 5545 /* re-sync apic's tpr */
eea1cff9
AP		 5546 if (!irqchip_in_kernel(vcpu->kvm)) {
5547 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5548 r = -EINVAL;
5549 goto out;
5550 }
5551 }
b6c7a5dc 5552
5287f194
AK		 5553 r = complete_mmio(vcpu);
5554 if (r <= 0)
5555 goto out;
5556
851ba692 5557 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5558
5559out:
f1d86e46 5560 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5561 if (vcpu->sigset_active)
5562 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5563
b6c7a5dc
HB		 5564 return r;
5565}
5566
5567int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5568{
7ae441ea
GN		 5569 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5570 /*
5571 * We are here if userspace calls get_regs() in the middle of
5572 * instruction emulation. Registers state needs to be copied
4a969980 5573 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 5574 * that usually, but some bad designed PV devices (vmware
5575 * backdoor interface) need this to work
5576 */
9dac77fa
AK		 5577 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5578 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea
GN		 5579 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5580 }
5fdbf976
MT		 5581 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5582 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5583 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5584 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5585 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5586 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5587 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5588 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5589#ifdef CONFIG_X86_64
5fdbf976
MT		 5590 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5591 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5592 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5593 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5594 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5595 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5596 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5597 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5598#endif
5599
5fdbf976 5600 regs->rip = kvm_rip_read(vcpu);
91586a3b 5601 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5602
b6c7a5dc
HB		 5603 return 0;
5604}
5605
5606int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5607{
7ae441ea
GN		 5608 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5609 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5610
5fdbf976
MT		 5611 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5612 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5613 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5614 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5615 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5616 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5617 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5618 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5619#ifdef CONFIG_X86_64
5fdbf976
MT		 5620 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5621 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5622 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5623 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5624 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5625 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5626 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5627 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5628#endif
5629
5fdbf976 5630 kvm_rip_write(vcpu, regs->rip);
91586a3b 5631 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5632
b4f14abd
JK		 5633 vcpu->arch.exception.pending = false;
5634
3842d135
AK		 5635 kvm_make_request(KVM_REQ_EVENT, vcpu);
5636
b6c7a5dc
HB		 5637 return 0;
5638}
5639
b6c7a5dc
HB		 5640void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5641{
5642 struct kvm_segment cs;
5643
3e6e0aab 5644 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5645 *db = cs.db;
5646 *l = cs.l;
5647}
5648EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5649
5650int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5651 struct kvm_sregs *sregs)
5652{
89a27f4d 5653 struct desc_ptr dt;
b6c7a5dc 5654
3e6e0aab
GT		 5655 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5656 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5657 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5658 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5659 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5660 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5661
3e6e0aab
GT		 5662 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5663 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5664
5665 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5666 sregs->idt.limit = dt.size;
5667 sregs->idt.base = dt.address;
b6c7a5dc 5668 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5669 sregs->gdt.limit = dt.size;
5670 sregs->gdt.base = dt.address;
b6c7a5dc 5671
4d4ec087 5672 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5673 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5674 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5675 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5676 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5677 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5678 sregs->apic_base = kvm_get_apic_base(vcpu);
5679
923c61bb 5680 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5681
36752c9b 5682 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5683 set_bit(vcpu->arch.interrupt.nr,
5684 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5685
b6c7a5dc
HB		 5686 return 0;
5687}
5688
62d9f0db
MT		 5689int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5690 struct kvm_mp_state *mp_state)
5691{
62d9f0db 5692 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5693 return 0;
5694}
5695
5696int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5697 struct kvm_mp_state *mp_state)
5698{
62d9f0db 5699 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5700 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5701 return 0;
5702}
5703
7f3d35fd
KW		 5704int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
5705 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 5706{
9d74191a 5707 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 5708 int ret;
e01c2426 5709
8ec4722d 5710 init_emulate_ctxt(vcpu);
c697518a 5711
7f3d35fd 5712 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 5713 has_error_code, error_code);
c697518a 5714
c697518a 5715 if (ret)
19d04437 5716 return EMULATE_FAIL;
37817f29 5717
9dac77fa 5718 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 5719 kvm_rip_write(vcpu, ctxt->eip);
5720 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 5721 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5722 return EMULATE_DONE;
37817f29
IE		 5723}
5724EXPORT_SYMBOL_GPL(kvm_task_switch);
5725
b6c7a5dc
HB		 5726int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5727 struct kvm_sregs *sregs)
5728{
5729 int mmu_reset_needed = 0;
63f42e02 5730 int pending_vec, max_bits, idx;
89a27f4d 5731 struct desc_ptr dt;
b6c7a5dc 5732
89a27f4d
GN		 5733 dt.size = sregs->idt.limit;
5734 dt.address = sregs->idt.base;
b6c7a5dc 5735 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5736 dt.size = sregs->gdt.limit;
5737 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5738 kvm_x86_ops->set_gdt(vcpu, &dt);
5739
ad312c7c 5740 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5741 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5742 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5743 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5744
2d3ad1f4 5745 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5746
f6801dff 5747 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5748 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5749 kvm_set_apic_base(vcpu, sregs->apic_base);
5750
4d4ec087 5751 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5752 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5753 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5754
fc78f519 5755 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5756 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 5757 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 5758 kvm_update_cpuid(vcpu);
63f42e02
XG		 5759
5760 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5761 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5762 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5763 mmu_reset_needed = 1;
5764 }
63f42e02 5765 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5766
5767 if (mmu_reset_needed)
5768 kvm_mmu_reset_context(vcpu);
5769
923c61bb
GN		 5770 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5771 pending_vec = find_first_bit(
5772 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5773 if (pending_vec < max_bits) {
66fd3f7f 5774 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 5775 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 5776 }
5777
3e6e0aab
GT		 5778 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5779 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5780 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5781 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5782 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5783 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5784
3e6e0aab
GT		 5785 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5786 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5787
5f0269f5
ME		 5788 update_cr8_intercept(vcpu);
5789
9c3e4aab 5790 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5791 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5792 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5793 !is_protmode(vcpu))
9c3e4aab
MT		 5794 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5795
3842d135
AK		 5796 kvm_make_request(KVM_REQ_EVENT, vcpu);
5797
b6c7a5dc
HB		 5798 return 0;
5799}
5800
d0bfb940
JK		 5801int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5802 struct kvm_guest_debug *dbg)
b6c7a5dc 5803{
355be0b9 5804 unsigned long rflags;
ae675ef0 5805 int i, r;
b6c7a5dc 5806
4f926bf2
JK		 5807 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5808 r = -EBUSY;
5809 if (vcpu->arch.exception.pending)
2122ff5e 5810 goto out;
4f926bf2
JK		 5811 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5812 kvm_queue_exception(vcpu, DB_VECTOR);
5813 else
5814 kvm_queue_exception(vcpu, BP_VECTOR);
5815 }
5816
91586a3b
JK		 5817 /*
5818 * Read rflags as long as potentially injected trace flags are still
5819 * filtered out.
5820 */
5821 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5822
5823 vcpu->guest_debug = dbg->control;
5824 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5825 vcpu->guest_debug = 0;
5826
5827 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5828 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5829 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5830 vcpu->arch.switch_db_regs =
5831 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5832 } else {
5833 for (i = 0; i < KVM_NR_DB_REGS; i++)
5834 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5835 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5836 }
5837
f92653ee
JK		 5838 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5839 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5840 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5841
91586a3b
JK		 5842 /*
5843 * Trigger an rflags update that will inject or remove the trace
5844 * flags.
5845 */
5846 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5847
355be0b9 5848 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5849
4f926bf2 5850 r = 0;
d0bfb940 5851
2122ff5e 5852out:
b6c7a5dc
HB		 5853
5854 return r;
5855}
5856
8b006791
ZX		 5857/*
5858 * Translate a guest virtual address to a guest physical address.
5859 */
5860int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5861 struct kvm_translation *tr)
5862{
5863 unsigned long vaddr = tr->linear_address;
5864 gpa_t gpa;
f656ce01 5865 int idx;
8b006791 5866
f656ce01 5867 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5868 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5869 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5870 tr->physical_address = gpa;
5871 tr->valid = gpa != UNMAPPED_GVA;
5872 tr->writeable = 1;
5873 tr->usermode = 0;
8b006791
ZX		 5874
5875 return 0;
5876}
5877
d0752060
HB		 5878int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5879{
98918833
SY		 5880 struct i387_fxsave_struct *fxsave =
5881 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5882
d0752060
HB		 5883 memcpy(fpu->fpr, fxsave->st_space, 128);
5884 fpu->fcw = fxsave->cwd;
5885 fpu->fsw = fxsave->swd;
5886 fpu->ftwx = fxsave->twd;
5887 fpu->last_opcode = fxsave->fop;
5888 fpu->last_ip = fxsave->rip;
5889 fpu->last_dp = fxsave->rdp;
5890 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5891
d0752060
HB		 5892 return 0;
5893}
5894
5895int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5896{
98918833
SY		 5897 struct i387_fxsave_struct *fxsave =
5898 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5899
d0752060
HB		 5900 memcpy(fxsave->st_space, fpu->fpr, 128);
5901 fxsave->cwd = fpu->fcw;
5902 fxsave->swd = fpu->fsw;
5903 fxsave->twd = fpu->ftwx;
5904 fxsave->fop = fpu->last_opcode;
5905 fxsave->rip = fpu->last_ip;
5906 fxsave->rdp = fpu->last_dp;
5907 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5908
d0752060
HB		 5909 return 0;
5910}
5911
10ab25cd 5912int fx_init(struct kvm_vcpu *vcpu)
d0752060 5913{
10ab25cd
JK		 5914 int err;
5915
5916 err = fpu_alloc(&vcpu->arch.guest_fpu);
5917 if (err)
5918 return err;
5919
98918833 5920 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5921
2acf923e
DC		 5922 /*
5923 * Ensure guest xcr0 is valid for loading
5924 */
5925 vcpu->arch.xcr0 = XSTATE_FP;
5926
ad312c7c 5927 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5928
5929 return 0;
d0752060
HB		 5930}
5931EXPORT_SYMBOL_GPL(fx_init);
5932
98918833
SY		 5933static void fx_free(struct kvm_vcpu *vcpu)
5934{
5935 fpu_free(&vcpu->arch.guest_fpu);
5936}
5937
d0752060
HB		 5938void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5939{
2608d7a1 5940 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5941 return;
5942
2acf923e
DC		 5943 /*
5944 * Restore all possible states in the guest,
5945 * and assume host would use all available bits.
5946 * Guest xcr0 would be loaded later.
5947 */
5948 kvm_put_guest_xcr0(vcpu);
d0752060 5949 vcpu->guest_fpu_loaded = 1;
7cf30855 5950 unlazy_fpu(current);
98918833 5951 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5952 trace_kvm_fpu(1);
d0752060 5953}
d0752060
HB		 5954
5955void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5956{
2acf923e
DC		 5957 kvm_put_guest_xcr0(vcpu);
5958
d0752060
HB		 5959 if (!vcpu->guest_fpu_loaded)
5960 return;
5961
5962 vcpu->guest_fpu_loaded = 0;
98918833 5963 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5964 ++vcpu->stat.fpu_reload;
a8eeb04a 5965 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5966 trace_kvm_fpu(0);
d0752060 5967}
e9b11c17
ZX		 5968
5969void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5970{
12f9a48f 5971 kvmclock_reset(vcpu);
7f1ea208 5972
f5f48ee1 5973 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5974 fx_free(vcpu);
e9b11c17
ZX		 5975 kvm_x86_ops->vcpu_free(vcpu);
5976}
5977
5978struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5979 unsigned int id)
5980{
6755bae8
ZA		 5981 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5982 printk_once(KERN_WARNING
5983 "kvm: SMP vm created on host with unstable TSC; "
5984 "guest TSC will not be reliable\n");
26e5215f
AK		 5985 return kvm_x86_ops->vcpu_create(kvm, id);
5986}
e9b11c17 5987
26e5215f
AK		 5988int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5989{
5990 int r;
e9b11c17 5991
0bed3b56 5992 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5993 vcpu_load(vcpu);
5994 r = kvm_arch_vcpu_reset(vcpu);
5995 if (r == 0)
5996 r = kvm_mmu_setup(vcpu);
5997 vcpu_put(vcpu);
e9b11c17 5998
26e5215f 5999 return r;
e9b11c17
ZX		 6000}
6001
d40ccc62 6002void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6003{
344d9588
GN		 6004 vcpu->arch.apf.msr_val = 0;
6005
e9b11c17
ZX		 6006 vcpu_load(vcpu);
6007 kvm_mmu_unload(vcpu);
6008 vcpu_put(vcpu);
6009
98918833 6010 fx_free(vcpu);
e9b11c17
ZX		 6011 kvm_x86_ops->vcpu_free(vcpu);
6012}
6013
6014int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6015{
7460fb4a
AK		 6016 atomic_set(&vcpu->arch.nmi_queued, 0);
6017 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6018 vcpu->arch.nmi_injected = false;
6019
42dbaa5a
JK		 6020 vcpu->arch.switch_db_regs = 0;
6021 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6022 vcpu->arch.dr6 = DR6_FIXED_1;
6023 vcpu->arch.dr7 = DR7_FIXED_1;
6024
3842d135 6025 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6026 vcpu->arch.apf.msr_val = 0;
c9aaa895 6027 vcpu->arch.st.msr_val = 0;
3842d135 6028
12f9a48f
GC		 6029 kvmclock_reset(vcpu);
6030
af585b92
GN		 6031 kvm_clear_async_pf_completion_queue(vcpu);
6032 kvm_async_pf_hash_reset(vcpu);
6033 vcpu->arch.apf.halted = false;
3842d135 6034
f5132b01
GN		 6035 kvm_pmu_reset(vcpu);
6036
e9b11c17
ZX		 6037 return kvm_x86_ops->vcpu_reset(vcpu);
6038}
6039
10474ae8 6040int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6041{
ca84d1a2
ZA		 6042 struct kvm *kvm;
6043 struct kvm_vcpu *vcpu;
6044 int i;
0dd6a6ed
ZA		 6045 int ret;
6046 u64 local_tsc;
6047 u64 max_tsc = 0;
6048 bool stable, backwards_tsc = false;
18863bdd
AK		 6049
6050 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6051 ret = kvm_x86_ops->hardware_enable(garbage);
6052 if (ret != 0)
6053 return ret;
6054
6055 local_tsc = native_read_tsc();
6056 stable = !check_tsc_unstable();
6057 list_for_each_entry(kvm, &vm_list, vm_list) {
6058 kvm_for_each_vcpu(i, vcpu, kvm) {
6059 if (!stable && vcpu->cpu == smp_processor_id())
6060 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6061 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6062 backwards_tsc = true;
6063 if (vcpu->arch.last_host_tsc > max_tsc)
6064 max_tsc = vcpu->arch.last_host_tsc;
6065 }
6066 }
6067 }
6068
6069 /*
6070 * Sometimes, even reliable TSCs go backwards. This happens on
6071 * platforms that reset TSC during suspend or hibernate actions, but
6072 * maintain synchronization. We must compensate. Fortunately, we can
6073 * detect that condition here, which happens early in CPU bringup,
6074 * before any KVM threads can be running. Unfortunately, we can't
6075 * bring the TSCs fully up to date with real time, as we aren't yet far
6076 * enough into CPU bringup that we know how much real time has actually
6077 * elapsed; our helper function, get_kernel_ns() will be using boot
6078 * variables that haven't been updated yet.
6079 *
6080 * So we simply find the maximum observed TSC above, then record the
6081 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6082 * the adjustment will be applied. Note that we accumulate
6083 * adjustments, in case multiple suspend cycles happen before some VCPU
6084 * gets a chance to run again. In the event that no KVM threads get a
6085 * chance to run, we will miss the entire elapsed period, as we'll have
6086 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6087 * loose cycle time. This isn't too big a deal, since the loss will be
6088 * uniform across all VCPUs (not to mention the scenario is extremely
6089 * unlikely). It is possible that a second hibernate recovery happens
6090 * much faster than a first, causing the observed TSC here to be
6091 * smaller; this would require additional padding adjustment, which is
6092 * why we set last_host_tsc to the local tsc observed here.
6093 *
6094 * N.B. - this code below runs only on platforms with reliable TSC,
6095 * as that is the only way backwards_tsc is set above. Also note
6096 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6097 * have the same delta_cyc adjustment applied if backwards_tsc
6098 * is detected. Note further, this adjustment is only done once,
6099 * as we reset last_host_tsc on all VCPUs to stop this from being
6100 * called multiple times (one for each physical CPU bringup).
6101 *
4a969980 6102 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6103 * will be compensated by the logic in vcpu_load, which sets the TSC to
6104 * catchup mode. This will catchup all VCPUs to real time, but cannot
6105 * guarantee that they stay in perfect synchronization.
6106 */
6107 if (backwards_tsc) {
6108 u64 delta_cyc = max_tsc - local_tsc;
6109 list_for_each_entry(kvm, &vm_list, vm_list) {
6110 kvm_for_each_vcpu(i, vcpu, kvm) {
6111 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6112 vcpu->arch.last_host_tsc = local_tsc;
6113 }
6114
6115 /*
6116 * We have to disable TSC offset matching.. if you were
6117 * booting a VM while issuing an S4 host suspend....
6118 * you may have some problem. Solving this issue is
6119 * left as an exercise to the reader.
6120 */
6121 kvm->arch.last_tsc_nsec = 0;
6122 kvm->arch.last_tsc_write = 0;
6123 }
6124
6125 }
6126 return 0;
e9b11c17
ZX		 6127}
6128
6129void kvm_arch_hardware_disable(void *garbage)
6130{
6131 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6132 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6133}
6134
6135int kvm_arch_hardware_setup(void)
6136{
6137 return kvm_x86_ops->hardware_setup();
6138}
6139
6140void kvm_arch_hardware_unsetup(void)
6141{
6142 kvm_x86_ops->hardware_unsetup();
6143}
6144
6145void kvm_arch_check_processor_compat(void *rtn)
6146{
6147 kvm_x86_ops->check_processor_compatibility(rtn);
6148}
6149
3e515705
AK		 6150bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6151{
6152 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6153}
6154
e9b11c17
ZX		 6155int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6156{
6157 struct page *page;
6158 struct kvm *kvm;
6159 int r;
6160
6161 BUG_ON(vcpu->kvm == NULL);
6162 kvm = vcpu->kvm;
6163
9aabc88f 6164 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6165 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6166 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6167 else
a4535290 6168 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6169
6170 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6171 if (!page) {
6172 r = -ENOMEM;
6173 goto fail;
6174 }
ad312c7c 6175 vcpu->arch.pio_data = page_address(page);
e9b11c17 6176
cc578287 6177 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6178
e9b11c17
ZX		 6179 r = kvm_mmu_create(vcpu);
6180 if (r < 0)
6181 goto fail_free_pio_data;
6182
6183 if (irqchip_in_kernel(kvm)) {
6184 r = kvm_create_lapic(vcpu);
6185 if (r < 0)
6186 goto fail_mmu_destroy;
6187 }
6188
890ca9ae
HY		 6189 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6190 GFP_KERNEL);
6191 if (!vcpu->arch.mce_banks) {
6192 r = -ENOMEM;
443c39bc 6193 goto fail_free_lapic;
890ca9ae
HY		 6194 }
6195 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6196
f5f48ee1
SY		 6197 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6198 goto fail_free_mce_banks;
6199
af585b92 6200 kvm_async_pf_hash_reset(vcpu);
f5132b01 6201 kvm_pmu_init(vcpu);
af585b92 6202
e9b11c17 6203 return 0;
f5f48ee1
SY		 6204fail_free_mce_banks:
6205 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6206fail_free_lapic:
6207 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6208fail_mmu_destroy:
6209 kvm_mmu_destroy(vcpu);
6210fail_free_pio_data:
ad312c7c 6211 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6212fail:
6213 return r;
6214}
6215
6216void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6217{
f656ce01
MT		 6218 int idx;
6219
f5132b01 6220 kvm_pmu_destroy(vcpu);
36cb93fd 6221 kfree(vcpu->arch.mce_banks);
e9b11c17 6222 kvm_free_lapic(vcpu);
f656ce01 6223 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6224 kvm_mmu_destroy(vcpu);
f656ce01 6225 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6226 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 6227}
d19a9cd2 6228
e08b9637 6229int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6230{
e08b9637
CO		 6231 if (type)
6232 return -EINVAL;
6233
f05e70ac 6234 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6235 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6236
5550af4d
SY		 6237 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6238 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6239
038f8c11 6240 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6241
d89f5eff 6242 return 0;
d19a9cd2
ZX		 6243}
6244
6245static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6246{
6247 vcpu_load(vcpu);
6248 kvm_mmu_unload(vcpu);
6249 vcpu_put(vcpu);
6250}
6251
6252static void kvm_free_vcpus(struct kvm *kvm)
6253{
6254 unsigned int i;
988a2cae 6255 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6256
6257 /*
6258 * Unpin any mmu pages first.
6259 */
af585b92
GN		 6260 kvm_for_each_vcpu(i, vcpu, kvm) {
6261 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6262 kvm_unload_vcpu_mmu(vcpu);
af585b92 6263 }
988a2cae
GN		 6264 kvm_for_each_vcpu(i, vcpu, kvm)
6265 kvm_arch_vcpu_free(vcpu);
6266
6267 mutex_lock(&kvm->lock);
6268 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6269 kvm->vcpus[i] = NULL;
d19a9cd2 6270
988a2cae
GN		 6271 atomic_set(&kvm->online_vcpus, 0);
6272 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6273}
6274
ad8ba2cd
SY		 6275void kvm_arch_sync_events(struct kvm *kvm)
6276{
ba4cef31 6277 kvm_free_all_assigned_devices(kvm);
aea924f6 6278 kvm_free_pit(kvm);
ad8ba2cd
SY		 6279}
6280
d19a9cd2
ZX		 6281void kvm_arch_destroy_vm(struct kvm *kvm)
6282{
6eb55818 6283 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6284 kfree(kvm->arch.vpic);
6285 kfree(kvm->arch.vioapic);
d19a9cd2 6286 kvm_free_vcpus(kvm);
3d45830c
AK		 6287 if (kvm->arch.apic_access_page)
6288 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6289 if (kvm->arch.ept_identity_pagetable)
6290 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6291}
0de10343 6292
db3fe4eb
TY		 6293void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6294 struct kvm_memory_slot *dont)
6295{
6296 int i;
6297
d89cc617
TY		 6298 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6299 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6300 kvm_kvfree(free->arch.rmap[i]);
6301 free->arch.rmap[i] = NULL;
77d11309 6302 }
d89cc617
TY		 6303 if (i == 0)
6304 continue;
6305
6306 if (!dont || free->arch.lpage_info[i - 1] !=
6307 dont->arch.lpage_info[i - 1]) {
6308 kvm_kvfree(free->arch.lpage_info[i - 1]);
6309 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6310 }
6311 }
6312}
6313
6314int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6315{
6316 int i;
6317
d89cc617 6318 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 6319 unsigned long ugfn;
6320 int lpages;
d89cc617 6321 int level = i + 1;
db3fe4eb
TY		 6322
6323 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6324 slot->base_gfn, level) + 1;
6325
d89cc617
TY		 6326 slot->arch.rmap[i] =
6327 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6328 if (!slot->arch.rmap[i])
77d11309 6329 goto out_free;
d89cc617
TY		 6330 if (i == 0)
6331 continue;
77d11309 6332
d89cc617
TY		 6333 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6334 sizeof(*slot->arch.lpage_info[i - 1]));
6335 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 6336 goto out_free;
6337
6338 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6339 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 6340 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6341 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 6342 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6343 /*
6344 * If the gfn and userspace address are not aligned wrt each
6345 * other, or if explicitly asked to, disable large page
6346 * support for this slot
6347 */
6348 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6349 !kvm_largepages_enabled()) {
6350 unsigned long j;
6351
6352 for (j = 0; j < lpages; ++j)
d89cc617 6353 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 6354 }
6355 }
6356
6357 return 0;
6358
6359out_free:
d89cc617
TY		 6360 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6361 kvm_kvfree(slot->arch.rmap[i]);
6362 slot->arch.rmap[i] = NULL;
6363 if (i == 0)
6364 continue;
6365
6366 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6367 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6368 }
6369 return -ENOMEM;
6370}
6371
f7784b8e
MT		 6372int kvm_arch_prepare_memory_region(struct kvm *kvm,
6373 struct kvm_memory_slot *memslot,
0de10343 6374 struct kvm_memory_slot old,
f7784b8e 6375 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6376 int user_alloc)
6377{
f7784b8e 6378 int npages = memslot->npages;
7ac77099
AK		 6379 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6380
6381 /* Prevent internal slot pages from being moved by fork()/COW. */
6382 if (memslot->id >= KVM_MEMORY_SLOTS)
6383 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6384
6385 /*To keep backward compatibility with older userspace,
4a969980 6386 *x86 needs to handle !user_alloc case.
0de10343
ZX		 6387 */
6388 if (!user_alloc) {
aab2eb7a 6389 if (npages && !old.npages) {
604b38ac
AA		 6390 unsigned long userspace_addr;
6391
6be5ceb0 6392 userspace_addr = vm_mmap(NULL, 0,
604b38ac
AA		 6393 npages * PAGE_SIZE,
6394 PROT_READ | PROT_WRITE,
7ac77099 6395 map_flags,
604b38ac 6396 0);
0de10343 6397
604b38ac
AA		 6398 if (IS_ERR((void *)userspace_addr))
6399 return PTR_ERR((void *)userspace_addr);
6400
604b38ac 6401 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6402 }
6403 }
6404
f7784b8e
MT		 6405
6406 return 0;
6407}
6408
6409void kvm_arch_commit_memory_region(struct kvm *kvm,
6410 struct kvm_userspace_memory_region *mem,
6411 struct kvm_memory_slot old,
6412 int user_alloc)
6413{
6414
48c0e4e9 6415 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e 6416
aab2eb7a 6417 if (!user_alloc && !old.user_alloc && old.npages && !npages) {
f7784b8e
MT		 6418 int ret;
6419
bfce281c 6420 ret = vm_munmap(old.userspace_addr,
f7784b8e 6421 old.npages * PAGE_SIZE);
f7784b8e
MT		 6422 if (ret < 0)
6423 printk(KERN_WARNING
6424 "kvm_vm_ioctl_set_memory_region: "
6425 "failed to munmap memory\n");
6426 }
6427
48c0e4e9
XG		 6428 if (!kvm->arch.n_requested_mmu_pages)
6429 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6430
7c8a83b7 6431 spin_lock(&kvm->mmu_lock);
48c0e4e9 6432 if (nr_mmu_pages)
0de10343 6433 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6434 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6435 spin_unlock(&kvm->mmu_lock);
0de10343 6436}
1d737c8a 6437
34d4cb8f
MT		 6438void kvm_arch_flush_shadow(struct kvm *kvm)
6439{
6440 kvm_mmu_zap_all(kvm);
8986ecc0 6441 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6442}
6443
1d737c8a
ZX		 6444int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6445{
af585b92
GN		 6446 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6447 !vcpu->arch.apf.halted)
6448 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100 6449 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
7460fb4a 6450 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 6451 (kvm_arch_interrupt_allowed(vcpu) &&
6452 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6453}
5736199a 6454
b6d33834 6455int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 6456{
b6d33834 6457 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 6458}
78646121
GN		 6459
6460int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6461{
6462 return kvm_x86_ops->interrupt_allowed(vcpu);
6463}
229456fc 6464
f92653ee
JK		 6465bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6466{
6467 unsigned long current_rip = kvm_rip_read(vcpu) +
6468 get_segment_base(vcpu, VCPU_SREG_CS);
6469
6470 return current_rip == linear_rip;
6471}
6472EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6473
94fe45da
JK		 6474unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6475{
6476 unsigned long rflags;
6477
6478 rflags = kvm_x86_ops->get_rflags(vcpu);
6479 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6480 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6481 return rflags;
6482}
6483EXPORT_SYMBOL_GPL(kvm_get_rflags);
6484
6485void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6486{
6487 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6488 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6489 rflags |= X86_EFLAGS_TF;
94fe45da 6490 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6491 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6492}
6493EXPORT_SYMBOL_GPL(kvm_set_rflags);
6494
56028d08
GN		 6495void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6496{
6497 int r;
6498
fb67e14f 6499 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6500 is_error_page(work->page))
56028d08
GN		 6501 return;
6502
6503 r = kvm_mmu_reload(vcpu);
6504 if (unlikely(r))
6505 return;
6506
fb67e14f
XG		 6507 if (!vcpu->arch.mmu.direct_map &&
6508 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6509 return;
6510
56028d08
GN		 6511 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6512}
6513
af585b92
GN		 6514static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6515{
6516 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6517}
6518
6519static inline u32 kvm_async_pf_next_probe(u32 key)
6520{
6521 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6522}
6523
6524static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6525{
6526 u32 key = kvm_async_pf_hash_fn(gfn);
6527
6528 while (vcpu->arch.apf.gfns[key] != ~0)
6529 key = kvm_async_pf_next_probe(key);
6530
6531 vcpu->arch.apf.gfns[key] = gfn;
6532}
6533
6534static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6535{
6536 int i;
6537 u32 key = kvm_async_pf_hash_fn(gfn);
6538
6539 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6540 (vcpu->arch.apf.gfns[key] != gfn &&
6541 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6542 key = kvm_async_pf_next_probe(key);
6543
6544 return key;
6545}
6546
6547bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6548{
6549 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6550}
6551
6552static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6553{
6554 u32 i, j, k;
6555
6556 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6557 while (true) {
6558 vcpu->arch.apf.gfns[i] = ~0;
6559 do {
6560 j = kvm_async_pf_next_probe(j);
6561 if (vcpu->arch.apf.gfns[j] == ~0)
6562 return;
6563 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6564 /*
6565 * k lies cyclically in ]i,j]
6566 * | i.k.j |
6567 * |....j i.k.| or |.k..j i...|
6568 */
6569 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6570 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6571 i = j;
6572 }
6573}
6574
7c90705b
GN		 6575static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6576{
6577
6578 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6579 sizeof(val));
6580}
6581
af585b92
GN		 6582void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6583 struct kvm_async_pf *work)
6584{
6389ee94
AK		 6585 struct x86_exception fault;
6586
7c90705b 6587 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6588 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6589
6590 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6591 (vcpu->arch.apf.send_user_only &&
6592 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6593 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6594 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6595 fault.vector = PF_VECTOR;
6596 fault.error_code_valid = true;
6597 fault.error_code = 0;
6598 fault.nested_page_fault = false;
6599 fault.address = work->arch.token;
6600 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6601 }
af585b92
GN		 6602}
6603
6604void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6605 struct kvm_async_pf *work)
6606{
6389ee94
AK		 6607 struct x86_exception fault;
6608
7c90705b
GN		 6609 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6610 if (is_error_page(work->page))
6611 work->arch.token = ~0; /* broadcast wakeup */
6612 else
6613 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6614
6615 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6616 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6617 fault.vector = PF_VECTOR;
6618 fault.error_code_valid = true;
6619 fault.error_code = 0;
6620 fault.nested_page_fault = false;
6621 fault.address = work->arch.token;
6622 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6623 }
e6d53e3b 6624 vcpu->arch.apf.halted = false;
a4fa1635 6625 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 6626}
6627
6628bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6629{
6630 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6631 return true;
6632 else
6633 return !kvm_event_needs_reinjection(vcpu) &&
6634 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6635}
6636
229456fc
MT		 6637EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6638EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6639EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6640EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6641EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6642EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6643EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6644EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6645EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6646EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6647EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6648EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Linux kernel - Deliverables
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