projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: x86: move MTRR related code to a separate file
[deliverable/linux.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
c9eab58f 30#include "assigned-dev.h"
313a3dc7 31
18068523 32#include <linux/clocksource.h>
4d5c5d0f 33#include <linux/interrupt.h>
313a3dc7
CO		 34#include <linux/kvm.h>
35#include <linux/fs.h>
36#include <linux/vmalloc.h>
5fb76f9b 37#include <linux/module.h>
0de10343 38#include <linux/mman.h>
2bacc55c 39#include <linux/highmem.h>
19de40a8 40#include <linux/iommu.h>
62c476c7 41#include <linux/intel-iommu.h>
c8076604 42#include <linux/cpufreq.h>
18863bdd 43#include <linux/user-return-notifier.h>
a983fb23 44#include <linux/srcu.h>
5a0e3ad6 45#include <linux/slab.h>
ff9d07a0 46#include <linux/perf_event.h>
7bee342a 47#include <linux/uaccess.h>
af585b92 48#include <linux/hash.h>
a1b60c1c 49#include <linux/pci.h>
16e8d74d
MT		 50#include <linux/timekeeper_internal.h>
51#include <linux/pvclock_gtod.h>
aec51dc4 52#include <trace/events/kvm.h>
2ed152af 53
229456fc
MT		 54#define CREATE_TRACE_POINTS
55#include "trace.h"
043405e1 56
24f1e32c 57#include <asm/debugreg.h>
d825ed0a 58#include <asm/msr.h>
a5f61300 59#include <asm/desc.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
6addfc42 90static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 91
97896d04 92struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 93EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 94
476bc001
RR		 95static bool ignore_msrs = 0;
96module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 97
9ed96e87
MT		 98unsigned int min_timer_period_us = 500;
99module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
100
630994b3
MT		 101static bool __read_mostly kvmclock_periodic_sync = true;
102module_param(kvmclock_periodic_sync, bool, S_IRUGO);
103
92a1f12d
JR		 104bool kvm_has_tsc_control;
105EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
106u32 kvm_max_guest_tsc_khz;
107EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
108
cc578287
ZA		 109/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
110static u32 tsc_tolerance_ppm = 250;
111module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
112
d0659d94
MT		 113/* lapic timer advance (tscdeadline mode only) in nanoseconds */
114unsigned int lapic_timer_advance_ns = 0;
115module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
116
16a96021
MT		 117static bool backwards_tsc_observed = false;
118
18863bdd
AK		 119#define KVM_NR_SHARED_MSRS 16
120
121struct kvm_shared_msrs_global {
122 int nr;
2bf78fa7 123 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 124};
125
126struct kvm_shared_msrs {
127 struct user_return_notifier urn;
128 bool registered;
2bf78fa7
SY		 129 struct kvm_shared_msr_values {
130 u64 host;
131 u64 curr;
132 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 133};
134
135static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 136static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 137
417bc304 138struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 139 { "pf_fixed", VCPU_STAT(pf_fixed) },
140 { "pf_guest", VCPU_STAT(pf_guest) },
141 { "tlb_flush", VCPU_STAT(tlb_flush) },
142 { "invlpg", VCPU_STAT(invlpg) },
143 { "exits", VCPU_STAT(exits) },
144 { "io_exits", VCPU_STAT(io_exits) },
145 { "mmio_exits", VCPU_STAT(mmio_exits) },
146 { "signal_exits", VCPU_STAT(signal_exits) },
147 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 148 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 149 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 150 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
ba1389b7 151 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 152 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 153 { "request_irq", VCPU_STAT(request_irq_exits) },
154 { "irq_exits", VCPU_STAT(irq_exits) },
155 { "host_state_reload", VCPU_STAT(host_state_reload) },
156 { "efer_reload", VCPU_STAT(efer_reload) },
157 { "fpu_reload", VCPU_STAT(fpu_reload) },
158 { "insn_emulation", VCPU_STAT(insn_emulation) },
159 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 160 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 161 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 162 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
163 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
164 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
165 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
166 { "mmu_flooded", VM_STAT(mmu_flooded) },
167 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 168 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 169 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 170 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 171 { "largepages", VM_STAT(lpages) },
417bc304
HB		 172 { NULL }
173};
174
2acf923e
DC		 175u64 __read_mostly host_xcr0;
176
b6785def 177static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 178
af585b92
GN		 179static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
180{
181 int i;
182 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
183 vcpu->arch.apf.gfns[i] = ~0;
184}
185
18863bdd
AK		 186static void kvm_on_user_return(struct user_return_notifier *urn)
187{
188 unsigned slot;
18863bdd
AK		 189 struct kvm_shared_msrs *locals
190 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 191 struct kvm_shared_msr_values *values;
18863bdd
AK		 192
193 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 194 values = &locals->values[slot];
195 if (values->host != values->curr) {
196 wrmsrl(shared_msrs_global.msrs[slot], values->host);
197 values->curr = values->host;
18863bdd
AK		 198 }
199 }
200 locals->registered = false;
201 user_return_notifier_unregister(urn);
202}
203
2bf78fa7 204static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 205{
18863bdd 206 u64 value;
013f6a5d
MT		 207 unsigned int cpu = smp_processor_id();
208 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 209
2bf78fa7
SY		 210 /* only read, and nobody should modify it at this time,
211 * so don't need lock */
212 if (slot >= shared_msrs_global.nr) {
213 printk(KERN_ERR "kvm: invalid MSR slot!");
214 return;
215 }
216 rdmsrl_safe(msr, &value);
217 smsr->values[slot].host = value;
218 smsr->values[slot].curr = value;
219}
220
221void kvm_define_shared_msr(unsigned slot, u32 msr)
222{
0123be42 223 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
18863bdd
AK		 224 if (slot >= shared_msrs_global.nr)
225 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 226 shared_msrs_global.msrs[slot] = msr;
227 /* we need ensured the shared_msr_global have been updated */
228 smp_wmb();
18863bdd
AK		 229}
230EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
231
232static void kvm_shared_msr_cpu_online(void)
233{
234 unsigned i;
18863bdd
AK		 235
236 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 237 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 238}
239
8b3c3104 240int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 241{
013f6a5d
MT		 242 unsigned int cpu = smp_processor_id();
243 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 244 int err;
18863bdd 245
2bf78fa7 246 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 247 return 0;
2bf78fa7 248 smsr->values[slot].curr = value;
8b3c3104
AH		 249 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
250 if (err)
251 return 1;
252
18863bdd
AK		 253 if (!smsr->registered) {
254 smsr->urn.on_user_return = kvm_on_user_return;
255 user_return_notifier_register(&smsr->urn);
256 smsr->registered = true;
257 }
8b3c3104 258 return 0;
18863bdd
AK		 259}
260EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
261
13a34e06 262static void drop_user_return_notifiers(void)
3548bab5 263{
013f6a5d
MT		 264 unsigned int cpu = smp_processor_id();
265 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 266
267 if (smsr->registered)
268 kvm_on_user_return(&smsr->urn);
269}
270
6866b83e
CO		 271u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
272{
8a5a87d9 273 return vcpu->arch.apic_base;
6866b83e
CO		 274}
275EXPORT_SYMBOL_GPL(kvm_get_apic_base);
276
58cb628d
JK		 277int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
278{
279 u64 old_state = vcpu->arch.apic_base &
280 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
281 u64 new_state = msr_info->data &
282 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
283 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
284 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
285
286 if (!msr_info->host_initiated &&
287 ((msr_info->data & reserved_bits) != 0 ||
288 new_state == X2APIC_ENABLE ||
289 (new_state == MSR_IA32_APICBASE_ENABLE &&
290 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
291 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
292 old_state == 0)))
293 return 1;
294
295 kvm_lapic_set_base(vcpu, msr_info->data);
296 return 0;
6866b83e
CO		 297}
298EXPORT_SYMBOL_GPL(kvm_set_apic_base);
299
2605fc21 300asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL		 301{
302 /* Fault while not rebooting. We want the trace. */
303 BUG();
304}
305EXPORT_SYMBOL_GPL(kvm_spurious_fault);
306
3fd28fce
ED		 307#define EXCPT_BENIGN 0
308#define EXCPT_CONTRIBUTORY 1
309#define EXCPT_PF 2
310
311static int exception_class(int vector)
312{
313 switch (vector) {
314 case PF_VECTOR:
315 return EXCPT_PF;
316 case DE_VECTOR:
317 case TS_VECTOR:
318 case NP_VECTOR:
319 case SS_VECTOR:
320 case GP_VECTOR:
321 return EXCPT_CONTRIBUTORY;
322 default:
323 break;
324 }
325 return EXCPT_BENIGN;
326}
327
d6e8c854
NA		 328#define EXCPT_FAULT 0
329#define EXCPT_TRAP 1
330#define EXCPT_ABORT 2
331#define EXCPT_INTERRUPT 3
332
333static int exception_type(int vector)
334{
335 unsigned int mask;
336
337 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
338 return EXCPT_INTERRUPT;
339
340 mask = 1 << vector;
341
342 /* #DB is trap, as instruction watchpoints are handled elsewhere */
343 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
344 return EXCPT_TRAP;
345
346 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
347 return EXCPT_ABORT;
348
349 /* Reserved exceptions will result in fault */
350 return EXCPT_FAULT;
351}
352
3fd28fce 353static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 354 unsigned nr, bool has_error, u32 error_code,
355 bool reinject)
3fd28fce
ED		 356{
357 u32 prev_nr;
358 int class1, class2;
359
3842d135
AK		 360 kvm_make_request(KVM_REQ_EVENT, vcpu);
361
3fd28fce
ED		 362 if (!vcpu->arch.exception.pending) {
363 queue:
3ffb2468
NA		 364 if (has_error && !is_protmode(vcpu))
365 has_error = false;
3fd28fce
ED		 366 vcpu->arch.exception.pending = true;
367 vcpu->arch.exception.has_error_code = has_error;
368 vcpu->arch.exception.nr = nr;
369 vcpu->arch.exception.error_code = error_code;
3f0fd292 370 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 371 return;
372 }
373
374 /* to check exception */
375 prev_nr = vcpu->arch.exception.nr;
376 if (prev_nr == DF_VECTOR) {
377 /* triple fault -> shutdown */
a8eeb04a 378 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 379 return;
380 }
381 class1 = exception_class(prev_nr);
382 class2 = exception_class(nr);
383 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
384 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
385 /* generate double fault per SDM Table 5-5 */
386 vcpu->arch.exception.pending = true;
387 vcpu->arch.exception.has_error_code = true;
388 vcpu->arch.exception.nr = DF_VECTOR;
389 vcpu->arch.exception.error_code = 0;
390 } else
391 /* replace previous exception with a new one in a hope
392 that instruction re-execution will regenerate lost
393 exception */
394 goto queue;
395}
396
298101da
AK		 397void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
398{
ce7ddec4 399 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 400}
401EXPORT_SYMBOL_GPL(kvm_queue_exception);
402
ce7ddec4
JR		 403void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
404{
405 kvm_multiple_exception(vcpu, nr, false, 0, true);
406}
407EXPORT_SYMBOL_GPL(kvm_requeue_exception);
408
db8fcefa 409void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 410{
db8fcefa
AP		 411 if (err)
412 kvm_inject_gp(vcpu, 0);
413 else
414 kvm_x86_ops->skip_emulated_instruction(vcpu);
415}
416EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 417
6389ee94 418void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 419{
420 ++vcpu->stat.pf_guest;
6389ee94
AK		 421 vcpu->arch.cr2 = fault->address;
422 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 423}
27d6c865 424EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 425
ef54bcfe 426static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 427{
6389ee94
AK		 428 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
429 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 430 else
6389ee94 431 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB		 432
433 return fault->nested_page_fault;
d4f8cf66
JR		 434}
435
3419ffc8
SY		 436void kvm_inject_nmi(struct kvm_vcpu *vcpu)
437{
7460fb4a
AK		 438 atomic_inc(&vcpu->arch.nmi_queued);
439 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 440}
441EXPORT_SYMBOL_GPL(kvm_inject_nmi);
442
298101da
AK		 443void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
444{
ce7ddec4 445 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 446}
447EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
448
ce7ddec4
JR		 449void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
450{
451 kvm_multiple_exception(vcpu, nr, true, error_code, true);
452}
453EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
454
0a79b009
AK		 455/*
456 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
457 * a #GP and return false.
458 */
459bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 460{
0a79b009
AK		 461 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
462 return true;
463 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
464 return false;
298101da 465}
0a79b009 466EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 467
16f8a6f9
NA		 468bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
469{
470 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
471 return true;
472
473 kvm_queue_exception(vcpu, UD_VECTOR);
474 return false;
475}
476EXPORT_SYMBOL_GPL(kvm_require_dr);
477
ec92fe44
JR		 478/*
479 * This function will be used to read from the physical memory of the currently
54bf36aa 480 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR		 481 * can read from guest physical or from the guest's guest physical memory.
482 */
483int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
484 gfn_t ngfn, void *data, int offset, int len,
485 u32 access)
486{
54987b7a 487 struct x86_exception exception;
ec92fe44
JR		 488 gfn_t real_gfn;
489 gpa_t ngpa;
490
491 ngpa = gfn_to_gpa(ngfn);
54987b7a 492 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR		 493 if (real_gfn == UNMAPPED_GVA)
494 return -EFAULT;
495
496 real_gfn = gpa_to_gfn(real_gfn);
497
54bf36aa 498 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR		 499}
500EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
501
69b0049a 502static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR		 503 void *data, int offset, int len, u32 access)
504{
505 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
506 data, offset, len, access);
507}
508
a03490ed
CO		 509/*
510 * Load the pae pdptrs. Return true is they are all valid.
511 */
ff03a073 512int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 513{
514 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
515 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
516 int i;
517 int ret;
ff03a073 518 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 519
ff03a073
JR		 520 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
521 offset * sizeof(u64), sizeof(pdpte),
522 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 523 if (ret < 0) {
524 ret = 0;
525 goto out;
526 }
527 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 528 if (is_present_gpte(pdpte[i]) &&
20c466b5 529 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 530 ret = 0;
531 goto out;
532 }
533 }
534 ret = 1;
535
ff03a073 536 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 537 __set_bit(VCPU_EXREG_PDPTR,
538 (unsigned long *)&vcpu->arch.regs_avail);
539 __set_bit(VCPU_EXREG_PDPTR,
540 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 541out:
a03490ed
CO		 542
543 return ret;
544}
cc4b6871 545EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 546
d835dfec
AK		 547static bool pdptrs_changed(struct kvm_vcpu *vcpu)
548{
ff03a073 549 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 550 bool changed = true;
3d06b8bf
JR		 551 int offset;
552 gfn_t gfn;
d835dfec
AK		 553 int r;
554
555 if (is_long_mode(vcpu) || !is_pae(vcpu))
556 return false;
557
6de4f3ad
AK		 558 if (!test_bit(VCPU_EXREG_PDPTR,
559 (unsigned long *)&vcpu->arch.regs_avail))
560 return true;
561
9f8fe504
AK		 562 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
563 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 564 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
565 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 566 if (r < 0)
567 goto out;
ff03a073 568 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 569out:
d835dfec
AK		 570
571 return changed;
572}
573
49a9b07e 574int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 575{
aad82703 576 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 577 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 578
f9a48e6a
AK		 579 cr0 |= X86_CR0_ET;
580
ab344828 581#ifdef CONFIG_X86_64
0f12244f
GN		 582 if (cr0 & 0xffffffff00000000UL)
583 return 1;
ab344828
GN		 584#endif
585
586 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 587
0f12244f
GN		 588 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
589 return 1;
a03490ed 590
0f12244f
GN		 591 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
592 return 1;
a03490ed
CO		 593
594 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
595#ifdef CONFIG_X86_64
f6801dff 596 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 597 int cs_db, cs_l;
598
0f12244f
GN		 599 if (!is_pae(vcpu))
600 return 1;
a03490ed 601 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 602 if (cs_l)
603 return 1;
a03490ed
CO		 604 } else
605#endif
ff03a073 606 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 607 kvm_read_cr3(vcpu)))
0f12244f 608 return 1;
a03490ed
CO		 609 }
610
ad756a16
MJ		 611 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
612 return 1;
613
a03490ed 614 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 615
d170c419 616 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 617 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 618 kvm_async_pf_hash_reset(vcpu);
619 }
e5f3f027 620
aad82703
SY		 621 if ((cr0 ^ old_cr0) & update_bits)
622 kvm_mmu_reset_context(vcpu);
b18d5431
XG		 623
624 if ((cr0 ^ old_cr0) & X86_CR0_CD)
625 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
626
0f12244f
GN		 627 return 0;
628}
2d3ad1f4 629EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 630
2d3ad1f4 631void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 632{
49a9b07e 633 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 634}
2d3ad1f4 635EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 636
42bdf991
MT		 637static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
638{
639 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
640 !vcpu->guest_xcr0_loaded) {
641 /* kvm_set_xcr() also depends on this */
642 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
643 vcpu->guest_xcr0_loaded = 1;
644 }
645}
646
647static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
648{
649 if (vcpu->guest_xcr0_loaded) {
650 if (vcpu->arch.xcr0 != host_xcr0)
651 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
652 vcpu->guest_xcr0_loaded = 0;
653 }
654}
655
69b0049a 656static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 657{
56c103ec
LJ		 658 u64 xcr0 = xcr;
659 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 660 u64 valid_bits;
2acf923e
DC		 661
662 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
663 if (index != XCR_XFEATURE_ENABLED_MASK)
664 return 1;
2acf923e
DC		 665 if (!(xcr0 & XSTATE_FP))
666 return 1;
667 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
668 return 1;
46c34cb0
PB		 669
670 /*
671 * Do not allow the guest to set bits that we do not support
672 * saving. However, xcr0 bit 0 is always set, even if the
673 * emulated CPU does not support XSAVE (see fx_init).
674 */
675 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
676 if (xcr0 & ~valid_bits)
2acf923e 677 return 1;
46c34cb0 678
390bd528
LJ		 679 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
680 return 1;
681
612263b3
CP		 682 if (xcr0 & XSTATE_AVX512) {
683 if (!(xcr0 & XSTATE_YMM))
684 return 1;
685 if ((xcr0 & XSTATE_AVX512) != XSTATE_AVX512)
686 return 1;
687 }
42bdf991 688 kvm_put_guest_xcr0(vcpu);
2acf923e 689 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 690
691 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
692 kvm_update_cpuid(vcpu);
2acf923e
DC		 693 return 0;
694}
695
696int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
697{
764bcbc5
Z		 698 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
699 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 700 kvm_inject_gp(vcpu, 0);
701 return 1;
702 }
703 return 0;
704}
705EXPORT_SYMBOL_GPL(kvm_set_xcr);
706
a83b29c6 707int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 708{
fc78f519 709 unsigned long old_cr4 = kvm_read_cr4(vcpu);
edc90b7d
XG		 710 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
711 X86_CR4_SMEP | X86_CR4_SMAP;
712
0f12244f
GN		 713 if (cr4 & CR4_RESERVED_BITS)
714 return 1;
a03490ed 715
2acf923e
DC		 716 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
717 return 1;
718
c68b734f
YW		 719 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
720 return 1;
721
97ec8c06
FW		 722 if (!guest_cpuid_has_smap(vcpu) && (cr4 & X86_CR4_SMAP))
723 return 1;
724
afcbf13f 725 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 726 return 1;
727
a03490ed 728 if (is_long_mode(vcpu)) {
0f12244f
GN		 729 if (!(cr4 & X86_CR4_PAE))
730 return 1;
a2edf57f
AK		 731 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
732 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 733 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
734 kvm_read_cr3(vcpu)))
0f12244f
GN		 735 return 1;
736
ad756a16
MJ		 737 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
738 if (!guest_cpuid_has_pcid(vcpu))
739 return 1;
740
741 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
742 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
743 return 1;
744 }
745
5e1746d6 746 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 747 return 1;
a03490ed 748
ad756a16
MJ		 749 if (((cr4 ^ old_cr4) & pdptr_bits) ||
750 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 751 kvm_mmu_reset_context(vcpu);
0f12244f 752
2acf923e 753 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 754 kvm_update_cpuid(vcpu);
2acf923e 755
0f12244f
GN		 756 return 0;
757}
2d3ad1f4 758EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 759
2390218b 760int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 761{
ac146235 762#ifdef CONFIG_X86_64
9d88fca7 763 cr3 &= ~CR3_PCID_INVD;
ac146235 764#endif
9d88fca7 765
9f8fe504 766 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 767 kvm_mmu_sync_roots(vcpu);
77c3913b 768 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 769 return 0;
d835dfec
AK		 770 }
771
a03490ed 772 if (is_long_mode(vcpu)) {
d9f89b88
JK		 773 if (cr3 & CR3_L_MODE_RESERVED_BITS)
774 return 1;
775 } else if (is_pae(vcpu) && is_paging(vcpu) &&
776 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 777 return 1;
a03490ed 778
0f12244f 779 vcpu->arch.cr3 = cr3;
aff48baa 780 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 781 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 782 return 0;
783}
2d3ad1f4 784EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 785
eea1cff9 786int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 787{
0f12244f
GN		 788 if (cr8 & CR8_RESERVED_BITS)
789 return 1;
a03490ed
CO		 790 if (irqchip_in_kernel(vcpu->kvm))
791 kvm_lapic_set_tpr(vcpu, cr8);
792 else
ad312c7c 793 vcpu->arch.cr8 = cr8;
0f12244f
GN		 794 return 0;
795}
2d3ad1f4 796EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 797
2d3ad1f4 798unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 799{
800 if (irqchip_in_kernel(vcpu->kvm))
801 return kvm_lapic_get_cr8(vcpu);
802 else
ad312c7c 803 return vcpu->arch.cr8;
a03490ed 804}
2d3ad1f4 805EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 806
ae561ede
NA		 807static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
808{
809 int i;
810
811 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
812 for (i = 0; i < KVM_NR_DB_REGS; i++)
813 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
814 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
815 }
816}
817
73aaf249
JK		 818static void kvm_update_dr6(struct kvm_vcpu *vcpu)
819{
820 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
821 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
822}
823
c8639010
JK		 824static void kvm_update_dr7(struct kvm_vcpu *vcpu)
825{
826 unsigned long dr7;
827
828 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
829 dr7 = vcpu->arch.guest_debug_dr7;
830 else
831 dr7 = vcpu->arch.dr7;
832 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB		 833 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
834 if (dr7 & DR7_BP_EN_MASK)
835 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK		 836}
837
6f43ed01
NA		 838static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
839{
840 u64 fixed = DR6_FIXED_1;
841
842 if (!guest_cpuid_has_rtm(vcpu))
843 fixed |= DR6_RTM;
844 return fixed;
845}
846
338dbc97 847static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 848{
849 switch (dr) {
850 case 0 ... 3:
851 vcpu->arch.db[dr] = val;
852 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
853 vcpu->arch.eff_db[dr] = val;
854 break;
855 case 4:
020df079
GN		 856 /* fall through */
857 case 6:
338dbc97
GN		 858 if (val & 0xffffffff00000000ULL)
859 return -1; /* #GP */
6f43ed01 860 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 861 kvm_update_dr6(vcpu);
020df079
GN		 862 break;
863 case 5:
020df079
GN		 864 /* fall through */
865 default: /* 7 */
338dbc97
GN		 866 if (val & 0xffffffff00000000ULL)
867 return -1; /* #GP */
020df079 868 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 869 kvm_update_dr7(vcpu);
020df079
GN		 870 break;
871 }
872
873 return 0;
874}
338dbc97
GN		 875
876int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
877{
16f8a6f9 878 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 879 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA		 880 return 1;
881 }
882 return 0;
338dbc97 883}
020df079
GN		 884EXPORT_SYMBOL_GPL(kvm_set_dr);
885
16f8a6f9 886int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 887{
888 switch (dr) {
889 case 0 ... 3:
890 *val = vcpu->arch.db[dr];
891 break;
892 case 4:
020df079
GN		 893 /* fall through */
894 case 6:
73aaf249
JK		 895 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
896 *val = vcpu->arch.dr6;
897 else
898 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 899 break;
900 case 5:
020df079
GN		 901 /* fall through */
902 default: /* 7 */
903 *val = vcpu->arch.dr7;
904 break;
905 }
338dbc97
GN		 906 return 0;
907}
020df079
GN		 908EXPORT_SYMBOL_GPL(kvm_get_dr);
909
022cd0e8
AK		 910bool kvm_rdpmc(struct kvm_vcpu *vcpu)
911{
912 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
913 u64 data;
914 int err;
915
916 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
917 if (err)
918 return err;
919 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
920 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
921 return err;
922}
923EXPORT_SYMBOL_GPL(kvm_rdpmc);
924
043405e1
CO		 925/*
926 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
927 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
928 *
929 * This list is modified at module load time to reflect the
e3267cbb 930 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB		 931 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
932 * may depend on host virtualization features rather than host cpu features.
043405e1 933 */
e3267cbb 934
043405e1
CO		 935static u32 msrs_to_save[] = {
936 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 937 MSR_STAR,
043405e1
CO		 938#ifdef CONFIG_X86_64
939 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
940#endif
b3897a49 941 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 942 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 943};
944
945static unsigned num_msrs_to_save;
946
62ef68bb
PB		 947static u32 emulated_msrs[] = {
948 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
949 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
950 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
951 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
952 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
953 MSR_KVM_PV_EOI_EN,
954
ba904635 955 MSR_IA32_TSC_ADJUST,
a3e06bbe 956 MSR_IA32_TSCDEADLINE,
043405e1 957 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 958 MSR_IA32_MCG_STATUS,
959 MSR_IA32_MCG_CTL,
64d60670 960 MSR_IA32_SMBASE,
043405e1
CO		 961};
962
62ef68bb
PB		 963static unsigned num_emulated_msrs;
964
384bb783 965bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 966{
b69e8cae 967 if (efer & efer_reserved_bits)
384bb783 968 return false;
15c4a640 969
1b2fd70c
AG		 970 if (efer & EFER_FFXSR) {
971 struct kvm_cpuid_entry2 *feat;
972
973 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 974 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 975 return false;
1b2fd70c
AG		 976 }
977
d8017474
AG		 978 if (efer & EFER_SVME) {
979 struct kvm_cpuid_entry2 *feat;
980
981 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 982 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 983 return false;
d8017474
AG		 984 }
985
384bb783
JK		 986 return true;
987}
988EXPORT_SYMBOL_GPL(kvm_valid_efer);
989
990static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
991{
992 u64 old_efer = vcpu->arch.efer;
993
994 if (!kvm_valid_efer(vcpu, efer))
995 return 1;
996
997 if (is_paging(vcpu)
998 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
999 return 1;
1000
15c4a640 1001 efer &= ~EFER_LMA;
f6801dff 1002 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1003
a3d204e2
SY		 1004 kvm_x86_ops->set_efer(vcpu, efer);
1005
aad82703
SY		 1006 /* Update reserved bits */
1007 if ((efer ^ old_efer) & EFER_NX)
1008 kvm_mmu_reset_context(vcpu);
1009
b69e8cae 1010 return 0;
15c4a640
CO		 1011}
1012
f2b4b7dd
JR		 1013void kvm_enable_efer_bits(u64 mask)
1014{
1015 efer_reserved_bits &= ~mask;
1016}
1017EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1018
15c4a640
CO		 1019/*
1020 * Writes msr value into into the appropriate "register".
1021 * Returns 0 on success, non-0 otherwise.
1022 * Assumes vcpu_load() was already called.
1023 */
8fe8ab46 1024int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1025{
854e8bb1
NA		 1026 switch (msr->index) {
1027 case MSR_FS_BASE:
1028 case MSR_GS_BASE:
1029 case MSR_KERNEL_GS_BASE:
1030 case MSR_CSTAR:
1031 case MSR_LSTAR:
1032 if (is_noncanonical_address(msr->data))
1033 return 1;
1034 break;
1035 case MSR_IA32_SYSENTER_EIP:
1036 case MSR_IA32_SYSENTER_ESP:
1037 /*
1038 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1039 * non-canonical address is written on Intel but not on
1040 * AMD (which ignores the top 32-bits, because it does
1041 * not implement 64-bit SYSENTER).
1042 *
1043 * 64-bit code should hence be able to write a non-canonical
1044 * value on AMD. Making the address canonical ensures that
1045 * vmentry does not fail on Intel after writing a non-canonical
1046 * value, and that something deterministic happens if the guest
1047 * invokes 64-bit SYSENTER.
1048 */
1049 msr->data = get_canonical(msr->data);
1050 }
8fe8ab46 1051 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1052}
854e8bb1 1053EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1054
313a3dc7
CO		 1055/*
1056 * Adapt set_msr() to msr_io()'s calling convention
1057 */
609e36d3
PB		 1058static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1059{
1060 struct msr_data msr;
1061 int r;
1062
1063 msr.index = index;
1064 msr.host_initiated = true;
1065 r = kvm_get_msr(vcpu, &msr);
1066 if (r)
1067 return r;
1068
1069 *data = msr.data;
1070 return 0;
1071}
1072
313a3dc7
CO		 1073static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1074{
8fe8ab46
WA		 1075 struct msr_data msr;
1076
1077 msr.data = *data;
1078 msr.index = index;
1079 msr.host_initiated = true;
1080 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 1081}
1082
16e8d74d
MT		 1083#ifdef CONFIG_X86_64
1084struct pvclock_gtod_data {
1085 seqcount_t seq;
1086
1087 struct { /* extract of a clocksource struct */
1088 int vclock_mode;
1089 cycle_t cycle_last;
1090 cycle_t mask;
1091 u32 mult;
1092 u32 shift;
1093 } clock;
1094
cbcf2dd3
TG		 1095 u64 boot_ns;
1096 u64 nsec_base;
16e8d74d
MT		 1097};
1098
1099static struct pvclock_gtod_data pvclock_gtod_data;
1100
1101static void update_pvclock_gtod(struct timekeeper *tk)
1102{
1103 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG		 1104 u64 boot_ns;
1105
876e7881 1106 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT		 1107
1108 write_seqcount_begin(&vdata->seq);
1109
1110 /* copy pvclock gtod data */
876e7881
PZ		 1111 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1112 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1113 vdata->clock.mask = tk->tkr_mono.mask;
1114 vdata->clock.mult = tk->tkr_mono.mult;
1115 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1116
cbcf2dd3 1117 vdata->boot_ns = boot_ns;
876e7881 1118 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d
MT		 1119
1120 write_seqcount_end(&vdata->seq);
1121}
1122#endif
1123
bab5bb39
NK		 1124void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1125{
1126 /*
1127 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1128 * vcpu_enter_guest. This function is only called from
1129 * the physical CPU that is running vcpu.
1130 */
1131 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1132}
16e8d74d 1133
18068523
GOC		 1134static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1135{
9ed3c444
AK		 1136 int version;
1137 int r;
50d0a0f9 1138 struct pvclock_wall_clock wc;
923de3cf 1139 struct timespec boot;
18068523
GOC		 1140
1141 if (!wall_clock)
1142 return;
1143
9ed3c444
AK		 1144 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1145 if (r)
1146 return;
1147
1148 if (version & 1)
1149 ++version; /* first time write, random junk */
1150
1151 ++version;
18068523 1152
18068523
GOC		 1153 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1154
50d0a0f9
GH		 1155 /*
1156 * The guest calculates current wall clock time by adding
34c238a1 1157 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1158 * wall clock specified here. guest system time equals host
1159 * system time for us, thus we must fill in host boot time here.
1160 */
923de3cf 1161 getboottime(&boot);
50d0a0f9 1162
4b648665
BR		 1163 if (kvm->arch.kvmclock_offset) {
1164 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1165 boot = timespec_sub(boot, ts);
1166 }
50d0a0f9
GH		 1167 wc.sec = boot.tv_sec;
1168 wc.nsec = boot.tv_nsec;
1169 wc.version = version;
18068523
GOC		 1170
1171 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1172
1173 version++;
1174 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1175}
1176
50d0a0f9
GH		 1177static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1178{
1179 uint32_t quotient, remainder;
1180
1181 /* Don't try to replace with do_div(), this one calculates
1182 * "(dividend << 32) / divisor" */
1183 __asm__ ( "divl %4"
1184 : "=a" (quotient), "=d" (remainder)
1185 : "0" (0), "1" (dividend), "r" (divisor) );
1186 return quotient;
1187}
1188
5f4e3f88
ZA		 1189static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1190 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1191{
5f4e3f88 1192 uint64_t scaled64;
50d0a0f9
GH		 1193 int32_t shift = 0;
1194 uint64_t tps64;
1195 uint32_t tps32;
1196
5f4e3f88
ZA		 1197 tps64 = base_khz * 1000LL;
1198 scaled64 = scaled_khz * 1000LL;
50933623 1199 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1200 tps64 >>= 1;
1201 shift--;
1202 }
1203
1204 tps32 = (uint32_t)tps64;
50933623
JK		 1205 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1206 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1207 scaled64 >>= 1;
1208 else
1209 tps32 <<= 1;
50d0a0f9
GH		 1210 shift++;
1211 }
1212
5f4e3f88
ZA		 1213 *pshift = shift;
1214 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1215
5f4e3f88
ZA		 1216 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1217 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1218}
1219
759379dd
ZA		 1220static inline u64 get_kernel_ns(void)
1221{
bb0b5812 1222 return ktime_get_boot_ns();
50d0a0f9
GH		 1223}
1224
d828199e 1225#ifdef CONFIG_X86_64
16e8d74d 1226static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1227#endif
16e8d74d 1228
c8076604 1229static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1230static unsigned long max_tsc_khz;
c8076604 1231
cc578287 1232static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1233{
cc578287
ZA		 1234 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1235 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1236}
1237
cc578287 1238static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1239{
cc578287
ZA		 1240 u64 v = (u64)khz * (1000000 + ppm);
1241 do_div(v, 1000000);
1242 return v;
1e993611
JR		 1243}
1244
cc578287 1245static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1246{
cc578287
ZA		 1247 u32 thresh_lo, thresh_hi;
1248 int use_scaling = 0;
217fc9cf 1249
03ba32ca
MT		 1250 /* tsc_khz can be zero if TSC calibration fails */
1251 if (this_tsc_khz == 0)
1252 return;
1253
c285545f
ZA		 1254 /* Compute a scale to convert nanoseconds in TSC cycles */
1255 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1256 &vcpu->arch.virtual_tsc_shift,
1257 &vcpu->arch.virtual_tsc_mult);
1258 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1259
1260 /*
1261 * Compute the variation in TSC rate which is acceptable
1262 * within the range of tolerance and decide if the
1263 * rate being applied is within that bounds of the hardware
1264 * rate. If so, no scaling or compensation need be done.
1265 */
1266 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1267 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1268 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1269 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1270 use_scaling = 1;
1271 }
1272 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1273}
1274
1275static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1276{
e26101b1 1277 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1278 vcpu->arch.virtual_tsc_mult,
1279 vcpu->arch.virtual_tsc_shift);
e26101b1 1280 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1281 return tsc;
1282}
1283
69b0049a 1284static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT		 1285{
1286#ifdef CONFIG_X86_64
1287 bool vcpus_matched;
b48aa97e
MT		 1288 struct kvm_arch *ka = &vcpu->kvm->arch;
1289 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1290
1291 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1292 atomic_read(&vcpu->kvm->online_vcpus));
1293
7f187922
MT		 1294 /*
1295 * Once the masterclock is enabled, always perform request in
1296 * order to update it.
1297 *
1298 * In order to enable masterclock, the host clocksource must be TSC
1299 * and the vcpus need to have matched TSCs. When that happens,
1300 * perform request to enable masterclock.
1301 */
1302 if (ka->use_master_clock ||
1303 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT		 1304 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1305
1306 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1307 atomic_read(&vcpu->kvm->online_vcpus),
1308 ka->use_master_clock, gtod->clock.vclock_mode);
1309#endif
1310}
1311
ba904635
WA		 1312static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1313{
1314 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1315 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1316}
1317
8fe8ab46 1318void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1319{
1320 struct kvm *kvm = vcpu->kvm;
f38e098f 1321 u64 offset, ns, elapsed;
99e3e30a 1322 unsigned long flags;
02626b6a 1323 s64 usdiff;
b48aa97e 1324 bool matched;
0d3da0d2 1325 bool already_matched;
8fe8ab46 1326 u64 data = msr->data;
99e3e30a 1327
038f8c11 1328 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1329 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1330 ns = get_kernel_ns();
f38e098f 1331 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1332
03ba32ca 1333 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1334 int faulted = 0;
1335
03ba32ca
MT		 1336 /* n.b - signed multiplication and division required */
1337 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1338#ifdef CONFIG_X86_64
03ba32ca 1339 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1340#else
03ba32ca 1341 /* do_div() only does unsigned */
8915aa27
MT		 1342 asm("1: idivl %[divisor]\n"
1343 "2: xor %%edx, %%edx\n"
1344 " movl $0, %[faulted]\n"
1345 "3:\n"
1346 ".section .fixup,\"ax\"\n"
1347 "4: movl $1, %[faulted]\n"
1348 " jmp 3b\n"
1349 ".previous\n"
1350
1351 _ASM_EXTABLE(1b, 4b)
1352
1353 : "=A"(usdiff), [faulted] "=r" (faulted)
1354 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1355
5d3cb0f6 1356#endif
03ba32ca
MT		 1357 do_div(elapsed, 1000);
1358 usdiff -= elapsed;
1359 if (usdiff < 0)
1360 usdiff = -usdiff;
8915aa27
MT		 1361
1362 /* idivl overflow => difference is larger than USEC_PER_SEC */
1363 if (faulted)
1364 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1365 } else
1366 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1367
1368 /*
5d3cb0f6
ZA		 1369 * Special case: TSC write with a small delta (1 second) of virtual
1370 * cycle time against real time is interpreted as an attempt to
1371 * synchronize the CPU.
1372 *
1373 * For a reliable TSC, we can match TSC offsets, and for an unstable
1374 * TSC, we add elapsed time in this computation. We could let the
1375 * compensation code attempt to catch up if we fall behind, but
1376 * it's better to try to match offsets from the beginning.
1377 */
02626b6a 1378 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1379 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1380 if (!check_tsc_unstable()) {
e26101b1 1381 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1382 pr_debug("kvm: matched tsc offset for %llu\n", data);
1383 } else {
857e4099 1384 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1385 data += delta;
1386 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1387 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1388 }
b48aa97e 1389 matched = true;
0d3da0d2 1390 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA		 1391 } else {
1392 /*
1393 * We split periods of matched TSC writes into generations.
1394 * For each generation, we track the original measured
1395 * nanosecond time, offset, and write, so if TSCs are in
1396 * sync, we can match exact offset, and if not, we can match
4a969980 1397 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1398 *
1399 * These values are tracked in kvm->arch.cur_xxx variables.
1400 */
1401 kvm->arch.cur_tsc_generation++;
1402 kvm->arch.cur_tsc_nsec = ns;
1403 kvm->arch.cur_tsc_write = data;
1404 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1405 matched = false;
0d3da0d2 1406 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1407 kvm->arch.cur_tsc_generation, data);
f38e098f 1408 }
e26101b1
ZA		 1409
1410 /*
1411 * We also track th most recent recorded KHZ, write and time to
1412 * allow the matching interval to be extended at each write.
1413 */
f38e098f
ZA		 1414 kvm->arch.last_tsc_nsec = ns;
1415 kvm->arch.last_tsc_write = data;
5d3cb0f6 1416 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1417
b183aa58 1418 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1419
1420 /* Keep track of which generation this VCPU has synchronized to */
1421 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1422 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1423 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1424
ba904635
WA		 1425 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1426 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1427 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1428 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1429
1430 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1431 if (!matched) {
b48aa97e 1432 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG		 1433 } else if (!already_matched) {
1434 kvm->arch.nr_vcpus_matched_tsc++;
1435 }
b48aa97e
MT		 1436
1437 kvm_track_tsc_matching(vcpu);
1438 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1439}
e26101b1 1440
99e3e30a
ZA		 1441EXPORT_SYMBOL_GPL(kvm_write_tsc);
1442
d828199e
MT		 1443#ifdef CONFIG_X86_64
1444
1445static cycle_t read_tsc(void)
1446{
1447 cycle_t ret;
1448 u64 last;
1449
1450 /*
1451 * Empirically, a fence (of type that depends on the CPU)
1452 * before rdtsc is enough to ensure that rdtsc is ordered
1453 * with respect to loads. The various CPU manuals are unclear
1454 * as to whether rdtsc can be reordered with later loads,
1455 * but no one has ever seen it happen.
1456 */
1457 rdtsc_barrier();
1458 ret = (cycle_t)vget_cycles();
1459
1460 last = pvclock_gtod_data.clock.cycle_last;
1461
1462 if (likely(ret >= last))
1463 return ret;
1464
1465 /*
1466 * GCC likes to generate cmov here, but this branch is extremely
1467 * predictable (it's just a funciton of time and the likely is
1468 * very likely) and there's a data dependence, so force GCC
1469 * to generate a branch instead. I don't barrier() because
1470 * we don't actually need a barrier, and if this function
1471 * ever gets inlined it will generate worse code.
1472 */
1473 asm volatile ("");
1474 return last;
1475}
1476
1477static inline u64 vgettsc(cycle_t *cycle_now)
1478{
1479 long v;
1480 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1481
1482 *cycle_now = read_tsc();
1483
1484 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1485 return v * gtod->clock.mult;
1486}
1487
cbcf2dd3 1488static int do_monotonic_boot(s64 *t, cycle_t *cycle_now)
d828199e 1489{
cbcf2dd3 1490 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1491 unsigned long seq;
d828199e 1492 int mode;
cbcf2dd3 1493 u64 ns;
d828199e 1494
d828199e
MT		 1495 do {
1496 seq = read_seqcount_begin(&gtod->seq);
1497 mode = gtod->clock.vclock_mode;
cbcf2dd3 1498 ns = gtod->nsec_base;
d828199e
MT		 1499 ns += vgettsc(cycle_now);
1500 ns >>= gtod->clock.shift;
cbcf2dd3 1501 ns += gtod->boot_ns;
d828199e 1502 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1503 *t = ns;
d828199e
MT		 1504
1505 return mode;
1506}
1507
1508/* returns true if host is using tsc clocksource */
1509static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1510{
d828199e
MT		 1511 /* checked again under seqlock below */
1512 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1513 return false;
1514
cbcf2dd3 1515 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e
MT		 1516}
1517#endif
1518
1519/*
1520 *
b48aa97e
MT		 1521 * Assuming a stable TSC across physical CPUS, and a stable TSC
1522 * across virtual CPUs, the following condition is possible.
1523 * Each numbered line represents an event visible to both
d828199e
MT		 1524 * CPUs at the next numbered event.
1525 *
1526 * "timespecX" represents host monotonic time. "tscX" represents
1527 * RDTSC value.
1528 *
1529 * VCPU0 on CPU0 | VCPU1 on CPU1
1530 *
1531 * 1. read timespec0,tsc0
1532 * 2. | timespec1 = timespec0 + N
1533 * | tsc1 = tsc0 + M
1534 * 3. transition to guest | transition to guest
1535 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1536 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1537 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1538 *
1539 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1540 *
1541 * - ret0 < ret1
1542 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1543 * ...
1544 * - 0 < N - M => M < N
1545 *
1546 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1547 * always the case (the difference between two distinct xtime instances
1548 * might be smaller then the difference between corresponding TSC reads,
1549 * when updating guest vcpus pvclock areas).
1550 *
1551 * To avoid that problem, do not allow visibility of distinct
1552 * system_timestamp/tsc_timestamp values simultaneously: use a master
1553 * copy of host monotonic time values. Update that master copy
1554 * in lockstep.
1555 *
b48aa97e 1556 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1557 *
1558 */
1559
1560static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1561{
1562#ifdef CONFIG_X86_64
1563 struct kvm_arch *ka = &kvm->arch;
1564 int vclock_mode;
b48aa97e
MT		 1565 bool host_tsc_clocksource, vcpus_matched;
1566
1567 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1568 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1569
1570 /*
1571 * If the host uses TSC clock, then passthrough TSC as stable
1572 * to the guest.
1573 */
b48aa97e 1574 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1575 &ka->master_kernel_ns,
1576 &ka->master_cycle_now);
1577
16a96021 1578 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
54750f2c
MT		 1579 && !backwards_tsc_observed
1580 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1581
d828199e
MT		 1582 if (ka->use_master_clock)
1583 atomic_set(&kvm_guest_has_master_clock, 1);
1584
1585 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1586 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1587 vcpus_matched);
d828199e
MT		 1588#endif
1589}
1590
2e762ff7
MT		 1591static void kvm_gen_update_masterclock(struct kvm *kvm)
1592{
1593#ifdef CONFIG_X86_64
1594 int i;
1595 struct kvm_vcpu *vcpu;
1596 struct kvm_arch *ka = &kvm->arch;
1597
1598 spin_lock(&ka->pvclock_gtod_sync_lock);
1599 kvm_make_mclock_inprogress_request(kvm);
1600 /* no guest entries from this point */
1601 pvclock_update_vm_gtod_copy(kvm);
1602
1603 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1604 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT		 1605
1606 /* guest entries allowed */
1607 kvm_for_each_vcpu(i, vcpu, kvm)
1608 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1609
1610 spin_unlock(&ka->pvclock_gtod_sync_lock);
1611#endif
1612}
1613
34c238a1 1614static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1615{
d828199e 1616 unsigned long flags, this_tsc_khz;
18068523 1617 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1618 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1619 s64 kernel_ns;
d828199e 1620 u64 tsc_timestamp, host_tsc;
0b79459b 1621 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1622 u8 pvclock_flags;
d828199e
MT		 1623 bool use_master_clock;
1624
1625 kernel_ns = 0;
1626 host_tsc = 0;
18068523 1627
d828199e
MT		 1628 /*
1629 * If the host uses TSC clock, then passthrough TSC as stable
1630 * to the guest.
1631 */
1632 spin_lock(&ka->pvclock_gtod_sync_lock);
1633 use_master_clock = ka->use_master_clock;
1634 if (use_master_clock) {
1635 host_tsc = ka->master_cycle_now;
1636 kernel_ns = ka->master_kernel_ns;
1637 }
1638 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1639
1640 /* Keep irq disabled to prevent changes to the clock */
1641 local_irq_save(flags);
89cbc767 1642 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
c09664bb
MT		 1643 if (unlikely(this_tsc_khz == 0)) {
1644 local_irq_restore(flags);
1645 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1646 return 1;
1647 }
d828199e
MT		 1648 if (!use_master_clock) {
1649 host_tsc = native_read_tsc();
1650 kernel_ns = get_kernel_ns();
1651 }
1652
1653 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1654
c285545f
ZA		 1655 /*
1656 * We may have to catch up the TSC to match elapsed wall clock
1657 * time for two reasons, even if kvmclock is used.
1658 * 1) CPU could have been running below the maximum TSC rate
1659 * 2) Broken TSC compensation resets the base at each VCPU
1660 * entry to avoid unknown leaps of TSC even when running
1661 * again on the same CPU. This may cause apparent elapsed
1662 * time to disappear, and the guest to stand still or run
1663 * very slowly.
1664 */
1665 if (vcpu->tsc_catchup) {
1666 u64 tsc = compute_guest_tsc(v, kernel_ns);
1667 if (tsc > tsc_timestamp) {
f1e2b260 1668 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1669 tsc_timestamp = tsc;
1670 }
50d0a0f9
GH		 1671 }
1672
18068523
GOC		 1673 local_irq_restore(flags);
1674
0b79459b 1675 if (!vcpu->pv_time_enabled)
c285545f 1676 return 0;
18068523 1677
e48672fa 1678 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1679 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1680 &vcpu->hv_clock.tsc_shift,
1681 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1682 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1683 }
1684
1685 /* With all the info we got, fill in the values */
1d5f066e 1686 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1687 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1688 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1689
09a0c3f1
OH		 1690 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1691 &guest_hv_clock, sizeof(guest_hv_clock))))
1692 return 0;
1693
5dca0d91
RK		 1694 /* This VCPU is paused, but it's legal for a guest to read another
1695 * VCPU's kvmclock, so we really have to follow the specification where
1696 * it says that version is odd if data is being modified, and even after
1697 * it is consistent.
1698 *
1699 * Version field updates must be kept separate. This is because
1700 * kvm_write_guest_cached might use a "rep movs" instruction, and
1701 * writes within a string instruction are weakly ordered. So there
1702 * are three writes overall.
1703 *
1704 * As a small optimization, only write the version field in the first
1705 * and third write. The vcpu->pv_time cache is still valid, because the
1706 * version field is the first in the struct.
18068523 1707 */
5dca0d91
RK		 1708 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1709
1710 vcpu->hv_clock.version = guest_hv_clock.version + 1;
1711 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1712 &vcpu->hv_clock,
1713 sizeof(vcpu->hv_clock.version));
1714
1715 smp_wmb();
78c0337a
MT		 1716
1717 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1718 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1719
1720 if (vcpu->pvclock_set_guest_stopped_request) {
1721 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1722 vcpu->pvclock_set_guest_stopped_request = false;
1723 }
1724
b7e60c5a
MT		 1725 pvclock_flags |= PVCLOCK_COUNTS_FROM_ZERO;
1726
d828199e
MT		 1727 /* If the host uses TSC clocksource, then it is stable */
1728 if (use_master_clock)
1729 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1730
78c0337a
MT		 1731 vcpu->hv_clock.flags = pvclock_flags;
1732
ce1a5e60
DM		 1733 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1734
0b79459b
AH		 1735 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1736 &vcpu->hv_clock,
1737 sizeof(vcpu->hv_clock));
5dca0d91
RK		 1738
1739 smp_wmb();
1740
1741 vcpu->hv_clock.version++;
1742 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1743 &vcpu->hv_clock,
1744 sizeof(vcpu->hv_clock.version));
8cfdc000 1745 return 0;
c8076604
GH		 1746}
1747
0061d53d
MT		 1748/*
1749 * kvmclock updates which are isolated to a given vcpu, such as
1750 * vcpu->cpu migration, should not allow system_timestamp from
1751 * the rest of the vcpus to remain static. Otherwise ntp frequency
1752 * correction applies to one vcpu's system_timestamp but not
1753 * the others.
1754 *
1755 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ		 1756 * We need to rate-limit these requests though, as they can
1757 * considerably slow guests that have a large number of vcpus.
1758 * The time for a remote vcpu to update its kvmclock is bound
1759 * by the delay we use to rate-limit the updates.
0061d53d
MT		 1760 */
1761
7e44e449
AJ		 1762#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
1763
1764static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT		 1765{
1766 int i;
7e44e449
AJ		 1767 struct delayed_work *dwork = to_delayed_work(work);
1768 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1769 kvmclock_update_work);
1770 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT		 1771 struct kvm_vcpu *vcpu;
1772
1773 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 1774 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT		 1775 kvm_vcpu_kick(vcpu);
1776 }
1777}
1778
7e44e449
AJ		 1779static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1780{
1781 struct kvm *kvm = v->kvm;
1782
105b21bb 1783 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ		 1784 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
1785 KVMCLOCK_UPDATE_DELAY);
1786}
1787
332967a3
AJ		 1788#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
1789
1790static void kvmclock_sync_fn(struct work_struct *work)
1791{
1792 struct delayed_work *dwork = to_delayed_work(work);
1793 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
1794 kvmclock_sync_work);
1795 struct kvm *kvm = container_of(ka, struct kvm, arch);
1796
630994b3
MT		 1797 if (!kvmclock_periodic_sync)
1798 return;
1799
332967a3
AJ		 1800 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
1801 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
1802 KVMCLOCK_SYNC_PERIOD);
1803}
1804
890ca9ae 1805static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1806{
890ca9ae
HY		 1807 u64 mcg_cap = vcpu->arch.mcg_cap;
1808 unsigned bank_num = mcg_cap & 0xff;
1809
15c4a640 1810 switch (msr) {
15c4a640 1811 case MSR_IA32_MCG_STATUS:
890ca9ae 1812 vcpu->arch.mcg_status = data;
15c4a640 1813 break;
c7ac679c 1814 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1815 if (!(mcg_cap & MCG_CTL_P))
1816 return 1;
1817 if (data != 0 && data != ~(u64)0)
1818 return -1;
1819 vcpu->arch.mcg_ctl = data;
1820 break;
1821 default:
1822 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 1823 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 1824 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1825 /* only 0 or all 1s can be written to IA32_MCi_CTL
1826 * some Linux kernels though clear bit 10 in bank 4 to
1827 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1828 * this to avoid an uncatched #GP in the guest
1829 */
890ca9ae 1830 if ((offset & 0x3) == 0 &&
114be429 1831 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1832 return -1;
1833 vcpu->arch.mce_banks[offset] = data;
1834 break;
1835 }
1836 return 1;
1837 }
1838 return 0;
1839}
1840
ffde22ac
ES		 1841static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1842{
1843 struct kvm *kvm = vcpu->kvm;
1844 int lm = is_long_mode(vcpu);
1845 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1846 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1847 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1848 : kvm->arch.xen_hvm_config.blob_size_32;
1849 u32 page_num = data & ~PAGE_MASK;
1850 u64 page_addr = data & PAGE_MASK;
1851 u8 *page;
1852 int r;
1853
1854 r = -E2BIG;
1855 if (page_num >= blob_size)
1856 goto out;
1857 r = -ENOMEM;
ff5c2c03
SL		 1858 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1859 if (IS_ERR(page)) {
1860 r = PTR_ERR(page);
ffde22ac 1861 goto out;
ff5c2c03 1862 }
54bf36aa 1863 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES		 1864 goto out_free;
1865 r = 0;
1866out_free:
1867 kfree(page);
1868out:
1869 return r;
1870}
1871
55cd8e5a
GN		 1872static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1873{
1874 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1875}
1876
1877static bool kvm_hv_msr_partition_wide(u32 msr)
1878{
1879 bool r = false;
1880 switch (msr) {
1881 case HV_X64_MSR_GUEST_OS_ID:
1882 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1883 case HV_X64_MSR_REFERENCE_TSC:
1884 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1885 r = true;
1886 break;
1887 }
1888
1889 return r;
1890}
1891
1892static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1893{
1894 struct kvm *kvm = vcpu->kvm;
1895
1896 switch (msr) {
1897 case HV_X64_MSR_GUEST_OS_ID:
1898 kvm->arch.hv_guest_os_id = data;
1899 /* setting guest os id to zero disables hypercall page */
1900 if (!kvm->arch.hv_guest_os_id)
1901 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1902 break;
1903 case HV_X64_MSR_HYPERCALL: {
1904 u64 gfn;
1905 unsigned long addr;
1906 u8 instructions[4];
1907
1908 /* if guest os id is not set hypercall should remain disabled */
1909 if (!kvm->arch.hv_guest_os_id)
1910 break;
1911 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1912 kvm->arch.hv_hypercall = data;
1913 break;
1914 }
1915 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1916 addr = gfn_to_hva(kvm, gfn);
1917 if (kvm_is_error_hva(addr))
1918 return 1;
1919 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1920 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1921 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1922 return 1;
1923 kvm->arch.hv_hypercall = data;
b94b64c9 1924 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1925 break;
1926 }
e984097b
VR		 1927 case HV_X64_MSR_REFERENCE_TSC: {
1928 u64 gfn;
1929 HV_REFERENCE_TSC_PAGE tsc_ref;
1930 memset(&tsc_ref, 0, sizeof(tsc_ref));
1931 kvm->arch.hv_tsc_page = data;
1932 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1933 break;
1934 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
e1fa108d 1935 if (kvm_write_guest(kvm, gfn << HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT,
e984097b
VR		 1936 &tsc_ref, sizeof(tsc_ref)))
1937 return 1;
1938 mark_page_dirty(kvm, gfn);
1939 break;
1940 }
55cd8e5a 1941 default:
a737f256
CD		 1942 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1943 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1944 return 1;
1945 }
1946 return 0;
1947}
1948
1949static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1950{
10388a07
GN		 1951 switch (msr) {
1952 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1953 u64 gfn;
10388a07 1954 unsigned long addr;
55cd8e5a 1955
10388a07
GN		 1956 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1957 vcpu->arch.hv_vapic = data;
b63cf42f
MT		 1958 if (kvm_lapic_enable_pv_eoi(vcpu, 0))
1959 return 1;
10388a07
GN		 1960 break;
1961 }
b3af1e88 1962 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
54bf36aa 1963 addr = kvm_vcpu_gfn_to_hva(vcpu, gfn);
10388a07
GN		 1964 if (kvm_is_error_hva(addr))
1965 return 1;
8b0cedff 1966 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1967 return 1;
1968 vcpu->arch.hv_vapic = data;
54bf36aa 1969 kvm_vcpu_mark_page_dirty(vcpu, gfn);
b63cf42f
MT		 1970 if (kvm_lapic_enable_pv_eoi(vcpu, gfn_to_gpa(gfn) | KVM_MSR_ENABLED))
1971 return 1;
10388a07
GN		 1972 break;
1973 }
1974 case HV_X64_MSR_EOI:
1975 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1976 case HV_X64_MSR_ICR:
1977 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1978 case HV_X64_MSR_TPR:
1979 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1980 default:
a737f256
CD		 1981 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1982 "data 0x%llx\n", msr, data);
10388a07
GN		 1983 return 1;
1984 }
1985
1986 return 0;
55cd8e5a
GN		 1987}
1988
344d9588
GN		 1989static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1990{
1991 gpa_t gpa = data & ~0x3f;
1992
4a969980 1993 /* Bits 2:5 are reserved, Should be zero */
6adba527 1994 if (data & 0x3c)
344d9588
GN		 1995 return 1;
1996
1997 vcpu->arch.apf.msr_val = data;
1998
1999 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2000 kvm_clear_async_pf_completion_queue(vcpu);
2001 kvm_async_pf_hash_reset(vcpu);
2002 return 0;
2003 }
2004
8f964525
AH		 2005 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
2006 sizeof(u32)))
344d9588
GN		 2007 return 1;
2008
6adba527 2009 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 2010 kvm_async_pf_wakeup_all(vcpu);
2011 return 0;
2012}
2013
12f9a48f
GC		 2014static void kvmclock_reset(struct kvm_vcpu *vcpu)
2015{
0b79459b 2016 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 2017}
2018
c9aaa895
GC		 2019static void accumulate_steal_time(struct kvm_vcpu *vcpu)
2020{
2021 u64 delta;
2022
2023 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2024 return;
2025
2026 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
2027 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2028 vcpu->arch.st.accum_steal = delta;
2029}
2030
2031static void record_steal_time(struct kvm_vcpu *vcpu)
2032{
2033 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2034 return;
2035
2036 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2037 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2038 return;
2039
2040 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
2041 vcpu->arch.st.steal.version += 2;
2042 vcpu->arch.st.accum_steal = 0;
2043
2044 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
2045 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2046}
2047
8fe8ab46 2048int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2049{
5753785f 2050 bool pr = false;
8fe8ab46
WA		 2051 u32 msr = msr_info->index;
2052 u64 data = msr_info->data;
5753785f 2053
15c4a640 2054 switch (msr) {
2e32b719
BP		 2055 case MSR_AMD64_NB_CFG:
2056 case MSR_IA32_UCODE_REV:
2057 case MSR_IA32_UCODE_WRITE:
2058 case MSR_VM_HSAVE_PA:
2059 case MSR_AMD64_PATCH_LOADER:
2060 case MSR_AMD64_BU_CFG2:
2061 break;
2062
15c4a640 2063 case MSR_EFER:
b69e8cae 2064 return set_efer(vcpu, data);
8f1589d9
AP		 2065 case MSR_K7_HWCR:
2066 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2067 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2068 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2069 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2070 if (data != 0) {
a737f256
CD		 2071 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2072 data);
8f1589d9
AP		 2073 return 1;
2074 }
15c4a640 2075 break;
f7c6d140
AP		 2076 case MSR_FAM10H_MMIO_CONF_BASE:
2077 if (data != 0) {
a737f256
CD		 2078 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2079 "0x%llx\n", data);
f7c6d140
AP		 2080 return 1;
2081 }
15c4a640 2082 break;
b5e2fec0
AG		 2083 case MSR_IA32_DEBUGCTLMSR:
2084 if (!data) {
2085 /* We support the non-activated case already */
2086 break;
2087 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2088 /* Values other than LBR and BTF are vendor-specific,
2089 thus reserved and should throw a #GP */
2090 return 1;
2091 }
a737f256
CD		 2092 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2093 __func__, data);
b5e2fec0 2094 break;
9ba075a6 2095 case 0x200 ... 0x2ff:
ff53604b 2096 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2097 case MSR_IA32_APICBASE:
58cb628d 2098 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2099 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2100 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2101 case MSR_IA32_TSCDEADLINE:
2102 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2103 break;
ba904635
WA		 2104 case MSR_IA32_TSC_ADJUST:
2105 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2106 if (!msr_info->host_initiated) {
d913b904 2107 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
ba904635
WA		 2108 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2109 }
2110 vcpu->arch.ia32_tsc_adjust_msr = data;
2111 }
2112 break;
15c4a640 2113 case MSR_IA32_MISC_ENABLE:
ad312c7c 2114 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2115 break;
64d60670
PB		 2116 case MSR_IA32_SMBASE:
2117 if (!msr_info->host_initiated)
2118 return 1;
2119 vcpu->arch.smbase = data;
2120 break;
11c6bffa 2121 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2122 case MSR_KVM_WALL_CLOCK:
2123 vcpu->kvm->arch.wall_clock = data;
2124 kvm_write_wall_clock(vcpu->kvm, data);
2125 break;
11c6bffa 2126 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2127 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2128 u64 gpa_offset;
54750f2c
MT		 2129 struct kvm_arch *ka = &vcpu->kvm->arch;
2130
12f9a48f 2131 kvmclock_reset(vcpu);
18068523 2132
54750f2c
MT		 2133 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2134 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2135
2136 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
2137 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
2138 &vcpu->requests);
2139
2140 ka->boot_vcpu_runs_old_kvmclock = tmp;
b7e60c5a
MT		 2141
2142 ka->kvmclock_offset = -get_kernel_ns();
54750f2c
MT		 2143 }
2144
18068523 2145 vcpu->arch.time = data;
0061d53d 2146 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2147
2148 /* we verify if the enable bit is set... */
2149 if (!(data & 1))
2150 break;
2151
0b79459b 2152 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2153
0b79459b 2154 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2155 &vcpu->arch.pv_time, data & ~1ULL,
2156 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2157 vcpu->arch.pv_time_enabled = false;
2158 else
2159 vcpu->arch.pv_time_enabled = true;
32cad84f 2160
18068523
GOC		 2161 break;
2162 }
344d9588
GN		 2163 case MSR_KVM_ASYNC_PF_EN:
2164 if (kvm_pv_enable_async_pf(vcpu, data))
2165 return 1;
2166 break;
c9aaa895
GC		 2167 case MSR_KVM_STEAL_TIME:
2168
2169 if (unlikely(!sched_info_on()))
2170 return 1;
2171
2172 if (data & KVM_STEAL_RESERVED_MASK)
2173 return 1;
2174
2175 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2176 data & KVM_STEAL_VALID_BITS,
2177 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2178 return 1;
2179
2180 vcpu->arch.st.msr_val = data;
2181
2182 if (!(data & KVM_MSR_ENABLED))
2183 break;
2184
2185 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2186
2187 preempt_disable();
2188 accumulate_steal_time(vcpu);
2189 preempt_enable();
2190
2191 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2192
2193 break;
ae7a2a3f
MT		 2194 case MSR_KVM_PV_EOI_EN:
2195 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2196 return 1;
2197 break;
c9aaa895 2198
890ca9ae
HY		 2199 case MSR_IA32_MCG_CTL:
2200 case MSR_IA32_MCG_STATUS:
81760dcc 2201 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
890ca9ae 2202 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2203
2204 /* Performance counters are not protected by a CPUID bit,
2205 * so we should check all of them in the generic path for the sake of
2206 * cross vendor migration.
2207 * Writing a zero into the event select MSRs disables them,
2208 * which we perfectly emulate ;-). Any other value should be at least
2209 * reported, some guests depend on them.
2210 */
71db6023
AP		 2211 case MSR_K7_EVNTSEL0:
2212 case MSR_K7_EVNTSEL1:
2213 case MSR_K7_EVNTSEL2:
2214 case MSR_K7_EVNTSEL3:
2215 if (data != 0)
a737f256
CD		 2216 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2217 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2218 break;
2219 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2220 * so we ignore writes to make it happy.
2221 */
71db6023
AP		 2222 case MSR_K7_PERFCTR0:
2223 case MSR_K7_PERFCTR1:
2224 case MSR_K7_PERFCTR2:
2225 case MSR_K7_PERFCTR3:
a737f256
CD		 2226 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2227 "0x%x data 0x%llx\n", msr, data);
71db6023 2228 break;
5753785f
GN		 2229 case MSR_P6_PERFCTR0:
2230 case MSR_P6_PERFCTR1:
2231 pr = true;
2232 case MSR_P6_EVNTSEL0:
2233 case MSR_P6_EVNTSEL1:
2234 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2235 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2236
2237 if (pr || data != 0)
a737f256
CD		 2238 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2239 "0x%x data 0x%llx\n", msr, data);
5753785f 2240 break;
84e0cefa
JS		 2241 case MSR_K7_CLK_CTL:
2242 /*
2243 * Ignore all writes to this no longer documented MSR.
2244 * Writes are only relevant for old K7 processors,
2245 * all pre-dating SVM, but a recommended workaround from
4a969980 2246 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2247 * affected processor models on the command line, hence
2248 * the need to ignore the workaround.
2249 */
2250 break;
55cd8e5a
GN		 2251 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2252 if (kvm_hv_msr_partition_wide(msr)) {
2253 int r;
2254 mutex_lock(&vcpu->kvm->lock);
2255 r = set_msr_hyperv_pw(vcpu, msr, data);
2256 mutex_unlock(&vcpu->kvm->lock);
2257 return r;
2258 } else
2259 return set_msr_hyperv(vcpu, msr, data);
2260 break;
91c9c3ed 2261 case MSR_IA32_BBL_CR_CTL3:
2262 /* Drop writes to this legacy MSR -- see rdmsr
2263 * counterpart for further detail.
2264 */
a737f256 2265 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2266 break;
2b036c6b
BO		 2267 case MSR_AMD64_OSVW_ID_LENGTH:
2268 if (!guest_cpuid_has_osvw(vcpu))
2269 return 1;
2270 vcpu->arch.osvw.length = data;
2271 break;
2272 case MSR_AMD64_OSVW_STATUS:
2273 if (!guest_cpuid_has_osvw(vcpu))
2274 return 1;
2275 vcpu->arch.osvw.status = data;
2276 break;
15c4a640 2277 default:
ffde22ac
ES		 2278 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2279 return xen_hvm_config(vcpu, data);
f5132b01 2280 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2281 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2282 if (!ignore_msrs) {
a737f256
CD		 2283 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2284 msr, data);
ed85c068
AP		 2285 return 1;
2286 } else {
a737f256
CD		 2287 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2288 msr, data);
ed85c068
AP		 2289 break;
2290 }
15c4a640
CO		 2291 }
2292 return 0;
2293}
2294EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2295
2296
2297/*
2298 * Reads an msr value (of 'msr_index') into 'pdata'.
2299 * Returns 0 on success, non-0 otherwise.
2300 * Assumes vcpu_load() was already called.
2301 */
609e36d3 2302int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2303{
609e36d3 2304 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2305}
ff651cb6 2306EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2307
890ca9ae 2308static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2309{
2310 u64 data;
890ca9ae
HY		 2311 u64 mcg_cap = vcpu->arch.mcg_cap;
2312 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2313
2314 switch (msr) {
15c4a640
CO		 2315 case MSR_IA32_P5_MC_ADDR:
2316 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2317 data = 0;
2318 break;
15c4a640 2319 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2320 data = vcpu->arch.mcg_cap;
2321 break;
c7ac679c 2322 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2323 if (!(mcg_cap & MCG_CTL_P))
2324 return 1;
2325 data = vcpu->arch.mcg_ctl;
2326 break;
2327 case MSR_IA32_MCG_STATUS:
2328 data = vcpu->arch.mcg_status;
2329 break;
2330 default:
2331 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2332 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY		 2333 u32 offset = msr - MSR_IA32_MC0_CTL;
2334 data = vcpu->arch.mce_banks[offset];
2335 break;
2336 }
2337 return 1;
2338 }
2339 *pdata = data;
2340 return 0;
2341}
2342
55cd8e5a
GN		 2343static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2344{
2345 u64 data = 0;
2346 struct kvm *kvm = vcpu->kvm;
2347
2348 switch (msr) {
2349 case HV_X64_MSR_GUEST_OS_ID:
2350 data = kvm->arch.hv_guest_os_id;
2351 break;
2352 case HV_X64_MSR_HYPERCALL:
2353 data = kvm->arch.hv_hypercall;
2354 break;
e984097b
VR		 2355 case HV_X64_MSR_TIME_REF_COUNT: {
2356 data =
2357 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2358 break;
2359 }
2360 case HV_X64_MSR_REFERENCE_TSC:
2361 data = kvm->arch.hv_tsc_page;
2362 break;
55cd8e5a 2363 default:
a737f256 2364 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2365 return 1;
2366 }
2367
2368 *pdata = data;
2369 return 0;
2370}
2371
2372static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2373{
2374 u64 data = 0;
2375
2376 switch (msr) {
2377 case HV_X64_MSR_VP_INDEX: {
2378 int r;
2379 struct kvm_vcpu *v;
684851a1
TY		 2380 kvm_for_each_vcpu(r, v, vcpu->kvm) {
2381 if (v == vcpu) {
55cd8e5a 2382 data = r;
684851a1
TY		 2383 break;
2384 }
2385 }
55cd8e5a
GN		 2386 break;
2387 }
10388a07
GN		 2388 case HV_X64_MSR_EOI:
2389 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2390 case HV_X64_MSR_ICR:
2391 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2392 case HV_X64_MSR_TPR:
2393 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2394 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2395 data = vcpu->arch.hv_vapic;
2396 break;
55cd8e5a 2397 default:
a737f256 2398 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2399 return 1;
2400 }
2401 *pdata = data;
2402 return 0;
2403}
2404
609e36d3 2405int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae
HY		 2406{
2407 u64 data;
2408
609e36d3 2409 switch (msr_info->index) {
890ca9ae 2410 case MSR_IA32_PLATFORM_ID:
15c4a640 2411 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2412 case MSR_IA32_DEBUGCTLMSR:
2413 case MSR_IA32_LASTBRANCHFROMIP:
2414 case MSR_IA32_LASTBRANCHTOIP:
2415 case MSR_IA32_LASTINTFROMIP:
2416 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2417 case MSR_K8_SYSCFG:
2418 case MSR_K7_HWCR:
61a6bd67 2419 case MSR_VM_HSAVE_PA:
9e699624 2420 case MSR_K7_EVNTSEL0:
dc9b2d93
WH		 2421 case MSR_K7_EVNTSEL1:
2422 case MSR_K7_EVNTSEL2:
2423 case MSR_K7_EVNTSEL3:
1f3ee616 2424 case MSR_K7_PERFCTR0:
dc9b2d93
WH		 2425 case MSR_K7_PERFCTR1:
2426 case MSR_K7_PERFCTR2:
2427 case MSR_K7_PERFCTR3:
1fdbd48c 2428 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2429 case MSR_AMD64_NB_CFG:
f7c6d140 2430 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2431 case MSR_AMD64_BU_CFG2:
609e36d3 2432 msr_info->data = 0;
15c4a640 2433 break;
5753785f
GN		 2434 case MSR_P6_PERFCTR0:
2435 case MSR_P6_PERFCTR1:
2436 case MSR_P6_EVNTSEL0:
2437 case MSR_P6_EVNTSEL1:
609e36d3
PB		 2438 if (kvm_pmu_msr(vcpu, msr_info->index))
2439 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2440 msr_info->data = 0;
5753785f 2441 break;
742bc670 2442 case MSR_IA32_UCODE_REV:
609e36d3 2443 msr_info->data = 0x100000000ULL;
742bc670 2444 break;
9ba075a6 2445 case MSR_MTRRcap:
609e36d3 2446 msr_info->data = 0x500 | KVM_NR_VAR_MTRR;
9ba075a6
AK		 2447 break;
2448 case 0x200 ... 0x2ff:
ff53604b 2449 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2450 case 0xcd: /* fsb frequency */
609e36d3 2451 msr_info->data = 3;
15c4a640 2452 break;
7b914098
JS		 2453 /*
2454 * MSR_EBC_FREQUENCY_ID
2455 * Conservative value valid for even the basic CPU models.
2456 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2457 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2458 * and 266MHz for model 3, or 4. Set Core Clock
2459 * Frequency to System Bus Frequency Ratio to 1 (bits
2460 * 31:24) even though these are only valid for CPU
2461 * models > 2, however guests may end up dividing or
2462 * multiplying by zero otherwise.
2463 */
2464 case MSR_EBC_FREQUENCY_ID:
609e36d3 2465 msr_info->data = 1 << 24;
7b914098 2466 break;
15c4a640 2467 case MSR_IA32_APICBASE:
609e36d3 2468 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2469 break;
0105d1a5 2470 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2471 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2472 break;
a3e06bbe 2473 case MSR_IA32_TSCDEADLINE:
609e36d3 2474 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2475 break;
ba904635 2476 case MSR_IA32_TSC_ADJUST:
609e36d3 2477 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2478 break;
15c4a640 2479 case MSR_IA32_MISC_ENABLE:
609e36d3 2480 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2481 break;
64d60670
PB		 2482 case MSR_IA32_SMBASE:
2483 if (!msr_info->host_initiated)
2484 return 1;
2485 msr_info->data = vcpu->arch.smbase;
2486 break;
847f0ad8
AG		 2487 case MSR_IA32_PERF_STATUS:
2488 /* TSC increment by tick */
609e36d3 2489 msr_info->data = 1000ULL;
847f0ad8
AG		 2490 /* CPU multiplier */
2491 data |= (((uint64_t)4ULL) << 40);
2492 break;
15c4a640 2493 case MSR_EFER:
609e36d3 2494 msr_info->data = vcpu->arch.efer;
15c4a640 2495 break;
18068523 2496 case MSR_KVM_WALL_CLOCK:
11c6bffa 2497 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2498 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC		 2499 break;
2500 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2501 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2502 msr_info->data = vcpu->arch.time;
18068523 2503 break;
344d9588 2504 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2505 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2506 break;
c9aaa895 2507 case MSR_KVM_STEAL_TIME:
609e36d3 2508 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2509 break;
1d92128f 2510 case MSR_KVM_PV_EOI_EN:
609e36d3 2511 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2512 break;
890ca9ae
HY		 2513 case MSR_IA32_P5_MC_ADDR:
2514 case MSR_IA32_P5_MC_TYPE:
2515 case MSR_IA32_MCG_CAP:
2516 case MSR_IA32_MCG_CTL:
2517 case MSR_IA32_MCG_STATUS:
81760dcc 2518 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2519 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS		 2520 case MSR_K7_CLK_CTL:
2521 /*
2522 * Provide expected ramp-up count for K7. All other
2523 * are set to zero, indicating minimum divisors for
2524 * every field.
2525 *
2526 * This prevents guest kernels on AMD host with CPU
2527 * type 6, model 8 and higher from exploding due to
2528 * the rdmsr failing.
2529 */
609e36d3 2530 msr_info->data = 0x20000000;
84e0cefa 2531 break;
55cd8e5a 2532 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
609e36d3 2533 if (kvm_hv_msr_partition_wide(msr_info->index)) {
55cd8e5a
GN		 2534 int r;
2535 mutex_lock(&vcpu->kvm->lock);
609e36d3 2536 r = get_msr_hyperv_pw(vcpu, msr_info->index, &msr_info->data);
55cd8e5a
GN		 2537 mutex_unlock(&vcpu->kvm->lock);
2538 return r;
2539 } else
609e36d3 2540 return get_msr_hyperv(vcpu, msr_info->index, &msr_info->data);
55cd8e5a 2541 break;
91c9c3ed 2542 case MSR_IA32_BBL_CR_CTL3:
2543 /* This legacy MSR exists but isn't fully documented in current
2544 * silicon. It is however accessed by winxp in very narrow
2545 * scenarios where it sets bit #19, itself documented as
2546 * a "reserved" bit. Best effort attempt to source coherent
2547 * read data here should the balance of the register be
2548 * interpreted by the guest:
2549 *
2550 * L2 cache control register 3: 64GB range, 256KB size,
2551 * enabled, latency 0x1, configured
2552 */
609e36d3 2553 msr_info->data = 0xbe702111;
91c9c3ed 2554 break;
2b036c6b
BO		 2555 case MSR_AMD64_OSVW_ID_LENGTH:
2556 if (!guest_cpuid_has_osvw(vcpu))
2557 return 1;
609e36d3 2558 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO		 2559 break;
2560 case MSR_AMD64_OSVW_STATUS:
2561 if (!guest_cpuid_has_osvw(vcpu))
2562 return 1;
609e36d3 2563 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2564 break;
15c4a640 2565 default:
609e36d3
PB		 2566 if (kvm_pmu_msr(vcpu, msr_info->index))
2567 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2568 if (!ignore_msrs) {
609e36d3 2569 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr_info->index);
ed85c068
AP		 2570 return 1;
2571 } else {
609e36d3
PB		 2572 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr_info->index);
2573 msr_info->data = 0;
ed85c068
AP		 2574 }
2575 break;
15c4a640 2576 }
15c4a640
CO		 2577 return 0;
2578}
2579EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2580
313a3dc7
CO		 2581/*
2582 * Read or write a bunch of msrs. All parameters are kernel addresses.
2583 *
2584 * @return number of msrs set successfully.
2585 */
2586static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2587 struct kvm_msr_entry *entries,
2588 int (*do_msr)(struct kvm_vcpu *vcpu,
2589 unsigned index, u64 *data))
2590{
f656ce01 2591 int i, idx;
313a3dc7 2592
f656ce01 2593 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2594 for (i = 0; i < msrs->nmsrs; ++i)
2595 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2596 break;
f656ce01 2597 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2598
313a3dc7
CO		 2599 return i;
2600}
2601
2602/*
2603 * Read or write a bunch of msrs. Parameters are user addresses.
2604 *
2605 * @return number of msrs set successfully.
2606 */
2607static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2608 int (*do_msr)(struct kvm_vcpu *vcpu,
2609 unsigned index, u64 *data),
2610 int writeback)
2611{
2612 struct kvm_msrs msrs;
2613 struct kvm_msr_entry *entries;
2614 int r, n;
2615 unsigned size;
2616
2617 r = -EFAULT;
2618 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2619 goto out;
2620
2621 r = -E2BIG;
2622 if (msrs.nmsrs >= MAX_IO_MSRS)
2623 goto out;
2624
313a3dc7 2625 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2626 entries = memdup_user(user_msrs->entries, size);
2627 if (IS_ERR(entries)) {
2628 r = PTR_ERR(entries);
313a3dc7 2629 goto out;
ff5c2c03 2630 }
313a3dc7
CO		 2631
2632 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2633 if (r < 0)
2634 goto out_free;
2635
2636 r = -EFAULT;
2637 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2638 goto out_free;
2639
2640 r = n;
2641
2642out_free:
7a73c028 2643 kfree(entries);
313a3dc7
CO		 2644out:
2645 return r;
2646}
2647
784aa3d7 2648int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX		 2649{
2650 int r;
2651
2652 switch (ext) {
2653 case KVM_CAP_IRQCHIP:
2654 case KVM_CAP_HLT:
2655 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2656 case KVM_CAP_SET_TSS_ADDR:
07716717 2657 case KVM_CAP_EXT_CPUID:
9c15bb1d 2658 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2659 case KVM_CAP_CLOCKSOURCE:
7837699f 2660 case KVM_CAP_PIT:
a28e4f5a 2661 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2662 case KVM_CAP_MP_STATE:
ed848624 2663 case KVM_CAP_SYNC_MMU:
a355c85c 2664 case KVM_CAP_USER_NMI:
52d939a0 2665 case KVM_CAP_REINJECT_CONTROL:
4925663a 2666 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2667 case KVM_CAP_IOEVENTFD:
f848a5a8 2668 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2669 case KVM_CAP_PIT2:
e9f42757 2670 case KVM_CAP_PIT_STATE2:
b927a3ce 2671 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2672 case KVM_CAP_XEN_HVM:
afbcf7ab 2673 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2674 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2675 case KVM_CAP_HYPERV:
10388a07 2676 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2677 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2678 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2679 case KVM_CAP_DEBUGREGS:
d2be1651 2680 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2681 case KVM_CAP_XSAVE:
344d9588 2682 case KVM_CAP_ASYNC_PF:
92a1f12d 2683 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2684 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2685 case KVM_CAP_READONLY_MEM:
5f66b620 2686 case KVM_CAP_HYPERV_TIME:
100943c5 2687 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2688 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA		 2689 case KVM_CAP_ENABLE_CAP_VM:
2690 case KVM_CAP_DISABLE_QUIRKS:
2a5bab10
AW		 2691#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2692 case KVM_CAP_ASSIGN_DEV_IRQ:
2693 case KVM_CAP_PCI_2_3:
2694#endif
018d00d2
ZX		 2695 r = 1;
2696 break;
6d396b55
PB		 2697 case KVM_CAP_X86_SMM:
2698 /* SMBASE is usually relocated above 1M on modern chipsets,
2699 * and SMM handlers might indeed rely on 4G segment limits,
2700 * so do not report SMM to be available if real mode is
2701 * emulated via vm86 mode. Still, do not go to great lengths
2702 * to avoid userspace's usage of the feature, because it is a
2703 * fringe case that is not enabled except via specific settings
2704 * of the module parameters.
2705 */
2706 r = kvm_x86_ops->cpu_has_high_real_mode_segbase();
2707 break;
542472b5
LV		 2708 case KVM_CAP_COALESCED_MMIO:
2709 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2710 break;
774ead3a
AK		 2711 case KVM_CAP_VAPIC:
2712 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2713 break;
f725230a 2714 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2715 r = KVM_SOFT_MAX_VCPUS;
2716 break;
2717 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2718 r = KVM_MAX_VCPUS;
2719 break;
a988b910 2720 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2721 r = KVM_USER_MEM_SLOTS;
a988b910 2722 break;
a68a6a72
MT		 2723 case KVM_CAP_PV_MMU: /* obsolete */
2724 r = 0;
2f333bcb 2725 break;
4cee4b72 2726#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2727 case KVM_CAP_IOMMU:
a1b60c1c 2728 r = iommu_present(&pci_bus_type);
62c476c7 2729 break;
4cee4b72 2730#endif
890ca9ae
HY		 2731 case KVM_CAP_MCE:
2732 r = KVM_MAX_MCE_BANKS;
2733 break;
2d5b5a66
SY		 2734 case KVM_CAP_XCRS:
2735 r = cpu_has_xsave;
2736 break;
92a1f12d
JR		 2737 case KVM_CAP_TSC_CONTROL:
2738 r = kvm_has_tsc_control;
2739 break;
018d00d2
ZX		 2740 default:
2741 r = 0;
2742 break;
2743 }
2744 return r;
2745
2746}
2747
043405e1
CO		 2748long kvm_arch_dev_ioctl(struct file *filp,
2749 unsigned int ioctl, unsigned long arg)
2750{
2751 void __user *argp = (void __user *)arg;
2752 long r;
2753
2754 switch (ioctl) {
2755 case KVM_GET_MSR_INDEX_LIST: {
2756 struct kvm_msr_list __user *user_msr_list = argp;
2757 struct kvm_msr_list msr_list;
2758 unsigned n;
2759
2760 r = -EFAULT;
2761 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2762 goto out;
2763 n = msr_list.nmsrs;
62ef68bb 2764 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO		 2765 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2766 goto out;
2767 r = -E2BIG;
e125e7b6 2768 if (n < msr_list.nmsrs)
043405e1
CO		 2769 goto out;
2770 r = -EFAULT;
2771 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2772 num_msrs_to_save * sizeof(u32)))
2773 goto out;
e125e7b6 2774 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2775 &emulated_msrs,
62ef68bb 2776 num_emulated_msrs * sizeof(u32)))
043405e1
CO		 2777 goto out;
2778 r = 0;
2779 break;
2780 }
9c15bb1d
BP		 2781 case KVM_GET_SUPPORTED_CPUID:
2782 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2783 struct kvm_cpuid2 __user *cpuid_arg = argp;
2784 struct kvm_cpuid2 cpuid;
2785
2786 r = -EFAULT;
2787 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2788 goto out;
9c15bb1d
BP		 2789
2790 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2791 ioctl);
674eea0f
AK		 2792 if (r)
2793 goto out;
2794
2795 r = -EFAULT;
2796 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2797 goto out;
2798 r = 0;
2799 break;
2800 }
890ca9ae
HY		 2801 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2802 u64 mce_cap;
2803
2804 mce_cap = KVM_MCE_CAP_SUPPORTED;
2805 r = -EFAULT;
2806 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2807 goto out;
2808 r = 0;
2809 break;
2810 }
043405e1
CO		 2811 default:
2812 r = -EINVAL;
2813 }
2814out:
2815 return r;
2816}
2817
f5f48ee1
SY		 2818static void wbinvd_ipi(void *garbage)
2819{
2820 wbinvd();
2821}
2822
2823static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2824{
e0f0bbc5 2825 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2826}
2827
313a3dc7
CO		 2828void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2829{
f5f48ee1
SY		 2830 /* Address WBINVD may be executed by guest */
2831 if (need_emulate_wbinvd(vcpu)) {
2832 if (kvm_x86_ops->has_wbinvd_exit())
2833 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2834 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2835 smp_call_function_single(vcpu->cpu,
2836 wbinvd_ipi, NULL, 1);
2837 }
2838
313a3dc7 2839 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2840
0dd6a6ed
ZA		 2841 /* Apply any externally detected TSC adjustments (due to suspend) */
2842 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2843 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2844 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2845 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2846 }
8f6055cb 2847
48434c20 2848 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2849 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2850 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2851 if (tsc_delta < 0)
2852 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2853 if (check_tsc_unstable()) {
b183aa58
ZA		 2854 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2855 vcpu->arch.last_guest_tsc);
2856 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2857 vcpu->arch.tsc_catchup = 1;
c285545f 2858 }
d98d07ca
MT		 2859 /*
2860 * On a host with synchronized TSC, there is no need to update
2861 * kvmclock on vcpu->cpu migration
2862 */
2863 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2864 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2865 if (vcpu->cpu != cpu)
2866 kvm_migrate_timers(vcpu);
e48672fa 2867 vcpu->cpu = cpu;
6b7d7e76 2868 }
c9aaa895
GC		 2869
2870 accumulate_steal_time(vcpu);
2871 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2872}
2873
2874void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2875{
02daab21 2876 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2877 kvm_put_guest_fpu(vcpu);
6f526ec5 2878 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2879}
2880
313a3dc7
CO		 2881static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2882 struct kvm_lapic_state *s)
2883{
5a71785d 2884 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2885 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2886
2887 return 0;
2888}
2889
2890static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2891 struct kvm_lapic_state *s)
2892{
64eb0620 2893 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2894 update_cr8_intercept(vcpu);
313a3dc7
CO		 2895
2896 return 0;
2897}
2898
f77bc6a4
ZX		 2899static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2900 struct kvm_interrupt *irq)
2901{
02cdb50f 2902 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2903 return -EINVAL;
2904 if (irqchip_in_kernel(vcpu->kvm))
2905 return -ENXIO;
f77bc6a4 2906
66fd3f7f 2907 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2908 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2909
f77bc6a4
ZX		 2910 return 0;
2911}
2912
c4abb7c9
JK		 2913static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2914{
c4abb7c9 2915 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2916
2917 return 0;
2918}
2919
f077825a
PB		 2920static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
2921{
64d60670
PB		 2922 kvm_make_request(KVM_REQ_SMI, vcpu);
2923
f077825a
PB		 2924 return 0;
2925}
2926
b209749f
AK		 2927static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2928 struct kvm_tpr_access_ctl *tac)
2929{
2930 if (tac->flags)
2931 return -EINVAL;
2932 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2933 return 0;
2934}
2935
890ca9ae
HY		 2936static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2937 u64 mcg_cap)
2938{
2939 int r;
2940 unsigned bank_num = mcg_cap & 0xff, bank;
2941
2942 r = -EINVAL;
a9e38c3e 2943 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2944 goto out;
2945 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2946 goto out;
2947 r = 0;
2948 vcpu->arch.mcg_cap = mcg_cap;
2949 /* Init IA32_MCG_CTL to all 1s */
2950 if (mcg_cap & MCG_CTL_P)
2951 vcpu->arch.mcg_ctl = ~(u64)0;
2952 /* Init IA32_MCi_CTL to all 1s */
2953 for (bank = 0; bank < bank_num; bank++)
2954 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2955out:
2956 return r;
2957}
2958
2959static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2960 struct kvm_x86_mce *mce)
2961{
2962 u64 mcg_cap = vcpu->arch.mcg_cap;
2963 unsigned bank_num = mcg_cap & 0xff;
2964 u64 *banks = vcpu->arch.mce_banks;
2965
2966 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2967 return -EINVAL;
2968 /*
2969 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2970 * reporting is disabled
2971 */
2972 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2973 vcpu->arch.mcg_ctl != ~(u64)0)
2974 return 0;
2975 banks += 4 * mce->bank;
2976 /*
2977 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2978 * reporting is disabled for the bank
2979 */
2980 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2981 return 0;
2982 if (mce->status & MCI_STATUS_UC) {
2983 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2984 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2985 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2986 return 0;
2987 }
2988 if (banks[1] & MCI_STATUS_VAL)
2989 mce->status |= MCI_STATUS_OVER;
2990 banks[2] = mce->addr;
2991 banks[3] = mce->misc;
2992 vcpu->arch.mcg_status = mce->mcg_status;
2993 banks[1] = mce->status;
2994 kvm_queue_exception(vcpu, MC_VECTOR);
2995 } else if (!(banks[1] & MCI_STATUS_VAL)
2996 || !(banks[1] & MCI_STATUS_UC)) {
2997 if (banks[1] & MCI_STATUS_VAL)
2998 mce->status |= MCI_STATUS_OVER;
2999 banks[2] = mce->addr;
3000 banks[3] = mce->misc;
3001 banks[1] = mce->status;
3002 } else
3003 banks[1] |= MCI_STATUS_OVER;
3004 return 0;
3005}
3006
3cfc3092
JK		 3007static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3008 struct kvm_vcpu_events *events)
3009{
7460fb4a 3010 process_nmi(vcpu);
03b82a30
JK		 3011 events->exception.injected =
3012 vcpu->arch.exception.pending &&
3013 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 3014 events->exception.nr = vcpu->arch.exception.nr;
3015 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3016 events->exception.pad = 0;
3cfc3092
JK		 3017 events->exception.error_code = vcpu->arch.exception.error_code;
3018
03b82a30
JK		 3019 events->interrupt.injected =
3020 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3021 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3022 events->interrupt.soft = 0;
37ccdcbe 3023 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK		 3024
3025 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3026 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3027 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3028 events->nmi.pad = 0;
3cfc3092 3029
66450a21 3030 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3031
f077825a
PB		 3032 events->smi.smm = is_smm(vcpu);
3033 events->smi.pending = vcpu->arch.smi_pending;
3034 events->smi.smm_inside_nmi =
3035 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3036 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3037
dab4b911 3038 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB		 3039 | KVM_VCPUEVENT_VALID_SHADOW
3040 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3041 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 3042}
3043
3044static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3045 struct kvm_vcpu_events *events)
3046{
dab4b911 3047 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3048 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB		 3049 | KVM_VCPUEVENT_VALID_SHADOW
3050 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK		 3051 return -EINVAL;
3052
7460fb4a 3053 process_nmi(vcpu);
3cfc3092
JK		 3054 vcpu->arch.exception.pending = events->exception.injected;
3055 vcpu->arch.exception.nr = events->exception.nr;
3056 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3057 vcpu->arch.exception.error_code = events->exception.error_code;
3058
3059 vcpu->arch.interrupt.pending = events->interrupt.injected;
3060 vcpu->arch.interrupt.nr = events->interrupt.nr;
3061 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 3062 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3063 kvm_x86_ops->set_interrupt_shadow(vcpu,
3064 events->interrupt.shadow);
3cfc3092
JK		 3065
3066 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 3067 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3068 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 3069 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3070
66450a21
JK		 3071 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
3072 kvm_vcpu_has_lapic(vcpu))
3073 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3074
f077825a
PB		 3075 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
3076 if (events->smi.smm)
3077 vcpu->arch.hflags |= HF_SMM_MASK;
3078 else
3079 vcpu->arch.hflags &= ~HF_SMM_MASK;
3080 vcpu->arch.smi_pending = events->smi.pending;
3081 if (events->smi.smm_inside_nmi)
3082 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
3083 else
3084 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3085 if (kvm_vcpu_has_lapic(vcpu)) {
3086 if (events->smi.latched_init)
3087 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3088 else
3089 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3090 }
3091 }
3092
3842d135
AK		 3093 kvm_make_request(KVM_REQ_EVENT, vcpu);
3094
3cfc3092
JK		 3095 return 0;
3096}
3097
a1efbe77
JK		 3098static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3099 struct kvm_debugregs *dbgregs)
3100{
73aaf249
JK		 3101 unsigned long val;
3102
a1efbe77 3103 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3104 kvm_get_dr(vcpu, 6, &val);
73aaf249 3105 dbgregs->dr6 = val;
a1efbe77
JK		 3106 dbgregs->dr7 = vcpu->arch.dr7;
3107 dbgregs->flags = 0;
97e69aa6 3108 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3109}
3110
3111static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3112 struct kvm_debugregs *dbgregs)
3113{
3114 if (dbgregs->flags)
3115 return -EINVAL;
3116
a1efbe77 3117 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3118 kvm_update_dr0123(vcpu);
a1efbe77 3119 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3120 kvm_update_dr6(vcpu);
a1efbe77 3121 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3122 kvm_update_dr7(vcpu);
a1efbe77 3123
a1efbe77
JK		 3124 return 0;
3125}
3126
df1daba7
PB		 3127#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3128
3129static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3130{
3131 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3132 u64 xstate_bv = xsave->xsave_hdr.xstate_bv;
3133 u64 valid;
3134
3135 /*
3136 * Copy legacy XSAVE area, to avoid complications with CPUID
3137 * leaves 0 and 1 in the loop below.
3138 */
3139 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3140
3141 /* Set XSTATE_BV */
3142 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3143
3144 /*
3145 * Copy each region from the possibly compacted offset to the
3146 * non-compacted offset.
3147 */
3148 valid = xstate_bv & ~XSTATE_FPSSE;
3149 while (valid) {
3150 u64 feature = valid & -valid;
3151 int index = fls64(feature) - 1;
3152 void *src = get_xsave_addr(xsave, feature);
3153
3154 if (src) {
3155 u32 size, offset, ecx, edx;
3156 cpuid_count(XSTATE_CPUID, index,
3157 &size, &offset, &ecx, &edx);
3158 memcpy(dest + offset, src, size);
3159 }
3160
3161 valid -= feature;
3162 }
3163}
3164
3165static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3166{
3167 struct xsave_struct *xsave = &vcpu->arch.guest_fpu.state->xsave;
3168 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3169 u64 valid;
3170
3171 /*
3172 * Copy legacy XSAVE area, to avoid complications with CPUID
3173 * leaves 0 and 1 in the loop below.
3174 */
3175 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3176
3177 /* Set XSTATE_BV and possibly XCOMP_BV. */
3178 xsave->xsave_hdr.xstate_bv = xstate_bv;
3179 if (cpu_has_xsaves)
3180 xsave->xsave_hdr.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
3181
3182 /*
3183 * Copy each region from the non-compacted offset to the
3184 * possibly compacted offset.
3185 */
3186 valid = xstate_bv & ~XSTATE_FPSSE;
3187 while (valid) {
3188 u64 feature = valid & -valid;
3189 int index = fls64(feature) - 1;
3190 void *dest = get_xsave_addr(xsave, feature);
3191
3192 if (dest) {
3193 u32 size, offset, ecx, edx;
3194 cpuid_count(XSTATE_CPUID, index,
3195 &size, &offset, &ecx, &edx);
3196 memcpy(dest, src + offset, size);
3197 } else
3198 WARN_ON_ONCE(1);
3199
3200 valid -= feature;
3201 }
3202}
3203
2d5b5a66
SY		 3204static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3205 struct kvm_xsave *guest_xsave)
3206{
4344ee98 3207 if (cpu_has_xsave) {
df1daba7
PB		 3208 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3209 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3210 } else {
2d5b5a66
SY		 3211 memcpy(guest_xsave->region,
3212 &vcpu->arch.guest_fpu.state->fxsave,
3213 sizeof(struct i387_fxsave_struct));
3214 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3215 XSTATE_FPSSE;
3216 }
3217}
3218
3219static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3220 struct kvm_xsave *guest_xsave)
3221{
3222 u64 xstate_bv =
3223 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3224
d7876f1b
PB		 3225 if (cpu_has_xsave) {
3226 /*
3227 * Here we allow setting states that are not present in
3228 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3229 * with old userspace.
3230 */
4ff41732 3231 if (xstate_bv & ~kvm_supported_xcr0())
d7876f1b 3232 return -EINVAL;
df1daba7 3233 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3234 } else {
2d5b5a66
SY		 3235 if (xstate_bv & ~XSTATE_FPSSE)
3236 return -EINVAL;
3237 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3238 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3239 }
3240 return 0;
3241}
3242
3243static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3244 struct kvm_xcrs *guest_xcrs)
3245{
3246 if (!cpu_has_xsave) {
3247 guest_xcrs->nr_xcrs = 0;
3248 return;
3249 }
3250
3251 guest_xcrs->nr_xcrs = 1;
3252 guest_xcrs->flags = 0;
3253 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3254 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3255}
3256
3257static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3258 struct kvm_xcrs *guest_xcrs)
3259{
3260 int i, r = 0;
3261
3262 if (!cpu_has_xsave)
3263 return -EINVAL;
3264
3265 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3266 return -EINVAL;
3267
3268 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3269 /* Only support XCR0 currently */
c67a04cb 3270 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3271 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3272 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3273 break;
3274 }
3275 if (r)
3276 r = -EINVAL;
3277 return r;
3278}
3279
1c0b28c2
EM		 3280/*
3281 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3282 * stopped by the hypervisor. This function will be called from the host only.
3283 * EINVAL is returned when the host attempts to set the flag for a guest that
3284 * does not support pv clocks.
3285 */
3286static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3287{
0b79459b 3288 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3289 return -EINVAL;
51d59c6b 3290 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3291 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3292 return 0;
3293}
3294
313a3dc7
CO		 3295long kvm_arch_vcpu_ioctl(struct file *filp,
3296 unsigned int ioctl, unsigned long arg)
3297{
3298 struct kvm_vcpu *vcpu = filp->private_data;
3299 void __user *argp = (void __user *)arg;
3300 int r;
d1ac91d8
AK		 3301 union {
3302 struct kvm_lapic_state *lapic;
3303 struct kvm_xsave *xsave;
3304 struct kvm_xcrs *xcrs;
3305 void *buffer;
3306 } u;
3307
3308 u.buffer = NULL;
313a3dc7
CO		 3309 switch (ioctl) {
3310 case KVM_GET_LAPIC: {
2204ae3c
MT		 3311 r = -EINVAL;
3312 if (!vcpu->arch.apic)
3313 goto out;
d1ac91d8 3314 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3315
b772ff36 3316 r = -ENOMEM;
d1ac91d8 3317 if (!u.lapic)
b772ff36 3318 goto out;
d1ac91d8 3319 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3320 if (r)
3321 goto out;
3322 r = -EFAULT;
d1ac91d8 3323 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3324 goto out;
3325 r = 0;
3326 break;
3327 }
3328 case KVM_SET_LAPIC: {
2204ae3c
MT		 3329 r = -EINVAL;
3330 if (!vcpu->arch.apic)
3331 goto out;
ff5c2c03 3332 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3333 if (IS_ERR(u.lapic))
3334 return PTR_ERR(u.lapic);
ff5c2c03 3335
d1ac91d8 3336 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3337 break;
3338 }
f77bc6a4
ZX		 3339 case KVM_INTERRUPT: {
3340 struct kvm_interrupt irq;
3341
3342 r = -EFAULT;
3343 if (copy_from_user(&irq, argp, sizeof irq))
3344 goto out;
3345 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3346 break;
3347 }
c4abb7c9
JK		 3348 case KVM_NMI: {
3349 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3350 break;
3351 }
f077825a
PB		 3352 case KVM_SMI: {
3353 r = kvm_vcpu_ioctl_smi(vcpu);
3354 break;
3355 }
313a3dc7
CO		 3356 case KVM_SET_CPUID: {
3357 struct kvm_cpuid __user *cpuid_arg = argp;
3358 struct kvm_cpuid cpuid;
3359
3360 r = -EFAULT;
3361 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3362 goto out;
3363 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3364 break;
3365 }
07716717
DK		 3366 case KVM_SET_CPUID2: {
3367 struct kvm_cpuid2 __user *cpuid_arg = argp;
3368 struct kvm_cpuid2 cpuid;
3369
3370 r = -EFAULT;
3371 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3372 goto out;
3373 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3374 cpuid_arg->entries);
07716717
DK		 3375 break;
3376 }
3377 case KVM_GET_CPUID2: {
3378 struct kvm_cpuid2 __user *cpuid_arg = argp;
3379 struct kvm_cpuid2 cpuid;
3380
3381 r = -EFAULT;
3382 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3383 goto out;
3384 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3385 cpuid_arg->entries);
07716717
DK		 3386 if (r)
3387 goto out;
3388 r = -EFAULT;
3389 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3390 goto out;
3391 r = 0;
3392 break;
3393 }
313a3dc7 3394 case KVM_GET_MSRS:
609e36d3 3395 r = msr_io(vcpu, argp, do_get_msr, 1);
313a3dc7
CO		 3396 break;
3397 case KVM_SET_MSRS:
3398 r = msr_io(vcpu, argp, do_set_msr, 0);
3399 break;
b209749f
AK		 3400 case KVM_TPR_ACCESS_REPORTING: {
3401 struct kvm_tpr_access_ctl tac;
3402
3403 r = -EFAULT;
3404 if (copy_from_user(&tac, argp, sizeof tac))
3405 goto out;
3406 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3407 if (r)
3408 goto out;
3409 r = -EFAULT;
3410 if (copy_to_user(argp, &tac, sizeof tac))
3411 goto out;
3412 r = 0;
3413 break;
3414 };
b93463aa
AK		 3415 case KVM_SET_VAPIC_ADDR: {
3416 struct kvm_vapic_addr va;
3417
3418 r = -EINVAL;
3419 if (!irqchip_in_kernel(vcpu->kvm))
3420 goto out;
3421 r = -EFAULT;
3422 if (copy_from_user(&va, argp, sizeof va))
3423 goto out;
fda4e2e8 3424 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3425 break;
3426 }
890ca9ae
HY		 3427 case KVM_X86_SETUP_MCE: {
3428 u64 mcg_cap;
3429
3430 r = -EFAULT;
3431 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3432 goto out;
3433 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3434 break;
3435 }
3436 case KVM_X86_SET_MCE: {
3437 struct kvm_x86_mce mce;
3438
3439 r = -EFAULT;
3440 if (copy_from_user(&mce, argp, sizeof mce))
3441 goto out;
3442 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3443 break;
3444 }
3cfc3092
JK		 3445 case KVM_GET_VCPU_EVENTS: {
3446 struct kvm_vcpu_events events;
3447
3448 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3449
3450 r = -EFAULT;
3451 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3452 break;
3453 r = 0;
3454 break;
3455 }
3456 case KVM_SET_VCPU_EVENTS: {
3457 struct kvm_vcpu_events events;
3458
3459 r = -EFAULT;
3460 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3461 break;
3462
3463 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3464 break;
3465 }
a1efbe77
JK		 3466 case KVM_GET_DEBUGREGS: {
3467 struct kvm_debugregs dbgregs;
3468
3469 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3470
3471 r = -EFAULT;
3472 if (copy_to_user(argp, &dbgregs,
3473 sizeof(struct kvm_debugregs)))
3474 break;
3475 r = 0;
3476 break;
3477 }
3478 case KVM_SET_DEBUGREGS: {
3479 struct kvm_debugregs dbgregs;
3480
3481 r = -EFAULT;
3482 if (copy_from_user(&dbgregs, argp,
3483 sizeof(struct kvm_debugregs)))
3484 break;
3485
3486 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3487 break;
3488 }
2d5b5a66 3489 case KVM_GET_XSAVE: {
d1ac91d8 3490 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3491 r = -ENOMEM;
d1ac91d8 3492 if (!u.xsave)
2d5b5a66
SY		 3493 break;
3494
d1ac91d8 3495 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3496
3497 r = -EFAULT;
d1ac91d8 3498 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3499 break;
3500 r = 0;
3501 break;
3502 }
3503 case KVM_SET_XSAVE: {
ff5c2c03 3504 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3505 if (IS_ERR(u.xsave))
3506 return PTR_ERR(u.xsave);
2d5b5a66 3507
d1ac91d8 3508 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3509 break;
3510 }
3511 case KVM_GET_XCRS: {
d1ac91d8 3512 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3513 r = -ENOMEM;
d1ac91d8 3514 if (!u.xcrs)
2d5b5a66
SY		 3515 break;
3516
d1ac91d8 3517 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3518
3519 r = -EFAULT;
d1ac91d8 3520 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3521 sizeof(struct kvm_xcrs)))
3522 break;
3523 r = 0;
3524 break;
3525 }
3526 case KVM_SET_XCRS: {
ff5c2c03 3527 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3528 if (IS_ERR(u.xcrs))
3529 return PTR_ERR(u.xcrs);
2d5b5a66 3530
d1ac91d8 3531 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3532 break;
3533 }
92a1f12d
JR		 3534 case KVM_SET_TSC_KHZ: {
3535 u32 user_tsc_khz;
3536
3537 r = -EINVAL;
92a1f12d
JR		 3538 user_tsc_khz = (u32)arg;
3539
3540 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3541 goto out;
3542
cc578287
ZA		 3543 if (user_tsc_khz == 0)
3544 user_tsc_khz = tsc_khz;
3545
3546 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3547
3548 r = 0;
3549 goto out;
3550 }
3551 case KVM_GET_TSC_KHZ: {
cc578287 3552 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3553 goto out;
3554 }
1c0b28c2
EM		 3555 case KVM_KVMCLOCK_CTRL: {
3556 r = kvm_set_guest_paused(vcpu);
3557 goto out;
3558 }
313a3dc7
CO		 3559 default:
3560 r = -EINVAL;
3561 }
3562out:
d1ac91d8 3563 kfree(u.buffer);
313a3dc7
CO		 3564 return r;
3565}
3566
5b1c1493
CO		 3567int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3568{
3569 return VM_FAULT_SIGBUS;
3570}
3571
1fe779f8
CO		 3572static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3573{
3574 int ret;
3575
3576 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3577 return -EINVAL;
1fe779f8
CO		 3578 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3579 return ret;
3580}
3581
b927a3ce
SY		 3582static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3583 u64 ident_addr)
3584{
3585 kvm->arch.ept_identity_map_addr = ident_addr;
3586 return 0;
3587}
3588
1fe779f8
CO		 3589static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3590 u32 kvm_nr_mmu_pages)
3591{
3592 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3593 return -EINVAL;
3594
79fac95e 3595 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3596
3597 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3598 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3599
79fac95e 3600 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3601 return 0;
3602}
3603
3604static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3605{
39de71ec 3606 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3607}
3608
1fe779f8
CO		 3609static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3610{
3611 int r;
3612
3613 r = 0;
3614 switch (chip->chip_id) {
3615 case KVM_IRQCHIP_PIC_MASTER:
3616 memcpy(&chip->chip.pic,
3617 &pic_irqchip(kvm)->pics[0],
3618 sizeof(struct kvm_pic_state));
3619 break;
3620 case KVM_IRQCHIP_PIC_SLAVE:
3621 memcpy(&chip->chip.pic,
3622 &pic_irqchip(kvm)->pics[1],
3623 sizeof(struct kvm_pic_state));
3624 break;
3625 case KVM_IRQCHIP_IOAPIC:
eba0226b 3626 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3627 break;
3628 default:
3629 r = -EINVAL;
3630 break;
3631 }
3632 return r;
3633}
3634
3635static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3636{
3637 int r;
3638
3639 r = 0;
3640 switch (chip->chip_id) {
3641 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3642 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3643 memcpy(&pic_irqchip(kvm)->pics[0],
3644 &chip->chip.pic,
3645 sizeof(struct kvm_pic_state));
f4f51050 3646 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3647 break;
3648 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3649 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3650 memcpy(&pic_irqchip(kvm)->pics[1],
3651 &chip->chip.pic,
3652 sizeof(struct kvm_pic_state));
f4f51050 3653 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3654 break;
3655 case KVM_IRQCHIP_IOAPIC:
eba0226b 3656 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3657 break;
3658 default:
3659 r = -EINVAL;
3660 break;
3661 }
3662 kvm_pic_update_irq(pic_irqchip(kvm));
3663 return r;
3664}
3665
e0f63cb9
SY		 3666static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3667{
3668 int r = 0;
3669
894a9c55 3670 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3671 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3672 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3673 return r;
3674}
3675
3676static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3677{
3678 int r = 0;
3679
894a9c55 3680 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3681 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3682 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3683 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3684 return r;
3685}
3686
3687static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3688{
3689 int r = 0;
3690
3691 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3692 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3693 sizeof(ps->channels));
3694 ps->flags = kvm->arch.vpit->pit_state.flags;
3695 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3696 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3697 return r;
3698}
3699
3700static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3701{
3702 int r = 0, start = 0;
3703 u32 prev_legacy, cur_legacy;
3704 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3705 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3706 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3707 if (!prev_legacy && cur_legacy)
3708 start = 1;
3709 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3710 sizeof(kvm->arch.vpit->pit_state.channels));
3711 kvm->arch.vpit->pit_state.flags = ps->flags;
3712 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3713 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3714 return r;
3715}
3716
52d939a0
MT		 3717static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3718 struct kvm_reinject_control *control)
3719{
3720 if (!kvm->arch.vpit)
3721 return -ENXIO;
894a9c55 3722 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3723 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3724 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3725 return 0;
3726}
3727
95d4c16c 3728/**
60c34612
TY		 3729 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3730 * @kvm: kvm instance
3731 * @log: slot id and address to which we copy the log
95d4c16c 3732 *
e108ff2f
PB		 3733 * Steps 1-4 below provide general overview of dirty page logging. See
3734 * kvm_get_dirty_log_protect() function description for additional details.
3735 *
3736 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
3737 * always flush the TLB (step 4) even if previous step failed and the dirty
3738 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
3739 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
3740 * writes will be marked dirty for next log read.
95d4c16c 3741 *
60c34612
TY		 3742 * 1. Take a snapshot of the bit and clear it if needed.
3743 * 2. Write protect the corresponding page.
e108ff2f
PB		 3744 * 3. Copy the snapshot to the userspace.
3745 * 4. Flush TLB's if needed.
5bb064dc 3746 */
60c34612 3747int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3748{
60c34612 3749 bool is_dirty = false;
e108ff2f 3750 int r;
5bb064dc 3751
79fac95e 3752 mutex_lock(&kvm->slots_lock);
5bb064dc 3753
88178fd4
KH		 3754 /*
3755 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
3756 */
3757 if (kvm_x86_ops->flush_log_dirty)
3758 kvm_x86_ops->flush_log_dirty(kvm);
3759
e108ff2f 3760 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG		 3761
3762 /*
3763 * All the TLBs can be flushed out of mmu lock, see the comments in
3764 * kvm_mmu_slot_remove_write_access().
3765 */
e108ff2f 3766 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG		 3767 if (is_dirty)
3768 kvm_flush_remote_tlbs(kvm);
3769
79fac95e 3770 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3771 return r;
3772}
3773
aa2fbe6d
YZ		 3774int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3775 bool line_status)
23d43cf9
CD		 3776{
3777 if (!irqchip_in_kernel(kvm))
3778 return -ENXIO;
3779
3780 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3781 irq_event->irq, irq_event->level,
3782 line_status);
23d43cf9
CD		 3783 return 0;
3784}
3785
90de4a18
NA		 3786static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
3787 struct kvm_enable_cap *cap)
3788{
3789 int r;
3790
3791 if (cap->flags)
3792 return -EINVAL;
3793
3794 switch (cap->cap) {
3795 case KVM_CAP_DISABLE_QUIRKS:
3796 kvm->arch.disabled_quirks = cap->args[0];
3797 r = 0;
3798 break;
3799 default:
3800 r = -EINVAL;
3801 break;
3802 }
3803 return r;
3804}
3805
1fe779f8
CO		 3806long kvm_arch_vm_ioctl(struct file *filp,
3807 unsigned int ioctl, unsigned long arg)
3808{
3809 struct kvm *kvm = filp->private_data;
3810 void __user *argp = (void __user *)arg;
367e1319 3811 int r = -ENOTTY;
f0d66275
DH		 3812 /*
3813 * This union makes it completely explicit to gcc-3.x
3814 * that these two variables' stack usage should be
3815 * combined, not added together.
3816 */
3817 union {
3818 struct kvm_pit_state ps;
e9f42757 3819 struct kvm_pit_state2 ps2;
c5ff41ce 3820 struct kvm_pit_config pit_config;
f0d66275 3821 } u;
1fe779f8
CO		 3822
3823 switch (ioctl) {
3824 case KVM_SET_TSS_ADDR:
3825 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3826 break;
b927a3ce
SY		 3827 case KVM_SET_IDENTITY_MAP_ADDR: {
3828 u64 ident_addr;
3829
3830 r = -EFAULT;
3831 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3832 goto out;
3833 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3834 break;
3835 }
1fe779f8
CO		 3836 case KVM_SET_NR_MMU_PAGES:
3837 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3838 break;
3839 case KVM_GET_NR_MMU_PAGES:
3840 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3841 break;
3ddea128
MT		 3842 case KVM_CREATE_IRQCHIP: {
3843 struct kvm_pic *vpic;
3844
3845 mutex_lock(&kvm->lock);
3846 r = -EEXIST;
3847 if (kvm->arch.vpic)
3848 goto create_irqchip_unlock;
3e515705
AK		 3849 r = -EINVAL;
3850 if (atomic_read(&kvm->online_vcpus))
3851 goto create_irqchip_unlock;
1fe779f8 3852 r = -ENOMEM;
3ddea128
MT		 3853 vpic = kvm_create_pic(kvm);
3854 if (vpic) {
1fe779f8
CO		 3855 r = kvm_ioapic_init(kvm);
3856 if (r) {
175504cd 3857 mutex_lock(&kvm->slots_lock);
72bb2fcd 3858 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3859 &vpic->dev_master);
3860 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3861 &vpic->dev_slave);
3862 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3863 &vpic->dev_eclr);
175504cd 3864 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3865 kfree(vpic);
3866 goto create_irqchip_unlock;
1fe779f8
CO		 3867 }
3868 } else
3ddea128
MT		 3869 goto create_irqchip_unlock;
3870 smp_wmb();
3871 kvm->arch.vpic = vpic;
3872 smp_wmb();
399ec807
AK		 3873 r = kvm_setup_default_irq_routing(kvm);
3874 if (r) {
175504cd 3875 mutex_lock(&kvm->slots_lock);
3ddea128 3876 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3877 kvm_ioapic_destroy(kvm);
3878 kvm_destroy_pic(kvm);
3ddea128 3879 mutex_unlock(&kvm->irq_lock);
175504cd 3880 mutex_unlock(&kvm->slots_lock);
399ec807 3881 }
3ddea128
MT		 3882 create_irqchip_unlock:
3883 mutex_unlock(&kvm->lock);
1fe779f8 3884 break;
3ddea128 3885 }
7837699f 3886 case KVM_CREATE_PIT:
c5ff41ce
JK		 3887 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3888 goto create_pit;
3889 case KVM_CREATE_PIT2:
3890 r = -EFAULT;
3891 if (copy_from_user(&u.pit_config, argp,
3892 sizeof(struct kvm_pit_config)))
3893 goto out;
3894 create_pit:
79fac95e 3895 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3896 r = -EEXIST;
3897 if (kvm->arch.vpit)
3898 goto create_pit_unlock;
7837699f 3899 r = -ENOMEM;
c5ff41ce 3900 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3901 if (kvm->arch.vpit)
3902 r = 0;
269e05e4 3903 create_pit_unlock:
79fac95e 3904 mutex_unlock(&kvm->slots_lock);
7837699f 3905 break;
1fe779f8
CO		 3906 case KVM_GET_IRQCHIP: {
3907 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3908 struct kvm_irqchip *chip;
1fe779f8 3909
ff5c2c03
SL		 3910 chip = memdup_user(argp, sizeof(*chip));
3911 if (IS_ERR(chip)) {
3912 r = PTR_ERR(chip);
1fe779f8 3913 goto out;
ff5c2c03
SL		 3914 }
3915
1fe779f8
CO		 3916 r = -ENXIO;
3917 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3918 goto get_irqchip_out;
3919 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3920 if (r)
f0d66275 3921 goto get_irqchip_out;
1fe779f8 3922 r = -EFAULT;
f0d66275
DH		 3923 if (copy_to_user(argp, chip, sizeof *chip))
3924 goto get_irqchip_out;
1fe779f8 3925 r = 0;
f0d66275
DH		 3926 get_irqchip_out:
3927 kfree(chip);
1fe779f8
CO		 3928 break;
3929 }
3930 case KVM_SET_IRQCHIP: {
3931 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3932 struct kvm_irqchip *chip;
1fe779f8 3933
ff5c2c03
SL		 3934 chip = memdup_user(argp, sizeof(*chip));
3935 if (IS_ERR(chip)) {
3936 r = PTR_ERR(chip);
1fe779f8 3937 goto out;
ff5c2c03
SL		 3938 }
3939
1fe779f8
CO		 3940 r = -ENXIO;
3941 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3942 goto set_irqchip_out;
3943 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3944 if (r)
f0d66275 3945 goto set_irqchip_out;
1fe779f8 3946 r = 0;
f0d66275
DH		 3947 set_irqchip_out:
3948 kfree(chip);
1fe779f8
CO		 3949 break;
3950 }
e0f63cb9 3951 case KVM_GET_PIT: {
e0f63cb9 3952 r = -EFAULT;
f0d66275 3953 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3954 goto out;
3955 r = -ENXIO;
3956 if (!kvm->arch.vpit)
3957 goto out;
f0d66275 3958 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3959 if (r)
3960 goto out;
3961 r = -EFAULT;
f0d66275 3962 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3963 goto out;
3964 r = 0;
3965 break;
3966 }
3967 case KVM_SET_PIT: {
e0f63cb9 3968 r = -EFAULT;
f0d66275 3969 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3970 goto out;
3971 r = -ENXIO;
3972 if (!kvm->arch.vpit)
3973 goto out;
f0d66275 3974 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3975 break;
3976 }
e9f42757
BK		 3977 case KVM_GET_PIT2: {
3978 r = -ENXIO;
3979 if (!kvm->arch.vpit)
3980 goto out;
3981 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3982 if (r)
3983 goto out;
3984 r = -EFAULT;
3985 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3986 goto out;
3987 r = 0;
3988 break;
3989 }
3990 case KVM_SET_PIT2: {
3991 r = -EFAULT;
3992 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3993 goto out;
3994 r = -ENXIO;
3995 if (!kvm->arch.vpit)
3996 goto out;
3997 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3998 break;
3999 }
52d939a0
MT		 4000 case KVM_REINJECT_CONTROL: {
4001 struct kvm_reinject_control control;
4002 r = -EFAULT;
4003 if (copy_from_user(&control, argp, sizeof(control)))
4004 goto out;
4005 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 4006 break;
4007 }
ffde22ac
ES		 4008 case KVM_XEN_HVM_CONFIG: {
4009 r = -EFAULT;
4010 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
4011 sizeof(struct kvm_xen_hvm_config)))
4012 goto out;
4013 r = -EINVAL;
4014 if (kvm->arch.xen_hvm_config.flags)
4015 goto out;
4016 r = 0;
4017 break;
4018 }
afbcf7ab 4019 case KVM_SET_CLOCK: {
afbcf7ab
GC		 4020 struct kvm_clock_data user_ns;
4021 u64 now_ns;
4022 s64 delta;
4023
4024 r = -EFAULT;
4025 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4026 goto out;
4027
4028 r = -EINVAL;
4029 if (user_ns.flags)
4030 goto out;
4031
4032 r = 0;
395c6b0a 4033 local_irq_disable();
759379dd 4034 now_ns = get_kernel_ns();
afbcf7ab 4035 delta = user_ns.clock - now_ns;
395c6b0a 4036 local_irq_enable();
afbcf7ab 4037 kvm->arch.kvmclock_offset = delta;
2e762ff7 4038 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 4039 break;
4040 }
4041 case KVM_GET_CLOCK: {
afbcf7ab
GC		 4042 struct kvm_clock_data user_ns;
4043 u64 now_ns;
4044
395c6b0a 4045 local_irq_disable();
759379dd 4046 now_ns = get_kernel_ns();
afbcf7ab 4047 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 4048 local_irq_enable();
afbcf7ab 4049 user_ns.flags = 0;
97e69aa6 4050 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 4051
4052 r = -EFAULT;
4053 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4054 goto out;
4055 r = 0;
4056 break;
4057 }
90de4a18
NA		 4058 case KVM_ENABLE_CAP: {
4059 struct kvm_enable_cap cap;
afbcf7ab 4060
90de4a18
NA		 4061 r = -EFAULT;
4062 if (copy_from_user(&cap, argp, sizeof(cap)))
4063 goto out;
4064 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4065 break;
4066 }
1fe779f8 4067 default:
c274e03a 4068 r = kvm_vm_ioctl_assigned_device(kvm, ioctl, arg);
1fe779f8
CO		 4069 }
4070out:
4071 return r;
4072}
4073
a16b043c 4074static void kvm_init_msr_list(void)
043405e1
CO		 4075{
4076 u32 dummy[2];
4077 unsigned i, j;
4078
62ef68bb 4079 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 4080 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4081 continue;
93c4adc7
PB		 4082
4083 /*
4084 * Even MSRs that are valid in the host may not be exposed
4085 * to the guests in some cases. We could work around this
4086 * in VMX with the generic MSR save/load machinery, but it
4087 * is not really worthwhile since it will really only
4088 * happen with nested virtualization.
4089 */
4090 switch (msrs_to_save[i]) {
4091 case MSR_IA32_BNDCFGS:
4092 if (!kvm_x86_ops->mpx_supported())
4093 continue;
4094 break;
4095 default:
4096 break;
4097 }
4098
043405e1
CO		 4099 if (j < i)
4100 msrs_to_save[j] = msrs_to_save[i];
4101 j++;
4102 }
4103 num_msrs_to_save = j;
62ef68bb
PB		 4104
4105 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4106 switch (emulated_msrs[i]) {
6d396b55
PB		 4107 case MSR_IA32_SMBASE:
4108 if (!kvm_x86_ops->cpu_has_high_real_mode_segbase())
4109 continue;
4110 break;
62ef68bb
PB		 4111 default:
4112 break;
4113 }
4114
4115 if (j < i)
4116 emulated_msrs[j] = emulated_msrs[i];
4117 j++;
4118 }
4119 num_emulated_msrs = j;
043405e1
CO		 4120}
4121
bda9020e
MT		 4122static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4123 const void *v)
bbd9b64e 4124{
70252a10
AK		 4125 int handled = 0;
4126 int n;
4127
4128 do {
4129 n = min(len, 8);
4130 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4131 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4132 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4133 break;
4134 handled += n;
4135 addr += n;
4136 len -= n;
4137 v += n;
4138 } while (len);
bbd9b64e 4139
70252a10 4140 return handled;
bbd9b64e
CO		 4141}
4142
bda9020e 4143static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4144{
70252a10
AK		 4145 int handled = 0;
4146 int n;
4147
4148 do {
4149 n = min(len, 8);
4150 if (!(vcpu->arch.apic &&
e32edf4f
NN		 4151 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4152 addr, n, v))
4153 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK		 4154 break;
4155 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
4156 handled += n;
4157 addr += n;
4158 len -= n;
4159 v += n;
4160 } while (len);
bbd9b64e 4161
70252a10 4162 return handled;
bbd9b64e
CO		 4163}
4164
2dafc6c2
GN		 4165static void kvm_set_segment(struct kvm_vcpu *vcpu,
4166 struct kvm_segment *var, int seg)
4167{
4168 kvm_x86_ops->set_segment(vcpu, var, seg);
4169}
4170
4171void kvm_get_segment(struct kvm_vcpu *vcpu,
4172 struct kvm_segment *var, int seg)
4173{
4174 kvm_x86_ops->get_segment(vcpu, var, seg);
4175}
4176
54987b7a
PB		 4177gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4178 struct x86_exception *exception)
02f59dc9
JR		 4179{
4180 gpa_t t_gpa;
02f59dc9
JR		 4181
4182 BUG_ON(!mmu_is_nested(vcpu));
4183
4184 /* NPT walks are always user-walks */
4185 access |= PFERR_USER_MASK;
54987b7a 4186 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR		 4187
4188 return t_gpa;
4189}
4190
ab9ae313
AK		 4191gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4192 struct x86_exception *exception)
1871c602
GN		 4193{
4194 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4195 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4196}
4197
ab9ae313
AK		 4198 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4199 struct x86_exception *exception)
1871c602
GN		 4200{
4201 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4202 access |= PFERR_FETCH_MASK;
ab9ae313 4203 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4204}
4205
ab9ae313
AK		 4206gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4207 struct x86_exception *exception)
1871c602
GN		 4208{
4209 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4210 access |= PFERR_WRITE_MASK;
ab9ae313 4211 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4212}
4213
4214/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4215gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4216 struct x86_exception *exception)
1871c602 4217{
ab9ae313 4218 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4219}
4220
4221static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4222 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4223 struct x86_exception *exception)
bbd9b64e
CO		 4224{
4225 void *data = val;
10589a46 4226 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4227
4228 while (bytes) {
14dfe855 4229 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4230 exception);
bbd9b64e 4231 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4232 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4233 int ret;
4234
bcc55cba 4235 if (gpa == UNMAPPED_GVA)
ab9ae313 4236 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB		 4237 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4238 offset, toread);
10589a46 4239 if (ret < 0) {
c3cd7ffa 4240 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4241 goto out;
4242 }
bbd9b64e 4243
77c2002e
IE		 4244 bytes -= toread;
4245 data += toread;
4246 addr += toread;
bbd9b64e 4247 }
10589a46 4248out:
10589a46 4249 return r;
bbd9b64e 4250}
77c2002e 4251
1871c602 4252/* used for instruction fetching */
0f65dd70
AK		 4253static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4254 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4255 struct x86_exception *exception)
1871c602 4256{
0f65dd70 4257 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4258 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB		 4259 unsigned offset;
4260 int ret;
0f65dd70 4261
44583cba
PB		 4262 /* Inline kvm_read_guest_virt_helper for speed. */
4263 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4264 exception);
4265 if (unlikely(gpa == UNMAPPED_GVA))
4266 return X86EMUL_PROPAGATE_FAULT;
4267
4268 offset = addr & (PAGE_SIZE-1);
4269 if (WARN_ON(offset + bytes > PAGE_SIZE))
4270 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB		 4271 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4272 offset, bytes);
44583cba
PB		 4273 if (unlikely(ret < 0))
4274 return X86EMUL_IO_NEEDED;
4275
4276 return X86EMUL_CONTINUE;
1871c602
GN		 4277}
4278
064aea77 4279int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4280 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4281 struct x86_exception *exception)
1871c602 4282{
0f65dd70 4283 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4284 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4285
1871c602 4286 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4287 exception);
1871c602 4288}
064aea77 4289EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4290
0f65dd70
AK		 4291static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4292 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4293 struct x86_exception *exception)
1871c602 4294{
0f65dd70 4295 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4296 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4297}
4298
6a4d7550 4299int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4300 gva_t addr, void *val,
2dafc6c2 4301 unsigned int bytes,
bcc55cba 4302 struct x86_exception *exception)
77c2002e 4303{
0f65dd70 4304 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4305 void *data = val;
4306 int r = X86EMUL_CONTINUE;
4307
4308 while (bytes) {
14dfe855
JR		 4309 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4310 PFERR_WRITE_MASK,
ab9ae313 4311 exception);
77c2002e
IE		 4312 unsigned offset = addr & (PAGE_SIZE-1);
4313 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4314 int ret;
4315
bcc55cba 4316 if (gpa == UNMAPPED_GVA)
ab9ae313 4317 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4318 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4319 if (ret < 0) {
c3cd7ffa 4320 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4321 goto out;
4322 }
4323
4324 bytes -= towrite;
4325 data += towrite;
4326 addr += towrite;
4327 }
4328out:
4329 return r;
4330}
6a4d7550 4331EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4332
af7cc7d1
XG		 4333static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4334 gpa_t *gpa, struct x86_exception *exception,
4335 bool write)
4336{
97d64b78
AK		 4337 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4338 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4339
97d64b78 4340 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06
FW		 4341 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
4342 vcpu->arch.access, access)) {
bebb106a
XG		 4343 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4344 (gva & (PAGE_SIZE - 1));
4f022648 4345 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4346 return 1;
4347 }
4348
af7cc7d1
XG		 4349 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4350
4351 if (*gpa == UNMAPPED_GVA)
4352 return -1;
4353
4354 /* For APIC access vmexit */
4355 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4356 return 1;
4357
4f022648
XG		 4358 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4359 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4360 return 1;
4f022648 4361 }
bebb106a 4362
af7cc7d1
XG		 4363 return 0;
4364}
4365
3200f405 4366int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4367 const void *val, int bytes)
bbd9b64e
CO		 4368{
4369 int ret;
4370
54bf36aa 4371 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4372 if (ret < 0)
bbd9b64e 4373 return 0;
f57f2ef5 4374 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4375 return 1;
4376}
4377
77d197b2
XG		 4378struct read_write_emulator_ops {
4379 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4380 int bytes);
4381 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4382 void *val, int bytes);
4383 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4384 int bytes, void *val);
4385 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4386 void *val, int bytes);
4387 bool write;
4388};
4389
4390static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4391{
4392 if (vcpu->mmio_read_completed) {
77d197b2 4393 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4394 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4395 vcpu->mmio_read_completed = 0;
4396 return 1;
4397 }
4398
4399 return 0;
4400}
4401
4402static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4403 void *val, int bytes)
4404{
54bf36aa 4405 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG		 4406}
4407
4408static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4409 void *val, int bytes)
4410{
4411 return emulator_write_phys(vcpu, gpa, val, bytes);
4412}
4413
4414static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4415{
4416 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4417 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4418}
4419
4420static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4421 void *val, int bytes)
4422{
4423 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4424 return X86EMUL_IO_NEEDED;
4425}
4426
4427static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4428 void *val, int bytes)
4429{
f78146b0
AK		 4430 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4431
87da7e66 4432 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4433 return X86EMUL_CONTINUE;
4434}
4435
0fbe9b0b 4436static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4437 .read_write_prepare = read_prepare,
4438 .read_write_emulate = read_emulate,
4439 .read_write_mmio = vcpu_mmio_read,
4440 .read_write_exit_mmio = read_exit_mmio,
4441};
4442
0fbe9b0b 4443static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4444 .read_write_emulate = write_emulate,
4445 .read_write_mmio = write_mmio,
4446 .read_write_exit_mmio = write_exit_mmio,
4447 .write = true,
4448};
4449
22388a3c
XG		 4450static int emulator_read_write_onepage(unsigned long addr, void *val,
4451 unsigned int bytes,
4452 struct x86_exception *exception,
4453 struct kvm_vcpu *vcpu,
0fbe9b0b 4454 const struct read_write_emulator_ops *ops)
bbd9b64e 4455{
af7cc7d1
XG		 4456 gpa_t gpa;
4457 int handled, ret;
22388a3c 4458 bool write = ops->write;
f78146b0 4459 struct kvm_mmio_fragment *frag;
10589a46 4460
22388a3c 4461 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4462
af7cc7d1 4463 if (ret < 0)
bbd9b64e 4464 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4465
4466 /* For APIC access vmexit */
af7cc7d1 4467 if (ret)
bbd9b64e
CO		 4468 goto mmio;
4469
22388a3c 4470 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4471 return X86EMUL_CONTINUE;
4472
4473mmio:
4474 /*
4475 * Is this MMIO handled locally?
4476 */
22388a3c 4477 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4478 if (handled == bytes)
bbd9b64e 4479 return X86EMUL_CONTINUE;
bbd9b64e 4480
70252a10
AK		 4481 gpa += handled;
4482 bytes -= handled;
4483 val += handled;
4484
87da7e66
XG		 4485 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4486 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4487 frag->gpa = gpa;
4488 frag->data = val;
4489 frag->len = bytes;
f78146b0 4490 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4491}
4492
52eb5a6d
XL		 4493static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4494 unsigned long addr,
22388a3c
XG		 4495 void *val, unsigned int bytes,
4496 struct x86_exception *exception,
0fbe9b0b 4497 const struct read_write_emulator_ops *ops)
bbd9b64e 4498{
0f65dd70 4499 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4500 gpa_t gpa;
4501 int rc;
4502
4503 if (ops->read_write_prepare &&
4504 ops->read_write_prepare(vcpu, val, bytes))
4505 return X86EMUL_CONTINUE;
4506
4507 vcpu->mmio_nr_fragments = 0;
0f65dd70 4508
bbd9b64e
CO		 4509 /* Crossing a page boundary? */
4510 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4511 int now;
bbd9b64e
CO		 4512
4513 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4514 rc = emulator_read_write_onepage(addr, val, now, exception,
4515 vcpu, ops);
4516
bbd9b64e
CO		 4517 if (rc != X86EMUL_CONTINUE)
4518 return rc;
4519 addr += now;
bac15531
NA		 4520 if (ctxt->mode != X86EMUL_MODE_PROT64)
4521 addr = (u32)addr;
bbd9b64e
CO		 4522 val += now;
4523 bytes -= now;
4524 }
22388a3c 4525
f78146b0
AK		 4526 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4527 vcpu, ops);
4528 if (rc != X86EMUL_CONTINUE)
4529 return rc;
4530
4531 if (!vcpu->mmio_nr_fragments)
4532 return rc;
4533
4534 gpa = vcpu->mmio_fragments[0].gpa;
4535
4536 vcpu->mmio_needed = 1;
4537 vcpu->mmio_cur_fragment = 0;
4538
87da7e66 4539 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4540 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4541 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4542 vcpu->run->mmio.phys_addr = gpa;
4543
4544 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4545}
4546
4547static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4548 unsigned long addr,
4549 void *val,
4550 unsigned int bytes,
4551 struct x86_exception *exception)
4552{
4553 return emulator_read_write(ctxt, addr, val, bytes,
4554 exception, &read_emultor);
4555}
4556
52eb5a6d 4557static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG		 4558 unsigned long addr,
4559 const void *val,
4560 unsigned int bytes,
4561 struct x86_exception *exception)
4562{
4563 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4564 exception, &write_emultor);
bbd9b64e 4565}
bbd9b64e 4566
daea3e73
AK		 4567#define CMPXCHG_TYPE(t, ptr, old, new) \
4568 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4569
4570#ifdef CONFIG_X86_64
4571# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4572#else
4573# define CMPXCHG64(ptr, old, new) \
9749a6c0 4574 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4575#endif
4576
0f65dd70
AK		 4577static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4578 unsigned long addr,
bbd9b64e
CO		 4579 const void *old,
4580 const void *new,
4581 unsigned int bytes,
0f65dd70 4582 struct x86_exception *exception)
bbd9b64e 4583{
0f65dd70 4584 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4585 gpa_t gpa;
4586 struct page *page;
4587 char *kaddr;
4588 bool exchanged;
2bacc55c 4589
daea3e73
AK		 4590 /* guests cmpxchg8b have to be emulated atomically */
4591 if (bytes > 8 || (bytes & (bytes - 1)))
4592 goto emul_write;
10589a46 4593
daea3e73 4594 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4595
daea3e73
AK		 4596 if (gpa == UNMAPPED_GVA ||
4597 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4598 goto emul_write;
2bacc55c 4599
daea3e73
AK		 4600 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4601 goto emul_write;
72dc67a6 4602
54bf36aa 4603 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4604 if (is_error_page(page))
c19b8bd6 4605 goto emul_write;
72dc67a6 4606
8fd75e12 4607 kaddr = kmap_atomic(page);
daea3e73
AK		 4608 kaddr += offset_in_page(gpa);
4609 switch (bytes) {
4610 case 1:
4611 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4612 break;
4613 case 2:
4614 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4615 break;
4616 case 4:
4617 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4618 break;
4619 case 8:
4620 exchanged = CMPXCHG64(kaddr, old, new);
4621 break;
4622 default:
4623 BUG();
2bacc55c 4624 }
8fd75e12 4625 kunmap_atomic(kaddr);
daea3e73
AK		 4626 kvm_release_page_dirty(page);
4627
4628 if (!exchanged)
4629 return X86EMUL_CMPXCHG_FAILED;
4630
54bf36aa 4631 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
f57f2ef5 4632 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4633
4634 return X86EMUL_CONTINUE;
4a5f48f6 4635
3200f405 4636emul_write:
daea3e73 4637 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4638
0f65dd70 4639 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4640}
4641
cf8f70bf
GN		 4642static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4643{
4644 /* TODO: String I/O for in kernel device */
4645 int r;
4646
4647 if (vcpu->arch.pio.in)
e32edf4f 4648 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
cf8f70bf
GN		 4649 vcpu->arch.pio.size, pd);
4650 else
e32edf4f 4651 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
cf8f70bf
GN		 4652 vcpu->arch.pio.port, vcpu->arch.pio.size,
4653 pd);
4654 return r;
4655}
4656
6f6fbe98
XG		 4657static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4658 unsigned short port, void *val,
4659 unsigned int count, bool in)
cf8f70bf 4660{
cf8f70bf 4661 vcpu->arch.pio.port = port;
6f6fbe98 4662 vcpu->arch.pio.in = in;
7972995b 4663 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4664 vcpu->arch.pio.size = size;
4665
4666 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4667 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4668 return 1;
4669 }
4670
4671 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4672 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4673 vcpu->run->io.size = size;
4674 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4675 vcpu->run->io.count = count;
4676 vcpu->run->io.port = port;
4677
4678 return 0;
4679}
4680
6f6fbe98
XG		 4681static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4682 int size, unsigned short port, void *val,
4683 unsigned int count)
cf8f70bf 4684{
ca1d4a9e 4685 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4686 int ret;
ca1d4a9e 4687
6f6fbe98
XG		 4688 if (vcpu->arch.pio.count)
4689 goto data_avail;
cf8f70bf 4690
6f6fbe98
XG		 4691 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4692 if (ret) {
4693data_avail:
4694 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 4695 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 4696 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4697 return 1;
4698 }
4699
cf8f70bf
GN		 4700 return 0;
4701}
4702
6f6fbe98
XG		 4703static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4704 int size, unsigned short port,
4705 const void *val, unsigned int count)
4706{
4707 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4708
4709 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 4710 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG		 4711 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4712}
4713
bbd9b64e
CO		 4714static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4715{
4716 return kvm_x86_ops->get_segment_base(vcpu, seg);
4717}
4718
3cb16fe7 4719static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4720{
3cb16fe7 4721 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4722}
4723
5cb56059 4724int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY		 4725{
4726 if (!need_emulate_wbinvd(vcpu))
4727 return X86EMUL_CONTINUE;
4728
4729 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4730 int cpu = get_cpu();
4731
4732 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4733 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4734 wbinvd_ipi, NULL, 1);
2eec7343 4735 put_cpu();
f5f48ee1 4736 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4737 } else
4738 wbinvd();
f5f48ee1
SY		 4739 return X86EMUL_CONTINUE;
4740}
5cb56059
JS		 4741
4742int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4743{
4744 kvm_x86_ops->skip_emulated_instruction(vcpu);
4745 return kvm_emulate_wbinvd_noskip(vcpu);
4746}
f5f48ee1
SY		 4747EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4748
5cb56059
JS		 4749
4750
bcaf5cc5
AK		 4751static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4752{
5cb56059 4753 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK		 4754}
4755
52eb5a6d
XL		 4756static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
4757 unsigned long *dest)
bbd9b64e 4758{
16f8a6f9 4759 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4760}
4761
52eb5a6d
XL		 4762static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
4763 unsigned long value)
bbd9b64e 4764{
338dbc97 4765
717746e3 4766 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4767}
4768
52a46617 4769static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4770{
52a46617 4771 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4772}
4773
717746e3 4774static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4775{
717746e3 4776 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4777 unsigned long value;
4778
4779 switch (cr) {
4780 case 0:
4781 value = kvm_read_cr0(vcpu);
4782 break;
4783 case 2:
4784 value = vcpu->arch.cr2;
4785 break;
4786 case 3:
9f8fe504 4787 value = kvm_read_cr3(vcpu);
52a46617
GN		 4788 break;
4789 case 4:
4790 value = kvm_read_cr4(vcpu);
4791 break;
4792 case 8:
4793 value = kvm_get_cr8(vcpu);
4794 break;
4795 default:
a737f256 4796 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4797 return 0;
4798 }
4799
4800 return value;
4801}
4802
717746e3 4803static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4804{
717746e3 4805 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4806 int res = 0;
4807
52a46617
GN		 4808 switch (cr) {
4809 case 0:
49a9b07e 4810 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4811 break;
4812 case 2:
4813 vcpu->arch.cr2 = val;
4814 break;
4815 case 3:
2390218b 4816 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4817 break;
4818 case 4:
a83b29c6 4819 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4820 break;
4821 case 8:
eea1cff9 4822 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4823 break;
4824 default:
a737f256 4825 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4826 res = -1;
52a46617 4827 }
0f12244f
GN		 4828
4829 return res;
52a46617
GN		 4830}
4831
717746e3 4832static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4833{
717746e3 4834 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4835}
4836
4bff1e86 4837static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4838{
4bff1e86 4839 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4840}
4841
4bff1e86 4842static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4843{
4bff1e86 4844 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4845}
4846
1ac9d0cf
AK		 4847static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4848{
4849 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4850}
4851
4852static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4853{
4854 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4855}
4856
4bff1e86
AK		 4857static unsigned long emulator_get_cached_segment_base(
4858 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4859{
4bff1e86 4860 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4861}
4862
1aa36616
AK		 4863static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4864 struct desc_struct *desc, u32 *base3,
4865 int seg)
2dafc6c2
GN		 4866{
4867 struct kvm_segment var;
4868
4bff1e86 4869 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4870 *selector = var.selector;
2dafc6c2 4871
378a8b09
GN		 4872 if (var.unusable) {
4873 memset(desc, 0, sizeof(*desc));
2dafc6c2 4874 return false;
378a8b09 4875 }
2dafc6c2
GN		 4876
4877 if (var.g)
4878 var.limit >>= 12;
4879 set_desc_limit(desc, var.limit);
4880 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4881#ifdef CONFIG_X86_64
4882 if (base3)
4883 *base3 = var.base >> 32;
4884#endif
2dafc6c2
GN		 4885 desc->type = var.type;
4886 desc->s = var.s;
4887 desc->dpl = var.dpl;
4888 desc->p = var.present;
4889 desc->avl = var.avl;
4890 desc->l = var.l;
4891 desc->d = var.db;
4892 desc->g = var.g;
4893
4894 return true;
4895}
4896
1aa36616
AK		 4897static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4898 struct desc_struct *desc, u32 base3,
4899 int seg)
2dafc6c2 4900{
4bff1e86 4901 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4902 struct kvm_segment var;
4903
1aa36616 4904 var.selector = selector;
2dafc6c2 4905 var.base = get_desc_base(desc);
5601d05b
GN		 4906#ifdef CONFIG_X86_64
4907 var.base |= ((u64)base3) << 32;
4908#endif
2dafc6c2
GN		 4909 var.limit = get_desc_limit(desc);
4910 if (desc->g)
4911 var.limit = (var.limit << 12) | 0xfff;
4912 var.type = desc->type;
2dafc6c2
GN		 4913 var.dpl = desc->dpl;
4914 var.db = desc->d;
4915 var.s = desc->s;
4916 var.l = desc->l;
4917 var.g = desc->g;
4918 var.avl = desc->avl;
4919 var.present = desc->p;
4920 var.unusable = !var.present;
4921 var.padding = 0;
4922
4923 kvm_set_segment(vcpu, &var, seg);
4924 return;
4925}
4926
717746e3
AK		 4927static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4928 u32 msr_index, u64 *pdata)
4929{
609e36d3
PB		 4930 struct msr_data msr;
4931 int r;
4932
4933 msr.index = msr_index;
4934 msr.host_initiated = false;
4935 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
4936 if (r)
4937 return r;
4938
4939 *pdata = msr.data;
4940 return 0;
717746e3
AK		 4941}
4942
4943static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4944 u32 msr_index, u64 data)
4945{
8fe8ab46
WA		 4946 struct msr_data msr;
4947
4948 msr.data = data;
4949 msr.index = msr_index;
4950 msr.host_initiated = false;
4951 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4952}
4953
64d60670
PB		 4954static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
4955{
4956 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4957
4958 return vcpu->arch.smbase;
4959}
4960
4961static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
4962{
4963 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4964
4965 vcpu->arch.smbase = smbase;
4966}
4967
67f4d428
NA		 4968static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
4969 u32 pmc)
4970{
4971 return kvm_pmu_check_pmc(emul_to_vcpu(ctxt), pmc);
4972}
4973
222d21aa
AK		 4974static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4975 u32 pmc, u64 *pdata)
4976{
4977 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4978}
4979
6c3287f7
AK		 4980static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4981{
4982 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4983}
4984
5037f6f3
AK		 4985static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4986{
4987 preempt_disable();
5197b808 4988 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4989 /*
4990 * CR0.TS may reference the host fpu state, not the guest fpu state,
4991 * so it may be clear at this point.
4992 */
4993 clts();
4994}
4995
4996static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4997{
4998 preempt_enable();
4999}
5000
2953538e 5001static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5002 struct x86_instruction_info *info,
c4f035c6
AK		 5003 enum x86_intercept_stage stage)
5004{
2953538e 5005 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 5006}
5007
0017f93a 5008static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 5009 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
5010{
0017f93a 5011 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 5012}
5013
dd856efa
AK		 5014static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5015{
5016 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5017}
5018
5019static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5020{
5021 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5022}
5023
801806d9
NA		 5024static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5025{
5026 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5027}
5028
0225fb50 5029static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 5030 .read_gpr = emulator_read_gpr,
5031 .write_gpr = emulator_write_gpr,
1871c602 5032 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5033 .write_std = kvm_write_guest_virt_system,
1871c602 5034 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 5035 .read_emulated = emulator_read_emulated,
5036 .write_emulated = emulator_write_emulated,
5037 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5038 .invlpg = emulator_invlpg,
cf8f70bf
GN		 5039 .pio_in_emulated = emulator_pio_in_emulated,
5040 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 5041 .get_segment = emulator_get_segment,
5042 .set_segment = emulator_set_segment,
5951c442 5043 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5044 .get_gdt = emulator_get_gdt,
160ce1f1 5045 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 5046 .set_gdt = emulator_set_gdt,
5047 .set_idt = emulator_set_idt,
52a46617
GN		 5048 .get_cr = emulator_get_cr,
5049 .set_cr = emulator_set_cr,
9c537244 5050 .cpl = emulator_get_cpl,
35aa5375
GN		 5051 .get_dr = emulator_get_dr,
5052 .set_dr = emulator_set_dr,
64d60670
PB		 5053 .get_smbase = emulator_get_smbase,
5054 .set_smbase = emulator_set_smbase,
717746e3
AK		 5055 .set_msr = emulator_set_msr,
5056 .get_msr = emulator_get_msr,
67f4d428 5057 .check_pmc = emulator_check_pmc,
222d21aa 5058 .read_pmc = emulator_read_pmc,
6c3287f7 5059 .halt = emulator_halt,
bcaf5cc5 5060 .wbinvd = emulator_wbinvd,
d6aa1000 5061 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 5062 .get_fpu = emulator_get_fpu,
5063 .put_fpu = emulator_put_fpu,
c4f035c6 5064 .intercept = emulator_intercept,
bdb42f5a 5065 .get_cpuid = emulator_get_cpuid,
801806d9 5066 .set_nmi_mask = emulator_set_nmi_mask,
bbd9b64e
CO		 5067};
5068
95cb2295
GN		 5069static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5070{
37ccdcbe 5071 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN		 5072 /*
5073 * an sti; sti; sequence only disable interrupts for the first
5074 * instruction. So, if the last instruction, be it emulated or
5075 * not, left the system with the INT_STI flag enabled, it
5076 * means that the last instruction is an sti. We should not
5077 * leave the flag on in this case. The same goes for mov ss
5078 */
37ccdcbe
PB		 5079 if (int_shadow & mask)
5080 mask = 0;
6addfc42 5081 if (unlikely(int_shadow || mask)) {
95cb2295 5082 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB		 5083 if (!mask)
5084 kvm_make_request(KVM_REQ_EVENT, vcpu);
5085 }
95cb2295
GN		 5086}
5087
ef54bcfe 5088static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN		 5089{
5090 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5091 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB		 5092 return kvm_propagate_fault(vcpu, &ctxt->exception);
5093
5094 if (ctxt->exception.error_code_valid)
da9cb575
AK		 5095 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5096 ctxt->exception.error_code);
54b8486f 5097 else
da9cb575 5098 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5099 return false;
54b8486f
GN		 5100}
5101
8ec4722d
MG		 5102static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5103{
adf52235 5104 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 5105 int cs_db, cs_l;
5106
8ec4722d
MG		 5107 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5108
adf52235
TY		 5109 ctxt->eflags = kvm_get_rflags(vcpu);
5110 ctxt->eip = kvm_rip_read(vcpu);
5111 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5112 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5113 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY		 5114 cs_db ? X86EMUL_MODE_PROT32 :
5115 X86EMUL_MODE_PROT16;
a584539b 5116 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB		 5117 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5118 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
a584539b 5119 ctxt->emul_flags = vcpu->arch.hflags;
adf52235 5120
dd856efa 5121 init_decode_cache(ctxt);
7ae441ea 5122 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 5123}
5124
71f9833b 5125int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5126{
9d74191a 5127 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 5128 int ret;
5129
5130 init_emulate_ctxt(vcpu);
5131
9dac77fa
AK		 5132 ctxt->op_bytes = 2;
5133 ctxt->ad_bytes = 2;
5134 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5135 ret = emulate_int_real(ctxt, irq);
63995653
MG		 5136
5137 if (ret != X86EMUL_CONTINUE)
5138 return EMULATE_FAIL;
5139
9dac77fa 5140 ctxt->eip = ctxt->_eip;
9d74191a
TY		 5141 kvm_rip_write(vcpu, ctxt->eip);
5142 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 5143
5144 if (irq == NMI_VECTOR)
7460fb4a 5145 vcpu->arch.nmi_pending = 0;
63995653
MG		 5146 else
5147 vcpu->arch.interrupt.pending = false;
5148
5149 return EMULATE_DONE;
5150}
5151EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5152
6d77dbfc
GN		 5153static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5154{
fc3a9157
JR		 5155 int r = EMULATE_DONE;
5156
6d77dbfc
GN		 5157 ++vcpu->stat.insn_emulation_fail;
5158 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5159 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR		 5160 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5161 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5162 vcpu->run->internal.ndata = 0;
5163 r = EMULATE_FAIL;
5164 }
6d77dbfc 5165 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 5166
5167 return r;
6d77dbfc
GN		 5168}
5169
93c05d3e 5170static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 5171 bool write_fault_to_shadow_pgtable,
5172 int emulation_type)
a6f177ef 5173{
95b3cf69 5174 gpa_t gpa = cr2;
8e3d9d06 5175 pfn_t pfn;
a6f177ef 5176
991eebf9
GN		 5177 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5178 return false;
5179
95b3cf69
XG		 5180 if (!vcpu->arch.mmu.direct_map) {
5181 /*
5182 * Write permission should be allowed since only
5183 * write access need to be emulated.
5184 */
5185 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5186
95b3cf69
XG		 5187 /*
5188 * If the mapping is invalid in guest, let cpu retry
5189 * it to generate fault.
5190 */
5191 if (gpa == UNMAPPED_GVA)
5192 return true;
5193 }
a6f177ef 5194
8e3d9d06
XG		 5195 /*
5196 * Do not retry the unhandleable instruction if it faults on the
5197 * readonly host memory, otherwise it will goto a infinite loop:
5198 * retry instruction -> write #PF -> emulation fail -> retry
5199 * instruction -> ...
5200 */
5201 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 5202
5203 /*
5204 * If the instruction failed on the error pfn, it can not be fixed,
5205 * report the error to userspace.
5206 */
5207 if (is_error_noslot_pfn(pfn))
5208 return false;
5209
5210 kvm_release_pfn_clean(pfn);
5211
5212 /* The instructions are well-emulated on direct mmu. */
5213 if (vcpu->arch.mmu.direct_map) {
5214 unsigned int indirect_shadow_pages;
5215
5216 spin_lock(&vcpu->kvm->mmu_lock);
5217 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5218 spin_unlock(&vcpu->kvm->mmu_lock);
5219
5220 if (indirect_shadow_pages)
5221 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5222
a6f177ef 5223 return true;
8e3d9d06 5224 }
a6f177ef 5225
95b3cf69
XG		 5226 /*
5227 * if emulation was due to access to shadowed page table
5228 * and it failed try to unshadow page and re-enter the
5229 * guest to let CPU execute the instruction.
5230 */
5231 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 5232
5233 /*
5234 * If the access faults on its page table, it can not
5235 * be fixed by unprotecting shadow page and it should
5236 * be reported to userspace.
5237 */
5238 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 5239}
5240
1cb3f3ae
XG		 5241static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5242 unsigned long cr2, int emulation_type)
5243{
5244 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5245 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5246
5247 last_retry_eip = vcpu->arch.last_retry_eip;
5248 last_retry_addr = vcpu->arch.last_retry_addr;
5249
5250 /*
5251 * If the emulation is caused by #PF and it is non-page_table
5252 * writing instruction, it means the VM-EXIT is caused by shadow
5253 * page protected, we can zap the shadow page and retry this
5254 * instruction directly.
5255 *
5256 * Note: if the guest uses a non-page-table modifying instruction
5257 * on the PDE that points to the instruction, then we will unmap
5258 * the instruction and go to an infinite loop. So, we cache the
5259 * last retried eip and the last fault address, if we meet the eip
5260 * and the address again, we can break out of the potential infinite
5261 * loop.
5262 */
5263 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5264
5265 if (!(emulation_type & EMULTYPE_RETRY))
5266 return false;
5267
5268 if (x86_page_table_writing_insn(ctxt))
5269 return false;
5270
5271 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5272 return false;
5273
5274 vcpu->arch.last_retry_eip = ctxt->eip;
5275 vcpu->arch.last_retry_addr = cr2;
5276
5277 if (!vcpu->arch.mmu.direct_map)
5278 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5279
22368028 5280 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5281
5282 return true;
5283}
5284
716d51ab
GN		 5285static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5286static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5287
64d60670 5288static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5289{
64d60670 5290 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB		 5291 /* This is a good place to trace that we are exiting SMM. */
5292 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5293
64d60670
PB		 5294 if (unlikely(vcpu->arch.smi_pending)) {
5295 kvm_make_request(KVM_REQ_SMI, vcpu);
5296 vcpu->arch.smi_pending = 0;
cd7764fe
PB		 5297 } else {
5298 /* Process a latched INIT, if any. */
5299 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670
PB		 5300 }
5301 }
699023e2
PB		 5302
5303 kvm_mmu_reset_context(vcpu);
64d60670
PB		 5304}
5305
5306static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5307{
5308 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5309
a584539b 5310 vcpu->arch.hflags = emul_flags;
64d60670
PB		 5311
5312 if (changed & HF_SMM_MASK)
5313 kvm_smm_changed(vcpu);
a584539b
PB		 5314}
5315
4a1e10d5
PB		 5316static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5317 unsigned long *db)
5318{
5319 u32 dr6 = 0;
5320 int i;
5321 u32 enable, rwlen;
5322
5323 enable = dr7;
5324 rwlen = dr7 >> 16;
5325 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5326 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5327 dr6 |= (1 << i);
5328 return dr6;
5329}
5330
6addfc42 5331static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, unsigned long rflags, int *r)
663f4c61
PB		 5332{
5333 struct kvm_run *kvm_run = vcpu->run;
5334
5335 /*
6addfc42
PB		 5336 * rflags is the old, "raw" value of the flags. The new value has
5337 * not been saved yet.
663f4c61
PB		 5338 *
5339 * This is correct even for TF set by the guest, because "the
5340 * processor will not generate this exception after the instruction
5341 * that sets the TF flag".
5342 */
663f4c61
PB		 5343 if (unlikely(rflags & X86_EFLAGS_TF)) {
5344 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
6f43ed01
NA		 5345 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 |
5346 DR6_RTM;
663f4c61
PB		 5347 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5348 kvm_run->debug.arch.exception = DB_VECTOR;
5349 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5350 *r = EMULATE_USER_EXIT;
5351 } else {
5352 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5353 /*
5354 * "Certain debug exceptions may clear bit 0-3. The
5355 * remaining contents of the DR6 register are never
5356 * cleared by the processor".
5357 */
5358 vcpu->arch.dr6 &= ~15;
6f43ed01 5359 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
663f4c61
PB		 5360 kvm_queue_exception(vcpu, DB_VECTOR);
5361 }
5362 }
5363}
5364
4a1e10d5
PB		 5365static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5366{
4a1e10d5
PB		 5367 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5368 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA		 5369 struct kvm_run *kvm_run = vcpu->run;
5370 unsigned long eip = kvm_get_linear_rip(vcpu);
5371 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5372 vcpu->arch.guest_debug_dr7,
5373 vcpu->arch.eff_db);
5374
5375 if (dr6 != 0) {
6f43ed01 5376 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5377 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB		 5378 kvm_run->debug.arch.exception = DB_VECTOR;
5379 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5380 *r = EMULATE_USER_EXIT;
5381 return true;
5382 }
5383 }
5384
4161a569
NA		 5385 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5386 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA		 5387 unsigned long eip = kvm_get_linear_rip(vcpu);
5388 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB		 5389 vcpu->arch.dr7,
5390 vcpu->arch.db);
5391
5392 if (dr6 != 0) {
5393 vcpu->arch.dr6 &= ~15;
6f43ed01 5394 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB		 5395 kvm_queue_exception(vcpu, DB_VECTOR);
5396 *r = EMULATE_DONE;
5397 return true;
5398 }
5399 }
5400
5401 return false;
5402}
5403
51d8b661
AP		 5404int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5405 unsigned long cr2,
dc25e89e
AP		 5406 int emulation_type,
5407 void *insn,
5408 int insn_len)
bbd9b64e 5409{
95cb2295 5410 int r;
9d74191a 5411 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5412 bool writeback = true;
93c05d3e 5413 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5414
93c05d3e
XG		 5415 /*
5416 * Clear write_fault_to_shadow_pgtable here to ensure it is
5417 * never reused.
5418 */
5419 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5420 kvm_clear_exception_queue(vcpu);
8d7d8102 5421
571008da 5422 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5423 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5424
5425 /*
5426 * We will reenter on the same instruction since
5427 * we do not set complete_userspace_io. This does not
5428 * handle watchpoints yet, those would be handled in
5429 * the emulate_ops.
5430 */
5431 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5432 return r;
5433
9d74191a
TY		 5434 ctxt->interruptibility = 0;
5435 ctxt->have_exception = false;
e0ad0b47 5436 ctxt->exception.vector = -1;
9d74191a 5437 ctxt->perm_ok = false;
bbd9b64e 5438
b51e974f 5439 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5440
9d74191a 5441 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5442
e46479f8 5443 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5444 ++vcpu->stat.insn_emulation;
1d2887e2 5445 if (r != EMULATION_OK) {
4005996e
AK		 5446 if (emulation_type & EMULTYPE_TRAP_UD)
5447 return EMULATE_FAIL;
991eebf9
GN		 5448 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5449 emulation_type))
bbd9b64e 5450 return EMULATE_DONE;
6d77dbfc
GN		 5451 if (emulation_type & EMULTYPE_SKIP)
5452 return EMULATE_FAIL;
5453 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5454 }
5455 }
5456
ba8afb6b 5457 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5458 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA		 5459 if (ctxt->eflags & X86_EFLAGS_RF)
5460 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN		 5461 return EMULATE_DONE;
5462 }
5463
1cb3f3ae
XG		 5464 if (retry_instruction(ctxt, cr2, emulation_type))
5465 return EMULATE_DONE;
5466
7ae441ea 5467 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5468 changes registers values during IO operation */
7ae441ea
GN		 5469 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5470 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5471 emulator_invalidate_register_cache(ctxt);
7ae441ea 5472 }
4d2179e1 5473
5cd21917 5474restart:
9d74191a 5475 r = x86_emulate_insn(ctxt);
bbd9b64e 5476
775fde86
JR		 5477 if (r == EMULATION_INTERCEPTED)
5478 return EMULATE_DONE;
5479
d2ddd1c4 5480 if (r == EMULATION_FAILED) {
991eebf9
GN		 5481 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5482 emulation_type))
c3cd7ffa
GN		 5483 return EMULATE_DONE;
5484
6d77dbfc 5485 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5486 }
5487
9d74191a 5488 if (ctxt->have_exception) {
d2ddd1c4 5489 r = EMULATE_DONE;
ef54bcfe
PB		 5490 if (inject_emulated_exception(vcpu))
5491 return r;
d2ddd1c4 5492 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5493 if (!vcpu->arch.pio.in) {
5494 /* FIXME: return into emulator if single-stepping. */
3457e419 5495 vcpu->arch.pio.count = 0;
0912c977 5496 } else {
7ae441ea 5497 writeback = false;
716d51ab
GN		 5498 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5499 }
ac0a48c3 5500 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5501 } else if (vcpu->mmio_needed) {
5502 if (!vcpu->mmio_is_write)
5503 writeback = false;
ac0a48c3 5504 r = EMULATE_USER_EXIT;
716d51ab 5505 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5506 } else if (r == EMULATION_RESTART)
5cd21917 5507 goto restart;
d2ddd1c4
GN		 5508 else
5509 r = EMULATE_DONE;
f850e2e6 5510
7ae441ea 5511 if (writeback) {
6addfc42 5512 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5513 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5514 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
a584539b
PB		 5515 if (vcpu->arch.hflags != ctxt->emul_flags)
5516 kvm_set_hflags(vcpu, ctxt->emul_flags);
9d74191a 5517 kvm_rip_write(vcpu, ctxt->eip);
663f4c61 5518 if (r == EMULATE_DONE)
6addfc42 5519 kvm_vcpu_check_singlestep(vcpu, rflags, &r);
38827dbd
NA		 5520 if (!ctxt->have_exception ||
5521 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5522 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB		 5523
5524 /*
5525 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5526 * do nothing, and it will be requested again as soon as
5527 * the shadow expires. But we still need to check here,
5528 * because POPF has no interrupt shadow.
5529 */
5530 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5531 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN		 5532 } else
5533 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5534
5535 return r;
de7d789a 5536}
51d8b661 5537EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5538
cf8f70bf 5539int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5540{
cf8f70bf 5541 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5542 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5543 size, port, &val, 1);
cf8f70bf 5544 /* do not return to emulator after return from userspace */
7972995b 5545 vcpu->arch.pio.count = 0;
de7d789a
CO		 5546 return ret;
5547}
cf8f70bf 5548EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5549
8cfdc000
ZA		 5550static void tsc_bad(void *info)
5551{
0a3aee0d 5552 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5553}
5554
5555static void tsc_khz_changed(void *data)
c8076604 5556{
8cfdc000
ZA		 5557 struct cpufreq_freqs *freq = data;
5558 unsigned long khz = 0;
5559
5560 if (data)
5561 khz = freq->new;
5562 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5563 khz = cpufreq_quick_get(raw_smp_processor_id());
5564 if (!khz)
5565 khz = tsc_khz;
0a3aee0d 5566 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5567}
5568
c8076604
GH		 5569static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5570 void *data)
5571{
5572 struct cpufreq_freqs *freq = data;
5573 struct kvm *kvm;
5574 struct kvm_vcpu *vcpu;
5575 int i, send_ipi = 0;
5576
8cfdc000
ZA		 5577 /*
5578 * We allow guests to temporarily run on slowing clocks,
5579 * provided we notify them after, or to run on accelerating
5580 * clocks, provided we notify them before. Thus time never
5581 * goes backwards.
5582 *
5583 * However, we have a problem. We can't atomically update
5584 * the frequency of a given CPU from this function; it is
5585 * merely a notifier, which can be called from any CPU.
5586 * Changing the TSC frequency at arbitrary points in time
5587 * requires a recomputation of local variables related to
5588 * the TSC for each VCPU. We must flag these local variables
5589 * to be updated and be sure the update takes place with the
5590 * new frequency before any guests proceed.
5591 *
5592 * Unfortunately, the combination of hotplug CPU and frequency
5593 * change creates an intractable locking scenario; the order
5594 * of when these callouts happen is undefined with respect to
5595 * CPU hotplug, and they can race with each other. As such,
5596 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5597 * undefined; you can actually have a CPU frequency change take
5598 * place in between the computation of X and the setting of the
5599 * variable. To protect against this problem, all updates of
5600 * the per_cpu tsc_khz variable are done in an interrupt
5601 * protected IPI, and all callers wishing to update the value
5602 * must wait for a synchronous IPI to complete (which is trivial
5603 * if the caller is on the CPU already). This establishes the
5604 * necessary total order on variable updates.
5605 *
5606 * Note that because a guest time update may take place
5607 * anytime after the setting of the VCPU's request bit, the
5608 * correct TSC value must be set before the request. However,
5609 * to ensure the update actually makes it to any guest which
5610 * starts running in hardware virtualization between the set
5611 * and the acquisition of the spinlock, we must also ping the
5612 * CPU after setting the request bit.
5613 *
5614 */
5615
c8076604
GH		 5616 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5617 return 0;
5618 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5619 return 0;
8cfdc000
ZA		 5620
5621 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5622
2f303b74 5623 spin_lock(&kvm_lock);
c8076604 5624 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5625 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5626 if (vcpu->cpu != freq->cpu)
5627 continue;
c285545f 5628 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5629 if (vcpu->cpu != smp_processor_id())
8cfdc000 5630 send_ipi = 1;
c8076604
GH		 5631 }
5632 }
2f303b74 5633 spin_unlock(&kvm_lock);
c8076604
GH		 5634
5635 if (freq->old < freq->new && send_ipi) {
5636 /*
5637 * We upscale the frequency. Must make the guest
5638 * doesn't see old kvmclock values while running with
5639 * the new frequency, otherwise we risk the guest sees
5640 * time go backwards.
5641 *
5642 * In case we update the frequency for another cpu
5643 * (which might be in guest context) send an interrupt
5644 * to kick the cpu out of guest context. Next time
5645 * guest context is entered kvmclock will be updated,
5646 * so the guest will not see stale values.
5647 */
8cfdc000 5648 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5649 }
5650 return 0;
5651}
5652
5653static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5654 .notifier_call = kvmclock_cpufreq_notifier
5655};
5656
5657static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5658 unsigned long action, void *hcpu)
5659{
5660 unsigned int cpu = (unsigned long)hcpu;
5661
5662 switch (action) {
5663 case CPU_ONLINE:
5664 case CPU_DOWN_FAILED:
5665 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5666 break;
5667 case CPU_DOWN_PREPARE:
5668 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5669 break;
5670 }
5671 return NOTIFY_OK;
5672}
5673
5674static struct notifier_block kvmclock_cpu_notifier_block = {
5675 .notifier_call = kvmclock_cpu_notifier,
5676 .priority = -INT_MAX
c8076604
GH		 5677};
5678
b820cc0c
ZA		 5679static void kvm_timer_init(void)
5680{
5681 int cpu;
5682
c285545f 5683 max_tsc_khz = tsc_khz;
460dd42e
SB		 5684
5685 cpu_notifier_register_begin();
b820cc0c 5686 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5687#ifdef CONFIG_CPU_FREQ
5688 struct cpufreq_policy policy;
5689 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5690 cpu = get_cpu();
5691 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5692 if (policy.cpuinfo.max_freq)
5693 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5694 put_cpu();
c285545f 5695#endif
b820cc0c
ZA		 5696 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5697 CPUFREQ_TRANSITION_NOTIFIER);
5698 }
c285545f 5699 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5700 for_each_online_cpu(cpu)
5701 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
460dd42e
SB		 5702
5703 __register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5704 cpu_notifier_register_done();
5705
b820cc0c
ZA		 5706}
5707
ff9d07a0
ZY		 5708static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5709
f5132b01 5710int kvm_is_in_guest(void)
ff9d07a0 5711{
086c9855 5712 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5713}
5714
5715static int kvm_is_user_mode(void)
5716{
5717 int user_mode = 3;
dcf46b94 5718
086c9855
AS		 5719 if (__this_cpu_read(current_vcpu))
5720 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5721
ff9d07a0
ZY		 5722 return user_mode != 0;
5723}
5724
5725static unsigned long kvm_get_guest_ip(void)
5726{
5727 unsigned long ip = 0;
dcf46b94 5728
086c9855
AS		 5729 if (__this_cpu_read(current_vcpu))
5730 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5731
ff9d07a0
ZY		 5732 return ip;
5733}
5734
5735static struct perf_guest_info_callbacks kvm_guest_cbs = {
5736 .is_in_guest = kvm_is_in_guest,
5737 .is_user_mode = kvm_is_user_mode,
5738 .get_guest_ip = kvm_get_guest_ip,
5739};
5740
5741void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5742{
086c9855 5743 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5744}
5745EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5746
5747void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5748{
086c9855 5749 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5750}
5751EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5752
ce88decf
XG		 5753static void kvm_set_mmio_spte_mask(void)
5754{
5755 u64 mask;
5756 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5757
5758 /*
5759 * Set the reserved bits and the present bit of an paging-structure
5760 * entry to generate page fault with PFER.RSV = 1.
5761 */
885032b9 5762 /* Mask the reserved physical address bits. */
d1431483 5763 mask = rsvd_bits(maxphyaddr, 51);
885032b9
XG		 5764
5765 /* Bit 62 is always reserved for 32bit host. */
5766 mask |= 0x3ull << 62;
5767
5768 /* Set the present bit. */
ce88decf
XG		 5769 mask |= 1ull;
5770
5771#ifdef CONFIG_X86_64
5772 /*
5773 * If reserved bit is not supported, clear the present bit to disable
5774 * mmio page fault.
5775 */
5776 if (maxphyaddr == 52)
5777 mask &= ~1ull;
5778#endif
5779
5780 kvm_mmu_set_mmio_spte_mask(mask);
5781}
5782
16e8d74d
MT		 5783#ifdef CONFIG_X86_64
5784static void pvclock_gtod_update_fn(struct work_struct *work)
5785{
d828199e
MT		 5786 struct kvm *kvm;
5787
5788 struct kvm_vcpu *vcpu;
5789 int i;
5790
2f303b74 5791 spin_lock(&kvm_lock);
d828199e
MT		 5792 list_for_each_entry(kvm, &vm_list, vm_list)
5793 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 5794 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 5795 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5796 spin_unlock(&kvm_lock);
16e8d74d
MT		 5797}
5798
5799static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5800
5801/*
5802 * Notification about pvclock gtod data update.
5803 */
5804static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5805 void *priv)
5806{
5807 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5808 struct timekeeper *tk = priv;
5809
5810 update_pvclock_gtod(tk);
5811
5812 /* disable master clock if host does not trust, or does not
5813 * use, TSC clocksource
5814 */
5815 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5816 atomic_read(&kvm_guest_has_master_clock) != 0)
5817 queue_work(system_long_wq, &pvclock_gtod_work);
5818
5819 return 0;
5820}
5821
5822static struct notifier_block pvclock_gtod_notifier = {
5823 .notifier_call = pvclock_gtod_notify,
5824};
5825#endif
5826
f8c16bba 5827int kvm_arch_init(void *opaque)
043405e1 5828{
b820cc0c 5829 int r;
6b61edf7 5830 struct kvm_x86_ops *ops = opaque;
f8c16bba 5831
f8c16bba
ZX		 5832 if (kvm_x86_ops) {
5833 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5834 r = -EEXIST;
5835 goto out;
f8c16bba
ZX		 5836 }
5837
5838 if (!ops->cpu_has_kvm_support()) {
5839 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5840 r = -EOPNOTSUPP;
5841 goto out;
f8c16bba
ZX		 5842 }
5843 if (ops->disabled_by_bios()) {
5844 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5845 r = -EOPNOTSUPP;
5846 goto out;
f8c16bba
ZX		 5847 }
5848
013f6a5d
MT		 5849 r = -ENOMEM;
5850 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5851 if (!shared_msrs) {
5852 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5853 goto out;
5854 }
5855
97db56ce
AK		 5856 r = kvm_mmu_module_init();
5857 if (r)
013f6a5d 5858 goto out_free_percpu;
97db56ce 5859
ce88decf 5860 kvm_set_mmio_spte_mask();
97db56ce 5861
f8c16bba 5862 kvm_x86_ops = ops;
920c8377 5863
7b52345e 5864 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5865 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5866
b820cc0c 5867 kvm_timer_init();
c8076604 5868
ff9d07a0
ZY		 5869 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5870
2acf923e
DC		 5871 if (cpu_has_xsave)
5872 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5873
c5cc421b 5874 kvm_lapic_init();
16e8d74d
MT		 5875#ifdef CONFIG_X86_64
5876 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5877#endif
5878
f8c16bba 5879 return 0;
56c6d28a 5880
013f6a5d
MT		 5881out_free_percpu:
5882 free_percpu(shared_msrs);
56c6d28a 5883out:
56c6d28a 5884 return r;
043405e1 5885}
8776e519 5886
f8c16bba
ZX		 5887void kvm_arch_exit(void)
5888{
ff9d07a0
ZY		 5889 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5890
888d256e
JK		 5891 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5892 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5893 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5894 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5895#ifdef CONFIG_X86_64
5896 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5897#endif
f8c16bba 5898 kvm_x86_ops = NULL;
56c6d28a 5899 kvm_mmu_module_exit();
013f6a5d 5900 free_percpu(shared_msrs);
56c6d28a 5901}
f8c16bba 5902
5cb56059 5903int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB		 5904{
5905 ++vcpu->stat.halt_exits;
5906 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5907 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5908 return 1;
5909 } else {
5910 vcpu->run->exit_reason = KVM_EXIT_HLT;
5911 return 0;
5912 }
5913}
5cb56059
JS		 5914EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
5915
5916int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5917{
5918 kvm_x86_ops->skip_emulated_instruction(vcpu);
5919 return kvm_vcpu_halt(vcpu);
5920}
8776e519
HB		 5921EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5922
55cd8e5a
GN		 5923int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5924{
5925 u64 param, ingpa, outgpa, ret;
5926 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5927 bool fast, longmode;
55cd8e5a
GN		 5928
5929 /*
5930 * hypercall generates UD from non zero cpl and real mode
5931 * per HYPER-V spec
5932 */
3eeb3288 5933 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5934 kvm_queue_exception(vcpu, UD_VECTOR);
5935 return 0;
5936 }
5937
a449c7aa 5938 longmode = is_64_bit_mode(vcpu);
55cd8e5a
GN		 5939
5940 if (!longmode) {
ccd46936
GN		 5941 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5942 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5943 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5944 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5945 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5946 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5947 }
5948#ifdef CONFIG_X86_64
5949 else {
5950 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5951 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5952 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5953 }
5954#endif
5955
5956 code = param & 0xffff;
5957 fast = (param >> 16) & 0x1;
5958 rep_cnt = (param >> 32) & 0xfff;
5959 rep_idx = (param >> 48) & 0xfff;
5960
5961 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5962
c25bc163
GN		 5963 switch (code) {
5964 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5965 kvm_vcpu_on_spin(vcpu);
5966 break;
5967 default:
5968 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5969 break;
5970 }
55cd8e5a
GN		 5971
5972 ret = res | (((u64)rep_done & 0xfff) << 32);
5973 if (longmode) {
5974 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5975 } else {
5976 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5977 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5978 }
5979
5980 return 1;
5981}
5982
6aef266c
SV		 5983/*
5984 * kvm_pv_kick_cpu_op: Kick a vcpu.
5985 *
5986 * @apicid - apicid of vcpu to be kicked.
5987 */
5988static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5989{
24d2166b 5990 struct kvm_lapic_irq lapic_irq;
6aef266c 5991
24d2166b
R		 5992 lapic_irq.shorthand = 0;
5993 lapic_irq.dest_mode = 0;
5994 lapic_irq.dest_id = apicid;
93bbf0b8 5995 lapic_irq.msi_redir_hint = false;
6aef266c 5996
24d2166b 5997 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 5998 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV		 5999}
6000
8776e519
HB		 6001int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6002{
6003 unsigned long nr, a0, a1, a2, a3, ret;
a449c7aa 6004 int op_64_bit, r = 1;
8776e519 6005
5cb56059
JS		 6006 kvm_x86_ops->skip_emulated_instruction(vcpu);
6007
55cd8e5a
GN		 6008 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6009 return kvm_hv_hypercall(vcpu);
6010
5fdbf976
MT		 6011 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6012 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6013 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6014 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6015 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6016
229456fc 6017 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6018
a449c7aa
NA		 6019 op_64_bit = is_64_bit_mode(vcpu);
6020 if (!op_64_bit) {
8776e519
HB		 6021 nr &= 0xFFFFFFFF;
6022 a0 &= 0xFFFFFFFF;
6023 a1 &= 0xFFFFFFFF;
6024 a2 &= 0xFFFFFFFF;
6025 a3 &= 0xFFFFFFFF;
6026 }
6027
07708c4a
JK		 6028 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6029 ret = -KVM_EPERM;
6030 goto out;
6031 }
6032
8776e519 6033 switch (nr) {
b93463aa
AK		 6034 case KVM_HC_VAPIC_POLL_IRQ:
6035 ret = 0;
6036 break;
6aef266c
SV		 6037 case KVM_HC_KICK_CPU:
6038 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6039 ret = 0;
6040 break;
8776e519
HB		 6041 default:
6042 ret = -KVM_ENOSYS;
6043 break;
6044 }
07708c4a 6045out:
a449c7aa
NA		 6046 if (!op_64_bit)
6047 ret = (u32)ret;
5fdbf976 6048 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6049 ++vcpu->stat.hypercalls;
2f333bcb 6050 return r;
8776e519
HB		 6051}
6052EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6053
b6785def 6054static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6055{
d6aa1000 6056 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6057 char instruction[3];
5fdbf976 6058 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6059
8776e519 6060 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6061
9d74191a 6062 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 6063}
6064
b6c7a5dc
HB		 6065/*
6066 * Check if userspace requested an interrupt window, and that the
6067 * interrupt window is open.
6068 *
6069 * No need to exit to userspace if we already have an interrupt queued.
6070 */
851ba692 6071static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6072{
8061823a 6073 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 6074 vcpu->run->request_interrupt_window &&
5df56646 6075 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 6076}
6077
851ba692 6078static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6079{
851ba692
AK		 6080 struct kvm_run *kvm_run = vcpu->run;
6081
91586a3b 6082 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6083 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6084 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6085 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 6086 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 6087 kvm_run->ready_for_interrupt_injection = 1;
4531220b 6088 else
b6c7a5dc 6089 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 6090 kvm_arch_interrupt_allowed(vcpu) &&
6091 !kvm_cpu_has_interrupt(vcpu) &&
6092 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 6093}
6094
95ba8273
GN		 6095static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6096{
6097 int max_irr, tpr;
6098
6099 if (!kvm_x86_ops->update_cr8_intercept)
6100 return;
6101
88c808fd
AK		 6102 if (!vcpu->arch.apic)
6103 return;
6104
8db3baa2
GN		 6105 if (!vcpu->arch.apic->vapic_addr)
6106 max_irr = kvm_lapic_find_highest_irr(vcpu);
6107 else
6108 max_irr = -1;
95ba8273
GN		 6109
6110 if (max_irr != -1)
6111 max_irr >>= 4;
6112
6113 tpr = kvm_lapic_get_cr8(vcpu);
6114
6115 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6116}
6117
b6b8a145 6118static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6119{
b6b8a145
JK		 6120 int r;
6121
95ba8273 6122 /* try to reinject previous events if any */
b59bb7bd 6123 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 6124 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6125 vcpu->arch.exception.has_error_code,
6126 vcpu->arch.exception.error_code);
d6e8c854
NA		 6127
6128 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6129 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6130 X86_EFLAGS_RF);
6131
6bdf0662
NA		 6132 if (vcpu->arch.exception.nr == DB_VECTOR &&
6133 (vcpu->arch.dr7 & DR7_GD)) {
6134 vcpu->arch.dr7 &= ~DR7_GD;
6135 kvm_update_dr7(vcpu);
6136 }
6137
b59bb7bd
GN		 6138 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
6139 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 6140 vcpu->arch.exception.error_code,
6141 vcpu->arch.exception.reinject);
b6b8a145 6142 return 0;
b59bb7bd
GN		 6143 }
6144
95ba8273
GN		 6145 if (vcpu->arch.nmi_injected) {
6146 kvm_x86_ops->set_nmi(vcpu);
b6b8a145 6147 return 0;
95ba8273
GN		 6148 }
6149
6150 if (vcpu->arch.interrupt.pending) {
66fd3f7f 6151 kvm_x86_ops->set_irq(vcpu);
b6b8a145
JK		 6152 return 0;
6153 }
6154
6155 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6156 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6157 if (r != 0)
6158 return r;
95ba8273
GN		 6159 }
6160
6161 /* try to inject new event if pending */
6162 if (vcpu->arch.nmi_pending) {
6163 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 6164 --vcpu->arch.nmi_pending;
95ba8273
GN		 6165 vcpu->arch.nmi_injected = true;
6166 kvm_x86_ops->set_nmi(vcpu);
6167 }
c7c9c56c 6168 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD		 6169 /*
6170 * Because interrupts can be injected asynchronously, we are
6171 * calling check_nested_events again here to avoid a race condition.
6172 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6173 * proposal and current concerns. Perhaps we should be setting
6174 * KVM_REQ_EVENT only on certain events and not unconditionally?
6175 */
6176 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6177 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6178 if (r != 0)
6179 return r;
6180 }
95ba8273 6181 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 6182 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6183 false);
6184 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 6185 }
6186 }
b6b8a145 6187 return 0;
95ba8273
GN		 6188}
6189
7460fb4a
AK		 6190static void process_nmi(struct kvm_vcpu *vcpu)
6191{
6192 unsigned limit = 2;
6193
6194 /*
6195 * x86 is limited to one NMI running, and one NMI pending after it.
6196 * If an NMI is already in progress, limit further NMIs to just one.
6197 * Otherwise, allow two (and we'll inject the first one immediately).
6198 */
6199 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6200 limit = 1;
6201
6202 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6203 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6204 kvm_make_request(KVM_REQ_EVENT, vcpu);
6205}
6206
660a5d51
PB		 6207#define put_smstate(type, buf, offset, val) \
6208 *(type *)((buf) + (offset) - 0x7e00) = val
6209
6210static u32 process_smi_get_segment_flags(struct kvm_segment *seg)
6211{
6212 u32 flags = 0;
6213 flags |= seg->g << 23;
6214 flags |= seg->db << 22;
6215 flags |= seg->l << 21;
6216 flags |= seg->avl << 20;
6217 flags |= seg->present << 15;
6218 flags |= seg->dpl << 13;
6219 flags |= seg->s << 12;
6220 flags |= seg->type << 8;
6221 return flags;
6222}
6223
6224static void process_smi_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
6225{
6226 struct kvm_segment seg;
6227 int offset;
6228
6229 kvm_get_segment(vcpu, &seg, n);
6230 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6231
6232 if (n < 3)
6233 offset = 0x7f84 + n * 12;
6234 else
6235 offset = 0x7f2c + (n - 3) * 12;
6236
6237 put_smstate(u32, buf, offset + 8, seg.base);
6238 put_smstate(u32, buf, offset + 4, seg.limit);
6239 put_smstate(u32, buf, offset, process_smi_get_segment_flags(&seg));
6240}
6241
6242static void process_smi_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
6243{
6244 struct kvm_segment seg;
6245 int offset;
6246 u16 flags;
6247
6248 kvm_get_segment(vcpu, &seg, n);
6249 offset = 0x7e00 + n * 16;
6250
6251 flags = process_smi_get_segment_flags(&seg) >> 8;
6252 put_smstate(u16, buf, offset, seg.selector);
6253 put_smstate(u16, buf, offset + 2, flags);
6254 put_smstate(u32, buf, offset + 4, seg.limit);
6255 put_smstate(u64, buf, offset + 8, seg.base);
6256}
6257
6258static void process_smi_save_state_32(struct kvm_vcpu *vcpu, char *buf)
6259{
6260 struct desc_ptr dt;
6261 struct kvm_segment seg;
6262 unsigned long val;
6263 int i;
6264
6265 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6266 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6267 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6268 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6269
6270 for (i = 0; i < 8; i++)
6271 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6272
6273 kvm_get_dr(vcpu, 6, &val);
6274 put_smstate(u32, buf, 0x7fcc, (u32)val);
6275 kvm_get_dr(vcpu, 7, &val);
6276 put_smstate(u32, buf, 0x7fc8, (u32)val);
6277
6278 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6279 put_smstate(u32, buf, 0x7fc4, seg.selector);
6280 put_smstate(u32, buf, 0x7f64, seg.base);
6281 put_smstate(u32, buf, 0x7f60, seg.limit);
6282 put_smstate(u32, buf, 0x7f5c, process_smi_get_segment_flags(&seg));
6283
6284 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6285 put_smstate(u32, buf, 0x7fc0, seg.selector);
6286 put_smstate(u32, buf, 0x7f80, seg.base);
6287 put_smstate(u32, buf, 0x7f7c, seg.limit);
6288 put_smstate(u32, buf, 0x7f78, process_smi_get_segment_flags(&seg));
6289
6290 kvm_x86_ops->get_gdt(vcpu, &dt);
6291 put_smstate(u32, buf, 0x7f74, dt.address);
6292 put_smstate(u32, buf, 0x7f70, dt.size);
6293
6294 kvm_x86_ops->get_idt(vcpu, &dt);
6295 put_smstate(u32, buf, 0x7f58, dt.address);
6296 put_smstate(u32, buf, 0x7f54, dt.size);
6297
6298 for (i = 0; i < 6; i++)
6299 process_smi_save_seg_32(vcpu, buf, i);
6300
6301 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6302
6303 /* revision id */
6304 put_smstate(u32, buf, 0x7efc, 0x00020000);
6305 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6306}
6307
6308static void process_smi_save_state_64(struct kvm_vcpu *vcpu, char *buf)
6309{
6310#ifdef CONFIG_X86_64
6311 struct desc_ptr dt;
6312 struct kvm_segment seg;
6313 unsigned long val;
6314 int i;
6315
6316 for (i = 0; i < 16; i++)
6317 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6318
6319 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6320 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6321
6322 kvm_get_dr(vcpu, 6, &val);
6323 put_smstate(u64, buf, 0x7f68, val);
6324 kvm_get_dr(vcpu, 7, &val);
6325 put_smstate(u64, buf, 0x7f60, val);
6326
6327 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6328 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6329 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6330
6331 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6332
6333 /* revision id */
6334 put_smstate(u32, buf, 0x7efc, 0x00020064);
6335
6336 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6337
6338 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6339 put_smstate(u16, buf, 0x7e90, seg.selector);
6340 put_smstate(u16, buf, 0x7e92, process_smi_get_segment_flags(&seg) >> 8);
6341 put_smstate(u32, buf, 0x7e94, seg.limit);
6342 put_smstate(u64, buf, 0x7e98, seg.base);
6343
6344 kvm_x86_ops->get_idt(vcpu, &dt);
6345 put_smstate(u32, buf, 0x7e84, dt.size);
6346 put_smstate(u64, buf, 0x7e88, dt.address);
6347
6348 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6349 put_smstate(u16, buf, 0x7e70, seg.selector);
6350 put_smstate(u16, buf, 0x7e72, process_smi_get_segment_flags(&seg) >> 8);
6351 put_smstate(u32, buf, 0x7e74, seg.limit);
6352 put_smstate(u64, buf, 0x7e78, seg.base);
6353
6354 kvm_x86_ops->get_gdt(vcpu, &dt);
6355 put_smstate(u32, buf, 0x7e64, dt.size);
6356 put_smstate(u64, buf, 0x7e68, dt.address);
6357
6358 for (i = 0; i < 6; i++)
6359 process_smi_save_seg_64(vcpu, buf, i);
6360#else
6361 WARN_ON_ONCE(1);
6362#endif
6363}
6364
64d60670
PB		 6365static void process_smi(struct kvm_vcpu *vcpu)
6366{
660a5d51
PB		 6367 struct kvm_segment cs, ds;
6368 char buf[512];
6369 u32 cr0;
6370
64d60670
PB		 6371 if (is_smm(vcpu)) {
6372 vcpu->arch.smi_pending = true;
6373 return;
6374 }
6375
660a5d51
PB		 6376 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
6377 vcpu->arch.hflags |= HF_SMM_MASK;
6378 memset(buf, 0, 512);
6379 if (guest_cpuid_has_longmode(vcpu))
6380 process_smi_save_state_64(vcpu, buf);
6381 else
6382 process_smi_save_state_32(vcpu, buf);
6383
54bf36aa 6384 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB		 6385
6386 if (kvm_x86_ops->get_nmi_mask(vcpu))
6387 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6388 else
6389 kvm_x86_ops->set_nmi_mask(vcpu, true);
6390
6391 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6392 kvm_rip_write(vcpu, 0x8000);
6393
6394 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6395 kvm_x86_ops->set_cr0(vcpu, cr0);
6396 vcpu->arch.cr0 = cr0;
6397
6398 kvm_x86_ops->set_cr4(vcpu, 0);
6399
6400 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6401
6402 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6403 cs.base = vcpu->arch.smbase;
6404
6405 ds.selector = 0;
6406 ds.base = 0;
6407
6408 cs.limit = ds.limit = 0xffffffff;
6409 cs.type = ds.type = 0x3;
6410 cs.dpl = ds.dpl = 0;
6411 cs.db = ds.db = 0;
6412 cs.s = ds.s = 1;
6413 cs.l = ds.l = 0;
6414 cs.g = ds.g = 1;
6415 cs.avl = ds.avl = 0;
6416 cs.present = ds.present = 1;
6417 cs.unusable = ds.unusable = 0;
6418 cs.padding = ds.padding = 0;
6419
6420 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6421 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6422 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6423 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6424 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6425 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6426
6427 if (guest_cpuid_has_longmode(vcpu))
6428 kvm_x86_ops->set_efer(vcpu, 0);
6429
6430 kvm_update_cpuid(vcpu);
6431 kvm_mmu_reset_context(vcpu);
64d60670
PB		 6432}
6433
3d81bc7e 6434static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 6435{
6436 u64 eoi_exit_bitmap[4];
cf9e65b7 6437 u32 tmr[8];
c7c9c56c 6438
3d81bc7e
YZ		 6439 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6440 return;
c7c9c56c
YZ		 6441
6442 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 6443 memset(tmr, 0, 32);
c7c9c56c 6444
cf9e65b7 6445 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 6446 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 6447 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 6448}
6449
a70656b6
RK		 6450static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6451{
6452 ++vcpu->stat.tlb_flush;
6453 kvm_x86_ops->tlb_flush(vcpu);
6454}
6455
4256f43f
TC		 6456void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6457{
c24ae0dc
TC		 6458 struct page *page = NULL;
6459
f439ed27
PB		 6460 if (!irqchip_in_kernel(vcpu->kvm))
6461 return;
6462
4256f43f
TC		 6463 if (!kvm_x86_ops->set_apic_access_page_addr)
6464 return;
6465
c24ae0dc 6466 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA		 6467 if (is_error_page(page))
6468 return;
c24ae0dc
TC		 6469 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6470
6471 /*
6472 * Do not pin apic access page in memory, the MMU notifier
6473 * will call us again if it is migrated or swapped out.
6474 */
6475 put_page(page);
4256f43f
TC		 6476}
6477EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6478
fe71557a
TC		 6479void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
6480 unsigned long address)
6481{
c24ae0dc
TC		 6482 /*
6483 * The physical address of apic access page is stored in the VMCS.
6484 * Update it when it becomes invalid.
6485 */
6486 if (address == gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT))
6487 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
fe71557a
TC		 6488}
6489
9357d939 6490/*
362c698f 6491 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY		 6492 * exiting to the userspace. Otherwise, the value will be returned to the
6493 * userspace.
6494 */
851ba692 6495static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 6496{
6497 int r;
6a8b1d13 6498 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 6499 vcpu->run->request_interrupt_window;
730dca42 6500 bool req_immediate_exit = false;
b6c7a5dc 6501
3e007509 6502 if (vcpu->requests) {
a8eeb04a 6503 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6504 kvm_mmu_unload(vcpu);
a8eeb04a 6505 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6506 __kvm_migrate_timers(vcpu);
d828199e
MT		 6507 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6508 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 6509 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6510 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 6511 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6512 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 6513 if (unlikely(r))
6514 goto out;
6515 }
a8eeb04a 6516 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6517 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6518 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6519 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6520 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6521 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 6522 r = 0;
6523 goto out;
6524 }
a8eeb04a 6525 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6526 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 6527 r = 0;
6528 goto out;
6529 }
a8eeb04a 6530 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 6531 vcpu->fpu_active = 0;
6532 kvm_x86_ops->fpu_deactivate(vcpu);
6533 }
af585b92
GN		 6534 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6535 /* Page is swapped out. Do synthetic halt */
6536 vcpu->arch.apf.halted = true;
6537 r = 1;
6538 goto out;
6539 }
c9aaa895
GC		 6540 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6541 record_steal_time(vcpu);
64d60670
PB		 6542 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6543 process_smi(vcpu);
7460fb4a
AK		 6544 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6545 process_nmi(vcpu);
f5132b01
GN		 6546 if (kvm_check_request(KVM_REQ_PMU, vcpu))
6547 kvm_handle_pmu_event(vcpu);
6548 if (kvm_check_request(KVM_REQ_PMI, vcpu))
6549 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 6550 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6551 vcpu_scan_ioapic(vcpu);
4256f43f
TC		 6552 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6553 kvm_vcpu_reload_apic_access_page(vcpu);
2f52d58c 6554 }
b93463aa 6555
b463a6f7 6556 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 6557 kvm_apic_accept_events(vcpu);
6558 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6559 r = 1;
6560 goto out;
6561 }
6562
b6b8a145
JK		 6563 if (inject_pending_event(vcpu, req_int_win) != 0)
6564 req_immediate_exit = true;
b463a6f7 6565 /* enable NMI/IRQ window open exits if needed */
b6b8a145 6566 else if (vcpu->arch.nmi_pending)
c9a7953f 6567 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 6568 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
c9a7953f 6569 kvm_x86_ops->enable_irq_window(vcpu);
b463a6f7
AK		 6570
6571 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 6572 /*
6573 * Update architecture specific hints for APIC
6574 * virtual interrupt delivery.
6575 */
6576 if (kvm_x86_ops->hwapic_irr_update)
6577 kvm_x86_ops->hwapic_irr_update(vcpu,
6578 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 6579 update_cr8_intercept(vcpu);
6580 kvm_lapic_sync_to_vapic(vcpu);
6581 }
6582 }
6583
d8368af8
AK		 6584 r = kvm_mmu_reload(vcpu);
6585 if (unlikely(r)) {
d905c069 6586 goto cancel_injection;
d8368af8
AK		 6587 }
6588
b6c7a5dc
HB		 6589 preempt_disable();
6590
6591 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 6592 if (vcpu->fpu_active)
6593 kvm_load_guest_fpu(vcpu);
2acf923e 6594 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 6595
6b7e2d09
XG		 6596 vcpu->mode = IN_GUEST_MODE;
6597
01b71917
MT		 6598 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6599
6b7e2d09
XG		 6600 /* We should set ->mode before check ->requests,
6601 * see the comment in make_all_cpus_request.
6602 */
01b71917 6603 smp_mb__after_srcu_read_unlock();
b6c7a5dc 6604
d94e1dc9 6605 local_irq_disable();
32f88400 6606
6b7e2d09 6607 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 6608 || need_resched() || signal_pending(current)) {
6b7e2d09 6609 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6610 smp_wmb();
6c142801
AK		 6611 local_irq_enable();
6612 preempt_enable();
01b71917 6613 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 6614 r = 1;
d905c069 6615 goto cancel_injection;
6c142801
AK		 6616 }
6617
d6185f20
NHE		 6618 if (req_immediate_exit)
6619 smp_send_reschedule(vcpu->cpu);
6620
ccf73aaf 6621 __kvm_guest_enter();
b6c7a5dc 6622
42dbaa5a 6623 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 6624 set_debugreg(0, 7);
6625 set_debugreg(vcpu->arch.eff_db[0], 0);
6626 set_debugreg(vcpu->arch.eff_db[1], 1);
6627 set_debugreg(vcpu->arch.eff_db[2], 2);
6628 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 6629 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 6630 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 6631 }
b6c7a5dc 6632
229456fc 6633 trace_kvm_entry(vcpu->vcpu_id);
d0659d94 6634 wait_lapic_expire(vcpu);
851ba692 6635 kvm_x86_ops->run(vcpu);
b6c7a5dc 6636
c77fb5fe
PB		 6637 /*
6638 * Do this here before restoring debug registers on the host. And
6639 * since we do this before handling the vmexit, a DR access vmexit
6640 * can (a) read the correct value of the debug registers, (b) set
6641 * KVM_DEBUGREG_WONT_EXIT again.
6642 */
6643 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
6644 int i;
6645
6646 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
6647 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
6648 for (i = 0; i < KVM_NR_DB_REGS; i++)
6649 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6650 }
6651
24f1e32c
FW		 6652 /*
6653 * If the guest has used debug registers, at least dr7
6654 * will be disabled while returning to the host.
6655 * If we don't have active breakpoints in the host, we don't
6656 * care about the messed up debug address registers. But if
6657 * we have some of them active, restore the old state.
6658 */
59d8eb53 6659 if (hw_breakpoint_active())
24f1e32c 6660 hw_breakpoint_restore();
42dbaa5a 6661
886b470c
MT		 6662 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6663 native_read_tsc());
1d5f066e 6664
6b7e2d09 6665 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6666 smp_wmb();
a547c6db
YZ		 6667
6668 /* Interrupt is enabled by handle_external_intr() */
6669 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6670
6671 ++vcpu->stat.exits;
6672
6673 /*
6674 * We must have an instruction between local_irq_enable() and
6675 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6676 * the interrupt shadow. The stat.exits increment will do nicely.
6677 * But we need to prevent reordering, hence this barrier():
6678 */
6679 barrier();
6680
6681 kvm_guest_exit();
6682
6683 preempt_enable();
6684
f656ce01 6685 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6686
b6c7a5dc
HB		 6687 /*
6688 * Profile KVM exit RIPs:
6689 */
6690 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6691 unsigned long rip = kvm_rip_read(vcpu);
6692 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6693 }
6694
cc578287
ZA		 6695 if (unlikely(vcpu->arch.tsc_always_catchup))
6696 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6697
5cfb1d5a
MT		 6698 if (vcpu->arch.apic_attention)
6699 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6700
851ba692 6701 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6702 return r;
6703
6704cancel_injection:
6705 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6706 if (unlikely(vcpu->arch.apic_attention))
6707 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6708out:
6709 return r;
6710}
b6c7a5dc 6711
362c698f
PB		 6712static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
6713{
9c8fd1ba
PB		 6714 if (!kvm_arch_vcpu_runnable(vcpu)) {
6715 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6716 kvm_vcpu_block(vcpu);
6717 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
6718 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
6719 return 1;
6720 }
362c698f
PB		 6721
6722 kvm_apic_accept_events(vcpu);
6723 switch(vcpu->arch.mp_state) {
6724 case KVM_MP_STATE_HALTED:
6725 vcpu->arch.pv.pv_unhalted = false;
6726 vcpu->arch.mp_state =
6727 KVM_MP_STATE_RUNNABLE;
6728 case KVM_MP_STATE_RUNNABLE:
6729 vcpu->arch.apf.halted = false;
6730 break;
6731 case KVM_MP_STATE_INIT_RECEIVED:
6732 break;
6733 default:
6734 return -EINTR;
6735 break;
6736 }
6737 return 1;
6738}
09cec754 6739
362c698f 6740static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6741{
6742 int r;
f656ce01 6743 struct kvm *kvm = vcpu->kvm;
d7690175 6744
f656ce01 6745 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6746
362c698f 6747 for (;;) {
af585b92
GN		 6748 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6749 !vcpu->arch.apf.halted)
851ba692 6750 r = vcpu_enter_guest(vcpu);
362c698f
PB		 6751 else
6752 r = vcpu_block(kvm, vcpu);
09cec754
GN		 6753 if (r <= 0)
6754 break;
6755
6756 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6757 if (kvm_cpu_has_pending_timer(vcpu))
6758 kvm_inject_pending_timer_irqs(vcpu);
6759
851ba692 6760 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6761 r = -EINTR;
851ba692 6762 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6763 ++vcpu->stat.request_irq_exits;
362c698f 6764 break;
09cec754 6765 }
af585b92
GN		 6766
6767 kvm_check_async_pf_completion(vcpu);
6768
09cec754
GN		 6769 if (signal_pending(current)) {
6770 r = -EINTR;
851ba692 6771 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 6772 ++vcpu->stat.signal_exits;
362c698f 6773 break;
09cec754
GN		 6774 }
6775 if (need_resched()) {
f656ce01 6776 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6777 cond_resched();
f656ce01 6778 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6779 }
b6c7a5dc
HB		 6780 }
6781
f656ce01 6782 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6783
6784 return r;
6785}
6786
716d51ab
GN		 6787static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6788{
6789 int r;
6790 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6791 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6792 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6793 if (r != EMULATE_DONE)
6794 return 0;
6795 return 1;
6796}
6797
6798static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6799{
6800 BUG_ON(!vcpu->arch.pio.count);
6801
6802 return complete_emulated_io(vcpu);
6803}
6804
f78146b0
AK		 6805/*
6806 * Implements the following, as a state machine:
6807 *
6808 * read:
6809 * for each fragment
87da7e66
XG		 6810 * for each mmio piece in the fragment
6811 * write gpa, len
6812 * exit
6813 * copy data
f78146b0
AK		 6814 * execute insn
6815 *
6816 * write:
6817 * for each fragment
87da7e66
XG		 6818 * for each mmio piece in the fragment
6819 * write gpa, len
6820 * copy data
6821 * exit
f78146b0 6822 */
716d51ab 6823static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6824{
6825 struct kvm_run *run = vcpu->run;
f78146b0 6826 struct kvm_mmio_fragment *frag;
87da7e66 6827 unsigned len;
5287f194 6828
716d51ab 6829 BUG_ON(!vcpu->mmio_needed);
5287f194 6830
716d51ab 6831 /* Complete previous fragment */
87da7e66
XG		 6832 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6833 len = min(8u, frag->len);
716d51ab 6834 if (!vcpu->mmio_is_write)
87da7e66
XG		 6835 memcpy(frag->data, run->mmio.data, len);
6836
6837 if (frag->len <= 8) {
6838 /* Switch to the next fragment. */
6839 frag++;
6840 vcpu->mmio_cur_fragment++;
6841 } else {
6842 /* Go forward to the next mmio piece. */
6843 frag->data += len;
6844 frag->gpa += len;
6845 frag->len -= len;
6846 }
6847
a08d3b3b 6848 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 6849 vcpu->mmio_needed = 0;
0912c977
PB		 6850
6851 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6852 if (vcpu->mmio_is_write)
716d51ab
GN		 6853 return 1;
6854 vcpu->mmio_read_completed = 1;
6855 return complete_emulated_io(vcpu);
6856 }
87da7e66 6857
716d51ab
GN		 6858 run->exit_reason = KVM_EXIT_MMIO;
6859 run->mmio.phys_addr = frag->gpa;
6860 if (vcpu->mmio_is_write)
87da7e66
XG		 6861 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6862 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6863 run->mmio.is_write = vcpu->mmio_is_write;
6864 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6865 return 0;
5287f194
AK		 6866}
6867
716d51ab 6868
b6c7a5dc
HB		 6869int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6870{
6871 int r;
6872 sigset_t sigsaved;
6873
e5c30142
AK		 6874 if (!tsk_used_math(current) && init_fpu(current))
6875 return -ENOMEM;
6876
ac9f6dc0
AK		 6877 if (vcpu->sigset_active)
6878 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6879
a4535290 6880 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6881 kvm_vcpu_block(vcpu);
66450a21 6882 kvm_apic_accept_events(vcpu);
d7690175 6883 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6884 r = -EAGAIN;
6885 goto out;
b6c7a5dc
HB		 6886 }
6887
b6c7a5dc 6888 /* re-sync apic's tpr */
eea1cff9
AP		 6889 if (!irqchip_in_kernel(vcpu->kvm)) {
6890 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6891 r = -EINVAL;
6892 goto out;
6893 }
6894 }
b6c7a5dc 6895
716d51ab
GN		 6896 if (unlikely(vcpu->arch.complete_userspace_io)) {
6897 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6898 vcpu->arch.complete_userspace_io = NULL;
6899 r = cui(vcpu);
6900 if (r <= 0)
6901 goto out;
6902 } else
6903 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6904
362c698f 6905 r = vcpu_run(vcpu);
b6c7a5dc
HB		 6906
6907out:
f1d86e46 6908 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6909 if (vcpu->sigset_active)
6910 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6911
b6c7a5dc
HB		 6912 return r;
6913}
6914
6915int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6916{
7ae441ea
GN		 6917 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6918 /*
6919 * We are here if userspace calls get_regs() in the middle of
6920 * instruction emulation. Registers state needs to be copied
4a969980 6921 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6922 * that usually, but some bad designed PV devices (vmware
6923 * backdoor interface) need this to work
6924 */
dd856efa 6925 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6926 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6927 }
5fdbf976
MT		 6928 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6929 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6930 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6931 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6932 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6933 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6934 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6935 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6936#ifdef CONFIG_X86_64
5fdbf976
MT		 6937 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6938 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6939 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6940 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6941 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6942 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6943 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6944 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6945#endif
6946
5fdbf976 6947 regs->rip = kvm_rip_read(vcpu);
91586a3b 6948 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6949
b6c7a5dc
HB		 6950 return 0;
6951}
6952
6953int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6954{
7ae441ea
GN		 6955 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6956 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6957
5fdbf976
MT		 6958 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6959 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6960 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6961 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6962 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6963 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6964 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6965 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6966#ifdef CONFIG_X86_64
5fdbf976
MT		 6967 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6968 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6969 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6970 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6971 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6972 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6973 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6974 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6975#endif
6976
5fdbf976 6977 kvm_rip_write(vcpu, regs->rip);
91586a3b 6978 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6979
b4f14abd
JK		 6980 vcpu->arch.exception.pending = false;
6981
3842d135
AK		 6982 kvm_make_request(KVM_REQ_EVENT, vcpu);
6983
b6c7a5dc
HB		 6984 return 0;
6985}
6986
b6c7a5dc
HB		 6987void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6988{
6989 struct kvm_segment cs;
6990
3e6e0aab 6991 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6992 *db = cs.db;
6993 *l = cs.l;
6994}
6995EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6996
6997int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6998 struct kvm_sregs *sregs)
6999{
89a27f4d 7000 struct desc_ptr dt;
b6c7a5dc 7001
3e6e0aab
GT		 7002 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7003 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7004 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7005 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7006 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7007 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7008
3e6e0aab
GT		 7009 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7010 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 7011
7012 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 7013 sregs->idt.limit = dt.size;
7014 sregs->idt.base = dt.address;
b6c7a5dc 7015 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 7016 sregs->gdt.limit = dt.size;
7017 sregs->gdt.base = dt.address;
b6c7a5dc 7018
4d4ec087 7019 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7020 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7021 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7022 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7023 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7024 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 7025 sregs->apic_base = kvm_get_apic_base(vcpu);
7026
923c61bb 7027 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7028
36752c9b 7029 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 7030 set_bit(vcpu->arch.interrupt.nr,
7031 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7032
b6c7a5dc
HB		 7033 return 0;
7034}
7035
62d9f0db
MT		 7036int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7037 struct kvm_mp_state *mp_state)
7038{
66450a21 7039 kvm_apic_accept_events(vcpu);
6aef266c
SV		 7040 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7041 vcpu->arch.pv.pv_unhalted)
7042 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7043 else
7044 mp_state->mp_state = vcpu->arch.mp_state;
7045
62d9f0db
MT		 7046 return 0;
7047}
7048
7049int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7050 struct kvm_mp_state *mp_state)
7051{
66450a21
JK		 7052 if (!kvm_vcpu_has_lapic(vcpu) &&
7053 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7054 return -EINVAL;
7055
7056 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7057 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7058 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7059 } else
7060 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7061 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 7062 return 0;
7063}
7064
7f3d35fd
KW		 7065int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7066 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7067{
9d74191a 7068 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7069 int ret;
e01c2426 7070
8ec4722d 7071 init_emulate_ctxt(vcpu);
c697518a 7072
7f3d35fd 7073 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7074 has_error_code, error_code);
c697518a 7075
c697518a 7076 if (ret)
19d04437 7077 return EMULATE_FAIL;
37817f29 7078
9d74191a
TY		 7079 kvm_rip_write(vcpu, ctxt->eip);
7080 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7081 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7082 return EMULATE_DONE;
37817f29
IE		 7083}
7084EXPORT_SYMBOL_GPL(kvm_task_switch);
7085
b6c7a5dc
HB		 7086int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7087 struct kvm_sregs *sregs)
7088{
58cb628d 7089 struct msr_data apic_base_msr;
b6c7a5dc 7090 int mmu_reset_needed = 0;
63f42e02 7091 int pending_vec, max_bits, idx;
89a27f4d 7092 struct desc_ptr dt;
b6c7a5dc 7093
6d1068b3
PM		 7094 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
7095 return -EINVAL;
7096
89a27f4d
GN		 7097 dt.size = sregs->idt.limit;
7098 dt.address = sregs->idt.base;
b6c7a5dc 7099 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 7100 dt.size = sregs->gdt.limit;
7101 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 7102 kvm_x86_ops->set_gdt(vcpu, &dt);
7103
ad312c7c 7104 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7105 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7106 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7107 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7108
2d3ad1f4 7109 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7110
f6801dff 7111 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7112 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 7113 apic_base_msr.data = sregs->apic_base;
7114 apic_base_msr.host_initiated = true;
7115 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 7116
4d4ec087 7117 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7118 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7119 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7120
fc78f519 7121 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7122 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 7123 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 7124 kvm_update_cpuid(vcpu);
63f42e02
XG		 7125
7126 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7127 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7128 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 7129 mmu_reset_needed = 1;
7130 }
63f42e02 7131 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 7132
7133 if (mmu_reset_needed)
7134 kvm_mmu_reset_context(vcpu);
7135
a50abc3b 7136 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 7137 pending_vec = find_first_bit(
7138 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7139 if (pending_vec < max_bits) {
66fd3f7f 7140 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7141 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 7142 }
7143
3e6e0aab
GT		 7144 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7145 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7146 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7147 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7148 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7149 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7150
3e6e0aab
GT		 7151 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7152 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7153
5f0269f5
ME		 7154 update_cr8_intercept(vcpu);
7155
9c3e4aab 7156 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7157 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7158 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7159 !is_protmode(vcpu))
9c3e4aab
MT		 7160 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7161
3842d135
AK		 7162 kvm_make_request(KVM_REQ_EVENT, vcpu);
7163
b6c7a5dc
HB		 7164 return 0;
7165}
7166
d0bfb940
JK		 7167int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7168 struct kvm_guest_debug *dbg)
b6c7a5dc 7169{
355be0b9 7170 unsigned long rflags;
ae675ef0 7171 int i, r;
b6c7a5dc 7172
4f926bf2
JK		 7173 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7174 r = -EBUSY;
7175 if (vcpu->arch.exception.pending)
2122ff5e 7176 goto out;
4f926bf2
JK		 7177 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7178 kvm_queue_exception(vcpu, DB_VECTOR);
7179 else
7180 kvm_queue_exception(vcpu, BP_VECTOR);
7181 }
7182
91586a3b
JK		 7183 /*
7184 * Read rflags as long as potentially injected trace flags are still
7185 * filtered out.
7186 */
7187 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 7188
7189 vcpu->guest_debug = dbg->control;
7190 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7191 vcpu->guest_debug = 0;
7192
7193 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 7194 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7195 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7196 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 7197 } else {
7198 for (i = 0; i < KVM_NR_DB_REGS; i++)
7199 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7200 }
c8639010 7201 kvm_update_dr7(vcpu);
ae675ef0 7202
f92653ee
JK		 7203 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7204 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7205 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7206
91586a3b
JK		 7207 /*
7208 * Trigger an rflags update that will inject or remove the trace
7209 * flags.
7210 */
7211 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7212
c8639010 7213 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 7214
4f926bf2 7215 r = 0;
d0bfb940 7216
2122ff5e 7217out:
b6c7a5dc
HB		 7218
7219 return r;
7220}
7221
8b006791
ZX		 7222/*
7223 * Translate a guest virtual address to a guest physical address.
7224 */
7225int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7226 struct kvm_translation *tr)
7227{
7228 unsigned long vaddr = tr->linear_address;
7229 gpa_t gpa;
f656ce01 7230 int idx;
8b006791 7231
f656ce01 7232 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7233 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7234 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 7235 tr->physical_address = gpa;
7236 tr->valid = gpa != UNMAPPED_GVA;
7237 tr->writeable = 1;
7238 tr->usermode = 0;
8b006791
ZX		 7239
7240 return 0;
7241}
7242
d0752060
HB		 7243int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7244{
98918833
SY		 7245 struct i387_fxsave_struct *fxsave =
7246 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 7247
d0752060
HB		 7248 memcpy(fpu->fpr, fxsave->st_space, 128);
7249 fpu->fcw = fxsave->cwd;
7250 fpu->fsw = fxsave->swd;
7251 fpu->ftwx = fxsave->twd;
7252 fpu->last_opcode = fxsave->fop;
7253 fpu->last_ip = fxsave->rip;
7254 fpu->last_dp = fxsave->rdp;
7255 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7256
d0752060
HB		 7257 return 0;
7258}
7259
7260int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7261{
98918833
SY		 7262 struct i387_fxsave_struct *fxsave =
7263 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 7264
d0752060
HB		 7265 memcpy(fxsave->st_space, fpu->fpr, 128);
7266 fxsave->cwd = fpu->fcw;
7267 fxsave->swd = fpu->fsw;
7268 fxsave->twd = fpu->ftwx;
7269 fxsave->fop = fpu->last_opcode;
7270 fxsave->rip = fpu->last_ip;
7271 fxsave->rdp = fpu->last_dp;
7272 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7273
d0752060
HB		 7274 return 0;
7275}
7276
d28bc9dd 7277int fx_init(struct kvm_vcpu *vcpu, bool init_event)
d0752060 7278{
10ab25cd
JK		 7279 int err;
7280
7281 err = fpu_alloc(&vcpu->arch.guest_fpu);
7282 if (err)
7283 return err;
7284
d28bc9dd
NA		 7285 if (!init_event)
7286 fpu_finit(&vcpu->arch.guest_fpu);
7287
df1daba7
PB		 7288 if (cpu_has_xsaves)
7289 vcpu->arch.guest_fpu.state->xsave.xsave_hdr.xcomp_bv =
7290 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7291
2acf923e
DC		 7292 /*
7293 * Ensure guest xcr0 is valid for loading
7294 */
7295 vcpu->arch.xcr0 = XSTATE_FP;
7296
ad312c7c 7297 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 7298
7299 return 0;
d0752060
HB		 7300}
7301EXPORT_SYMBOL_GPL(fx_init);
7302
98918833
SY		 7303static void fx_free(struct kvm_vcpu *vcpu)
7304{
7305 fpu_free(&vcpu->arch.guest_fpu);
7306}
7307
d0752060
HB		 7308void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7309{
2608d7a1 7310 if (vcpu->guest_fpu_loaded)
d0752060
HB		 7311 return;
7312
2acf923e
DC		 7313 /*
7314 * Restore all possible states in the guest,
7315 * and assume host would use all available bits.
7316 * Guest xcr0 would be loaded later.
7317 */
7318 kvm_put_guest_xcr0(vcpu);
d0752060 7319 vcpu->guest_fpu_loaded = 1;
b1a74bf8 7320 __kernel_fpu_begin();
98918833 7321 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 7322 trace_kvm_fpu(1);
d0752060 7323}
d0752060
HB		 7324
7325void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7326{
2acf923e
DC		 7327 kvm_put_guest_xcr0(vcpu);
7328
653f52c3
RR		 7329 if (!vcpu->guest_fpu_loaded) {
7330 vcpu->fpu_counter = 0;
d0752060 7331 return;
653f52c3 7332 }
d0752060
HB		 7333
7334 vcpu->guest_fpu_loaded = 0;
98918833 7335 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 7336 __kernel_fpu_end();
f096ed85 7337 ++vcpu->stat.fpu_reload;
653f52c3
RR		 7338 /*
7339 * If using eager FPU mode, or if the guest is a frequent user
7340 * of the FPU, just leave the FPU active for next time.
7341 * Every 255 times fpu_counter rolls over to 0; a guest that uses
7342 * the FPU in bursts will revert to loading it on demand.
7343 */
a9b4fb7e 7344 if (!vcpu->arch.eager_fpu) {
653f52c3
RR		 7345 if (++vcpu->fpu_counter < 5)
7346 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
7347 }
0c04851c 7348 trace_kvm_fpu(0);
d0752060 7349}
e9b11c17
ZX		 7350
7351void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7352{
12f9a48f 7353 kvmclock_reset(vcpu);
7f1ea208 7354
f5f48ee1 7355 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 7356 fx_free(vcpu);
e9b11c17
ZX		 7357 kvm_x86_ops->vcpu_free(vcpu);
7358}
7359
7360struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7361 unsigned int id)
7362{
c447e76b
LL		 7363 struct kvm_vcpu *vcpu;
7364
6755bae8
ZA		 7365 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7366 printk_once(KERN_WARNING
7367 "kvm: SMP vm created on host with unstable TSC; "
7368 "guest TSC will not be reliable\n");
c447e76b
LL		 7369
7370 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7371
7372 /*
7373 * Activate fpu unconditionally in case the guest needs eager FPU. It will be
7374 * deactivated soon if it doesn't.
7375 */
7376 kvm_x86_ops->fpu_activate(vcpu);
7377 return vcpu;
26e5215f 7378}
e9b11c17 7379
26e5215f
AK		 7380int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7381{
7382 int r;
e9b11c17 7383
0bed3b56 7384 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 7385 r = vcpu_load(vcpu);
7386 if (r)
7387 return r;
d28bc9dd 7388 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7389 kvm_mmu_setup(vcpu);
e9b11c17 7390 vcpu_put(vcpu);
e9b11c17 7391
26e5215f 7392 return r;
e9b11c17
ZX		 7393}
7394
31928aa5 7395void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7396{
8fe8ab46 7397 struct msr_data msr;
332967a3 7398 struct kvm *kvm = vcpu->kvm;
42897d86 7399
31928aa5
DD		 7400 if (vcpu_load(vcpu))
7401 return;
8fe8ab46
WA		 7402 msr.data = 0x0;
7403 msr.index = MSR_IA32_TSC;
7404 msr.host_initiated = true;
7405 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 7406 vcpu_put(vcpu);
7407
630994b3
MT		 7408 if (!kvmclock_periodic_sync)
7409 return;
7410
332967a3
AJ		 7411 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7412 KVMCLOCK_SYNC_PERIOD);
42897d86
MT		 7413}
7414
d40ccc62 7415void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7416{
9fc77441 7417 int r;
344d9588
GN		 7418 vcpu->arch.apf.msr_val = 0;
7419
9fc77441
MT		 7420 r = vcpu_load(vcpu);
7421 BUG_ON(r);
e9b11c17
ZX		 7422 kvm_mmu_unload(vcpu);
7423 vcpu_put(vcpu);
7424
98918833 7425 fx_free(vcpu);
e9b11c17
ZX		 7426 kvm_x86_ops->vcpu_free(vcpu);
7427}
7428
d28bc9dd 7429void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7430{
e69fab5d
PB		 7431 vcpu->arch.hflags = 0;
7432
7460fb4a
AK		 7433 atomic_set(&vcpu->arch.nmi_queued, 0);
7434 vcpu->arch.nmi_pending = 0;
448fa4a9 7435 vcpu->arch.nmi_injected = false;
5f7552d4
NA		 7436 kvm_clear_interrupt_queue(vcpu);
7437 kvm_clear_exception_queue(vcpu);
448fa4a9 7438
42dbaa5a 7439 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7440 kvm_update_dr0123(vcpu);
6f43ed01 7441 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7442 kvm_update_dr6(vcpu);
42dbaa5a 7443 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7444 kvm_update_dr7(vcpu);
42dbaa5a 7445
1119022c
NA		 7446 vcpu->arch.cr2 = 0;
7447
3842d135 7448 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7449 vcpu->arch.apf.msr_val = 0;
c9aaa895 7450 vcpu->arch.st.msr_val = 0;
3842d135 7451
12f9a48f
GC		 7452 kvmclock_reset(vcpu);
7453
af585b92
GN		 7454 kvm_clear_async_pf_completion_queue(vcpu);
7455 kvm_async_pf_hash_reset(vcpu);
7456 vcpu->arch.apf.halted = false;
3842d135 7457
64d60670 7458 if (!init_event) {
d28bc9dd 7459 kvm_pmu_reset(vcpu);
64d60670
PB		 7460 vcpu->arch.smbase = 0x30000;
7461 }
f5132b01 7462
66f7b72e
JS		 7463 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7464 vcpu->arch.regs_avail = ~0;
7465 vcpu->arch.regs_dirty = ~0;
7466
d28bc9dd 7467 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX		 7468}
7469
2b4a273b 7470void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK		 7471{
7472 struct kvm_segment cs;
7473
7474 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
7475 cs.selector = vector << 8;
7476 cs.base = vector << 12;
7477 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
7478 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 7479}
7480
13a34e06 7481int kvm_arch_hardware_enable(void)
e9b11c17 7482{
ca84d1a2
ZA		 7483 struct kvm *kvm;
7484 struct kvm_vcpu *vcpu;
7485 int i;
0dd6a6ed
ZA		 7486 int ret;
7487 u64 local_tsc;
7488 u64 max_tsc = 0;
7489 bool stable, backwards_tsc = false;
18863bdd
AK		 7490
7491 kvm_shared_msr_cpu_online();
13a34e06 7492 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA		 7493 if (ret != 0)
7494 return ret;
7495
7496 local_tsc = native_read_tsc();
7497 stable = !check_tsc_unstable();
7498 list_for_each_entry(kvm, &vm_list, vm_list) {
7499 kvm_for_each_vcpu(i, vcpu, kvm) {
7500 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 7501 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7502 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
7503 backwards_tsc = true;
7504 if (vcpu->arch.last_host_tsc > max_tsc)
7505 max_tsc = vcpu->arch.last_host_tsc;
7506 }
7507 }
7508 }
7509
7510 /*
7511 * Sometimes, even reliable TSCs go backwards. This happens on
7512 * platforms that reset TSC during suspend or hibernate actions, but
7513 * maintain synchronization. We must compensate. Fortunately, we can
7514 * detect that condition here, which happens early in CPU bringup,
7515 * before any KVM threads can be running. Unfortunately, we can't
7516 * bring the TSCs fully up to date with real time, as we aren't yet far
7517 * enough into CPU bringup that we know how much real time has actually
7518 * elapsed; our helper function, get_kernel_ns() will be using boot
7519 * variables that haven't been updated yet.
7520 *
7521 * So we simply find the maximum observed TSC above, then record the
7522 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
7523 * the adjustment will be applied. Note that we accumulate
7524 * adjustments, in case multiple suspend cycles happen before some VCPU
7525 * gets a chance to run again. In the event that no KVM threads get a
7526 * chance to run, we will miss the entire elapsed period, as we'll have
7527 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
7528 * loose cycle time. This isn't too big a deal, since the loss will be
7529 * uniform across all VCPUs (not to mention the scenario is extremely
7530 * unlikely). It is possible that a second hibernate recovery happens
7531 * much faster than a first, causing the observed TSC here to be
7532 * smaller; this would require additional padding adjustment, which is
7533 * why we set last_host_tsc to the local tsc observed here.
7534 *
7535 * N.B. - this code below runs only on platforms with reliable TSC,
7536 * as that is the only way backwards_tsc is set above. Also note
7537 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
7538 * have the same delta_cyc adjustment applied if backwards_tsc
7539 * is detected. Note further, this adjustment is only done once,
7540 * as we reset last_host_tsc on all VCPUs to stop this from being
7541 * called multiple times (one for each physical CPU bringup).
7542 *
4a969980 7543 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 7544 * will be compensated by the logic in vcpu_load, which sets the TSC to
7545 * catchup mode. This will catchup all VCPUs to real time, but cannot
7546 * guarantee that they stay in perfect synchronization.
7547 */
7548 if (backwards_tsc) {
7549 u64 delta_cyc = max_tsc - local_tsc;
16a96021 7550 backwards_tsc_observed = true;
0dd6a6ed
ZA		 7551 list_for_each_entry(kvm, &vm_list, vm_list) {
7552 kvm_for_each_vcpu(i, vcpu, kvm) {
7553 vcpu->arch.tsc_offset_adjustment += delta_cyc;
7554 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 7555 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA		 7556 }
7557
7558 /*
7559 * We have to disable TSC offset matching.. if you were
7560 * booting a VM while issuing an S4 host suspend....
7561 * you may have some problem. Solving this issue is
7562 * left as an exercise to the reader.
7563 */
7564 kvm->arch.last_tsc_nsec = 0;
7565 kvm->arch.last_tsc_write = 0;
7566 }
7567
7568 }
7569 return 0;
e9b11c17
ZX		 7570}
7571
13a34e06 7572void kvm_arch_hardware_disable(void)
e9b11c17 7573{
13a34e06
RK		 7574 kvm_x86_ops->hardware_disable();
7575 drop_user_return_notifiers();
e9b11c17
ZX		 7576}
7577
7578int kvm_arch_hardware_setup(void)
7579{
9e9c3fe4
NA		 7580 int r;
7581
7582 r = kvm_x86_ops->hardware_setup();
7583 if (r != 0)
7584 return r;
7585
7586 kvm_init_msr_list();
7587 return 0;
e9b11c17
ZX		 7588}
7589
7590void kvm_arch_hardware_unsetup(void)
7591{
7592 kvm_x86_ops->hardware_unsetup();
7593}
7594
7595void kvm_arch_check_processor_compat(void *rtn)
7596{
7597 kvm_x86_ops->check_processor_compatibility(rtn);
7598}
7599
3e515705
AK		 7600bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
7601{
7602 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
7603}
7604
54e9818f
GN		 7605struct static_key kvm_no_apic_vcpu __read_mostly;
7606
e9b11c17
ZX		 7607int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
7608{
7609 struct page *page;
7610 struct kvm *kvm;
7611 int r;
7612
7613 BUG_ON(vcpu->kvm == NULL);
7614 kvm = vcpu->kvm;
7615
6aef266c 7616 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 7617 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
58d269d8 7618 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 7619 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 7620 else
a4535290 7621 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 7622
7623 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
7624 if (!page) {
7625 r = -ENOMEM;
7626 goto fail;
7627 }
ad312c7c 7628 vcpu->arch.pio_data = page_address(page);
e9b11c17 7629
cc578287 7630 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 7631
e9b11c17
ZX		 7632 r = kvm_mmu_create(vcpu);
7633 if (r < 0)
7634 goto fail_free_pio_data;
7635
7636 if (irqchip_in_kernel(kvm)) {
7637 r = kvm_create_lapic(vcpu);
7638 if (r < 0)
7639 goto fail_mmu_destroy;
54e9818f
GN		 7640 } else
7641 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 7642
890ca9ae
HY		 7643 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
7644 GFP_KERNEL);
7645 if (!vcpu->arch.mce_banks) {
7646 r = -ENOMEM;
443c39bc 7647 goto fail_free_lapic;
890ca9ae
HY		 7648 }
7649 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
7650
f1797359
WY		 7651 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
7652 r = -ENOMEM;
f5f48ee1 7653 goto fail_free_mce_banks;
f1797359 7654 }
f5f48ee1 7655
d28bc9dd 7656 r = fx_init(vcpu, false);
66f7b72e
JS		 7657 if (r)
7658 goto fail_free_wbinvd_dirty_mask;
7659
ba904635 7660 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 7661 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 7662
7663 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 7664 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 7665
5a4f55cd
EK		 7666 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
7667
74545705
RK		 7668 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
7669
af585b92 7670 kvm_async_pf_hash_reset(vcpu);
f5132b01 7671 kvm_pmu_init(vcpu);
af585b92 7672
e9b11c17 7673 return 0;
66f7b72e
JS		 7674fail_free_wbinvd_dirty_mask:
7675 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 7676fail_free_mce_banks:
7677 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 7678fail_free_lapic:
7679 kvm_free_lapic(vcpu);
e9b11c17
ZX		 7680fail_mmu_destroy:
7681 kvm_mmu_destroy(vcpu);
7682fail_free_pio_data:
ad312c7c 7683 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 7684fail:
7685 return r;
7686}
7687
7688void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
7689{
f656ce01
MT		 7690 int idx;
7691
f5132b01 7692 kvm_pmu_destroy(vcpu);
36cb93fd 7693 kfree(vcpu->arch.mce_banks);
e9b11c17 7694 kvm_free_lapic(vcpu);
f656ce01 7695 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 7696 kvm_mmu_destroy(vcpu);
f656ce01 7697 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 7698 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 7699 if (!irqchip_in_kernel(vcpu->kvm))
7700 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 7701}
d19a9cd2 7702
e790d9ef
RK		 7703void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
7704{
ae97a3b8 7705 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK		 7706}
7707
e08b9637 7708int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7709{
e08b9637
CO		 7710 if (type)
7711 return -EINVAL;
7712
6ef768fa 7713 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 7714 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7715 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7716 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7717 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7718
5550af4d
SY		 7719 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7720 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7721 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7722 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7723 &kvm->arch.irq_sources_bitmap);
5550af4d 7724
038f8c11 7725 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7726 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7727 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7728
7729 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7730
7e44e449 7731 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 7732 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 7733
d89f5eff 7734 return 0;
d19a9cd2
ZX		 7735}
7736
7737static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7738{
9fc77441
MT		 7739 int r;
7740 r = vcpu_load(vcpu);
7741 BUG_ON(r);
d19a9cd2
ZX		 7742 kvm_mmu_unload(vcpu);
7743 vcpu_put(vcpu);
7744}
7745
7746static void kvm_free_vcpus(struct kvm *kvm)
7747{
7748 unsigned int i;
988a2cae 7749 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7750
7751 /*
7752 * Unpin any mmu pages first.
7753 */
af585b92
GN		 7754 kvm_for_each_vcpu(i, vcpu, kvm) {
7755 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7756 kvm_unload_vcpu_mmu(vcpu);
af585b92 7757 }
988a2cae
GN		 7758 kvm_for_each_vcpu(i, vcpu, kvm)
7759 kvm_arch_vcpu_free(vcpu);
7760
7761 mutex_lock(&kvm->lock);
7762 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7763 kvm->vcpus[i] = NULL;
d19a9cd2 7764
988a2cae
GN		 7765 atomic_set(&kvm->online_vcpus, 0);
7766 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7767}
7768
ad8ba2cd
SY		 7769void kvm_arch_sync_events(struct kvm *kvm)
7770{
332967a3 7771 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 7772 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
ba4cef31 7773 kvm_free_all_assigned_devices(kvm);
aea924f6 7774 kvm_free_pit(kvm);
ad8ba2cd
SY		 7775}
7776
9da0e4d5
PB		 7777int __x86_set_memory_region(struct kvm *kvm,
7778 const struct kvm_userspace_memory_region *mem)
7779{
7780 int i, r;
7781
7782 /* Called with kvm->slots_lock held. */
7783 BUG_ON(mem->slot >= KVM_MEM_SLOTS_NUM);
7784
7785 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
7786 struct kvm_userspace_memory_region m = *mem;
7787
7788 m.slot |= i << 16;
7789 r = __kvm_set_memory_region(kvm, &m);
7790 if (r < 0)
7791 return r;
7792 }
7793
7794 return 0;
7795}
7796EXPORT_SYMBOL_GPL(__x86_set_memory_region);
7797
7798int x86_set_memory_region(struct kvm *kvm,
7799 const struct kvm_userspace_memory_region *mem)
7800{
7801 int r;
7802
7803 mutex_lock(&kvm->slots_lock);
7804 r = __x86_set_memory_region(kvm, mem);
7805 mutex_unlock(&kvm->slots_lock);
7806
7807 return r;
7808}
7809EXPORT_SYMBOL_GPL(x86_set_memory_region);
7810
d19a9cd2
ZX		 7811void kvm_arch_destroy_vm(struct kvm *kvm)
7812{
27469d29
AH		 7813 if (current->mm == kvm->mm) {
7814 /*
7815 * Free memory regions allocated on behalf of userspace,
7816 * unless the the memory map has changed due to process exit
7817 * or fd copying.
7818 */
7819 struct kvm_userspace_memory_region mem;
7820 memset(&mem, 0, sizeof(mem));
7821 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
9da0e4d5 7822 x86_set_memory_region(kvm, &mem);
27469d29
AH		 7823
7824 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
9da0e4d5 7825 x86_set_memory_region(kvm, &mem);
27469d29
AH		 7826
7827 mem.slot = TSS_PRIVATE_MEMSLOT;
9da0e4d5 7828 x86_set_memory_region(kvm, &mem);
27469d29 7829 }
6eb55818 7830 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7831 kfree(kvm->arch.vpic);
7832 kfree(kvm->arch.vioapic);
d19a9cd2 7833 kvm_free_vcpus(kvm);
1e08ec4a 7834 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7835}
0de10343 7836
5587027c 7837void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7838 struct kvm_memory_slot *dont)
7839{
7840 int i;
7841
d89cc617
TY		 7842 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7843 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 7844 kvfree(free->arch.rmap[i]);
d89cc617 7845 free->arch.rmap[i] = NULL;
77d11309 7846 }
d89cc617
TY		 7847 if (i == 0)
7848 continue;
7849
7850 if (!dont || free->arch.lpage_info[i - 1] !=
7851 dont->arch.lpage_info[i - 1]) {
548ef284 7852 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 7853 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7854 }
7855 }
7856}
7857
5587027c
AK		 7858int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7859 unsigned long npages)
db3fe4eb
TY		 7860{
7861 int i;
7862
d89cc617 7863 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7864 unsigned long ugfn;
7865 int lpages;
d89cc617 7866 int level = i + 1;
db3fe4eb
TY		 7867
7868 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7869 slot->base_gfn, level) + 1;
7870
d89cc617
TY		 7871 slot->arch.rmap[i] =
7872 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7873 if (!slot->arch.rmap[i])
77d11309 7874 goto out_free;
d89cc617
TY		 7875 if (i == 0)
7876 continue;
77d11309 7877
d89cc617
TY		 7878 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7879 sizeof(*slot->arch.lpage_info[i - 1]));
7880 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7881 goto out_free;
7882
7883 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7884 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7885 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7886 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7887 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7888 /*
7889 * If the gfn and userspace address are not aligned wrt each
7890 * other, or if explicitly asked to, disable large page
7891 * support for this slot
7892 */
7893 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7894 !kvm_largepages_enabled()) {
7895 unsigned long j;
7896
7897 for (j = 0; j < lpages; ++j)
d89cc617 7898 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7899 }
7900 }
7901
7902 return 0;
7903
7904out_free:
d89cc617 7905 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 7906 kvfree(slot->arch.rmap[i]);
d89cc617
TY		 7907 slot->arch.rmap[i] = NULL;
7908 if (i == 0)
7909 continue;
7910
548ef284 7911 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 7912 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7913 }
7914 return -ENOMEM;
7915}
7916
15f46015 7917void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 7918{
e6dff7d1
TY		 7919 /*
7920 * memslots->generation has been incremented.
7921 * mmio generation may have reached its maximum value.
7922 */
54bf36aa 7923 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY		 7924}
7925
f7784b8e
MT		 7926int kvm_arch_prepare_memory_region(struct kvm *kvm,
7927 struct kvm_memory_slot *memslot,
09170a49 7928 const struct kvm_userspace_memory_region *mem,
7b6195a9 7929 enum kvm_mr_change change)
0de10343 7930{
7a905b14
TY		 7931 /*
7932 * Only private memory slots need to be mapped here since
7933 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7934 */
7b6195a9 7935 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7936 unsigned long userspace_addr;
604b38ac 7937
7a905b14
TY		 7938 /*
7939 * MAP_SHARED to prevent internal slot pages from being moved
7940 * by fork()/COW.
7941 */
7b6195a9 7942 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7943 PROT_READ | PROT_WRITE,
7944 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7945
7a905b14
TY		 7946 if (IS_ERR((void *)userspace_addr))
7947 return PTR_ERR((void *)userspace_addr);
604b38ac 7948
7a905b14 7949 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7950 }
7951
f7784b8e
MT		 7952 return 0;
7953}
7954
88178fd4
KH		 7955static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
7956 struct kvm_memory_slot *new)
7957{
7958 /* Still write protect RO slot */
7959 if (new->flags & KVM_MEM_READONLY) {
7960 kvm_mmu_slot_remove_write_access(kvm, new);
7961 return;
7962 }
7963
7964 /*
7965 * Call kvm_x86_ops dirty logging hooks when they are valid.
7966 *
7967 * kvm_x86_ops->slot_disable_log_dirty is called when:
7968 *
7969 * - KVM_MR_CREATE with dirty logging is disabled
7970 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
7971 *
7972 * The reason is, in case of PML, we need to set D-bit for any slots
7973 * with dirty logging disabled in order to eliminate unnecessary GPA
7974 * logging in PML buffer (and potential PML buffer full VMEXT). This
7975 * guarantees leaving PML enabled during guest's lifetime won't have
7976 * any additonal overhead from PML when guest is running with dirty
7977 * logging disabled for memory slots.
7978 *
7979 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
7980 * to dirty logging mode.
7981 *
7982 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
7983 *
7984 * In case of write protect:
7985 *
7986 * Write protect all pages for dirty logging.
7987 *
7988 * All the sptes including the large sptes which point to this
7989 * slot are set to readonly. We can not create any new large
7990 * spte on this slot until the end of the logging.
7991 *
7992 * See the comments in fast_page_fault().
7993 */
7994 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
7995 if (kvm_x86_ops->slot_enable_log_dirty)
7996 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
7997 else
7998 kvm_mmu_slot_remove_write_access(kvm, new);
7999 } else {
8000 if (kvm_x86_ops->slot_disable_log_dirty)
8001 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8002 }
8003}
8004
f7784b8e 8005void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8006 const struct kvm_userspace_memory_region *mem,
8482644a 8007 const struct kvm_memory_slot *old,
f36f3f28 8008 const struct kvm_memory_slot *new,
8482644a 8009 enum kvm_mr_change change)
f7784b8e 8010{
8482644a 8011 int nr_mmu_pages = 0;
f7784b8e 8012
f36f3f28 8013 if (change == KVM_MR_DELETE && old->id >= KVM_USER_MEM_SLOTS) {
f7784b8e
MT		 8014 int ret;
8015
8482644a
TY		 8016 ret = vm_munmap(old->userspace_addr,
8017 old->npages * PAGE_SIZE);
f7784b8e
MT		 8018 if (ret < 0)
8019 printk(KERN_WARNING
8020 "kvm_vm_ioctl_set_memory_region: "
8021 "failed to munmap memory\n");
8022 }
8023
48c0e4e9
XG		 8024 if (!kvm->arch.n_requested_mmu_pages)
8025 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8026
48c0e4e9 8027 if (nr_mmu_pages)
0de10343 8028 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8029
3ea3b7fa
WL		 8030 /*
8031 * Dirty logging tracks sptes in 4k granularity, meaning that large
8032 * sptes have to be split. If live migration is successful, the guest
8033 * in the source machine will be destroyed and large sptes will be
8034 * created in the destination. However, if the guest continues to run
8035 * in the source machine (for example if live migration fails), small
8036 * sptes will remain around and cause bad performance.
8037 *
8038 * Scan sptes if dirty logging has been stopped, dropping those
8039 * which can be collapsed into a single large-page spte. Later
8040 * page faults will create the large-page sptes.
8041 */
8042 if ((change != KVM_MR_DELETE) &&
8043 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8044 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8045 kvm_mmu_zap_collapsible_sptes(kvm, new);
8046
c972f3b1 8047 /*
88178fd4 8048 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8049 *
88178fd4
KH		 8050 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8051 * been zapped so no dirty logging staff is needed for old slot. For
8052 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8053 * new and it's also covered when dealing with the new slot.
f36f3f28
PB		 8054 *
8055 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8056 */
88178fd4 8057 if (change != KVM_MR_DELETE)
f36f3f28 8058 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8059}
1d737c8a 8060
2df72e9b 8061void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8062{
6ca18b69 8063 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 8064}
8065
2df72e9b
MT		 8066void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8067 struct kvm_memory_slot *slot)
8068{
6ca18b69 8069 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 8070}
8071
1d737c8a
ZX		 8072int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8073{
b6b8a145
JK		 8074 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
8075 kvm_x86_ops->check_nested_events(vcpu, false);
8076
af585b92
GN		 8077 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
8078 !vcpu->arch.apf.halted)
8079 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 8080 || kvm_apic_has_events(vcpu)
6aef266c 8081 || vcpu->arch.pv.pv_unhalted
7460fb4a 8082 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 8083 (kvm_arch_interrupt_allowed(vcpu) &&
8084 kvm_cpu_has_interrupt(vcpu));
1d737c8a 8085}
5736199a 8086
b6d33834 8087int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8088{
b6d33834 8089 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8090}
78646121
GN		 8091
8092int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8093{
8094 return kvm_x86_ops->interrupt_allowed(vcpu);
8095}
229456fc 8096
82b32774 8097unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8098{
82b32774
NA		 8099 if (is_64_bit_mode(vcpu))
8100 return kvm_rip_read(vcpu);
8101 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8102 kvm_rip_read(vcpu));
8103}
8104EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8105
82b32774
NA		 8106bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8107{
8108 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK		 8109}
8110EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8111
94fe45da
JK		 8112unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8113{
8114 unsigned long rflags;
8115
8116 rflags = kvm_x86_ops->get_rflags(vcpu);
8117 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8118 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 8119 return rflags;
8120}
8121EXPORT_SYMBOL_GPL(kvm_get_rflags);
8122
6addfc42 8123static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK		 8124{
8125 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8126 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8127 rflags |= X86_EFLAGS_TF;
94fe45da 8128 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB		 8129}
8130
8131void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8132{
8133 __kvm_set_rflags(vcpu, rflags);
3842d135 8134 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 8135}
8136EXPORT_SYMBOL_GPL(kvm_set_rflags);
8137
56028d08
GN		 8138void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8139{
8140 int r;
8141
fb67e14f 8142 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8143 work->wakeup_all)
56028d08
GN		 8144 return;
8145
8146 r = kvm_mmu_reload(vcpu);
8147 if (unlikely(r))
8148 return;
8149
fb67e14f
XG		 8150 if (!vcpu->arch.mmu.direct_map &&
8151 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8152 return;
8153
56028d08
GN		 8154 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8155}
8156
af585b92
GN		 8157static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8158{
8159 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8160}
8161
8162static inline u32 kvm_async_pf_next_probe(u32 key)
8163{
8164 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8165}
8166
8167static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8168{
8169 u32 key = kvm_async_pf_hash_fn(gfn);
8170
8171 while (vcpu->arch.apf.gfns[key] != ~0)
8172 key = kvm_async_pf_next_probe(key);
8173
8174 vcpu->arch.apf.gfns[key] = gfn;
8175}
8176
8177static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8178{
8179 int i;
8180 u32 key = kvm_async_pf_hash_fn(gfn);
8181
8182 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 8183 (vcpu->arch.apf.gfns[key] != gfn &&
8184 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 8185 key = kvm_async_pf_next_probe(key);
8186
8187 return key;
8188}
8189
8190bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8191{
8192 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8193}
8194
8195static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8196{
8197 u32 i, j, k;
8198
8199 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8200 while (true) {
8201 vcpu->arch.apf.gfns[i] = ~0;
8202 do {
8203 j = kvm_async_pf_next_probe(j);
8204 if (vcpu->arch.apf.gfns[j] == ~0)
8205 return;
8206 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8207 /*
8208 * k lies cyclically in ]i,j]
8209 * | i.k.j |
8210 * |....j i.k.| or |.k..j i...|
8211 */
8212 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8213 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8214 i = j;
8215 }
8216}
8217
7c90705b
GN		 8218static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8219{
8220
8221 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8222 sizeof(val));
8223}
8224
af585b92
GN		 8225void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8226 struct kvm_async_pf *work)
8227{
6389ee94
AK		 8228 struct x86_exception fault;
8229
7c90705b 8230 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8231 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 8232
8233 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 8234 (vcpu->arch.apf.send_user_only &&
8235 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 8236 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8237 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 8238 fault.vector = PF_VECTOR;
8239 fault.error_code_valid = true;
8240 fault.error_code = 0;
8241 fault.nested_page_fault = false;
8242 fault.address = work->arch.token;
8243 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8244 }
af585b92
GN		 8245}
8246
8247void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8248 struct kvm_async_pf *work)
8249{
6389ee94
AK		 8250 struct x86_exception fault;
8251
7c90705b 8252 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 8253 if (work->wakeup_all)
7c90705b
GN		 8254 work->arch.token = ~0; /* broadcast wakeup */
8255 else
8256 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
8257
8258 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
8259 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 8260 fault.vector = PF_VECTOR;
8261 fault.error_code_valid = true;
8262 fault.error_code = 0;
8263 fault.nested_page_fault = false;
8264 fault.address = work->arch.token;
8265 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8266 }
e6d53e3b 8267 vcpu->arch.apf.halted = false;
a4fa1635 8268 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 8269}
8270
8271bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8272{
8273 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8274 return true;
8275 else
8276 return !kvm_event_needs_reinjection(vcpu) &&
8277 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 8278}
8279
e0f0bbc5
AW		 8280void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8281{
8282 atomic_inc(&kvm->arch.noncoherent_dma_count);
8283}
8284EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8285
8286void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8287{
8288 atomic_dec(&kvm->arch.noncoherent_dma_count);
8289}
8290EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8291
8292bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8293{
8294 return atomic_read(&kvm->arch.noncoherent_dma_count);
8295}
8296EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8297
229456fc
MT		 8298EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
8299EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8300EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8301EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8302EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8303EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8304EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8305EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8306EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8307EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8308EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8309EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8310EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8311EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8312EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
Linux kernel - Deliverables
This page took 2.409919 seconds and 5 git commands to generate.