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KVM: x86 emulator: Add support for mov seg, r (0x8e) instruction
[deliverable/linux.git] / arch / x86 / kvm / x86_emulate.c
CommitLineData
6aa8b732
AK		 1/******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
6aa8b732
AK		 29#define DPRINTF(x...) do {} while (0)
30#endif
6aa8b732 31#include <linux/module.h>
edf88417 32#include <asm/kvm_x86_emulate.h>
6aa8b732
AK		 33
34/*
35 * Opcode effective-address decode tables.
36 * Note that we only emulate instructions that have at least one memory
37 * operand (excluding implicit stack references). We assume that stack
38 * references and instruction fetches will never occur in special memory
39 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
40 * not be handled.
41 */
42
43/* Operand sizes: 8-bit operands or specified/overridden size. */
44#define ByteOp (1<<0) /* 8-bit operands. */
45/* Destination operand type. */
46#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
47#define DstReg (2<<1) /* Register operand. */
48#define DstMem (3<<1) /* Memory operand. */
49#define DstMask (3<<1)
50/* Source operand type. */
51#define SrcNone (0<<3) /* No source operand. */
52#define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */
53#define SrcReg (1<<3) /* Register operand. */
54#define SrcMem (2<<3) /* Memory operand. */
55#define SrcMem16 (3<<3) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<3) /* Memory operand (32-bit). */
57#define SrcImm (5<<3) /* Immediate operand. */
58#define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */
59#define SrcMask (7<<3)
60/* Generic ModRM decode. */
61#define ModRM (1<<6)
62/* Destination is only written; never read. */
63#define Mov (1<<7)
038e51de 64#define BitOp (1<<8)
c7e75a3d 65#define MemAbs (1<<9) /* Memory operand is absolute displacement */
b9fa9d6b 66#define String (1<<10) /* String instruction (rep capable) */
6e3d5dfb 67#define Stack (1<<11) /* Stack instruction (push/pop) */
e09d082c
AK		 68#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
69#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
70#define GroupMask 0xff /* Group number stored in bits 0:7 */
6aa8b732 71
43bb19cd 72enum {
1d6ad207 73 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 74 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
43bb19cd
AK		 75};
76
c7e75a3d 77static u16 opcode_table[256] = {
6aa8b732
AK		 78 /* 0x00 - 0x07 */
79 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
80 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
81 0, 0, 0, 0,
82 /* 0x08 - 0x0F */
83 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
84 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
85 0, 0, 0, 0,
86 /* 0x10 - 0x17 */
87 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
88 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
89 0, 0, 0, 0,
90 /* 0x18 - 0x1F */
91 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
92 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
93 0, 0, 0, 0,
94 /* 0x20 - 0x27 */
95 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
96 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
19eb938e 97 SrcImmByte, SrcImm, 0, 0,
6aa8b732
AK		 98 /* 0x28 - 0x2F */
99 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
100 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
101 0, 0, 0, 0,
102 /* 0x30 - 0x37 */
103 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
104 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
105 0, 0, 0, 0,
106 /* 0x38 - 0x3F */
107 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
108 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
109 0, 0, 0, 0,
d77a2507 110 /* 0x40 - 0x47 */
33615aa9 111 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 112 /* 0x48 - 0x4F */
33615aa9 113 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 114 /* 0x50 - 0x57 */
6e3d5dfb
AK		 115 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
116 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 117 /* 0x58 - 0x5F */
6e3d5dfb
AK		 118 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
119 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 120 /* 0x60 - 0x67 */
6aa8b732 121 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 122 0, 0, 0, 0,
123 /* 0x68 - 0x6F */
6e3d5dfb 124 0, 0, ImplicitOps | Mov | Stack, 0,
e70669ab
LV		 125 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
126 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4
NK		 127 /* 0x70 - 0x77 */
128 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
129 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
130 /* 0x78 - 0x7F */
131 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
132 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732 133 /* 0x80 - 0x87 */
1d6ad207
AK		 134 Group | Group1_80, Group | Group1_81,
135 Group | Group1_82, Group | Group1_83,
6aa8b732
AK		 136 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
137 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
138 /* 0x88 - 0x8F */
139 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
140 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
4257198a
GT		 141 0, ModRM | DstReg,
142 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
6aa8b732 143 /* 0x90 - 0x9F */
6e3d5dfb
AK		 144 0, 0, 0, 0, 0, 0, 0, 0,
145 0, 0, 0, 0, ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 146 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 147 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
148 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
b9fa9d6b
AK		 149 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
150 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 151 /* 0xA8 - 0xAF */
b9fa9d6b
AK		 152 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
153 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
154 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 155 /* 0xB0 - 0xBF */
615ac125
GT		 156 0, 0, 0, 0, 0, 0, 0, 0,
157 DstReg | SrcImm | Mov, 0, 0, 0, 0, 0, 0, 0,
6aa8b732 158 /* 0xC0 - 0xC7 */
d9413cd7 159 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 160 0, ImplicitOps | Stack, 0, 0,
d9413cd7 161 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732
AK		 162 /* 0xC8 - 0xCF */
163 0, 0, 0, 0, 0, 0, 0, 0,
164 /* 0xD0 - 0xD7 */
165 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
166 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
167 0, 0, 0, 0,
168 /* 0xD8 - 0xDF */
169 0, 0, 0, 0, 0, 0, 0, 0,
098c937b
NK		 170 /* 0xE0 - 0xE7 */
171 0, 0, 0, 0, 0, 0, 0, 0,
172 /* 0xE8 - 0xEF */
954cd36f
GT		 173 ImplicitOps | Stack, SrcImm | ImplicitOps,
174 ImplicitOps, SrcImmByte | ImplicitOps,
6e3d5dfb 175 0, 0, 0, 0,
6aa8b732
AK		 176 /* 0xF0 - 0xF7 */
177 0, 0, 0, 0,
7d858a19 178 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 179 /* 0xF8 - 0xFF */
b284be57 180 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fd60754e 181 0, 0, Group | Group4, Group | Group5,
6aa8b732
AK		 182};
183
038e51de 184static u16 twobyte_table[256] = {
6aa8b732 185 /* 0x00 - 0x0F */
d95058a1 186 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
651a3e29 187 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 188 /* 0x10 - 0x1F */
189 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
190 /* 0x20 - 0x2F */
191 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
192 0, 0, 0, 0, 0, 0, 0, 0,
193 /* 0x30 - 0x3F */
35f3f286 194 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 195 /* 0x40 - 0x47 */
196 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
197 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
198 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
199 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
200 /* 0x48 - 0x4F */
201 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
202 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
203 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
204 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
205 /* 0x50 - 0x5F */
206 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
207 /* 0x60 - 0x6F */
208 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
209 /* 0x70 - 0x7F */
210 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
211 /* 0x80 - 0x8F */
bbe9abbd
NK		 212 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
213 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
214 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
215 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 216 /* 0x90 - 0x9F */
217 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
218 /* 0xA0 - 0xA7 */
038e51de 219 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732 220 /* 0xA8 - 0xAF */
038e51de 221 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732
AK		 222 /* 0xB0 - 0xB7 */
223 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 224 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 225 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
226 DstReg | SrcMem16 | ModRM | Mov,
227 /* 0xB8 - 0xBF */
038e51de 228 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 229 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
230 DstReg | SrcMem16 | ModRM | Mov,
231 /* 0xC0 - 0xCF */
a012e65a
SY		 232 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
233 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 234 /* 0xD0 - 0xDF */
235 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
236 /* 0xE0 - 0xEF */
237 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
238 /* 0xF0 - 0xFF */
239 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
240};
241
e09d082c 242static u16 group_table[] = {
1d6ad207
AK		 243 [Group1_80*8] =
244 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
245 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
246 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
247 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
248 [Group1_81*8] =
249 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
250 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
251 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
252 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
253 [Group1_82*8] =
254 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
255 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
256 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
257 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
258 [Group1_83*8] =
259 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
260 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
261 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
262 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 263 [Group1A*8] =
264 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 265 [Group3_Byte*8] =
266 ByteOp | SrcImm | DstMem | ModRM, 0,
267 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
268 0, 0, 0, 0,
269 [Group3*8] =
270 DstMem | SrcImm | ModRM | SrcImm, 0,
271 DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
272 0, 0, 0, 0,
fd60754e
AK		 273 [Group4*8] =
274 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
275 0, 0, 0, 0, 0, 0,
276 [Group5*8] =
277 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM, 0, 0,
278 SrcMem | ModRM, 0, SrcMem | ModRM | Stack, 0,
d95058a1
AK		 279 [Group7*8] =
280 0, 0, ModRM | SrcMem, ModRM | SrcMem,
16286d08
AK		 281 SrcNone | ModRM | DstMem | Mov, 0,
282 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
e09d082c
AK		 283};
284
285static u16 group2_table[] = {
d95058a1 286 [Group7*8] =
16286d08
AK		 287 SrcNone | ModRM, 0, 0, 0,
288 SrcNone | ModRM | DstMem | Mov, 0,
289 SrcMem16 | ModRM | Mov, 0,
e09d082c
AK		 290};
291
6aa8b732
AK		 292/* EFLAGS bit definitions. */
293#define EFLG_OF (1<<11)
294#define EFLG_DF (1<<10)
295#define EFLG_SF (1<<7)
296#define EFLG_ZF (1<<6)
297#define EFLG_AF (1<<4)
298#define EFLG_PF (1<<2)
299#define EFLG_CF (1<<0)
300
301/*
302 * Instruction emulation:
303 * Most instructions are emulated directly via a fragment of inline assembly
304 * code. This allows us to save/restore EFLAGS and thus very easily pick up
305 * any modified flags.
306 */
307
05b3e0c2 308#if defined(CONFIG_X86_64)
6aa8b732
AK		 309#define _LO32 "k" /* force 32-bit operand */
310#define _STK "%%rsp" /* stack pointer */
311#elif defined(__i386__)
312#define _LO32 "" /* force 32-bit operand */
313#define _STK "%%esp" /* stack pointer */
314#endif
315
316/*
317 * These EFLAGS bits are restored from saved value during emulation, and
318 * any changes are written back to the saved value after emulation.
319 */
320#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
321
322/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 323#define _PRE_EFLAGS(_sav, _msk, _tmp) \
324 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
325 "movl %"_sav",%"_LO32 _tmp"; " \
326 "push %"_tmp"; " \
327 "push %"_tmp"; " \
328 "movl %"_msk",%"_LO32 _tmp"; " \
329 "andl %"_LO32 _tmp",("_STK"); " \
330 "pushf; " \
331 "notl %"_LO32 _tmp"; " \
332 "andl %"_LO32 _tmp",("_STK"); " \
333 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
334 "pop %"_tmp"; " \
335 "orl %"_LO32 _tmp",("_STK"); " \
336 "popf; " \
337 "pop %"_sav"; "
6aa8b732
AK		 338
339/* After executing instruction: write-back necessary bits in EFLAGS. */
340#define _POST_EFLAGS(_sav, _msk, _tmp) \
341 /* _sav |= EFLAGS & _msk; */ \
342 "pushf; " \
343 "pop %"_tmp"; " \
344 "andl %"_msk",%"_LO32 _tmp"; " \
345 "orl %"_LO32 _tmp",%"_sav"; "
346
347/* Raw emulation: instruction has two explicit operands. */
348#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
349 do { \
350 unsigned long _tmp; \
351 \
352 switch ((_dst).bytes) { \
353 case 2: \
354 __asm__ __volatile__ ( \
d77c26fc 355 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 356 _op"w %"_wx"3,%1; " \
d77c26fc 357 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 358 : "=m" (_eflags), "=m" ((_dst).val), \
359 "=&r" (_tmp) \
d77c26fc 360 : _wy ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 361 break; \
362 case 4: \
363 __asm__ __volatile__ ( \
d77c26fc 364 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 365 _op"l %"_lx"3,%1; " \
d77c26fc 366 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 367 : "=m" (_eflags), "=m" ((_dst).val), \
368 "=&r" (_tmp) \
d77c26fc 369 : _ly ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 370 break; \
371 case 8: \
372 __emulate_2op_8byte(_op, _src, _dst, \
373 _eflags, _qx, _qy); \
374 break; \
375 } \
376 } while (0)
377
378#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
379 do { \
77cd337f 380 unsigned long __tmp; \
d77c26fc 381 switch ((_dst).bytes) { \
6aa8b732
AK		 382 case 1: \
383 __asm__ __volatile__ ( \
d77c26fc 384 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 385 _op"b %"_bx"3,%1; " \
d77c26fc 386 _POST_EFLAGS("0", "4", "2") \
6aa8b732 387 : "=m" (_eflags), "=m" ((_dst).val), \
77cd337f 388 "=&r" (__tmp) \
d77c26fc 389 : _by ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 390 break; \
391 default: \
392 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
393 _wx, _wy, _lx, _ly, _qx, _qy); \
394 break; \
395 } \
396 } while (0)
397
398/* Source operand is byte-sized and may be restricted to just %cl. */
399#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
400 __emulate_2op(_op, _src, _dst, _eflags, \
401 "b", "c", "b", "c", "b", "c", "b", "c")
402
403/* Source operand is byte, word, long or quad sized. */
404#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
405 __emulate_2op(_op, _src, _dst, _eflags, \
406 "b", "q", "w", "r", _LO32, "r", "", "r")
407
408/* Source operand is word, long or quad sized. */
409#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
410 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
411 "w", "r", _LO32, "r", "", "r")
412
413/* Instruction has only one explicit operand (no source operand). */
414#define emulate_1op(_op, _dst, _eflags) \
415 do { \
416 unsigned long _tmp; \
417 \
d77c26fc 418 switch ((_dst).bytes) { \
6aa8b732
AK		 419 case 1: \
420 __asm__ __volatile__ ( \
d77c26fc 421 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 422 _op"b %1; " \
d77c26fc 423 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 424 : "=m" (_eflags), "=m" ((_dst).val), \
425 "=&r" (_tmp) \
d77c26fc 426 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 427 break; \
428 case 2: \
429 __asm__ __volatile__ ( \
d77c26fc 430 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 431 _op"w %1; " \
d77c26fc 432 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 433 : "=m" (_eflags), "=m" ((_dst).val), \
434 "=&r" (_tmp) \
d77c26fc 435 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 436 break; \
437 case 4: \
438 __asm__ __volatile__ ( \
d77c26fc 439 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 440 _op"l %1; " \
d77c26fc 441 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 442 : "=m" (_eflags), "=m" ((_dst).val), \
443 "=&r" (_tmp) \
d77c26fc 444 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 445 break; \
446 case 8: \
447 __emulate_1op_8byte(_op, _dst, _eflags); \
448 break; \
449 } \
450 } while (0)
451
452/* Emulate an instruction with quadword operands (x86/64 only). */
05b3e0c2 453#if defined(CONFIG_X86_64)
6aa8b732
AK		 454#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
455 do { \
456 __asm__ __volatile__ ( \
d77c26fc 457 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 458 _op"q %"_qx"3,%1; " \
d77c26fc 459 _POST_EFLAGS("0", "4", "2") \
6aa8b732 460 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
d77c26fc 461 : _qy ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 462 } while (0)
463
464#define __emulate_1op_8byte(_op, _dst, _eflags) \
465 do { \
466 __asm__ __volatile__ ( \
d77c26fc 467 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 468 _op"q %1; " \
d77c26fc 469 _POST_EFLAGS("0", "3", "2") \
6aa8b732 470 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
d77c26fc 471 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 472 } while (0)
473
474#elif defined(__i386__)
475#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
476#define __emulate_1op_8byte(_op, _dst, _eflags)
477#endif /* __i386__ */
478
479/* Fetch next part of the instruction being emulated. */
480#define insn_fetch(_type, _size, _eip) \
481({ unsigned long _x; \
62266869 482 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
d77c26fc 483 if (rc != 0) \
6aa8b732
AK		 484 goto done; \
485 (_eip) += (_size); \
486 (_type)_x; \
487})
488
ddcb2885
HH		 489static inline unsigned long ad_mask(struct decode_cache *c)
490{
491 return (1UL << (c->ad_bytes << 3)) - 1;
492}
493
6aa8b732 494/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 495static inline unsigned long
496address_mask(struct decode_cache *c, unsigned long reg)
497{
498 if (c->ad_bytes == sizeof(unsigned long))
499 return reg;
500 else
501 return reg & ad_mask(c);
502}
503
504static inline unsigned long
505register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
506{
507 return base + address_mask(c, reg);
508}
509
7a957275
HH		 510static inline void
511register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
512{
513 if (c->ad_bytes == sizeof(unsigned long))
514 *reg += inc;
515 else
516 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
517}
6aa8b732 518
7a957275
HH		 519static inline void jmp_rel(struct decode_cache *c, int rel)
520{
521 register_address_increment(c, &c->eip, rel);
522}
098c937b 523
62266869
AK		 524static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
525 struct x86_emulate_ops *ops,
526 unsigned long linear, u8 *dest)
527{
528 struct fetch_cache *fc = &ctxt->decode.fetch;
529 int rc;
530 int size;
531
532 if (linear < fc->start || linear >= fc->end) {
533 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
534 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
535 if (rc)
536 return rc;
537 fc->start = linear;
538 fc->end = linear + size;
539 }
540 *dest = fc->data[linear - fc->start];
541 return 0;
542}
543
544static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
545 struct x86_emulate_ops *ops,
546 unsigned long eip, void *dest, unsigned size)
547{
548 int rc = 0;
549
550 eip += ctxt->cs_base;
551 while (size--) {
552 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
553 if (rc)
554 return rc;
555 }
556 return 0;
557}
558
1e3c5cb0
RR		 559/*
560 * Given the 'reg' portion of a ModRM byte, and a register block, return a
561 * pointer into the block that addresses the relevant register.
562 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
563 */
564static void *decode_register(u8 modrm_reg, unsigned long *regs,
565 int highbyte_regs)
6aa8b732
AK		 566{
567 void *p;
568
569 p = &regs[modrm_reg];
570 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
571 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
572 return p;
573}
574
575static int read_descriptor(struct x86_emulate_ctxt *ctxt,
576 struct x86_emulate_ops *ops,
577 void *ptr,
578 u16 *size, unsigned long *address, int op_bytes)
579{
580 int rc;
581
582 if (op_bytes == 2)
583 op_bytes = 3;
584 *address = 0;
cebff02b
LV		 585 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
586 ctxt->vcpu);
6aa8b732
AK		 587 if (rc)
588 return rc;
cebff02b
LV		 589 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
590 ctxt->vcpu);
6aa8b732
AK		 591 return rc;
592}
593
bbe9abbd
NK		 594static int test_cc(unsigned int condition, unsigned int flags)
595{
596 int rc = 0;
597
598 switch ((condition & 15) >> 1) {
599 case 0: /* o */
600 rc |= (flags & EFLG_OF);
601 break;
602 case 1: /* b/c/nae */
603 rc |= (flags & EFLG_CF);
604 break;
605 case 2: /* z/e */
606 rc |= (flags & EFLG_ZF);
607 break;
608 case 3: /* be/na */
609 rc |= (flags & (EFLG_CF|EFLG_ZF));
610 break;
611 case 4: /* s */
612 rc |= (flags & EFLG_SF);
613 break;
614 case 5: /* p/pe */
615 rc |= (flags & EFLG_PF);
616 break;
617 case 7: /* le/ng */
618 rc |= (flags & EFLG_ZF);
619 /* fall through */
620 case 6: /* l/nge */
621 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
622 break;
623 }
624
625 /* Odd condition identifiers (lsb == 1) have inverted sense. */
626 return (!!rc ^ (condition & 1));
627}
628
3c118e24
AK		 629static void decode_register_operand(struct operand *op,
630 struct decode_cache *c,
3c118e24
AK		 631 int inhibit_bytereg)
632{
33615aa9 633 unsigned reg = c->modrm_reg;
9f1ef3f8 634 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 635
636 if (!(c->d & ModRM))
637 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 638 op->type = OP_REG;
639 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 640 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 641 op->val = *(u8 *)op->ptr;
642 op->bytes = 1;
643 } else {
33615aa9 644 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 645 op->bytes = c->op_bytes;
646 switch (op->bytes) {
647 case 2:
648 op->val = *(u16 *)op->ptr;
649 break;
650 case 4:
651 op->val = *(u32 *)op->ptr;
652 break;
653 case 8:
654 op->val = *(u64 *) op->ptr;
655 break;
656 }
657 }
658 op->orig_val = op->val;
659}
660
1c73ef66
AK		 661static int decode_modrm(struct x86_emulate_ctxt *ctxt,
662 struct x86_emulate_ops *ops)
663{
664 struct decode_cache *c = &ctxt->decode;
665 u8 sib;
666 int index_reg = 0, base_reg = 0, scale, rip_relative = 0;
667 int rc = 0;
668
669 if (c->rex_prefix) {
670 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
671 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
672 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
673 }
674
675 c->modrm = insn_fetch(u8, 1, c->eip);
676 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
677 c->modrm_reg |= (c->modrm & 0x38) >> 3;
678 c->modrm_rm |= (c->modrm & 0x07);
679 c->modrm_ea = 0;
680 c->use_modrm_ea = 1;
681
682 if (c->modrm_mod == 3) {
107d6d2e
AK		 683 c->modrm_ptr = decode_register(c->modrm_rm,
684 c->regs, c->d & ByteOp);
685 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 686 return rc;
687 }
688
689 if (c->ad_bytes == 2) {
690 unsigned bx = c->regs[VCPU_REGS_RBX];
691 unsigned bp = c->regs[VCPU_REGS_RBP];
692 unsigned si = c->regs[VCPU_REGS_RSI];
693 unsigned di = c->regs[VCPU_REGS_RDI];
694
695 /* 16-bit ModR/M decode. */
696 switch (c->modrm_mod) {
697 case 0:
698 if (c->modrm_rm == 6)
699 c->modrm_ea += insn_fetch(u16, 2, c->eip);
700 break;
701 case 1:
702 c->modrm_ea += insn_fetch(s8, 1, c->eip);
703 break;
704 case 2:
705 c->modrm_ea += insn_fetch(u16, 2, c->eip);
706 break;
707 }
708 switch (c->modrm_rm) {
709 case 0:
710 c->modrm_ea += bx + si;
711 break;
712 case 1:
713 c->modrm_ea += bx + di;
714 break;
715 case 2:
716 c->modrm_ea += bp + si;
717 break;
718 case 3:
719 c->modrm_ea += bp + di;
720 break;
721 case 4:
722 c->modrm_ea += si;
723 break;
724 case 5:
725 c->modrm_ea += di;
726 break;
727 case 6:
728 if (c->modrm_mod != 0)
729 c->modrm_ea += bp;
730 break;
731 case 7:
732 c->modrm_ea += bx;
733 break;
734 }
735 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
736 (c->modrm_rm == 6 && c->modrm_mod != 0))
737 if (!c->override_base)
738 c->override_base = &ctxt->ss_base;
739 c->modrm_ea = (u16)c->modrm_ea;
740 } else {
741 /* 32/64-bit ModR/M decode. */
742 switch (c->modrm_rm) {
743 case 4:
744 case 12:
745 sib = insn_fetch(u8, 1, c->eip);
746 index_reg |= (sib >> 3) & 7;
747 base_reg |= sib & 7;
748 scale = sib >> 6;
749
750 switch (base_reg) {
751 case 5:
752 if (c->modrm_mod != 0)
753 c->modrm_ea += c->regs[base_reg];
754 else
755 c->modrm_ea +=
756 insn_fetch(s32, 4, c->eip);
757 break;
758 default:
759 c->modrm_ea += c->regs[base_reg];
760 }
761 switch (index_reg) {
762 case 4:
763 break;
764 default:
765 c->modrm_ea += c->regs[index_reg] << scale;
766 }
767 break;
768 case 5:
769 if (c->modrm_mod != 0)
770 c->modrm_ea += c->regs[c->modrm_rm];
771 else if (ctxt->mode == X86EMUL_MODE_PROT64)
772 rip_relative = 1;
773 break;
774 default:
775 c->modrm_ea += c->regs[c->modrm_rm];
776 break;
777 }
778 switch (c->modrm_mod) {
779 case 0:
780 if (c->modrm_rm == 5)
781 c->modrm_ea += insn_fetch(s32, 4, c->eip);
782 break;
783 case 1:
784 c->modrm_ea += insn_fetch(s8, 1, c->eip);
785 break;
786 case 2:
787 c->modrm_ea += insn_fetch(s32, 4, c->eip);
788 break;
789 }
790 }
791 if (rip_relative) {
792 c->modrm_ea += c->eip;
793 switch (c->d & SrcMask) {
794 case SrcImmByte:
795 c->modrm_ea += 1;
796 break;
797 case SrcImm:
798 if (c->d & ByteOp)
799 c->modrm_ea += 1;
800 else
801 if (c->op_bytes == 8)
802 c->modrm_ea += 4;
803 else
804 c->modrm_ea += c->op_bytes;
805 }
806 }
807done:
808 return rc;
809}
810
811static int decode_abs(struct x86_emulate_ctxt *ctxt,
812 struct x86_emulate_ops *ops)
813{
814 struct decode_cache *c = &ctxt->decode;
815 int rc = 0;
816
817 switch (c->ad_bytes) {
818 case 2:
819 c->modrm_ea = insn_fetch(u16, 2, c->eip);
820 break;
821 case 4:
822 c->modrm_ea = insn_fetch(u32, 4, c->eip);
823 break;
824 case 8:
825 c->modrm_ea = insn_fetch(u64, 8, c->eip);
826 break;
827 }
828done:
829 return rc;
830}
831
6aa8b732 832int
8b4caf66 833x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 834{
e4e03ded 835 struct decode_cache *c = &ctxt->decode;
6aa8b732 836 int rc = 0;
6aa8b732 837 int mode = ctxt->mode;
e09d082c 838 int def_op_bytes, def_ad_bytes, group;
6aa8b732
AK		 839
840 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 841
e4e03ded 842 memset(c, 0, sizeof(struct decode_cache));
ad312c7c
ZX		 843 c->eip = ctxt->vcpu->arch.rip;
844 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 845
846 switch (mode) {
847 case X86EMUL_MODE_REAL:
848 case X86EMUL_MODE_PROT16:
f21b8bf4 849 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 850 break;
851 case X86EMUL_MODE_PROT32:
f21b8bf4 852 def_op_bytes = def_ad_bytes = 4;
6aa8b732 853 break;
05b3e0c2 854#ifdef CONFIG_X86_64
6aa8b732 855 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 856 def_op_bytes = 4;
857 def_ad_bytes = 8;
6aa8b732
AK		 858 break;
859#endif
860 default:
861 return -1;
862 }
863
f21b8bf4
AK		 864 c->op_bytes = def_op_bytes;
865 c->ad_bytes = def_ad_bytes;
866
6aa8b732 867 /* Legacy prefixes. */
b4c6abfe 868 for (;;) {
e4e03ded 869 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 870 case 0x66: /* operand-size override */
f21b8bf4
AK		 871 /* switch between 2/4 bytes */
872 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 873 break;
874 case 0x67: /* address-size override */
875 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 876 /* switch between 4/8 bytes */
f21b8bf4 877 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 878 else
e4e03ded 879 /* switch between 2/4 bytes */
f21b8bf4 880 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732
AK		 881 break;
882 case 0x2e: /* CS override */
e4e03ded 883 c->override_base = &ctxt->cs_base;
6aa8b732
AK		 884 break;
885 case 0x3e: /* DS override */
e4e03ded 886 c->override_base = &ctxt->ds_base;
6aa8b732
AK		 887 break;
888 case 0x26: /* ES override */
e4e03ded 889 c->override_base = &ctxt->es_base;
6aa8b732
AK		 890 break;
891 case 0x64: /* FS override */
e4e03ded 892 c->override_base = &ctxt->fs_base;
6aa8b732
AK		 893 break;
894 case 0x65: /* GS override */
e4e03ded 895 c->override_base = &ctxt->gs_base;
6aa8b732
AK		 896 break;
897 case 0x36: /* SS override */
e4e03ded 898 c->override_base = &ctxt->ss_base;
6aa8b732 899 break;
b4c6abfe
LV		 900 case 0x40 ... 0x4f: /* REX */
901 if (mode != X86EMUL_MODE_PROT64)
902 goto done_prefixes;
33615aa9 903 c->rex_prefix = c->b;
b4c6abfe 904 continue;
6aa8b732 905 case 0xf0: /* LOCK */
e4e03ded 906 c->lock_prefix = 1;
6aa8b732 907 break;
ae6200ba 908 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 909 c->rep_prefix = REPNE_PREFIX;
910 break;
6aa8b732 911 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 912 c->rep_prefix = REPE_PREFIX;
6aa8b732 913 break;
6aa8b732
AK		 914 default:
915 goto done_prefixes;
916 }
b4c6abfe
LV		 917
918 /* Any legacy prefix after a REX prefix nullifies its effect. */
919
33615aa9 920 c->rex_prefix = 0;
6aa8b732
AK		 921 }
922
923done_prefixes:
924
925 /* REX prefix. */
1c73ef66 926 if (c->rex_prefix)
33615aa9 927 if (c->rex_prefix & 8)
e4e03ded 928 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 929
930 /* Opcode byte(s). */
e4e03ded
LV		 931 c->d = opcode_table[c->b];
932 if (c->d == 0) {
6aa8b732 933 /* Two-byte opcode? */
e4e03ded
LV		 934 if (c->b == 0x0f) {
935 c->twobyte = 1;
936 c->b = insn_fetch(u8, 1, c->eip);
937 c->d = twobyte_table[c->b];
6aa8b732 938 }
e09d082c 939 }
6aa8b732 940
e09d082c
AK		 941 if (c->d & Group) {
942 group = c->d & GroupMask;
943 c->modrm = insn_fetch(u8, 1, c->eip);
944 --c->eip;
945
946 group = (group << 3) + ((c->modrm >> 3) & 7);
947 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
948 c->d = group2_table[group];
949 else
950 c->d = group_table[group];
951 }
952
953 /* Unrecognised? */
954 if (c->d == 0) {
955 DPRINTF("Cannot emulate %02x\n", c->b);
956 return -1;
6aa8b732
AK		 957 }
958
6e3d5dfb
AK		 959 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
960 c->op_bytes = 8;
961
6aa8b732 962 /* ModRM and SIB bytes. */
1c73ef66
AK		 963 if (c->d & ModRM)
964 rc = decode_modrm(ctxt, ops);
965 else if (c->d & MemAbs)
966 rc = decode_abs(ctxt, ops);
967 if (rc)
968 goto done;
6aa8b732 969
c7e75a3d
AK		 970 if (!c->override_base)
971 c->override_base = &ctxt->ds_base;
972 if (mode == X86EMUL_MODE_PROT64 &&
973 c->override_base != &ctxt->fs_base &&
974 c->override_base != &ctxt->gs_base)
975 c->override_base = NULL;
976
977 if (c->override_base)
978 c->modrm_ea += *c->override_base;
979
980 if (c->ad_bytes != 8)
981 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 982 /*
983 * Decode and fetch the source operand: register, memory
984 * or immediate.
985 */
e4e03ded 986 switch (c->d & SrcMask) {
6aa8b732
AK		 987 case SrcNone:
988 break;
989 case SrcReg:
9f1ef3f8 990 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 991 break;
992 case SrcMem16:
e4e03ded 993 c->src.bytes = 2;
6aa8b732
AK		 994 goto srcmem_common;
995 case SrcMem32:
e4e03ded 996 c->src.bytes = 4;
6aa8b732
AK		 997 goto srcmem_common;
998 case SrcMem:
e4e03ded
LV		 999 c->src.bytes = (c->d & ByteOp) ? 1 :
1000 c->op_bytes;
b85b9ee9 1001 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1002 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1003 break;
d77c26fc 1004 srcmem_common:
4e62417b
AJ		 1005 /*
1006 * For instructions with a ModR/M byte, switch to register
1007 * access if Mod = 3.
1008 */
e4e03ded
LV		 1009 if ((c->d & ModRM) && c->modrm_mod == 3) {
1010 c->src.type = OP_REG;
66b85505 1011 c->src.val = c->modrm_val;
107d6d2e 1012 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1013 break;
1014 }
e4e03ded 1015 c->src.type = OP_MEM;
6aa8b732
AK		 1016 break;
1017 case SrcImm:
e4e03ded
LV		 1018 c->src.type = OP_IMM;
1019 c->src.ptr = (unsigned long *)c->eip;
1020 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1021 if (c->src.bytes == 8)
1022 c->src.bytes = 4;
6aa8b732 1023 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1024 switch (c->src.bytes) {
6aa8b732 1025 case 1:
e4e03ded 1026 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1027 break;
1028 case 2:
e4e03ded 1029 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1030 break;
1031 case 4:
e4e03ded 1032 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1033 break;
1034 }
1035 break;
1036 case SrcImmByte:
e4e03ded
LV		 1037 c->src.type = OP_IMM;
1038 c->src.ptr = (unsigned long *)c->eip;
1039 c->src.bytes = 1;
1040 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1041 break;
1042 }
1043
038e51de 1044 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1045 switch (c->d & DstMask) {
038e51de
AK		 1046 case ImplicitOps:
1047 /* Special instructions do their own operand decoding. */
8b4caf66 1048 return 0;
038e51de 1049 case DstReg:
9f1ef3f8 1050 decode_register_operand(&c->dst, c,
3c118e24 1051 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1052 break;
1053 case DstMem:
e4e03ded 1054 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1055 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1056 c->dst.type = OP_REG;
66b85505 1057 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1058 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1059 break;
1060 }
8b4caf66
LV		 1061 c->dst.type = OP_MEM;
1062 break;
1063 }
1064
1065done:
1066 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1067}
1068
8cdbd2c9
LV		 1069static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1070{
1071 struct decode_cache *c = &ctxt->decode;
1072
1073 c->dst.type = OP_MEM;
1074 c->dst.bytes = c->op_bytes;
1075 c->dst.val = c->src.val;
7a957275 1076 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
e4706772 1077 c->dst.ptr = (void *) register_address(c, ctxt->ss_base,
8cdbd2c9
LV		 1078 c->regs[VCPU_REGS_RSP]);
1079}
1080
1081static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1082 struct x86_emulate_ops *ops)
1083{
1084 struct decode_cache *c = &ctxt->decode;
1085 int rc;
1086
e4706772 1087 rc = ops->read_std(register_address(c, ctxt->ss_base,
8cdbd2c9
LV		 1088 c->regs[VCPU_REGS_RSP]),
1089 &c->dst.val, c->dst.bytes, ctxt->vcpu);
1090 if (rc != 0)
1091 return rc;
1092
7a957275 1093 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->dst.bytes);
8cdbd2c9
LV		 1094
1095 return 0;
1096}
1097
05f086f8 1098static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1099{
05f086f8 1100 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1101 switch (c->modrm_reg) {
1102 case 0: /* rol */
05f086f8 1103 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1104 break;
1105 case 1: /* ror */
05f086f8 1106 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1107 break;
1108 case 2: /* rcl */
05f086f8 1109 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1110 break;
1111 case 3: /* rcr */
05f086f8 1112 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1113 break;
1114 case 4: /* sal/shl */
1115 case 6: /* sal/shl */
05f086f8 1116 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1117 break;
1118 case 5: /* shr */
05f086f8 1119 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1120 break;
1121 case 7: /* sar */
05f086f8 1122 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1123 break;
1124 }
1125}
1126
1127static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1128 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1129{
1130 struct decode_cache *c = &ctxt->decode;
1131 int rc = 0;
1132
1133 switch (c->modrm_reg) {
1134 case 0 ... 1: /* test */
05f086f8 1135 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1136 break;
1137 case 2: /* not */
1138 c->dst.val = ~c->dst.val;
1139 break;
1140 case 3: /* neg */
05f086f8 1141 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1142 break;
1143 default:
1144 DPRINTF("Cannot emulate %02x\n", c->b);
1145 rc = X86EMUL_UNHANDLEABLE;
1146 break;
1147 }
8cdbd2c9
LV		 1148 return rc;
1149}
1150
1151static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1152 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1153{
1154 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1155
1156 switch (c->modrm_reg) {
1157 case 0: /* inc */
05f086f8 1158 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1159 break;
1160 case 1: /* dec */
05f086f8 1161 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1162 break;
1163 case 4: /* jmp abs */
fd60754e 1164 c->eip = c->src.val;
8cdbd2c9
LV		 1165 break;
1166 case 6: /* push */
fd60754e 1167 emulate_push(ctxt);
8cdbd2c9 1168 break;
8cdbd2c9
LV		 1169 }
1170 return 0;
1171}
1172
1173static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1174 struct x86_emulate_ops *ops,
e8d8d7fe 1175 unsigned long memop)
8cdbd2c9
LV		 1176{
1177 struct decode_cache *c = &ctxt->decode;
1178 u64 old, new;
1179 int rc;
1180
e8d8d7fe 1181 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
8cdbd2c9
LV		 1182 if (rc != 0)
1183 return rc;
1184
1185 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1186 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1187
1188 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1189 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1190 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1191
1192 } else {
1193 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1194 (u32) c->regs[VCPU_REGS_RBX];
1195
e8d8d7fe 1196 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
8cdbd2c9
LV		 1197 if (rc != 0)
1198 return rc;
05f086f8 1199 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1200 }
1201 return 0;
1202}
1203
1204static inline int writeback(struct x86_emulate_ctxt *ctxt,
1205 struct x86_emulate_ops *ops)
1206{
1207 int rc;
1208 struct decode_cache *c = &ctxt->decode;
1209
1210 switch (c->dst.type) {
1211 case OP_REG:
1212 /* The 4-byte case *is* correct:
1213 * in 64-bit mode we zero-extend.
1214 */
1215 switch (c->dst.bytes) {
1216 case 1:
1217 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1218 break;
1219 case 2:
1220 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1221 break;
1222 case 4:
1223 *c->dst.ptr = (u32)c->dst.val;
1224 break; /* 64b: zero-ext */
1225 case 8:
1226 *c->dst.ptr = c->dst.val;
1227 break;
1228 }
1229 break;
1230 case OP_MEM:
1231 if (c->lock_prefix)
1232 rc = ops->cmpxchg_emulated(
1233 (unsigned long)c->dst.ptr,
1234 &c->dst.orig_val,
1235 &c->dst.val,
1236 c->dst.bytes,
1237 ctxt->vcpu);
1238 else
1239 rc = ops->write_emulated(
1240 (unsigned long)c->dst.ptr,
1241 &c->dst.val,
1242 c->dst.bytes,
1243 ctxt->vcpu);
1244 if (rc != 0)
1245 return rc;
a01af5ec
LV		 1246 break;
1247 case OP_NONE:
1248 /* no writeback */
1249 break;
8cdbd2c9
LV		 1250 default:
1251 break;
1252 }
1253 return 0;
1254}
1255
8b4caf66 1256int
1be3aa47 1257x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 1258{
e8d8d7fe 1259 unsigned long memop = 0;
8b4caf66 1260 u64 msr_data;
3427318f 1261 unsigned long saved_eip = 0;
8b4caf66 1262 struct decode_cache *c = &ctxt->decode;
1be3aa47 1263 int rc = 0;
8b4caf66 1264
3427318f
LV		 1265 /* Shadow copy of register state. Committed on successful emulation.
1266 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1267 * modify them.
1268 */
1269
ad312c7c 1270 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f
LV		 1271 saved_eip = c->eip;
1272
c7e75a3d 1273 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
e8d8d7fe 1274 memop = c->modrm_ea;
8b4caf66 1275
b9fa9d6b
AK		 1276 if (c->rep_prefix && (c->d & String)) {
1277 /* All REP prefixes have the same first termination condition */
1278 if (c->regs[VCPU_REGS_RCX] == 0) {
ad312c7c 1279 ctxt->vcpu->arch.rip = c->eip;
b9fa9d6b
AK		 1280 goto done;
1281 }
1282 /* The second termination condition only applies for REPE
1283 * and REPNE. Test if the repeat string operation prefix is
1284 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1285 * corresponding termination condition according to:
1286 * - if REPE/REPZ and ZF = 0 then done
1287 * - if REPNE/REPNZ and ZF = 1 then done
1288 */
1289 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1290 (c->b == 0xae) || (c->b == 0xaf)) {
1291 if ((c->rep_prefix == REPE_PREFIX) &&
1292 ((ctxt->eflags & EFLG_ZF) == 0)) {
ad312c7c 1293 ctxt->vcpu->arch.rip = c->eip;
b9fa9d6b
AK		 1294 goto done;
1295 }
1296 if ((c->rep_prefix == REPNE_PREFIX) &&
1297 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
ad312c7c 1298 ctxt->vcpu->arch.rip = c->eip;
b9fa9d6b
AK		 1299 goto done;
1300 }
1301 }
1302 c->regs[VCPU_REGS_RCX]--;
ad312c7c 1303 c->eip = ctxt->vcpu->arch.rip;
b9fa9d6b
AK		 1304 }
1305
8b4caf66 1306 if (c->src.type == OP_MEM) {
e8d8d7fe 1307 c->src.ptr = (unsigned long *)memop;
8b4caf66 1308 c->src.val = 0;
d77c26fc
MD		 1309 rc = ops->read_emulated((unsigned long)c->src.ptr,
1310 &c->src.val,
1311 c->src.bytes,
1312 ctxt->vcpu);
1313 if (rc != 0)
8b4caf66
LV		 1314 goto done;
1315 c->src.orig_val = c->src.val;
1316 }
1317
1318 if ((c->d & DstMask) == ImplicitOps)
1319 goto special_insn;
1320
1321
1322 if (c->dst.type == OP_MEM) {
e8d8d7fe 1323 c->dst.ptr = (unsigned long *)memop;
8b4caf66
LV		 1324 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1325 c->dst.val = 0;
e4e03ded
LV		 1326 if (c->d & BitOp) {
1327 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1328
e4e03ded
LV		 1329 c->dst.ptr = (void *)c->dst.ptr +
1330 (c->src.val & mask) / 8;
038e51de 1331 }
e4e03ded
LV		 1332 if (!(c->d & Mov) &&
1333 /* optimisation - avoid slow emulated read */
1334 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1335 &c->dst.val,
1336 c->dst.bytes, ctxt->vcpu)) != 0))
038e51de 1337 goto done;
038e51de 1338 }
e4e03ded 1339 c->dst.orig_val = c->dst.val;
038e51de 1340
018a98db
AK		 1341special_insn:
1342
e4e03ded 1343 if (c->twobyte)
6aa8b732
AK		 1344 goto twobyte_insn;
1345
e4e03ded 1346 switch (c->b) {
6aa8b732
AK		 1347 case 0x00 ... 0x05:
1348 add: /* add */
05f086f8 1349 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1350 break;
1351 case 0x08 ... 0x0d:
1352 or: /* or */
05f086f8 1353 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1354 break;
1355 case 0x10 ... 0x15:
1356 adc: /* adc */
05f086f8 1357 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1358 break;
1359 case 0x18 ... 0x1d:
1360 sbb: /* sbb */
05f086f8 1361 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1362 break;
19eb938e 1363 case 0x20 ... 0x23:
6aa8b732 1364 and: /* and */
05f086f8 1365 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732 1366 break;
19eb938e 1367 case 0x24: /* and al imm8 */
e4e03ded
LV		 1368 c->dst.type = OP_REG;
1369 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1370 c->dst.val = *(u8 *)c->dst.ptr;
1371 c->dst.bytes = 1;
1372 c->dst.orig_val = c->dst.val;
19eb938e
NK		 1373 goto and;
1374 case 0x25: /* and ax imm16, or eax imm32 */
e4e03ded
LV		 1375 c->dst.type = OP_REG;
1376 c->dst.bytes = c->op_bytes;
1377 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1378 if (c->op_bytes == 2)
1379 c->dst.val = *(u16 *)c->dst.ptr;
19eb938e 1380 else
e4e03ded
LV		 1381 c->dst.val = *(u32 *)c->dst.ptr;
1382 c->dst.orig_val = c->dst.val;
19eb938e 1383 goto and;
6aa8b732
AK		 1384 case 0x28 ... 0x2d:
1385 sub: /* sub */
05f086f8 1386 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1387 break;
1388 case 0x30 ... 0x35:
1389 xor: /* xor */
05f086f8 1390 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1391 break;
1392 case 0x38 ... 0x3d:
1393 cmp: /* cmp */
05f086f8 1394 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 1395 break;
33615aa9
AK		 1396 case 0x40 ... 0x47: /* inc r16/r32 */
1397 emulate_1op("inc", c->dst, ctxt->eflags);
1398 break;
1399 case 0x48 ... 0x4f: /* dec r16/r32 */
1400 emulate_1op("dec", c->dst, ctxt->eflags);
1401 break;
1402 case 0x50 ... 0x57: /* push reg */
1403 c->dst.type = OP_MEM;
1404 c->dst.bytes = c->op_bytes;
1405 c->dst.val = c->src.val;
7a957275 1406 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
33615aa9
AK		 1407 -c->op_bytes);
1408 c->dst.ptr = (void *) register_address(
e4706772 1409 c, ctxt->ss_base, c->regs[VCPU_REGS_RSP]);
33615aa9
AK		 1410 break;
1411 case 0x58 ... 0x5f: /* pop reg */
1412 pop_instruction:
e4706772 1413 if ((rc = ops->read_std(register_address(c, ctxt->ss_base,
33615aa9
AK		 1414 c->regs[VCPU_REGS_RSP]), c->dst.ptr,
1415 c->op_bytes, ctxt->vcpu)) != 0)
1416 goto done;
1417
7a957275 1418 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
33615aa9
AK		 1419 c->op_bytes);
1420 c->dst.type = OP_NONE; /* Disable writeback. */
1421 break;
6aa8b732 1422 case 0x63: /* movsxd */
8b4caf66 1423 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1424 goto cannot_emulate;
e4e03ded 1425 c->dst.val = (s32) c->src.val;
6aa8b732 1426 break;
018a98db
AK		 1427 case 0x6a: /* push imm8 */
1428 c->src.val = 0L;
1429 c->src.val = insn_fetch(s8, 1, c->eip);
1430 emulate_push(ctxt);
1431 break;
1432 case 0x6c: /* insb */
1433 case 0x6d: /* insw/insd */
1434 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1435 1,
1436 (c->d & ByteOp) ? 1 : c->op_bytes,
1437 c->rep_prefix ?
e4706772 1438 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1439 (ctxt->eflags & EFLG_DF),
e4706772 1440 register_address(c, ctxt->es_base,
018a98db
AK		 1441 c->regs[VCPU_REGS_RDI]),
1442 c->rep_prefix,
1443 c->regs[VCPU_REGS_RDX]) == 0) {
1444 c->eip = saved_eip;
1445 return -1;
1446 }
1447 return 0;
1448 case 0x6e: /* outsb */
1449 case 0x6f: /* outsw/outsd */
1450 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1451 0,
1452 (c->d & ByteOp) ? 1 : c->op_bytes,
1453 c->rep_prefix ?
e4706772 1454 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1455 (ctxt->eflags & EFLG_DF),
e4706772 1456 register_address(c, c->override_base ?
018a98db
AK		 1457 *c->override_base :
1458 ctxt->ds_base,
1459 c->regs[VCPU_REGS_RSI]),
1460 c->rep_prefix,
1461 c->regs[VCPU_REGS_RDX]) == 0) {
1462 c->eip = saved_eip;
1463 return -1;
1464 }
1465 return 0;
1466 case 0x70 ... 0x7f: /* jcc (short) */ {
1467 int rel = insn_fetch(s8, 1, c->eip);
1468
1469 if (test_cc(c->b, ctxt->eflags))
7a957275 1470 jmp_rel(c, rel);
018a98db
AK		 1471 break;
1472 }
6aa8b732 1473 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 1474 switch (c->modrm_reg) {
6aa8b732
AK		 1475 case 0:
1476 goto add;
1477 case 1:
1478 goto or;
1479 case 2:
1480 goto adc;
1481 case 3:
1482 goto sbb;
1483 case 4:
1484 goto and;
1485 case 5:
1486 goto sub;
1487 case 6:
1488 goto xor;
1489 case 7:
1490 goto cmp;
1491 }
1492 break;
1493 case 0x84 ... 0x85:
05f086f8 1494 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1495 break;
1496 case 0x86 ... 0x87: /* xchg */
1497 /* Write back the register source. */
e4e03ded 1498 switch (c->dst.bytes) {
6aa8b732 1499 case 1:
e4e03ded 1500 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 1501 break;
1502 case 2:
e4e03ded 1503 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 1504 break;
1505 case 4:
e4e03ded 1506 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 1507 break; /* 64b reg: zero-extend */
1508 case 8:
e4e03ded 1509 *c->src.ptr = c->dst.val;
6aa8b732
AK		 1510 break;
1511 }
1512 /*
1513 * Write back the memory destination with implicit LOCK
1514 * prefix.
1515 */
e4e03ded
LV		 1516 c->dst.val = c->src.val;
1517 c->lock_prefix = 1;
6aa8b732 1518 break;
6aa8b732 1519 case 0x88 ... 0x8b: /* mov */
7de75248 1520 goto mov;
7e0b54b1 1521 case 0x8d: /* lea r16/r32, m */
f9b7aab3 1522 c->dst.val = c->modrm_ea;
7e0b54b1 1523 break;
4257198a
GT		 1524 case 0x8e: { /* mov seg, r/m16 */
1525 uint16_t sel;
1526 int type_bits;
1527 int err;
1528
1529 sel = c->src.val;
1530 if (c->modrm_reg <= 5) {
1531 type_bits = (c->modrm_reg == 1) ? 9 : 1;
1532 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
1533 type_bits, c->modrm_reg);
1534 } else {
1535 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
1536 c->modrm);
1537 goto cannot_emulate;
1538 }
1539
1540 if (err < 0)
1541 goto cannot_emulate;
1542
1543 c->dst.type = OP_NONE; /* Disable writeback. */
1544 break;
1545 }
6aa8b732 1546 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 1547 rc = emulate_grp1a(ctxt, ops);
1548 if (rc != 0)
6aa8b732 1549 goto done;
6aa8b732 1550 break;
fd2a7608 1551 case 0x9c: /* pushf */
05f086f8 1552 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 1553 emulate_push(ctxt);
1554 break;
535eabcf 1555 case 0x9d: /* popf */
05f086f8 1556 c->dst.ptr = (unsigned long *) &ctxt->eflags;
535eabcf 1557 goto pop_instruction;
018a98db
AK		 1558 case 0xa0 ... 0xa1: /* mov */
1559 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1560 c->dst.val = c->src.val;
1561 break;
1562 case 0xa2 ... 0xa3: /* mov */
1563 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1564 break;
6aa8b732 1565 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 1566 c->dst.type = OP_MEM;
1567 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1568 c->dst.ptr = (unsigned long *)register_address(c,
e4e03ded
LV		 1569 ctxt->es_base,
1570 c->regs[VCPU_REGS_RDI]);
e4706772 1571 if ((rc = ops->read_emulated(register_address(c,
e4e03ded
LV		 1572 c->override_base ? *c->override_base :
1573 ctxt->ds_base,
1574 c->regs[VCPU_REGS_RSI]),
1575 &c->dst.val,
1576 c->dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1577 goto done;
7a957275 1578 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1579 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1580 : c->dst.bytes);
7a957275 1581 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1582 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1583 : c->dst.bytes);
6aa8b732
AK		 1584 break;
1585 case 0xa6 ... 0xa7: /* cmps */
d7e5117a
GT		 1586 c->src.type = OP_NONE; /* Disable writeback. */
1587 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1588 c->src.ptr = (unsigned long *)register_address(c,
d7e5117a
GT		 1589 c->override_base ? *c->override_base :
1590 ctxt->ds_base,
1591 c->regs[VCPU_REGS_RSI]);
1592 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1593 &c->src.val,
1594 c->src.bytes,
1595 ctxt->vcpu)) != 0)
1596 goto done;
1597
1598 c->dst.type = OP_NONE; /* Disable writeback. */
1599 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1600 c->dst.ptr = (unsigned long *)register_address(c,
d7e5117a
GT		 1601 ctxt->es_base,
1602 c->regs[VCPU_REGS_RDI]);
1603 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1604 &c->dst.val,
1605 c->dst.bytes,
1606 ctxt->vcpu)) != 0)
1607 goto done;
1608
1609 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1610
1611 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1612
7a957275 1613 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
d7e5117a
GT		 1614 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1615 : c->src.bytes);
7a957275 1616 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
d7e5117a
GT		 1617 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1618 : c->dst.bytes);
1619
1620 break;
6aa8b732 1621 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 1622 c->dst.type = OP_MEM;
1623 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1624 c->dst.ptr = (unsigned long *)register_address(c,
a7e6c88a
SY		 1625 ctxt->es_base,
1626 c->regs[VCPU_REGS_RDI]);
e4e03ded 1627 c->dst.val = c->regs[VCPU_REGS_RAX];
7a957275 1628 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1629 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1630 : c->dst.bytes);
6aa8b732
AK		 1631 break;
1632 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 1633 c->dst.type = OP_REG;
1634 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1635 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
e4706772 1636 if ((rc = ops->read_emulated(register_address(c,
a7e6c88a
SY		 1637 c->override_base ? *c->override_base :
1638 ctxt->ds_base,
1639 c->regs[VCPU_REGS_RSI]),
1640 &c->dst.val,
1641 c->dst.bytes,
1642 ctxt->vcpu)) != 0)
6aa8b732 1643 goto done;
7a957275 1644 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1645 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1646 : c->dst.bytes);
6aa8b732
AK		 1647 break;
1648 case 0xae ... 0xaf: /* scas */
1649 DPRINTF("Urk! I don't handle SCAS.\n");
1650 goto cannot_emulate;
615ac125
GT		 1651 case 0xb8: /* mov r, imm */
1652 goto mov;
018a98db
AK		 1653 case 0xc0 ... 0xc1:
1654 emulate_grp2(ctxt);
1655 break;
111de5d6
AK		 1656 case 0xc3: /* ret */
1657 c->dst.ptr = &c->eip;
1658 goto pop_instruction;
018a98db
AK		 1659 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1660 mov:
1661 c->dst.val = c->src.val;
1662 break;
1663 case 0xd0 ... 0xd1: /* Grp2 */
1664 c->src.val = 1;
1665 emulate_grp2(ctxt);
1666 break;
1667 case 0xd2 ... 0xd3: /* Grp2 */
1668 c->src.val = c->regs[VCPU_REGS_RCX];
1669 emulate_grp2(ctxt);
1670 break;
1a52e051
NK		 1671 case 0xe8: /* call (near) */ {
1672 long int rel;
e4e03ded 1673 switch (c->op_bytes) {
1a52e051 1674 case 2:
e4e03ded 1675 rel = insn_fetch(s16, 2, c->eip);
1a52e051
NK		 1676 break;
1677 case 4:
e4e03ded 1678 rel = insn_fetch(s32, 4, c->eip);
1a52e051 1679 break;
1a52e051
NK		 1680 default:
1681 DPRINTF("Call: Invalid op_bytes\n");
1682 goto cannot_emulate;
1683 }
e4e03ded 1684 c->src.val = (unsigned long) c->eip;
7a957275 1685 jmp_rel(c, rel);
e4e03ded 1686 c->op_bytes = c->ad_bytes;
8cdbd2c9
LV		 1687 emulate_push(ctxt);
1688 break;
1a52e051
NK		 1689 }
1690 case 0xe9: /* jmp rel */
954cd36f
GT		 1691 goto jmp;
1692 case 0xea: /* jmp far */ {
1693 uint32_t eip;
1694 uint16_t sel;
1695
1696 switch (c->op_bytes) {
1697 case 2:
1698 eip = insn_fetch(u16, 2, c->eip);
1699 break;
1700 case 4:
1701 eip = insn_fetch(u32, 4, c->eip);
1702 break;
1703 default:
1704 DPRINTF("jmp far: Invalid op_bytes\n");
1705 goto cannot_emulate;
1706 }
1707 sel = insn_fetch(u16, 2, c->eip);
1708 if (kvm_load_segment_descriptor(ctxt->vcpu, sel, 9, VCPU_SREG_CS) < 0) {
1709 DPRINTF("jmp far: Failed to load CS descriptor\n");
1710 goto cannot_emulate;
1711 }
1712
1713 c->eip = eip;
1714 break;
1715 }
1716 case 0xeb:
1717 jmp: /* jmp rel short */
7a957275 1718 jmp_rel(c, c->src.val);
a01af5ec 1719 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 1720 break;
111de5d6 1721 case 0xf4: /* hlt */
ad312c7c 1722 ctxt->vcpu->arch.halt_request = 1;
111de5d6
AK		 1723 goto done;
1724 case 0xf5: /* cmc */
1725 /* complement carry flag from eflags reg */
1726 ctxt->eflags ^= EFLG_CF;
1727 c->dst.type = OP_NONE; /* Disable writeback. */
1728 break;
018a98db
AK		 1729 case 0xf6 ... 0xf7: /* Grp3 */
1730 rc = emulate_grp3(ctxt, ops);
1731 if (rc != 0)
1732 goto done;
1733 break;
111de5d6
AK		 1734 case 0xf8: /* clc */
1735 ctxt->eflags &= ~EFLG_CF;
1736 c->dst.type = OP_NONE; /* Disable writeback. */
1737 break;
1738 case 0xfa: /* cli */
1739 ctxt->eflags &= ~X86_EFLAGS_IF;
1740 c->dst.type = OP_NONE; /* Disable writeback. */
1741 break;
1742 case 0xfb: /* sti */
1743 ctxt->eflags |= X86_EFLAGS_IF;
1744 c->dst.type = OP_NONE; /* Disable writeback. */
1745 break;
018a98db
AK		 1746 case 0xfe ... 0xff: /* Grp4/Grp5 */
1747 rc = emulate_grp45(ctxt, ops);
1748 if (rc != 0)
1749 goto done;
1750 break;
6aa8b732 1751 }
018a98db
AK		 1752
1753writeback:
1754 rc = writeback(ctxt, ops);
1755 if (rc != 0)
1756 goto done;
1757
1758 /* Commit shadow register state. */
ad312c7c
ZX		 1759 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
1760 ctxt->vcpu->arch.rip = c->eip;
018a98db
AK		 1761
1762done:
1763 if (rc == X86EMUL_UNHANDLEABLE) {
1764 c->eip = saved_eip;
1765 return -1;
1766 }
1767 return 0;
6aa8b732
AK		 1768
1769twobyte_insn:
e4e03ded 1770 switch (c->b) {
6aa8b732 1771 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 1772 switch (c->modrm_reg) {
6aa8b732
AK		 1773 u16 size;
1774 unsigned long address;
1775
aca7f966 1776 case 0: /* vmcall */
e4e03ded 1777 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 1778 goto cannot_emulate;
1779
7aa81cc0
AL		 1780 rc = kvm_fix_hypercall(ctxt->vcpu);
1781 if (rc)
1782 goto done;
1783
33e3885d
AK		 1784 /* Let the processor re-execute the fixed hypercall */
1785 c->eip = ctxt->vcpu->arch.rip;
16286d08
AK		 1786 /* Disable writeback. */
1787 c->dst.type = OP_NONE;
aca7f966 1788 break;
6aa8b732 1789 case 2: /* lgdt */
e4e03ded
LV		 1790 rc = read_descriptor(ctxt, ops, c->src.ptr,
1791 &size, &address, c->op_bytes);
6aa8b732
AK		 1792 if (rc)
1793 goto done;
1794 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 1795 /* Disable writeback. */
1796 c->dst.type = OP_NONE;
6aa8b732 1797 break;
aca7f966 1798 case 3: /* lidt/vmmcall */
e4e03ded 1799 if (c->modrm_mod == 3 && c->modrm_rm == 1) {
7aa81cc0
AL		 1800 rc = kvm_fix_hypercall(ctxt->vcpu);
1801 if (rc)
1802 goto done;
1803 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1804 } else {
e4e03ded 1805 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 1806 &size, &address,
e4e03ded 1807 c->op_bytes);
aca7f966
AL		 1808 if (rc)
1809 goto done;
1810 realmode_lidt(ctxt->vcpu, size, address);
1811 }
16286d08
AK		 1812 /* Disable writeback. */
1813 c->dst.type = OP_NONE;
6aa8b732
AK		 1814 break;
1815 case 4: /* smsw */
16286d08
AK		 1816 c->dst.bytes = 2;
1817 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
6aa8b732
AK		 1818 break;
1819 case 6: /* lmsw */
16286d08
AK		 1820 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
1821 &ctxt->eflags);
dc7457ea 1822 c->dst.type = OP_NONE;
6aa8b732
AK		 1823 break;
1824 case 7: /* invlpg*/
e8d8d7fe 1825 emulate_invlpg(ctxt->vcpu, memop);
16286d08
AK		 1826 /* Disable writeback. */
1827 c->dst.type = OP_NONE;
6aa8b732
AK		 1828 break;
1829 default:
1830 goto cannot_emulate;
1831 }
1832 break;
018a98db
AK		 1833 case 0x06:
1834 emulate_clts(ctxt->vcpu);
1835 c->dst.type = OP_NONE;
1836 break;
1837 case 0x08: /* invd */
1838 case 0x09: /* wbinvd */
1839 case 0x0d: /* GrpP (prefetch) */
1840 case 0x18: /* Grp16 (prefetch/nop) */
1841 c->dst.type = OP_NONE;
1842 break;
1843 case 0x20: /* mov cr, reg */
1844 if (c->modrm_mod != 3)
1845 goto cannot_emulate;
1846 c->regs[c->modrm_rm] =
1847 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1848 c->dst.type = OP_NONE; /* no writeback */
1849 break;
6aa8b732 1850 case 0x21: /* mov from dr to reg */
e4e03ded 1851 if (c->modrm_mod != 3)
6aa8b732 1852 goto cannot_emulate;
8cdbd2c9 1853 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 1854 if (rc)
1855 goto cannot_emulate;
1856 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1857 break;
018a98db
AK		 1858 case 0x22: /* mov reg, cr */
1859 if (c->modrm_mod != 3)
1860 goto cannot_emulate;
1861 realmode_set_cr(ctxt->vcpu,
1862 c->modrm_reg, c->modrm_val, &ctxt->eflags);
1863 c->dst.type = OP_NONE;
1864 break;
6aa8b732 1865 case 0x23: /* mov from reg to dr */
e4e03ded 1866 if (c->modrm_mod != 3)
6aa8b732 1867 goto cannot_emulate;
e4e03ded
LV		 1868 rc = emulator_set_dr(ctxt, c->modrm_reg,
1869 c->regs[c->modrm_rm]);
a01af5ec
LV		 1870 if (rc)
1871 goto cannot_emulate;
1872 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1873 break;
018a98db
AK		 1874 case 0x30:
1875 /* wrmsr */
1876 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1877 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1878 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
1879 if (rc) {
c1a5d4f9 1880 kvm_inject_gp(ctxt->vcpu, 0);
ad312c7c 1881 c->eip = ctxt->vcpu->arch.rip;
018a98db
AK		 1882 }
1883 rc = X86EMUL_CONTINUE;
1884 c->dst.type = OP_NONE;
1885 break;
1886 case 0x32:
1887 /* rdmsr */
1888 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
1889 if (rc) {
c1a5d4f9 1890 kvm_inject_gp(ctxt->vcpu, 0);
ad312c7c 1891 c->eip = ctxt->vcpu->arch.rip;
018a98db
AK		 1892 } else {
1893 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
1894 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
1895 }
1896 rc = X86EMUL_CONTINUE;
1897 c->dst.type = OP_NONE;
1898 break;
6aa8b732 1899 case 0x40 ... 0x4f: /* cmov */
e4e03ded 1900 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 1901 if (!test_cc(c->b, ctxt->eflags))
1902 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1903 break;
018a98db
AK		 1904 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1905 long int rel;
1906
1907 switch (c->op_bytes) {
1908 case 2:
1909 rel = insn_fetch(s16, 2, c->eip);
1910 break;
1911 case 4:
1912 rel = insn_fetch(s32, 4, c->eip);
1913 break;
1914 case 8:
1915 rel = insn_fetch(s64, 8, c->eip);
1916 break;
1917 default:
1918 DPRINTF("jnz: Invalid op_bytes\n");
1919 goto cannot_emulate;
1920 }
1921 if (test_cc(c->b, ctxt->eflags))
7a957275 1922 jmp_rel(c, rel);
018a98db
AK		 1923 c->dst.type = OP_NONE;
1924 break;
1925 }
7de75248
NK		 1926 case 0xa3:
1927 bt: /* bt */
e4f8e039 1928 c->dst.type = OP_NONE;
e4e03ded
LV		 1929 /* only subword offset */
1930 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1931 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248
NK		 1932 break;
1933 case 0xab:
1934 bts: /* bts */
e4e03ded
LV		 1935 /* only subword offset */
1936 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1937 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 1938 break;
6aa8b732
AK		 1939 case 0xb0 ... 0xb1: /* cmpxchg */
1940 /*
1941 * Save real source value, then compare EAX against
1942 * destination.
1943 */
e4e03ded
LV		 1944 c->src.orig_val = c->src.val;
1945 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 1946 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1947 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 1948 /* Success: write back to memory. */
e4e03ded 1949 c->dst.val = c->src.orig_val;
6aa8b732
AK		 1950 } else {
1951 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 1952 c->dst.type = OP_REG;
1953 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 1954 }
1955 break;
6aa8b732
AK		 1956 case 0xb3:
1957 btr: /* btr */
e4e03ded
LV		 1958 /* only subword offset */
1959 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1960 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 1961 break;
6aa8b732 1962 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 1963 c->dst.bytes = c->op_bytes;
1964 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
1965 : (u16) c->src.val;
6aa8b732 1966 break;
6aa8b732 1967 case 0xba: /* Grp8 */
e4e03ded 1968 switch (c->modrm_reg & 3) {
6aa8b732
AK		 1969 case 0:
1970 goto bt;
1971 case 1:
1972 goto bts;
1973 case 2:
1974 goto btr;
1975 case 3:
1976 goto btc;
1977 }
1978 break;
7de75248
NK		 1979 case 0xbb:
1980 btc: /* btc */
e4e03ded
LV		 1981 /* only subword offset */
1982 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1983 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 1984 break;
6aa8b732 1985 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 1986 c->dst.bytes = c->op_bytes;
1987 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
1988 (s16) c->src.val;
6aa8b732 1989 break;
a012e65a 1990 case 0xc3: /* movnti */
e4e03ded
LV		 1991 c->dst.bytes = c->op_bytes;
1992 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
1993 (u64) c->src.val;
a012e65a 1994 break;
6aa8b732 1995 case 0xc7: /* Grp9 (cmpxchg8b) */
e8d8d7fe 1996 rc = emulate_grp9(ctxt, ops, memop);
8cdbd2c9
LV		 1997 if (rc != 0)
1998 goto done;
018a98db 1999 c->dst.type = OP_NONE;
8cdbd2c9 2000 break;
6aa8b732
AK		 2001 }
2002 goto writeback;
2003
2004cannot_emulate:
e4e03ded 2005 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 2006 c->eip = saved_eip;
6aa8b732
AK		 2007 return -1;
2008}
Linux kernel - Deliverables
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