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KVM: x86 emulator: Complete ljmp decoding at decode stage
[deliverable/linux.git] / arch / x86 / kvm / x86_emulate.c
CommitLineData
6aa8b732
AK		 1/******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
5fdbf976 29#include "kvm_cache_regs.h"
6aa8b732
AK		 30#define DPRINTF(x...) do {} while (0)
31#endif
6aa8b732 32#include <linux/module.h>
edf88417 33#include <asm/kvm_x86_emulate.h>
6aa8b732
AK		 34
35/*
36 * Opcode effective-address decode tables.
37 * Note that we only emulate instructions that have at least one memory
38 * operand (excluding implicit stack references). We assume that stack
39 * references and instruction fetches will never occur in special memory
40 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
41 * not be handled.
42 */
43
44/* Operand sizes: 8-bit operands or specified/overridden size. */
45#define ByteOp (1<<0) /* 8-bit operands. */
46/* Destination operand type. */
47#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
48#define DstReg (2<<1) /* Register operand. */
49#define DstMem (3<<1) /* Memory operand. */
9c9fddd0
GT		 50#define DstAcc (4<<1) /* Destination Accumulator */
51#define DstMask (7<<1)
6aa8b732 52/* Source operand type. */
9c9fddd0
GT		 53#define SrcNone (0<<4) /* No source operand. */
54#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
55#define SrcReg (1<<4) /* Register operand. */
56#define SrcMem (2<<4) /* Memory operand. */
57#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
58#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
59#define SrcImm (5<<4) /* Immediate operand. */
60#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 61#define SrcOne (7<<4) /* Implied '1' */
9c9fddd0 62#define SrcMask (7<<4)
6aa8b732 63/* Generic ModRM decode. */
9c9fddd0 64#define ModRM (1<<7)
6aa8b732 65/* Destination is only written; never read. */
9c9fddd0
GT		 66#define Mov (1<<8)
67#define BitOp (1<<9)
68#define MemAbs (1<<10) /* Memory operand is absolute displacement */
69#define String (1<<12) /* String instruction (rep capable) */
70#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 71#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
72#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
73#define GroupMask 0xff /* Group number stored in bits 0:7 */
0dc8d10f
GT		 74/* Source 2 operand type */
75#define Src2None (0<<29)
76#define Src2CL (1<<29)
77#define Src2ImmByte (2<<29)
78#define Src2One (3<<29)
a5f868bd 79#define Src2Imm16 (4<<29)
0dc8d10f 80#define Src2Mask (7<<29)
6aa8b732 81
43bb19cd 82enum {
1d6ad207 83 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 84 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
43bb19cd
AK		 85};
86
45ed60b3 87static u32 opcode_table[256] = {
6aa8b732
AK		 88 /* 0x00 - 0x07 */
89 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
90 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
291fd39b 91 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, 0, 0,
6aa8b732
AK		 92 /* 0x08 - 0x0F */
93 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
94 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
95 0, 0, 0, 0,
96 /* 0x10 - 0x17 */
97 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
98 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
99 0, 0, 0, 0,
100 /* 0x18 - 0x1F */
101 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
102 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
103 0, 0, 0, 0,
104 /* 0x20 - 0x27 */
105 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
106 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
aa3a816b 107 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732
AK		 108 /* 0x28 - 0x2F */
109 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
110 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
111 0, 0, 0, 0,
112 /* 0x30 - 0x37 */
113 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
114 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
115 0, 0, 0, 0,
116 /* 0x38 - 0x3F */
117 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
118 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
8a9fee67
GT		 119 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
120 0, 0,
d77a2507 121 /* 0x40 - 0x47 */
33615aa9 122 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 123 /* 0x48 - 0x4F */
33615aa9 124 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 125 /* 0x50 - 0x57 */
6e3d5dfb
AK		 126 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
127 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 128 /* 0x58 - 0x5F */
6e3d5dfb
AK		 129 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
130 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 131 /* 0x60 - 0x67 */
6aa8b732 132 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 133 0, 0, 0, 0,
134 /* 0x68 - 0x6F */
91ed7a0e 135 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
e70669ab
LV		 136 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
137 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4
NK		 138 /* 0x70 - 0x77 */
139 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
140 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
141 /* 0x78 - 0x7F */
142 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
143 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732 144 /* 0x80 - 0x87 */
1d6ad207
AK		 145 Group | Group1_80, Group | Group1_81,
146 Group | Group1_82, Group | Group1_83,
6aa8b732
AK		 147 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
148 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
149 /* 0x88 - 0x8F */
150 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
151 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
38d5bc6d 152 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
4257198a 153 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
b13354f8
MG		 154 /* 0x90 - 0x97 */
155 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
156 /* 0x98 - 0x9F */
0654169e
GN		 157 0, 0, SrcImm | Src2Imm16, 0,
158 ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 159 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 160 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
161 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
b9fa9d6b
AK		 162 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
163 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 164 /* 0xA8 - 0xAF */
b9fa9d6b
AK		 165 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
166 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
167 ByteOp | ImplicitOps | String, ImplicitOps | String,
a5e2e82b
MG		 168 /* 0xB0 - 0xB7 */
169 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
170 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
171 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
172 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
173 /* 0xB8 - 0xBF */
174 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
175 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
176 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
177 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
6aa8b732 178 /* 0xC0 - 0xC7 */
d9413cd7 179 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 180 0, ImplicitOps | Stack, 0, 0,
d9413cd7 181 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732 182 /* 0xC8 - 0xCF */
a77ab5ea 183 0, 0, 0, ImplicitOps | Stack, 0, 0, 0, 0,
6aa8b732
AK		 184 /* 0xD0 - 0xD7 */
185 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
186 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
187 0, 0, 0, 0,
188 /* 0xD8 - 0xDF */
189 0, 0, 0, 0, 0, 0, 0, 0,
098c937b 190 /* 0xE0 - 0xE7 */
a6a3034c
MG		 191 0, 0, 0, 0,
192 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
193 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
098c937b 194 /* 0xE8 - 0xEF */
954cd36f 195 ImplicitOps | Stack, SrcImm | ImplicitOps,
782b877c 196 SrcImm | Src2Imm16, SrcImmByte | ImplicitOps,
a6a3034c
MG		 197 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
198 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
6aa8b732
AK		 199 /* 0xF0 - 0xF7 */
200 0, 0, 0, 0,
7d858a19 201 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 202 /* 0xF8 - 0xFF */
b284be57 203 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fb4616f4 204 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
6aa8b732
AK		 205};
206
45ed60b3 207static u32 twobyte_table[256] = {
6aa8b732 208 /* 0x00 - 0x0F */
d95058a1 209 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
651a3e29 210 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 211 /* 0x10 - 0x1F */
212 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
213 /* 0x20 - 0x2F */
214 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
215 0, 0, 0, 0, 0, 0, 0, 0,
216 /* 0x30 - 0x3F */
35f3f286 217 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 218 /* 0x40 - 0x47 */
219 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
220 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
221 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
222 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
223 /* 0x48 - 0x4F */
224 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
225 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
226 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
227 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
228 /* 0x50 - 0x5F */
229 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
230 /* 0x60 - 0x6F */
231 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
232 /* 0x70 - 0x7F */
233 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
234 /* 0x80 - 0x8F */
bbe9abbd
NK		 235 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
236 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
237 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
238 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 239 /* 0x90 - 0x9F */
240 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
241 /* 0xA0 - 0xA7 */
9bf8ea42
GT		 242 0, 0, 0, DstMem | SrcReg | ModRM | BitOp,
243 DstMem | SrcReg | Src2ImmByte | ModRM,
244 DstMem | SrcReg | Src2CL | ModRM, 0, 0,
6aa8b732 245 /* 0xA8 - 0xAF */
9bf8ea42
GT		 246 0, 0, 0, DstMem | SrcReg | ModRM | BitOp,
247 DstMem | SrcReg | Src2ImmByte | ModRM,
248 DstMem | SrcReg | Src2CL | ModRM,
249 ModRM, 0,
6aa8b732
AK		 250 /* 0xB0 - 0xB7 */
251 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 252 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 253 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
254 DstReg | SrcMem16 | ModRM | Mov,
255 /* 0xB8 - 0xBF */
038e51de 256 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 257 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
258 DstReg | SrcMem16 | ModRM | Mov,
259 /* 0xC0 - 0xCF */
a012e65a
SY		 260 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
261 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 262 /* 0xD0 - 0xDF */
263 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
264 /* 0xE0 - 0xEF */
265 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
266 /* 0xF0 - 0xFF */
267 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
268};
269
45ed60b3 270static u32 group_table[] = {
1d6ad207
AK		 271 [Group1_80*8] =
272 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
273 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
274 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
275 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
276 [Group1_81*8] =
277 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
278 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
279 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
280 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
281 [Group1_82*8] =
282 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
283 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
284 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
285 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
286 [Group1_83*8] =
287 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
288 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
289 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
290 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 291 [Group1A*8] =
292 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 293 [Group3_Byte*8] =
294 ByteOp | SrcImm | DstMem | ModRM, 0,
295 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
296 0, 0, 0, 0,
297 [Group3*8] =
41afa025 298 DstMem | SrcImm | ModRM, 0,
6eb06cb2 299 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
7d858a19 300 0, 0, 0, 0,
fd60754e
AK		 301 [Group4*8] =
302 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
303 0, 0, 0, 0, 0, 0,
304 [Group5*8] =
d19292e4
MG		 305 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
306 SrcMem | ModRM | Stack, 0,
ef46f18e 307 SrcMem | ModRM | Stack, 0, SrcMem | ModRM | Stack, 0,
d95058a1
AK		 308 [Group7*8] =
309 0, 0, ModRM | SrcMem, ModRM | SrcMem,
16286d08
AK		 310 SrcNone | ModRM | DstMem | Mov, 0,
311 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
e09d082c
AK		 312};
313
45ed60b3 314static u32 group2_table[] = {
d95058a1 315 [Group7*8] =
fbce554e 316 SrcNone | ModRM, 0, 0, SrcNone | ModRM,
16286d08
AK		 317 SrcNone | ModRM | DstMem | Mov, 0,
318 SrcMem16 | ModRM | Mov, 0,
e09d082c
AK		 319};
320
6aa8b732
AK		 321/* EFLAGS bit definitions. */
322#define EFLG_OF (1<<11)
323#define EFLG_DF (1<<10)
324#define EFLG_SF (1<<7)
325#define EFLG_ZF (1<<6)
326#define EFLG_AF (1<<4)
327#define EFLG_PF (1<<2)
328#define EFLG_CF (1<<0)
329
330/*
331 * Instruction emulation:
332 * Most instructions are emulated directly via a fragment of inline assembly
333 * code. This allows us to save/restore EFLAGS and thus very easily pick up
334 * any modified flags.
335 */
336
05b3e0c2 337#if defined(CONFIG_X86_64)
6aa8b732
AK		 338#define _LO32 "k" /* force 32-bit operand */
339#define _STK "%%rsp" /* stack pointer */
340#elif defined(__i386__)
341#define _LO32 "" /* force 32-bit operand */
342#define _STK "%%esp" /* stack pointer */
343#endif
344
345/*
346 * These EFLAGS bits are restored from saved value during emulation, and
347 * any changes are written back to the saved value after emulation.
348 */
349#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
350
351/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 352#define _PRE_EFLAGS(_sav, _msk, _tmp) \
353 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
354 "movl %"_sav",%"_LO32 _tmp"; " \
355 "push %"_tmp"; " \
356 "push %"_tmp"; " \
357 "movl %"_msk",%"_LO32 _tmp"; " \
358 "andl %"_LO32 _tmp",("_STK"); " \
359 "pushf; " \
360 "notl %"_LO32 _tmp"; " \
361 "andl %"_LO32 _tmp",("_STK"); " \
362 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
363 "pop %"_tmp"; " \
364 "orl %"_LO32 _tmp",("_STK"); " \
365 "popf; " \
366 "pop %"_sav"; "
6aa8b732
AK		 367
368/* After executing instruction: write-back necessary bits in EFLAGS. */
369#define _POST_EFLAGS(_sav, _msk, _tmp) \
370 /* _sav |= EFLAGS & _msk; */ \
371 "pushf; " \
372 "pop %"_tmp"; " \
373 "andl %"_msk",%"_LO32 _tmp"; " \
374 "orl %"_LO32 _tmp",%"_sav"; "
375
dda96d8f
AK		 376#ifdef CONFIG_X86_64
377#define ON64(x) x
378#else
379#define ON64(x)
380#endif
381
6b7ad61f
AK		 382#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
383 do { \
384 __asm__ __volatile__ ( \
385 _PRE_EFLAGS("0", "4", "2") \
386 _op _suffix " %"_x"3,%1; " \
387 _POST_EFLAGS("0", "4", "2") \
388 : "=m" (_eflags), "=m" ((_dst).val), \
389 "=&r" (_tmp) \
390 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 391 } while (0)
6b7ad61f
AK		 392
393
6aa8b732
AK		 394/* Raw emulation: instruction has two explicit operands. */
395#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 396 do { \
397 unsigned long _tmp; \
398 \
399 switch ((_dst).bytes) { \
400 case 2: \
401 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
402 break; \
403 case 4: \
404 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
405 break; \
406 case 8: \
407 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
408 break; \
409 } \
6aa8b732
AK		 410 } while (0)
411
412#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
413 do { \
6b7ad61f 414 unsigned long _tmp; \
d77c26fc 415 switch ((_dst).bytes) { \
6aa8b732 416 case 1: \
6b7ad61f 417 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 418 break; \
419 default: \
420 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
421 _wx, _wy, _lx, _ly, _qx, _qy); \
422 break; \
423 } \
424 } while (0)
425
426/* Source operand is byte-sized and may be restricted to just %cl. */
427#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
428 __emulate_2op(_op, _src, _dst, _eflags, \
429 "b", "c", "b", "c", "b", "c", "b", "c")
430
431/* Source operand is byte, word, long or quad sized. */
432#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
433 __emulate_2op(_op, _src, _dst, _eflags, \
434 "b", "q", "w", "r", _LO32, "r", "", "r")
435
436/* Source operand is word, long or quad sized. */
437#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
438 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
439 "w", "r", _LO32, "r", "", "r")
440
d175226a
GT		 441/* Instruction has three operands and one operand is stored in ECX register */
442#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
443 do { \
444 unsigned long _tmp; \
445 _type _clv = (_cl).val; \
446 _type _srcv = (_src).val; \
447 _type _dstv = (_dst).val; \
448 \
449 __asm__ __volatile__ ( \
450 _PRE_EFLAGS("0", "5", "2") \
451 _op _suffix " %4,%1 \n" \
452 _POST_EFLAGS("0", "5", "2") \
453 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
454 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
455 ); \
456 \
457 (_cl).val = (unsigned long) _clv; \
458 (_src).val = (unsigned long) _srcv; \
459 (_dst).val = (unsigned long) _dstv; \
460 } while (0)
461
462#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
463 do { \
464 switch ((_dst).bytes) { \
465 case 2: \
466 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
467 "w", unsigned short); \
468 break; \
469 case 4: \
470 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
471 "l", unsigned int); \
472 break; \
473 case 8: \
474 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
475 "q", unsigned long)); \
476 break; \
477 } \
478 } while (0)
479
dda96d8f 480#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 481 do { \
482 unsigned long _tmp; \
483 \
dda96d8f
AK		 484 __asm__ __volatile__ ( \
485 _PRE_EFLAGS("0", "3", "2") \
486 _op _suffix " %1; " \
487 _POST_EFLAGS("0", "3", "2") \
488 : "=m" (_eflags), "+m" ((_dst).val), \
489 "=&r" (_tmp) \
490 : "i" (EFLAGS_MASK)); \
491 } while (0)
492
493/* Instruction has only one explicit operand (no source operand). */
494#define emulate_1op(_op, _dst, _eflags) \
495 do { \
d77c26fc 496 switch ((_dst).bytes) { \
dda96d8f
AK		 497 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
498 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
499 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
500 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 501 } \
502 } while (0)
503
6aa8b732
AK		 504/* Fetch next part of the instruction being emulated. */
505#define insn_fetch(_type, _size, _eip) \
506({ unsigned long _x; \
62266869 507 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
d77c26fc 508 if (rc != 0) \
6aa8b732
AK		 509 goto done; \
510 (_eip) += (_size); \
511 (_type)_x; \
512})
513
ddcb2885
HH		 514static inline unsigned long ad_mask(struct decode_cache *c)
515{
516 return (1UL << (c->ad_bytes << 3)) - 1;
517}
518
6aa8b732 519/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 520static inline unsigned long
521address_mask(struct decode_cache *c, unsigned long reg)
522{
523 if (c->ad_bytes == sizeof(unsigned long))
524 return reg;
525 else
526 return reg & ad_mask(c);
527}
528
529static inline unsigned long
530register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
531{
532 return base + address_mask(c, reg);
533}
534
7a957275
HH		 535static inline void
536register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
537{
538 if (c->ad_bytes == sizeof(unsigned long))
539 *reg += inc;
540 else
541 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
542}
6aa8b732 543
7a957275
HH		 544static inline void jmp_rel(struct decode_cache *c, int rel)
545{
546 register_address_increment(c, &c->eip, rel);
547}
098c937b 548
7a5b56df
AK		 549static void set_seg_override(struct decode_cache *c, int seg)
550{
551 c->has_seg_override = true;
552 c->seg_override = seg;
553}
554
555static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
556{
557 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
558 return 0;
559
560 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
561}
562
563static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
564 struct decode_cache *c)
565{
566 if (!c->has_seg_override)
567 return 0;
568
569 return seg_base(ctxt, c->seg_override);
570}
571
572static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
573{
574 return seg_base(ctxt, VCPU_SREG_ES);
575}
576
577static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
578{
579 return seg_base(ctxt, VCPU_SREG_SS);
580}
581
62266869
AK		 582static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
583 struct x86_emulate_ops *ops,
584 unsigned long linear, u8 *dest)
585{
586 struct fetch_cache *fc = &ctxt->decode.fetch;
587 int rc;
588 int size;
589
590 if (linear < fc->start || linear >= fc->end) {
591 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
592 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
593 if (rc)
594 return rc;
595 fc->start = linear;
596 fc->end = linear + size;
597 }
598 *dest = fc->data[linear - fc->start];
599 return 0;
600}
601
602static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
603 struct x86_emulate_ops *ops,
604 unsigned long eip, void *dest, unsigned size)
605{
606 int rc = 0;
607
608 eip += ctxt->cs_base;
609 while (size--) {
610 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
611 if (rc)
612 return rc;
613 }
614 return 0;
615}
616
1e3c5cb0
RR		 617/*
618 * Given the 'reg' portion of a ModRM byte, and a register block, return a
619 * pointer into the block that addresses the relevant register.
620 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
621 */
622static void *decode_register(u8 modrm_reg, unsigned long *regs,
623 int highbyte_regs)
6aa8b732
AK		 624{
625 void *p;
626
627 p = &regs[modrm_reg];
628 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
629 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
630 return p;
631}
632
633static int read_descriptor(struct x86_emulate_ctxt *ctxt,
634 struct x86_emulate_ops *ops,
635 void *ptr,
636 u16 *size, unsigned long *address, int op_bytes)
637{
638 int rc;
639
640 if (op_bytes == 2)
641 op_bytes = 3;
642 *address = 0;
cebff02b
LV		 643 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
644 ctxt->vcpu);
6aa8b732
AK		 645 if (rc)
646 return rc;
cebff02b
LV		 647 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
648 ctxt->vcpu);
6aa8b732
AK		 649 return rc;
650}
651
bbe9abbd
NK		 652static int test_cc(unsigned int condition, unsigned int flags)
653{
654 int rc = 0;
655
656 switch ((condition & 15) >> 1) {
657 case 0: /* o */
658 rc |= (flags & EFLG_OF);
659 break;
660 case 1: /* b/c/nae */
661 rc |= (flags & EFLG_CF);
662 break;
663 case 2: /* z/e */
664 rc |= (flags & EFLG_ZF);
665 break;
666 case 3: /* be/na */
667 rc |= (flags & (EFLG_CF|EFLG_ZF));
668 break;
669 case 4: /* s */
670 rc |= (flags & EFLG_SF);
671 break;
672 case 5: /* p/pe */
673 rc |= (flags & EFLG_PF);
674 break;
675 case 7: /* le/ng */
676 rc |= (flags & EFLG_ZF);
677 /* fall through */
678 case 6: /* l/nge */
679 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
680 break;
681 }
682
683 /* Odd condition identifiers (lsb == 1) have inverted sense. */
684 return (!!rc ^ (condition & 1));
685}
686
3c118e24
AK		 687static void decode_register_operand(struct operand *op,
688 struct decode_cache *c,
3c118e24
AK		 689 int inhibit_bytereg)
690{
33615aa9 691 unsigned reg = c->modrm_reg;
9f1ef3f8 692 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 693
694 if (!(c->d & ModRM))
695 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 696 op->type = OP_REG;
697 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 698 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 699 op->val = *(u8 *)op->ptr;
700 op->bytes = 1;
701 } else {
33615aa9 702 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 703 op->bytes = c->op_bytes;
704 switch (op->bytes) {
705 case 2:
706 op->val = *(u16 *)op->ptr;
707 break;
708 case 4:
709 op->val = *(u32 *)op->ptr;
710 break;
711 case 8:
712 op->val = *(u64 *) op->ptr;
713 break;
714 }
715 }
716 op->orig_val = op->val;
717}
718
1c73ef66
AK		 719static int decode_modrm(struct x86_emulate_ctxt *ctxt,
720 struct x86_emulate_ops *ops)
721{
722 struct decode_cache *c = &ctxt->decode;
723 u8 sib;
f5b4edcd 724 int index_reg = 0, base_reg = 0, scale;
1c73ef66
AK		 725 int rc = 0;
726
727 if (c->rex_prefix) {
728 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
729 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
730 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
731 }
732
733 c->modrm = insn_fetch(u8, 1, c->eip);
734 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
735 c->modrm_reg |= (c->modrm & 0x38) >> 3;
736 c->modrm_rm |= (c->modrm & 0x07);
737 c->modrm_ea = 0;
738 c->use_modrm_ea = 1;
739
740 if (c->modrm_mod == 3) {
107d6d2e
AK		 741 c->modrm_ptr = decode_register(c->modrm_rm,
742 c->regs, c->d & ByteOp);
743 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 744 return rc;
745 }
746
747 if (c->ad_bytes == 2) {
748 unsigned bx = c->regs[VCPU_REGS_RBX];
749 unsigned bp = c->regs[VCPU_REGS_RBP];
750 unsigned si = c->regs[VCPU_REGS_RSI];
751 unsigned di = c->regs[VCPU_REGS_RDI];
752
753 /* 16-bit ModR/M decode. */
754 switch (c->modrm_mod) {
755 case 0:
756 if (c->modrm_rm == 6)
757 c->modrm_ea += insn_fetch(u16, 2, c->eip);
758 break;
759 case 1:
760 c->modrm_ea += insn_fetch(s8, 1, c->eip);
761 break;
762 case 2:
763 c->modrm_ea += insn_fetch(u16, 2, c->eip);
764 break;
765 }
766 switch (c->modrm_rm) {
767 case 0:
768 c->modrm_ea += bx + si;
769 break;
770 case 1:
771 c->modrm_ea += bx + di;
772 break;
773 case 2:
774 c->modrm_ea += bp + si;
775 break;
776 case 3:
777 c->modrm_ea += bp + di;
778 break;
779 case 4:
780 c->modrm_ea += si;
781 break;
782 case 5:
783 c->modrm_ea += di;
784 break;
785 case 6:
786 if (c->modrm_mod != 0)
787 c->modrm_ea += bp;
788 break;
789 case 7:
790 c->modrm_ea += bx;
791 break;
792 }
793 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
794 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 795 if (!c->has_seg_override)
796 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 797 c->modrm_ea = (u16)c->modrm_ea;
798 } else {
799 /* 32/64-bit ModR/M decode. */
84411d85 800 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 801 sib = insn_fetch(u8, 1, c->eip);
802 index_reg |= (sib >> 3) & 7;
803 base_reg |= sib & 7;
804 scale = sib >> 6;
805
dc71d0f1
AK		 806 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
807 c->modrm_ea += insn_fetch(s32, 4, c->eip);
808 else
1c73ef66 809 c->modrm_ea += c->regs[base_reg];
dc71d0f1 810 if (index_reg != 4)
1c73ef66 811 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 812 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
813 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 814 c->rip_relative = 1;
84411d85 815 } else
1c73ef66 816 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 817 switch (c->modrm_mod) {
818 case 0:
819 if (c->modrm_rm == 5)
820 c->modrm_ea += insn_fetch(s32, 4, c->eip);
821 break;
822 case 1:
823 c->modrm_ea += insn_fetch(s8, 1, c->eip);
824 break;
825 case 2:
826 c->modrm_ea += insn_fetch(s32, 4, c->eip);
827 break;
828 }
829 }
1c73ef66
AK		 830done:
831 return rc;
832}
833
834static int decode_abs(struct x86_emulate_ctxt *ctxt,
835 struct x86_emulate_ops *ops)
836{
837 struct decode_cache *c = &ctxt->decode;
838 int rc = 0;
839
840 switch (c->ad_bytes) {
841 case 2:
842 c->modrm_ea = insn_fetch(u16, 2, c->eip);
843 break;
844 case 4:
845 c->modrm_ea = insn_fetch(u32, 4, c->eip);
846 break;
847 case 8:
848 c->modrm_ea = insn_fetch(u64, 8, c->eip);
849 break;
850 }
851done:
852 return rc;
853}
854
6aa8b732 855int
8b4caf66 856x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 857{
e4e03ded 858 struct decode_cache *c = &ctxt->decode;
6aa8b732 859 int rc = 0;
6aa8b732 860 int mode = ctxt->mode;
e09d082c 861 int def_op_bytes, def_ad_bytes, group;
6aa8b732
AK		 862
863 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 864
e4e03ded 865 memset(c, 0, sizeof(struct decode_cache));
5fdbf976 866 c->eip = kvm_rip_read(ctxt->vcpu);
7a5b56df 867 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
ad312c7c 868 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 869
870 switch (mode) {
871 case X86EMUL_MODE_REAL:
872 case X86EMUL_MODE_PROT16:
f21b8bf4 873 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 874 break;
875 case X86EMUL_MODE_PROT32:
f21b8bf4 876 def_op_bytes = def_ad_bytes = 4;
6aa8b732 877 break;
05b3e0c2 878#ifdef CONFIG_X86_64
6aa8b732 879 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 880 def_op_bytes = 4;
881 def_ad_bytes = 8;
6aa8b732
AK		 882 break;
883#endif
884 default:
885 return -1;
886 }
887
f21b8bf4
AK		 888 c->op_bytes = def_op_bytes;
889 c->ad_bytes = def_ad_bytes;
890
6aa8b732 891 /* Legacy prefixes. */
b4c6abfe 892 for (;;) {
e4e03ded 893 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 894 case 0x66: /* operand-size override */
f21b8bf4
AK		 895 /* switch between 2/4 bytes */
896 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 897 break;
898 case 0x67: /* address-size override */
899 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 900 /* switch between 4/8 bytes */
f21b8bf4 901 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 902 else
e4e03ded 903 /* switch between 2/4 bytes */
f21b8bf4 904 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 905 break;
7a5b56df 906 case 0x26: /* ES override */
6aa8b732 907 case 0x2e: /* CS override */
7a5b56df 908 case 0x36: /* SS override */
6aa8b732 909 case 0x3e: /* DS override */
7a5b56df 910 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 911 break;
912 case 0x64: /* FS override */
6aa8b732 913 case 0x65: /* GS override */
7a5b56df 914 set_seg_override(c, c->b & 7);
6aa8b732 915 break;
b4c6abfe
LV		 916 case 0x40 ... 0x4f: /* REX */
917 if (mode != X86EMUL_MODE_PROT64)
918 goto done_prefixes;
33615aa9 919 c->rex_prefix = c->b;
b4c6abfe 920 continue;
6aa8b732 921 case 0xf0: /* LOCK */
e4e03ded 922 c->lock_prefix = 1;
6aa8b732 923 break;
ae6200ba 924 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 925 c->rep_prefix = REPNE_PREFIX;
926 break;
6aa8b732 927 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 928 c->rep_prefix = REPE_PREFIX;
6aa8b732 929 break;
6aa8b732
AK		 930 default:
931 goto done_prefixes;
932 }
b4c6abfe
LV		 933
934 /* Any legacy prefix after a REX prefix nullifies its effect. */
935
33615aa9 936 c->rex_prefix = 0;
6aa8b732
AK		 937 }
938
939done_prefixes:
940
941 /* REX prefix. */
1c73ef66 942 if (c->rex_prefix)
33615aa9 943 if (c->rex_prefix & 8)
e4e03ded 944 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 945
946 /* Opcode byte(s). */
e4e03ded
LV		 947 c->d = opcode_table[c->b];
948 if (c->d == 0) {
6aa8b732 949 /* Two-byte opcode? */
e4e03ded
LV		 950 if (c->b == 0x0f) {
951 c->twobyte = 1;
952 c->b = insn_fetch(u8, 1, c->eip);
953 c->d = twobyte_table[c->b];
6aa8b732 954 }
e09d082c 955 }
6aa8b732 956
e09d082c
AK		 957 if (c->d & Group) {
958 group = c->d & GroupMask;
959 c->modrm = insn_fetch(u8, 1, c->eip);
960 --c->eip;
961
962 group = (group << 3) + ((c->modrm >> 3) & 7);
963 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
964 c->d = group2_table[group];
965 else
966 c->d = group_table[group];
967 }
968
969 /* Unrecognised? */
970 if (c->d == 0) {
971 DPRINTF("Cannot emulate %02x\n", c->b);
972 return -1;
6aa8b732
AK		 973 }
974
6e3d5dfb
AK		 975 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
976 c->op_bytes = 8;
977
6aa8b732 978 /* ModRM and SIB bytes. */
1c73ef66
AK		 979 if (c->d & ModRM)
980 rc = decode_modrm(ctxt, ops);
981 else if (c->d & MemAbs)
982 rc = decode_abs(ctxt, ops);
983 if (rc)
984 goto done;
6aa8b732 985
7a5b56df
AK		 986 if (!c->has_seg_override)
987 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 988
7a5b56df
AK		 989 if (!(!c->twobyte && c->b == 0x8d))
990 c->modrm_ea += seg_override_base(ctxt, c);
c7e75a3d
AK		 991
992 if (c->ad_bytes != 8)
993 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 994 /*
995 * Decode and fetch the source operand: register, memory
996 * or immediate.
997 */
e4e03ded 998 switch (c->d & SrcMask) {
6aa8b732
AK		 999 case SrcNone:
1000 break;
1001 case SrcReg:
9f1ef3f8 1002 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 1003 break;
1004 case SrcMem16:
e4e03ded 1005 c->src.bytes = 2;
6aa8b732
AK		 1006 goto srcmem_common;
1007 case SrcMem32:
e4e03ded 1008 c->src.bytes = 4;
6aa8b732
AK		 1009 goto srcmem_common;
1010 case SrcMem:
e4e03ded
LV		 1011 c->src.bytes = (c->d & ByteOp) ? 1 :
1012 c->op_bytes;
b85b9ee9 1013 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1014 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1015 break;
d77c26fc 1016 srcmem_common:
4e62417b
AJ		 1017 /*
1018 * For instructions with a ModR/M byte, switch to register
1019 * access if Mod = 3.
1020 */
e4e03ded
LV		 1021 if ((c->d & ModRM) && c->modrm_mod == 3) {
1022 c->src.type = OP_REG;
66b85505 1023 c->src.val = c->modrm_val;
107d6d2e 1024 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1025 break;
1026 }
e4e03ded 1027 c->src.type = OP_MEM;
6aa8b732
AK		 1028 break;
1029 case SrcImm:
e4e03ded
LV		 1030 c->src.type = OP_IMM;
1031 c->src.ptr = (unsigned long *)c->eip;
1032 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1033 if (c->src.bytes == 8)
1034 c->src.bytes = 4;
6aa8b732 1035 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1036 switch (c->src.bytes) {
6aa8b732 1037 case 1:
e4e03ded 1038 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1039 break;
1040 case 2:
e4e03ded 1041 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1042 break;
1043 case 4:
e4e03ded 1044 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1045 break;
1046 }
1047 break;
1048 case SrcImmByte:
e4e03ded
LV		 1049 c->src.type = OP_IMM;
1050 c->src.ptr = (unsigned long *)c->eip;
1051 c->src.bytes = 1;
1052 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732 1053 break;
bfcadf83
GT		 1054 case SrcOne:
1055 c->src.bytes = 1;
1056 c->src.val = 1;
1057 break;
6aa8b732
AK		 1058 }
1059
0dc8d10f
GT		 1060 /*
1061 * Decode and fetch the second source operand: register, memory
1062 * or immediate.
1063 */
1064 switch (c->d & Src2Mask) {
1065 case Src2None:
1066 break;
1067 case Src2CL:
1068 c->src2.bytes = 1;
1069 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1070 break;
1071 case Src2ImmByte:
1072 c->src2.type = OP_IMM;
1073 c->src2.ptr = (unsigned long *)c->eip;
1074 c->src2.bytes = 1;
1075 c->src2.val = insn_fetch(u8, 1, c->eip);
1076 break;
a5f868bd
GN		 1077 case Src2Imm16:
1078 c->src2.type = OP_IMM;
1079 c->src2.ptr = (unsigned long *)c->eip;
1080 c->src2.bytes = 2;
1081 c->src2.val = insn_fetch(u16, 2, c->eip);
1082 break;
0dc8d10f
GT		 1083 case Src2One:
1084 c->src2.bytes = 1;
1085 c->src2.val = 1;
1086 break;
1087 }
1088
038e51de 1089 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1090 switch (c->d & DstMask) {
038e51de
AK		 1091 case ImplicitOps:
1092 /* Special instructions do their own operand decoding. */
8b4caf66 1093 return 0;
038e51de 1094 case DstReg:
9f1ef3f8 1095 decode_register_operand(&c->dst, c,
3c118e24 1096 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1097 break;
1098 case DstMem:
e4e03ded 1099 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1100 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1101 c->dst.type = OP_REG;
66b85505 1102 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1103 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1104 break;
1105 }
8b4caf66
LV		 1106 c->dst.type = OP_MEM;
1107 break;
9c9fddd0
GT		 1108 case DstAcc:
1109 c->dst.type = OP_REG;
1110 c->dst.bytes = c->op_bytes;
1111 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1112 switch (c->op_bytes) {
1113 case 1:
1114 c->dst.val = *(u8 *)c->dst.ptr;
1115 break;
1116 case 2:
1117 c->dst.val = *(u16 *)c->dst.ptr;
1118 break;
1119 case 4:
1120 c->dst.val = *(u32 *)c->dst.ptr;
1121 break;
1122 }
1123 c->dst.orig_val = c->dst.val;
1124 break;
8b4caf66
LV		 1125 }
1126
f5b4edcd
AK		 1127 if (c->rip_relative)
1128 c->modrm_ea += c->eip;
1129
8b4caf66
LV		 1130done:
1131 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1132}
1133
8cdbd2c9
LV		 1134static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1135{
1136 struct decode_cache *c = &ctxt->decode;
1137
1138 c->dst.type = OP_MEM;
1139 c->dst.bytes = c->op_bytes;
1140 c->dst.val = c->src.val;
7a957275 1141 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
7a5b56df 1142 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1143 c->regs[VCPU_REGS_RSP]);
1144}
1145
faa5a3ae 1146static int emulate_pop(struct x86_emulate_ctxt *ctxt,
350f69dc
AK		 1147 struct x86_emulate_ops *ops,
1148 void *dest, int len)
8cdbd2c9
LV		 1149{
1150 struct decode_cache *c = &ctxt->decode;
1151 int rc;
1152
781d0edc
AK		 1153 rc = ops->read_emulated(register_address(c, ss_base(ctxt),
1154 c->regs[VCPU_REGS_RSP]),
350f69dc 1155 dest, len, ctxt->vcpu);
8cdbd2c9
LV		 1156 if (rc != 0)
1157 return rc;
1158
350f69dc 1159 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
faa5a3ae
AK		 1160 return rc;
1161}
8cdbd2c9 1162
faa5a3ae
AK		 1163static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1164 struct x86_emulate_ops *ops)
1165{
1166 struct decode_cache *c = &ctxt->decode;
1167 int rc;
1168
350f69dc 1169 rc = emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
faa5a3ae
AK		 1170 if (rc != 0)
1171 return rc;
8cdbd2c9
LV		 1172 return 0;
1173}
1174
05f086f8 1175static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1176{
05f086f8 1177 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1178 switch (c->modrm_reg) {
1179 case 0: /* rol */
05f086f8 1180 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1181 break;
1182 case 1: /* ror */
05f086f8 1183 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1184 break;
1185 case 2: /* rcl */
05f086f8 1186 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1187 break;
1188 case 3: /* rcr */
05f086f8 1189 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1190 break;
1191 case 4: /* sal/shl */
1192 case 6: /* sal/shl */
05f086f8 1193 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1194 break;
1195 case 5: /* shr */
05f086f8 1196 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1197 break;
1198 case 7: /* sar */
05f086f8 1199 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1200 break;
1201 }
1202}
1203
1204static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1205 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1206{
1207 struct decode_cache *c = &ctxt->decode;
1208 int rc = 0;
1209
1210 switch (c->modrm_reg) {
1211 case 0 ... 1: /* test */
05f086f8 1212 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1213 break;
1214 case 2: /* not */
1215 c->dst.val = ~c->dst.val;
1216 break;
1217 case 3: /* neg */
05f086f8 1218 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1219 break;
1220 default:
1221 DPRINTF("Cannot emulate %02x\n", c->b);
1222 rc = X86EMUL_UNHANDLEABLE;
1223 break;
1224 }
8cdbd2c9
LV		 1225 return rc;
1226}
1227
1228static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1229 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1230{
1231 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1232
1233 switch (c->modrm_reg) {
1234 case 0: /* inc */
05f086f8 1235 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1236 break;
1237 case 1: /* dec */
05f086f8 1238 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1239 break;
d19292e4
MG		 1240 case 2: /* call near abs */ {
1241 long int old_eip;
1242 old_eip = c->eip;
1243 c->eip = c->src.val;
1244 c->src.val = old_eip;
1245 emulate_push(ctxt);
1246 break;
1247 }
8cdbd2c9 1248 case 4: /* jmp abs */
fd60754e 1249 c->eip = c->src.val;
8cdbd2c9
LV		 1250 break;
1251 case 6: /* push */
fd60754e 1252 emulate_push(ctxt);
8cdbd2c9 1253 break;
8cdbd2c9
LV		 1254 }
1255 return 0;
1256}
1257
1258static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1259 struct x86_emulate_ops *ops,
e8d8d7fe 1260 unsigned long memop)
8cdbd2c9
LV		 1261{
1262 struct decode_cache *c = &ctxt->decode;
1263 u64 old, new;
1264 int rc;
1265
e8d8d7fe 1266 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
8cdbd2c9
LV		 1267 if (rc != 0)
1268 return rc;
1269
1270 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1271 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1272
1273 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1274 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1275 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1276
1277 } else {
1278 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1279 (u32) c->regs[VCPU_REGS_RBX];
1280
e8d8d7fe 1281 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
8cdbd2c9
LV		 1282 if (rc != 0)
1283 return rc;
05f086f8 1284 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1285 }
1286 return 0;
1287}
1288
a77ab5ea
AK		 1289static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1290 struct x86_emulate_ops *ops)
1291{
1292 struct decode_cache *c = &ctxt->decode;
1293 int rc;
1294 unsigned long cs;
1295
1296 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1297 if (rc)
1298 return rc;
1299 if (c->op_bytes == 4)
1300 c->eip = (u32)c->eip;
1301 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1302 if (rc)
1303 return rc;
1304 rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)cs, 1, VCPU_SREG_CS);
1305 return rc;
1306}
1307
8cdbd2c9
LV		 1308static inline int writeback(struct x86_emulate_ctxt *ctxt,
1309 struct x86_emulate_ops *ops)
1310{
1311 int rc;
1312 struct decode_cache *c = &ctxt->decode;
1313
1314 switch (c->dst.type) {
1315 case OP_REG:
1316 /* The 4-byte case *is* correct:
1317 * in 64-bit mode we zero-extend.
1318 */
1319 switch (c->dst.bytes) {
1320 case 1:
1321 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1322 break;
1323 case 2:
1324 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1325 break;
1326 case 4:
1327 *c->dst.ptr = (u32)c->dst.val;
1328 break; /* 64b: zero-ext */
1329 case 8:
1330 *c->dst.ptr = c->dst.val;
1331 break;
1332 }
1333 break;
1334 case OP_MEM:
1335 if (c->lock_prefix)
1336 rc = ops->cmpxchg_emulated(
1337 (unsigned long)c->dst.ptr,
1338 &c->dst.orig_val,
1339 &c->dst.val,
1340 c->dst.bytes,
1341 ctxt->vcpu);
1342 else
1343 rc = ops->write_emulated(
1344 (unsigned long)c->dst.ptr,
1345 &c->dst.val,
1346 c->dst.bytes,
1347 ctxt->vcpu);
1348 if (rc != 0)
1349 return rc;
a01af5ec
LV		 1350 break;
1351 case OP_NONE:
1352 /* no writeback */
1353 break;
8cdbd2c9
LV		 1354 default:
1355 break;
1356 }
1357 return 0;
1358}
1359
8b4caf66 1360int
1be3aa47 1361x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 1362{
e8d8d7fe 1363 unsigned long memop = 0;
8b4caf66 1364 u64 msr_data;
3427318f 1365 unsigned long saved_eip = 0;
8b4caf66 1366 struct decode_cache *c = &ctxt->decode;
a6a3034c
MG		 1367 unsigned int port;
1368 int io_dir_in;
1be3aa47 1369 int rc = 0;
8b4caf66 1370
3427318f
LV		 1371 /* Shadow copy of register state. Committed on successful emulation.
1372 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1373 * modify them.
1374 */
1375
ad312c7c 1376 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f
LV		 1377 saved_eip = c->eip;
1378
c7e75a3d 1379 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
e8d8d7fe 1380 memop = c->modrm_ea;
8b4caf66 1381
b9fa9d6b
AK		 1382 if (c->rep_prefix && (c->d & String)) {
1383 /* All REP prefixes have the same first termination condition */
1384 if (c->regs[VCPU_REGS_RCX] == 0) {
5fdbf976 1385 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1386 goto done;
1387 }
1388 /* The second termination condition only applies for REPE
1389 * and REPNE. Test if the repeat string operation prefix is
1390 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1391 * corresponding termination condition according to:
1392 * - if REPE/REPZ and ZF = 0 then done
1393 * - if REPNE/REPNZ and ZF = 1 then done
1394 */
1395 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1396 (c->b == 0xae) || (c->b == 0xaf)) {
1397 if ((c->rep_prefix == REPE_PREFIX) &&
1398 ((ctxt->eflags & EFLG_ZF) == 0)) {
5fdbf976 1399 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1400 goto done;
1401 }
1402 if ((c->rep_prefix == REPNE_PREFIX) &&
1403 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
5fdbf976 1404 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1405 goto done;
1406 }
1407 }
1408 c->regs[VCPU_REGS_RCX]--;
5fdbf976 1409 c->eip = kvm_rip_read(ctxt->vcpu);
b9fa9d6b
AK		 1410 }
1411
8b4caf66 1412 if (c->src.type == OP_MEM) {
e8d8d7fe 1413 c->src.ptr = (unsigned long *)memop;
8b4caf66 1414 c->src.val = 0;
d77c26fc
MD		 1415 rc = ops->read_emulated((unsigned long)c->src.ptr,
1416 &c->src.val,
1417 c->src.bytes,
1418 ctxt->vcpu);
1419 if (rc != 0)
8b4caf66
LV		 1420 goto done;
1421 c->src.orig_val = c->src.val;
1422 }
1423
1424 if ((c->d & DstMask) == ImplicitOps)
1425 goto special_insn;
1426
1427
1428 if (c->dst.type == OP_MEM) {
e8d8d7fe 1429 c->dst.ptr = (unsigned long *)memop;
8b4caf66
LV		 1430 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1431 c->dst.val = 0;
e4e03ded
LV		 1432 if (c->d & BitOp) {
1433 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1434
e4e03ded
LV		 1435 c->dst.ptr = (void *)c->dst.ptr +
1436 (c->src.val & mask) / 8;
038e51de 1437 }
e4e03ded
LV		 1438 if (!(c->d & Mov) &&
1439 /* optimisation - avoid slow emulated read */
1440 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1441 &c->dst.val,
1442 c->dst.bytes, ctxt->vcpu)) != 0))
038e51de 1443 goto done;
038e51de 1444 }
e4e03ded 1445 c->dst.orig_val = c->dst.val;
038e51de 1446
018a98db
AK		 1447special_insn:
1448
e4e03ded 1449 if (c->twobyte)
6aa8b732
AK		 1450 goto twobyte_insn;
1451
e4e03ded 1452 switch (c->b) {
6aa8b732
AK		 1453 case 0x00 ... 0x05:
1454 add: /* add */
05f086f8 1455 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1456 break;
1457 case 0x08 ... 0x0d:
1458 or: /* or */
05f086f8 1459 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1460 break;
1461 case 0x10 ... 0x15:
1462 adc: /* adc */
05f086f8 1463 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1464 break;
1465 case 0x18 ... 0x1d:
1466 sbb: /* sbb */
05f086f8 1467 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1468 break;
aa3a816b 1469 case 0x20 ... 0x25:
6aa8b732 1470 and: /* and */
05f086f8 1471 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1472 break;
1473 case 0x28 ... 0x2d:
1474 sub: /* sub */
05f086f8 1475 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1476 break;
1477 case 0x30 ... 0x35:
1478 xor: /* xor */
05f086f8 1479 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1480 break;
1481 case 0x38 ... 0x3d:
1482 cmp: /* cmp */
05f086f8 1483 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 1484 break;
33615aa9
AK		 1485 case 0x40 ... 0x47: /* inc r16/r32 */
1486 emulate_1op("inc", c->dst, ctxt->eflags);
1487 break;
1488 case 0x48 ... 0x4f: /* dec r16/r32 */
1489 emulate_1op("dec", c->dst, ctxt->eflags);
1490 break;
1491 case 0x50 ... 0x57: /* push reg */
2786b014 1492 emulate_push(ctxt);
33615aa9
AK		 1493 break;
1494 case 0x58 ... 0x5f: /* pop reg */
1495 pop_instruction:
350f69dc 1496 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
8a09b687 1497 if (rc != 0)
33615aa9 1498 goto done;
33615aa9 1499 break;
6aa8b732 1500 case 0x63: /* movsxd */
8b4caf66 1501 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1502 goto cannot_emulate;
e4e03ded 1503 c->dst.val = (s32) c->src.val;
6aa8b732 1504 break;
91ed7a0e 1505 case 0x68: /* push imm */
018a98db 1506 case 0x6a: /* push imm8 */
018a98db
AK		 1507 emulate_push(ctxt);
1508 break;
1509 case 0x6c: /* insb */
1510 case 0x6d: /* insw/insd */
1511 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1512 1,
1513 (c->d & ByteOp) ? 1 : c->op_bytes,
1514 c->rep_prefix ?
e4706772 1515 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1516 (ctxt->eflags & EFLG_DF),
7a5b56df 1517 register_address(c, es_base(ctxt),
018a98db
AK		 1518 c->regs[VCPU_REGS_RDI]),
1519 c->rep_prefix,
1520 c->regs[VCPU_REGS_RDX]) == 0) {
1521 c->eip = saved_eip;
1522 return -1;
1523 }
1524 return 0;
1525 case 0x6e: /* outsb */
1526 case 0x6f: /* outsw/outsd */
1527 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1528 0,
1529 (c->d & ByteOp) ? 1 : c->op_bytes,
1530 c->rep_prefix ?
e4706772 1531 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1532 (ctxt->eflags & EFLG_DF),
7a5b56df
AK		 1533 register_address(c,
1534 seg_override_base(ctxt, c),
018a98db
AK		 1535 c->regs[VCPU_REGS_RSI]),
1536 c->rep_prefix,
1537 c->regs[VCPU_REGS_RDX]) == 0) {
1538 c->eip = saved_eip;
1539 return -1;
1540 }
1541 return 0;
1542 case 0x70 ... 0x7f: /* jcc (short) */ {
1543 int rel = insn_fetch(s8, 1, c->eip);
1544
1545 if (test_cc(c->b, ctxt->eflags))
7a957275 1546 jmp_rel(c, rel);
018a98db
AK		 1547 break;
1548 }
6aa8b732 1549 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 1550 switch (c->modrm_reg) {
6aa8b732
AK		 1551 case 0:
1552 goto add;
1553 case 1:
1554 goto or;
1555 case 2:
1556 goto adc;
1557 case 3:
1558 goto sbb;
1559 case 4:
1560 goto and;
1561 case 5:
1562 goto sub;
1563 case 6:
1564 goto xor;
1565 case 7:
1566 goto cmp;
1567 }
1568 break;
1569 case 0x84 ... 0x85:
05f086f8 1570 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1571 break;
1572 case 0x86 ... 0x87: /* xchg */
b13354f8 1573 xchg:
6aa8b732 1574 /* Write back the register source. */
e4e03ded 1575 switch (c->dst.bytes) {
6aa8b732 1576 case 1:
e4e03ded 1577 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 1578 break;
1579 case 2:
e4e03ded 1580 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 1581 break;
1582 case 4:
e4e03ded 1583 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 1584 break; /* 64b reg: zero-extend */
1585 case 8:
e4e03ded 1586 *c->src.ptr = c->dst.val;
6aa8b732
AK		 1587 break;
1588 }
1589 /*
1590 * Write back the memory destination with implicit LOCK
1591 * prefix.
1592 */
e4e03ded
LV		 1593 c->dst.val = c->src.val;
1594 c->lock_prefix = 1;
6aa8b732 1595 break;
6aa8b732 1596 case 0x88 ... 0x8b: /* mov */
7de75248 1597 goto mov;
38d5bc6d
GT		 1598 case 0x8c: { /* mov r/m, sreg */
1599 struct kvm_segment segreg;
1600
1601 if (c->modrm_reg <= 5)
1602 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
1603 else {
1604 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
1605 c->modrm);
1606 goto cannot_emulate;
1607 }
1608 c->dst.val = segreg.selector;
1609 break;
1610 }
7e0b54b1 1611 case 0x8d: /* lea r16/r32, m */
f9b7aab3 1612 c->dst.val = c->modrm_ea;
7e0b54b1 1613 break;
4257198a
GT		 1614 case 0x8e: { /* mov seg, r/m16 */
1615 uint16_t sel;
1616 int type_bits;
1617 int err;
1618
1619 sel = c->src.val;
1620 if (c->modrm_reg <= 5) {
1621 type_bits = (c->modrm_reg == 1) ? 9 : 1;
1622 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
1623 type_bits, c->modrm_reg);
1624 } else {
1625 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
1626 c->modrm);
1627 goto cannot_emulate;
1628 }
1629
1630 if (err < 0)
1631 goto cannot_emulate;
1632
1633 c->dst.type = OP_NONE; /* Disable writeback. */
1634 break;
1635 }
6aa8b732 1636 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 1637 rc = emulate_grp1a(ctxt, ops);
1638 if (rc != 0)
6aa8b732 1639 goto done;
6aa8b732 1640 break;
b13354f8
MG		 1641 case 0x90: /* nop / xchg r8,rax */
1642 if (!(c->rex_prefix & 1)) { /* nop */
1643 c->dst.type = OP_NONE;
1644 break;
1645 }
1646 case 0x91 ... 0x97: /* xchg reg,rax */
1647 c->src.type = c->dst.type = OP_REG;
1648 c->src.bytes = c->dst.bytes = c->op_bytes;
1649 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
1650 c->src.val = *(c->src.ptr);
1651 goto xchg;
fd2a7608 1652 case 0x9c: /* pushf */
05f086f8 1653 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 1654 emulate_push(ctxt);
1655 break;
535eabcf 1656 case 0x9d: /* popf */
2b48cc75 1657 c->dst.type = OP_REG;
05f086f8 1658 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2b48cc75 1659 c->dst.bytes = c->op_bytes;
535eabcf 1660 goto pop_instruction;
018a98db
AK		 1661 case 0xa0 ... 0xa1: /* mov */
1662 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1663 c->dst.val = c->src.val;
1664 break;
1665 case 0xa2 ... 0xa3: /* mov */
1666 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1667 break;
6aa8b732 1668 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 1669 c->dst.type = OP_MEM;
1670 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1671 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1672 es_base(ctxt),
e4e03ded 1673 c->regs[VCPU_REGS_RDI]);
e4706772 1674 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 1675 seg_override_base(ctxt, c),
e4e03ded
LV		 1676 c->regs[VCPU_REGS_RSI]),
1677 &c->dst.val,
1678 c->dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1679 goto done;
7a957275 1680 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1681 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1682 : c->dst.bytes);
7a957275 1683 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1684 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1685 : c->dst.bytes);
6aa8b732
AK		 1686 break;
1687 case 0xa6 ... 0xa7: /* cmps */
d7e5117a
GT		 1688 c->src.type = OP_NONE; /* Disable writeback. */
1689 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1690 c->src.ptr = (unsigned long *)register_address(c,
7a5b56df 1691 seg_override_base(ctxt, c),
d7e5117a
GT		 1692 c->regs[VCPU_REGS_RSI]);
1693 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1694 &c->src.val,
1695 c->src.bytes,
1696 ctxt->vcpu)) != 0)
1697 goto done;
1698
1699 c->dst.type = OP_NONE; /* Disable writeback. */
1700 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1701 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1702 es_base(ctxt),
d7e5117a
GT		 1703 c->regs[VCPU_REGS_RDI]);
1704 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1705 &c->dst.val,
1706 c->dst.bytes,
1707 ctxt->vcpu)) != 0)
1708 goto done;
1709
1710 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1711
1712 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1713
7a957275 1714 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
d7e5117a
GT		 1715 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1716 : c->src.bytes);
7a957275 1717 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
d7e5117a
GT		 1718 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1719 : c->dst.bytes);
1720
1721 break;
6aa8b732 1722 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 1723 c->dst.type = OP_MEM;
1724 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1725 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1726 es_base(ctxt),
a7e6c88a 1727 c->regs[VCPU_REGS_RDI]);
e4e03ded 1728 c->dst.val = c->regs[VCPU_REGS_RAX];
7a957275 1729 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1730 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1731 : c->dst.bytes);
6aa8b732
AK		 1732 break;
1733 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 1734 c->dst.type = OP_REG;
1735 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1736 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
e4706772 1737 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 1738 seg_override_base(ctxt, c),
a7e6c88a
SY		 1739 c->regs[VCPU_REGS_RSI]),
1740 &c->dst.val,
1741 c->dst.bytes,
1742 ctxt->vcpu)) != 0)
6aa8b732 1743 goto done;
7a957275 1744 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1745 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1746 : c->dst.bytes);
6aa8b732
AK		 1747 break;
1748 case 0xae ... 0xaf: /* scas */
1749 DPRINTF("Urk! I don't handle SCAS.\n");
1750 goto cannot_emulate;
a5e2e82b 1751 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 1752 goto mov;
018a98db
AK		 1753 case 0xc0 ... 0xc1:
1754 emulate_grp2(ctxt);
1755 break;
111de5d6 1756 case 0xc3: /* ret */
cf5de4f8 1757 c->dst.type = OP_REG;
111de5d6 1758 c->dst.ptr = &c->eip;
cf5de4f8 1759 c->dst.bytes = c->op_bytes;
111de5d6 1760 goto pop_instruction;
018a98db
AK		 1761 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1762 mov:
1763 c->dst.val = c->src.val;
1764 break;
a77ab5ea
AK		 1765 case 0xcb: /* ret far */
1766 rc = emulate_ret_far(ctxt, ops);
1767 if (rc)
1768 goto done;
1769 break;
018a98db
AK		 1770 case 0xd0 ... 0xd1: /* Grp2 */
1771 c->src.val = 1;
1772 emulate_grp2(ctxt);
1773 break;
1774 case 0xd2 ... 0xd3: /* Grp2 */
1775 c->src.val = c->regs[VCPU_REGS_RCX];
1776 emulate_grp2(ctxt);
1777 break;
a6a3034c
MG		 1778 case 0xe4: /* inb */
1779 case 0xe5: /* in */
1780 port = insn_fetch(u8, 1, c->eip);
1781 io_dir_in = 1;
1782 goto do_io;
1783 case 0xe6: /* outb */
1784 case 0xe7: /* out */
1785 port = insn_fetch(u8, 1, c->eip);
1786 io_dir_in = 0;
1787 goto do_io;
1a52e051
NK		 1788 case 0xe8: /* call (near) */ {
1789 long int rel;
e4e03ded 1790 switch (c->op_bytes) {
1a52e051 1791 case 2:
e4e03ded 1792 rel = insn_fetch(s16, 2, c->eip);
1a52e051
NK		 1793 break;
1794 case 4:
e4e03ded 1795 rel = insn_fetch(s32, 4, c->eip);
1a52e051 1796 break;
1a52e051
NK		 1797 default:
1798 DPRINTF("Call: Invalid op_bytes\n");
1799 goto cannot_emulate;
1800 }
e4e03ded 1801 c->src.val = (unsigned long) c->eip;
7a957275 1802 jmp_rel(c, rel);
8cdbd2c9
LV		 1803 emulate_push(ctxt);
1804 break;
1a52e051
NK		 1805 }
1806 case 0xe9: /* jmp rel */
954cd36f 1807 goto jmp;
782b877c
GN		 1808 case 0xea: /* jmp far */
1809 if (kvm_load_segment_descriptor(ctxt->vcpu, c->src2.val, 9,
1810 VCPU_SREG_CS) < 0) {
954cd36f
GT		 1811 DPRINTF("jmp far: Failed to load CS descriptor\n");
1812 goto cannot_emulate;
1813 }
1814
782b877c 1815 c->eip = c->src.val;
954cd36f 1816 break;
954cd36f
GT		 1817 case 0xeb:
1818 jmp: /* jmp rel short */
7a957275 1819 jmp_rel(c, c->src.val);
a01af5ec 1820 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 1821 break;
a6a3034c
MG		 1822 case 0xec: /* in al,dx */
1823 case 0xed: /* in (e/r)ax,dx */
1824 port = c->regs[VCPU_REGS_RDX];
1825 io_dir_in = 1;
1826 goto do_io;
1827 case 0xee: /* out al,dx */
1828 case 0xef: /* out (e/r)ax,dx */
1829 port = c->regs[VCPU_REGS_RDX];
1830 io_dir_in = 0;
1831 do_io: if (kvm_emulate_pio(ctxt->vcpu, NULL, io_dir_in,
1832 (c->d & ByteOp) ? 1 : c->op_bytes,
1833 port) != 0) {
1834 c->eip = saved_eip;
1835 goto cannot_emulate;
1836 }
e93f36bc 1837 break;
111de5d6 1838 case 0xf4: /* hlt */
ad312c7c 1839 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 1840 break;
111de5d6
AK		 1841 case 0xf5: /* cmc */
1842 /* complement carry flag from eflags reg */
1843 ctxt->eflags ^= EFLG_CF;
1844 c->dst.type = OP_NONE; /* Disable writeback. */
1845 break;
018a98db
AK		 1846 case 0xf6 ... 0xf7: /* Grp3 */
1847 rc = emulate_grp3(ctxt, ops);
1848 if (rc != 0)
1849 goto done;
1850 break;
111de5d6
AK		 1851 case 0xf8: /* clc */
1852 ctxt->eflags &= ~EFLG_CF;
1853 c->dst.type = OP_NONE; /* Disable writeback. */
1854 break;
1855 case 0xfa: /* cli */
1856 ctxt->eflags &= ~X86_EFLAGS_IF;
1857 c->dst.type = OP_NONE; /* Disable writeback. */
1858 break;
1859 case 0xfb: /* sti */
1860 ctxt->eflags |= X86_EFLAGS_IF;
1861 c->dst.type = OP_NONE; /* Disable writeback. */
1862 break;
fb4616f4
MG		 1863 case 0xfc: /* cld */
1864 ctxt->eflags &= ~EFLG_DF;
1865 c->dst.type = OP_NONE; /* Disable writeback. */
1866 break;
1867 case 0xfd: /* std */
1868 ctxt->eflags |= EFLG_DF;
1869 c->dst.type = OP_NONE; /* Disable writeback. */
1870 break;
018a98db
AK		 1871 case 0xfe ... 0xff: /* Grp4/Grp5 */
1872 rc = emulate_grp45(ctxt, ops);
1873 if (rc != 0)
1874 goto done;
1875 break;
6aa8b732 1876 }
018a98db
AK		 1877
1878writeback:
1879 rc = writeback(ctxt, ops);
1880 if (rc != 0)
1881 goto done;
1882
1883 /* Commit shadow register state. */
ad312c7c 1884 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
5fdbf976 1885 kvm_rip_write(ctxt->vcpu, c->eip);
018a98db
AK		 1886
1887done:
1888 if (rc == X86EMUL_UNHANDLEABLE) {
1889 c->eip = saved_eip;
1890 return -1;
1891 }
1892 return 0;
6aa8b732
AK		 1893
1894twobyte_insn:
e4e03ded 1895 switch (c->b) {
6aa8b732 1896 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 1897 switch (c->modrm_reg) {
6aa8b732
AK		 1898 u16 size;
1899 unsigned long address;
1900
aca7f966 1901 case 0: /* vmcall */
e4e03ded 1902 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 1903 goto cannot_emulate;
1904
7aa81cc0
AL		 1905 rc = kvm_fix_hypercall(ctxt->vcpu);
1906 if (rc)
1907 goto done;
1908
33e3885d 1909 /* Let the processor re-execute the fixed hypercall */
5fdbf976 1910 c->eip = kvm_rip_read(ctxt->vcpu);
16286d08
AK		 1911 /* Disable writeback. */
1912 c->dst.type = OP_NONE;
aca7f966 1913 break;
6aa8b732 1914 case 2: /* lgdt */
e4e03ded
LV		 1915 rc = read_descriptor(ctxt, ops, c->src.ptr,
1916 &size, &address, c->op_bytes);
6aa8b732
AK		 1917 if (rc)
1918 goto done;
1919 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 1920 /* Disable writeback. */
1921 c->dst.type = OP_NONE;
6aa8b732 1922 break;
aca7f966 1923 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 1924 if (c->modrm_mod == 3) {
1925 switch (c->modrm_rm) {
1926 case 1:
1927 rc = kvm_fix_hypercall(ctxt->vcpu);
1928 if (rc)
1929 goto done;
1930 break;
1931 default:
1932 goto cannot_emulate;
1933 }
aca7f966 1934 } else {
e4e03ded 1935 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 1936 &size, &address,
e4e03ded 1937 c->op_bytes);
aca7f966
AL		 1938 if (rc)
1939 goto done;
1940 realmode_lidt(ctxt->vcpu, size, address);
1941 }
16286d08
AK		 1942 /* Disable writeback. */
1943 c->dst.type = OP_NONE;
6aa8b732
AK		 1944 break;
1945 case 4: /* smsw */
16286d08
AK		 1946 c->dst.bytes = 2;
1947 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
6aa8b732
AK		 1948 break;
1949 case 6: /* lmsw */
16286d08
AK		 1950 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
1951 &ctxt->eflags);
dc7457ea 1952 c->dst.type = OP_NONE;
6aa8b732
AK		 1953 break;
1954 case 7: /* invlpg*/
e8d8d7fe 1955 emulate_invlpg(ctxt->vcpu, memop);
16286d08
AK		 1956 /* Disable writeback. */
1957 c->dst.type = OP_NONE;
6aa8b732
AK		 1958 break;
1959 default:
1960 goto cannot_emulate;
1961 }
1962 break;
018a98db
AK		 1963 case 0x06:
1964 emulate_clts(ctxt->vcpu);
1965 c->dst.type = OP_NONE;
1966 break;
1967 case 0x08: /* invd */
1968 case 0x09: /* wbinvd */
1969 case 0x0d: /* GrpP (prefetch) */
1970 case 0x18: /* Grp16 (prefetch/nop) */
1971 c->dst.type = OP_NONE;
1972 break;
1973 case 0x20: /* mov cr, reg */
1974 if (c->modrm_mod != 3)
1975 goto cannot_emulate;
1976 c->regs[c->modrm_rm] =
1977 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1978 c->dst.type = OP_NONE; /* no writeback */
1979 break;
6aa8b732 1980 case 0x21: /* mov from dr to reg */
e4e03ded 1981 if (c->modrm_mod != 3)
6aa8b732 1982 goto cannot_emulate;
8cdbd2c9 1983 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 1984 if (rc)
1985 goto cannot_emulate;
1986 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1987 break;
018a98db
AK		 1988 case 0x22: /* mov reg, cr */
1989 if (c->modrm_mod != 3)
1990 goto cannot_emulate;
1991 realmode_set_cr(ctxt->vcpu,
1992 c->modrm_reg, c->modrm_val, &ctxt->eflags);
1993 c->dst.type = OP_NONE;
1994 break;
6aa8b732 1995 case 0x23: /* mov from reg to dr */
e4e03ded 1996 if (c->modrm_mod != 3)
6aa8b732 1997 goto cannot_emulate;
e4e03ded
LV		 1998 rc = emulator_set_dr(ctxt, c->modrm_reg,
1999 c->regs[c->modrm_rm]);
a01af5ec
LV		 2000 if (rc)
2001 goto cannot_emulate;
2002 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 2003 break;
018a98db
AK		 2004 case 0x30:
2005 /* wrmsr */
2006 msr_data = (u32)c->regs[VCPU_REGS_RAX]
2007 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
2008 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
2009 if (rc) {
c1a5d4f9 2010 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 2011 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 2012 }
2013 rc = X86EMUL_CONTINUE;
2014 c->dst.type = OP_NONE;
2015 break;
2016 case 0x32:
2017 /* rdmsr */
2018 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
2019 if (rc) {
c1a5d4f9 2020 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 2021 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 2022 } else {
2023 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
2024 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
2025 }
2026 rc = X86EMUL_CONTINUE;
2027 c->dst.type = OP_NONE;
2028 break;
6aa8b732 2029 case 0x40 ... 0x4f: /* cmov */
e4e03ded 2030 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 2031 if (!test_cc(c->b, ctxt->eflags))
2032 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 2033 break;
018a98db
AK		 2034 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
2035 long int rel;
2036
2037 switch (c->op_bytes) {
2038 case 2:
2039 rel = insn_fetch(s16, 2, c->eip);
2040 break;
2041 case 4:
2042 rel = insn_fetch(s32, 4, c->eip);
2043 break;
2044 case 8:
2045 rel = insn_fetch(s64, 8, c->eip);
2046 break;
2047 default:
2048 DPRINTF("jnz: Invalid op_bytes\n");
2049 goto cannot_emulate;
2050 }
2051 if (test_cc(c->b, ctxt->eflags))
7a957275 2052 jmp_rel(c, rel);
018a98db
AK		 2053 c->dst.type = OP_NONE;
2054 break;
2055 }
7de75248
NK		 2056 case 0xa3:
2057 bt: /* bt */
e4f8e039 2058 c->dst.type = OP_NONE;
e4e03ded
LV		 2059 /* only subword offset */
2060 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2061 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 2062 break;
9bf8ea42
GT		 2063 case 0xa4: /* shld imm8, r, r/m */
2064 case 0xa5: /* shld cl, r, r/m */
2065 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
2066 break;
7de75248
NK		 2067 case 0xab:
2068 bts: /* bts */
e4e03ded
LV		 2069 /* only subword offset */
2070 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2071 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 2072 break;
9bf8ea42
GT		 2073 case 0xac: /* shrd imm8, r, r/m */
2074 case 0xad: /* shrd cl, r, r/m */
2075 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
2076 break;
2a7c5b8b
GC		 2077 case 0xae: /* clflush */
2078 break;
6aa8b732
AK		 2079 case 0xb0 ... 0xb1: /* cmpxchg */
2080 /*
2081 * Save real source value, then compare EAX against
2082 * destination.
2083 */
e4e03ded
LV		 2084 c->src.orig_val = c->src.val;
2085 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 2086 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2087 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 2088 /* Success: write back to memory. */
e4e03ded 2089 c->dst.val = c->src.orig_val;
6aa8b732
AK		 2090 } else {
2091 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 2092 c->dst.type = OP_REG;
2093 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2094 }
2095 break;
6aa8b732
AK		 2096 case 0xb3:
2097 btr: /* btr */
e4e03ded
LV		 2098 /* only subword offset */
2099 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2100 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 2101 break;
6aa8b732 2102 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 2103 c->dst.bytes = c->op_bytes;
2104 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
2105 : (u16) c->src.val;
6aa8b732 2106 break;
6aa8b732 2107 case 0xba: /* Grp8 */
e4e03ded 2108 switch (c->modrm_reg & 3) {
6aa8b732
AK		 2109 case 0:
2110 goto bt;
2111 case 1:
2112 goto bts;
2113 case 2:
2114 goto btr;
2115 case 3:
2116 goto btc;
2117 }
2118 break;
7de75248
NK		 2119 case 0xbb:
2120 btc: /* btc */
e4e03ded
LV		 2121 /* only subword offset */
2122 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2123 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 2124 break;
6aa8b732 2125 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 2126 c->dst.bytes = c->op_bytes;
2127 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
2128 (s16) c->src.val;
6aa8b732 2129 break;
a012e65a 2130 case 0xc3: /* movnti */
e4e03ded
LV		 2131 c->dst.bytes = c->op_bytes;
2132 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
2133 (u64) c->src.val;
a012e65a 2134 break;
6aa8b732 2135 case 0xc7: /* Grp9 (cmpxchg8b) */
e8d8d7fe 2136 rc = emulate_grp9(ctxt, ops, memop);
8cdbd2c9
LV		 2137 if (rc != 0)
2138 goto done;
018a98db 2139 c->dst.type = OP_NONE;
8cdbd2c9 2140 break;
6aa8b732
AK		 2141 }
2142 goto writeback;
2143
2144cannot_emulate:
e4e03ded 2145 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 2146 c->eip = saved_eip;
6aa8b732
AK		 2147 return -1;
2148}
Linux kernel - Deliverables
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