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KVM: x86 emulator: Add cmp al, imm and cmp ax, imm instructions (ocodes 3c, 3d)
[deliverable/linux.git] / arch / x86 / kvm / x86_emulate.c
CommitLineData
6aa8b732
AK		 1/******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
5fdbf976 29#include "kvm_cache_regs.h"
6aa8b732
AK		 30#define DPRINTF(x...) do {} while (0)
31#endif
6aa8b732 32#include <linux/module.h>
edf88417 33#include <asm/kvm_x86_emulate.h>
6aa8b732
AK		 34
35/*
36 * Opcode effective-address decode tables.
37 * Note that we only emulate instructions that have at least one memory
38 * operand (excluding implicit stack references). We assume that stack
39 * references and instruction fetches will never occur in special memory
40 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
41 * not be handled.
42 */
43
44/* Operand sizes: 8-bit operands or specified/overridden size. */
45#define ByteOp (1<<0) /* 8-bit operands. */
46/* Destination operand type. */
47#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
48#define DstReg (2<<1) /* Register operand. */
49#define DstMem (3<<1) /* Memory operand. */
9c9fddd0
GT		 50#define DstAcc (4<<1) /* Destination Accumulator */
51#define DstMask (7<<1)
6aa8b732 52/* Source operand type. */
9c9fddd0
GT		 53#define SrcNone (0<<4) /* No source operand. */
54#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
55#define SrcReg (1<<4) /* Register operand. */
56#define SrcMem (2<<4) /* Memory operand. */
57#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
58#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
59#define SrcImm (5<<4) /* Immediate operand. */
60#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
61#define SrcMask (7<<4)
6aa8b732 62/* Generic ModRM decode. */
9c9fddd0 63#define ModRM (1<<7)
6aa8b732 64/* Destination is only written; never read. */
9c9fddd0
GT		 65#define Mov (1<<8)
66#define BitOp (1<<9)
67#define MemAbs (1<<10) /* Memory operand is absolute displacement */
68#define String (1<<12) /* String instruction (rep capable) */
69#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 70#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
71#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
72#define GroupMask 0xff /* Group number stored in bits 0:7 */
6aa8b732 73
43bb19cd 74enum {
1d6ad207 75 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 76 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
43bb19cd
AK		 77};
78
c7e75a3d 79static u16 opcode_table[256] = {
6aa8b732
AK		 80 /* 0x00 - 0x07 */
81 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
82 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
83 0, 0, 0, 0,
84 /* 0x08 - 0x0F */
85 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
86 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
87 0, 0, 0, 0,
88 /* 0x10 - 0x17 */
89 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
90 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
91 0, 0, 0, 0,
92 /* 0x18 - 0x1F */
93 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
94 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
95 0, 0, 0, 0,
96 /* 0x20 - 0x27 */
97 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
98 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
19eb938e 99 SrcImmByte, SrcImm, 0, 0,
6aa8b732
AK		 100 /* 0x28 - 0x2F */
101 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
102 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
103 0, 0, 0, 0,
104 /* 0x30 - 0x37 */
105 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
106 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
107 0, 0, 0, 0,
108 /* 0x38 - 0x3F */
109 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
110 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
8a9fee67
GT		 111 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
112 0, 0,
d77a2507 113 /* 0x40 - 0x47 */
33615aa9 114 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 115 /* 0x48 - 0x4F */
33615aa9 116 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 117 /* 0x50 - 0x57 */
6e3d5dfb
AK		 118 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
119 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 120 /* 0x58 - 0x5F */
6e3d5dfb
AK		 121 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
122 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 123 /* 0x60 - 0x67 */
6aa8b732 124 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 125 0, 0, 0, 0,
126 /* 0x68 - 0x6F */
91ed7a0e 127 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
e70669ab
LV		 128 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
129 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4
NK		 130 /* 0x70 - 0x77 */
131 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
132 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
133 /* 0x78 - 0x7F */
134 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
135 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732 136 /* 0x80 - 0x87 */
1d6ad207
AK		 137 Group | Group1_80, Group | Group1_81,
138 Group | Group1_82, Group | Group1_83,
6aa8b732
AK		 139 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
140 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
141 /* 0x88 - 0x8F */
142 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
143 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
38d5bc6d 144 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
4257198a 145 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
b13354f8
MG		 146 /* 0x90 - 0x97 */
147 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
148 /* 0x98 - 0x9F */
6e3d5dfb 149 0, 0, 0, 0, ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 150 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 151 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
152 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
b9fa9d6b
AK		 153 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
154 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 155 /* 0xA8 - 0xAF */
b9fa9d6b
AK		 156 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
157 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
158 ByteOp | ImplicitOps | String, ImplicitOps | String,
a5e2e82b
MG		 159 /* 0xB0 - 0xB7 */
160 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
161 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
162 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
163 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
164 /* 0xB8 - 0xBF */
165 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
166 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
167 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
168 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
6aa8b732 169 /* 0xC0 - 0xC7 */
d9413cd7 170 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 171 0, ImplicitOps | Stack, 0, 0,
d9413cd7 172 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732
AK		 173 /* 0xC8 - 0xCF */
174 0, 0, 0, 0, 0, 0, 0, 0,
175 /* 0xD0 - 0xD7 */
176 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
177 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
178 0, 0, 0, 0,
179 /* 0xD8 - 0xDF */
180 0, 0, 0, 0, 0, 0, 0, 0,
098c937b 181 /* 0xE0 - 0xE7 */
a6a3034c
MG		 182 0, 0, 0, 0,
183 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
184 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
098c937b 185 /* 0xE8 - 0xEF */
954cd36f
GT		 186 ImplicitOps | Stack, SrcImm | ImplicitOps,
187 ImplicitOps, SrcImmByte | ImplicitOps,
a6a3034c
MG		 188 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
189 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
6aa8b732
AK		 190 /* 0xF0 - 0xF7 */
191 0, 0, 0, 0,
7d858a19 192 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 193 /* 0xF8 - 0xFF */
b284be57 194 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fb4616f4 195 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
6aa8b732
AK		 196};
197
038e51de 198static u16 twobyte_table[256] = {
6aa8b732 199 /* 0x00 - 0x0F */
d95058a1 200 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
651a3e29 201 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 202 /* 0x10 - 0x1F */
203 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
204 /* 0x20 - 0x2F */
205 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
206 0, 0, 0, 0, 0, 0, 0, 0,
207 /* 0x30 - 0x3F */
35f3f286 208 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 209 /* 0x40 - 0x47 */
210 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
211 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
212 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
213 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
214 /* 0x48 - 0x4F */
215 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
216 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
217 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
218 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
219 /* 0x50 - 0x5F */
220 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
221 /* 0x60 - 0x6F */
222 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
223 /* 0x70 - 0x7F */
224 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
225 /* 0x80 - 0x8F */
bbe9abbd
NK		 226 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
227 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
228 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
229 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 230 /* 0x90 - 0x9F */
231 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
232 /* 0xA0 - 0xA7 */
038e51de 233 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732 234 /* 0xA8 - 0xAF */
2a7c5b8b 235 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, ModRM, 0,
6aa8b732
AK		 236 /* 0xB0 - 0xB7 */
237 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 238 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 239 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
240 DstReg | SrcMem16 | ModRM | Mov,
241 /* 0xB8 - 0xBF */
038e51de 242 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 243 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
244 DstReg | SrcMem16 | ModRM | Mov,
245 /* 0xC0 - 0xCF */
a012e65a
SY		 246 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
247 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 248 /* 0xD0 - 0xDF */
249 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
250 /* 0xE0 - 0xEF */
251 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
252 /* 0xF0 - 0xFF */
253 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
254};
255
e09d082c 256static u16 group_table[] = {
1d6ad207
AK		 257 [Group1_80*8] =
258 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
259 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
260 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
261 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
262 [Group1_81*8] =
263 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
264 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
265 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
266 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
267 [Group1_82*8] =
268 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
269 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
270 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
271 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
272 [Group1_83*8] =
273 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
274 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
275 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
276 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 277 [Group1A*8] =
278 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 279 [Group3_Byte*8] =
280 ByteOp | SrcImm | DstMem | ModRM, 0,
281 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
282 0, 0, 0, 0,
283 [Group3*8] =
41afa025 284 DstMem | SrcImm | ModRM, 0,
6eb06cb2 285 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
7d858a19 286 0, 0, 0, 0,
fd60754e
AK		 287 [Group4*8] =
288 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
289 0, 0, 0, 0, 0, 0,
290 [Group5*8] =
d19292e4
MG		 291 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
292 SrcMem | ModRM | Stack, 0,
ef46f18e 293 SrcMem | ModRM | Stack, 0, SrcMem | ModRM | Stack, 0,
d95058a1
AK		 294 [Group7*8] =
295 0, 0, ModRM | SrcMem, ModRM | SrcMem,
16286d08
AK		 296 SrcNone | ModRM | DstMem | Mov, 0,
297 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
e09d082c
AK		 298};
299
300static u16 group2_table[] = {
d95058a1 301 [Group7*8] =
16286d08
AK		 302 SrcNone | ModRM, 0, 0, 0,
303 SrcNone | ModRM | DstMem | Mov, 0,
304 SrcMem16 | ModRM | Mov, 0,
e09d082c
AK		 305};
306
6aa8b732
AK		 307/* EFLAGS bit definitions. */
308#define EFLG_OF (1<<11)
309#define EFLG_DF (1<<10)
310#define EFLG_SF (1<<7)
311#define EFLG_ZF (1<<6)
312#define EFLG_AF (1<<4)
313#define EFLG_PF (1<<2)
314#define EFLG_CF (1<<0)
315
316/*
317 * Instruction emulation:
318 * Most instructions are emulated directly via a fragment of inline assembly
319 * code. This allows us to save/restore EFLAGS and thus very easily pick up
320 * any modified flags.
321 */
322
05b3e0c2 323#if defined(CONFIG_X86_64)
6aa8b732
AK		 324#define _LO32 "k" /* force 32-bit operand */
325#define _STK "%%rsp" /* stack pointer */
326#elif defined(__i386__)
327#define _LO32 "" /* force 32-bit operand */
328#define _STK "%%esp" /* stack pointer */
329#endif
330
331/*
332 * These EFLAGS bits are restored from saved value during emulation, and
333 * any changes are written back to the saved value after emulation.
334 */
335#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
336
337/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 338#define _PRE_EFLAGS(_sav, _msk, _tmp) \
339 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
340 "movl %"_sav",%"_LO32 _tmp"; " \
341 "push %"_tmp"; " \
342 "push %"_tmp"; " \
343 "movl %"_msk",%"_LO32 _tmp"; " \
344 "andl %"_LO32 _tmp",("_STK"); " \
345 "pushf; " \
346 "notl %"_LO32 _tmp"; " \
347 "andl %"_LO32 _tmp",("_STK"); " \
348 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
349 "pop %"_tmp"; " \
350 "orl %"_LO32 _tmp",("_STK"); " \
351 "popf; " \
352 "pop %"_sav"; "
6aa8b732
AK		 353
354/* After executing instruction: write-back necessary bits in EFLAGS. */
355#define _POST_EFLAGS(_sav, _msk, _tmp) \
356 /* _sav |= EFLAGS & _msk; */ \
357 "pushf; " \
358 "pop %"_tmp"; " \
359 "andl %"_msk",%"_LO32 _tmp"; " \
360 "orl %"_LO32 _tmp",%"_sav"; "
361
362/* Raw emulation: instruction has two explicit operands. */
363#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
364 do { \
365 unsigned long _tmp; \
366 \
367 switch ((_dst).bytes) { \
368 case 2: \
369 __asm__ __volatile__ ( \
d77c26fc 370 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 371 _op"w %"_wx"3,%1; " \
d77c26fc 372 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 373 : "=m" (_eflags), "=m" ((_dst).val), \
374 "=&r" (_tmp) \
d77c26fc 375 : _wy ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 376 break; \
377 case 4: \
378 __asm__ __volatile__ ( \
d77c26fc 379 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 380 _op"l %"_lx"3,%1; " \
d77c26fc 381 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 382 : "=m" (_eflags), "=m" ((_dst).val), \
383 "=&r" (_tmp) \
d77c26fc 384 : _ly ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 385 break; \
386 case 8: \
387 __emulate_2op_8byte(_op, _src, _dst, \
388 _eflags, _qx, _qy); \
389 break; \
390 } \
391 } while (0)
392
393#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
394 do { \
77cd337f 395 unsigned long __tmp; \
d77c26fc 396 switch ((_dst).bytes) { \
6aa8b732
AK		 397 case 1: \
398 __asm__ __volatile__ ( \
d77c26fc 399 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 400 _op"b %"_bx"3,%1; " \
d77c26fc 401 _POST_EFLAGS("0", "4", "2") \
6aa8b732 402 : "=m" (_eflags), "=m" ((_dst).val), \
77cd337f 403 "=&r" (__tmp) \
d77c26fc 404 : _by ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 405 break; \
406 default: \
407 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
408 _wx, _wy, _lx, _ly, _qx, _qy); \
409 break; \
410 } \
411 } while (0)
412
413/* Source operand is byte-sized and may be restricted to just %cl. */
414#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
415 __emulate_2op(_op, _src, _dst, _eflags, \
416 "b", "c", "b", "c", "b", "c", "b", "c")
417
418/* Source operand is byte, word, long or quad sized. */
419#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
420 __emulate_2op(_op, _src, _dst, _eflags, \
421 "b", "q", "w", "r", _LO32, "r", "", "r")
422
423/* Source operand is word, long or quad sized. */
424#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
425 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
426 "w", "r", _LO32, "r", "", "r")
427
428/* Instruction has only one explicit operand (no source operand). */
429#define emulate_1op(_op, _dst, _eflags) \
430 do { \
431 unsigned long _tmp; \
432 \
d77c26fc 433 switch ((_dst).bytes) { \
6aa8b732
AK		 434 case 1: \
435 __asm__ __volatile__ ( \
d77c26fc 436 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 437 _op"b %1; " \
d77c26fc 438 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 439 : "=m" (_eflags), "=m" ((_dst).val), \
440 "=&r" (_tmp) \
d77c26fc 441 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 442 break; \
443 case 2: \
444 __asm__ __volatile__ ( \
d77c26fc 445 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 446 _op"w %1; " \
d77c26fc 447 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 448 : "=m" (_eflags), "=m" ((_dst).val), \
449 "=&r" (_tmp) \
d77c26fc 450 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 451 break; \
452 case 4: \
453 __asm__ __volatile__ ( \
d77c26fc 454 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 455 _op"l %1; " \
d77c26fc 456 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 457 : "=m" (_eflags), "=m" ((_dst).val), \
458 "=&r" (_tmp) \
d77c26fc 459 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 460 break; \
461 case 8: \
462 __emulate_1op_8byte(_op, _dst, _eflags); \
463 break; \
464 } \
465 } while (0)
466
467/* Emulate an instruction with quadword operands (x86/64 only). */
05b3e0c2 468#if defined(CONFIG_X86_64)
6aa8b732
AK		 469#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
470 do { \
471 __asm__ __volatile__ ( \
d77c26fc 472 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 473 _op"q %"_qx"3,%1; " \
d77c26fc 474 _POST_EFLAGS("0", "4", "2") \
6aa8b732 475 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
d77c26fc 476 : _qy ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 477 } while (0)
478
479#define __emulate_1op_8byte(_op, _dst, _eflags) \
480 do { \
481 __asm__ __volatile__ ( \
d77c26fc 482 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 483 _op"q %1; " \
d77c26fc 484 _POST_EFLAGS("0", "3", "2") \
6aa8b732 485 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
d77c26fc 486 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 487 } while (0)
488
489#elif defined(__i386__)
490#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
491#define __emulate_1op_8byte(_op, _dst, _eflags)
492#endif /* __i386__ */
493
494/* Fetch next part of the instruction being emulated. */
495#define insn_fetch(_type, _size, _eip) \
496({ unsigned long _x; \
62266869 497 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
d77c26fc 498 if (rc != 0) \
6aa8b732
AK		 499 goto done; \
500 (_eip) += (_size); \
501 (_type)_x; \
502})
503
ddcb2885
HH		 504static inline unsigned long ad_mask(struct decode_cache *c)
505{
506 return (1UL << (c->ad_bytes << 3)) - 1;
507}
508
6aa8b732 509/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 510static inline unsigned long
511address_mask(struct decode_cache *c, unsigned long reg)
512{
513 if (c->ad_bytes == sizeof(unsigned long))
514 return reg;
515 else
516 return reg & ad_mask(c);
517}
518
519static inline unsigned long
520register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
521{
522 return base + address_mask(c, reg);
523}
524
7a957275
HH		 525static inline void
526register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
527{
528 if (c->ad_bytes == sizeof(unsigned long))
529 *reg += inc;
530 else
531 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
532}
6aa8b732 533
7a957275
HH		 534static inline void jmp_rel(struct decode_cache *c, int rel)
535{
536 register_address_increment(c, &c->eip, rel);
537}
098c937b 538
7a5b56df
AK		 539static void set_seg_override(struct decode_cache *c, int seg)
540{
541 c->has_seg_override = true;
542 c->seg_override = seg;
543}
544
545static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
546{
547 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
548 return 0;
549
550 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
551}
552
553static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
554 struct decode_cache *c)
555{
556 if (!c->has_seg_override)
557 return 0;
558
559 return seg_base(ctxt, c->seg_override);
560}
561
562static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
563{
564 return seg_base(ctxt, VCPU_SREG_ES);
565}
566
567static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
568{
569 return seg_base(ctxt, VCPU_SREG_SS);
570}
571
62266869
AK		 572static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
573 struct x86_emulate_ops *ops,
574 unsigned long linear, u8 *dest)
575{
576 struct fetch_cache *fc = &ctxt->decode.fetch;
577 int rc;
578 int size;
579
580 if (linear < fc->start || linear >= fc->end) {
581 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
582 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
583 if (rc)
584 return rc;
585 fc->start = linear;
586 fc->end = linear + size;
587 }
588 *dest = fc->data[linear - fc->start];
589 return 0;
590}
591
592static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
593 struct x86_emulate_ops *ops,
594 unsigned long eip, void *dest, unsigned size)
595{
596 int rc = 0;
597
598 eip += ctxt->cs_base;
599 while (size--) {
600 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
601 if (rc)
602 return rc;
603 }
604 return 0;
605}
606
1e3c5cb0
RR		 607/*
608 * Given the 'reg' portion of a ModRM byte, and a register block, return a
609 * pointer into the block that addresses the relevant register.
610 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
611 */
612static void *decode_register(u8 modrm_reg, unsigned long *regs,
613 int highbyte_regs)
6aa8b732
AK		 614{
615 void *p;
616
617 p = &regs[modrm_reg];
618 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
619 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
620 return p;
621}
622
623static int read_descriptor(struct x86_emulate_ctxt *ctxt,
624 struct x86_emulate_ops *ops,
625 void *ptr,
626 u16 *size, unsigned long *address, int op_bytes)
627{
628 int rc;
629
630 if (op_bytes == 2)
631 op_bytes = 3;
632 *address = 0;
cebff02b
LV		 633 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
634 ctxt->vcpu);
6aa8b732
AK		 635 if (rc)
636 return rc;
cebff02b
LV		 637 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
638 ctxt->vcpu);
6aa8b732
AK		 639 return rc;
640}
641
bbe9abbd
NK		 642static int test_cc(unsigned int condition, unsigned int flags)
643{
644 int rc = 0;
645
646 switch ((condition & 15) >> 1) {
647 case 0: /* o */
648 rc |= (flags & EFLG_OF);
649 break;
650 case 1: /* b/c/nae */
651 rc |= (flags & EFLG_CF);
652 break;
653 case 2: /* z/e */
654 rc |= (flags & EFLG_ZF);
655 break;
656 case 3: /* be/na */
657 rc |= (flags & (EFLG_CF|EFLG_ZF));
658 break;
659 case 4: /* s */
660 rc |= (flags & EFLG_SF);
661 break;
662 case 5: /* p/pe */
663 rc |= (flags & EFLG_PF);
664 break;
665 case 7: /* le/ng */
666 rc |= (flags & EFLG_ZF);
667 /* fall through */
668 case 6: /* l/nge */
669 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
670 break;
671 }
672
673 /* Odd condition identifiers (lsb == 1) have inverted sense. */
674 return (!!rc ^ (condition & 1));
675}
676
3c118e24
AK		 677static void decode_register_operand(struct operand *op,
678 struct decode_cache *c,
3c118e24
AK		 679 int inhibit_bytereg)
680{
33615aa9 681 unsigned reg = c->modrm_reg;
9f1ef3f8 682 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 683
684 if (!(c->d & ModRM))
685 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 686 op->type = OP_REG;
687 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 688 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 689 op->val = *(u8 *)op->ptr;
690 op->bytes = 1;
691 } else {
33615aa9 692 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 693 op->bytes = c->op_bytes;
694 switch (op->bytes) {
695 case 2:
696 op->val = *(u16 *)op->ptr;
697 break;
698 case 4:
699 op->val = *(u32 *)op->ptr;
700 break;
701 case 8:
702 op->val = *(u64 *) op->ptr;
703 break;
704 }
705 }
706 op->orig_val = op->val;
707}
708
1c73ef66
AK		 709static int decode_modrm(struct x86_emulate_ctxt *ctxt,
710 struct x86_emulate_ops *ops)
711{
712 struct decode_cache *c = &ctxt->decode;
713 u8 sib;
f5b4edcd 714 int index_reg = 0, base_reg = 0, scale;
1c73ef66
AK		 715 int rc = 0;
716
717 if (c->rex_prefix) {
718 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
719 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
720 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
721 }
722
723 c->modrm = insn_fetch(u8, 1, c->eip);
724 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
725 c->modrm_reg |= (c->modrm & 0x38) >> 3;
726 c->modrm_rm |= (c->modrm & 0x07);
727 c->modrm_ea = 0;
728 c->use_modrm_ea = 1;
729
730 if (c->modrm_mod == 3) {
107d6d2e
AK		 731 c->modrm_ptr = decode_register(c->modrm_rm,
732 c->regs, c->d & ByteOp);
733 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 734 return rc;
735 }
736
737 if (c->ad_bytes == 2) {
738 unsigned bx = c->regs[VCPU_REGS_RBX];
739 unsigned bp = c->regs[VCPU_REGS_RBP];
740 unsigned si = c->regs[VCPU_REGS_RSI];
741 unsigned di = c->regs[VCPU_REGS_RDI];
742
743 /* 16-bit ModR/M decode. */
744 switch (c->modrm_mod) {
745 case 0:
746 if (c->modrm_rm == 6)
747 c->modrm_ea += insn_fetch(u16, 2, c->eip);
748 break;
749 case 1:
750 c->modrm_ea += insn_fetch(s8, 1, c->eip);
751 break;
752 case 2:
753 c->modrm_ea += insn_fetch(u16, 2, c->eip);
754 break;
755 }
756 switch (c->modrm_rm) {
757 case 0:
758 c->modrm_ea += bx + si;
759 break;
760 case 1:
761 c->modrm_ea += bx + di;
762 break;
763 case 2:
764 c->modrm_ea += bp + si;
765 break;
766 case 3:
767 c->modrm_ea += bp + di;
768 break;
769 case 4:
770 c->modrm_ea += si;
771 break;
772 case 5:
773 c->modrm_ea += di;
774 break;
775 case 6:
776 if (c->modrm_mod != 0)
777 c->modrm_ea += bp;
778 break;
779 case 7:
780 c->modrm_ea += bx;
781 break;
782 }
783 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
784 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 785 if (!c->has_seg_override)
786 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 787 c->modrm_ea = (u16)c->modrm_ea;
788 } else {
789 /* 32/64-bit ModR/M decode. */
84411d85 790 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 791 sib = insn_fetch(u8, 1, c->eip);
792 index_reg |= (sib >> 3) & 7;
793 base_reg |= sib & 7;
794 scale = sib >> 6;
795
dc71d0f1
AK		 796 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
797 c->modrm_ea += insn_fetch(s32, 4, c->eip);
798 else
1c73ef66 799 c->modrm_ea += c->regs[base_reg];
dc71d0f1 800 if (index_reg != 4)
1c73ef66 801 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 802 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
803 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 804 c->rip_relative = 1;
84411d85 805 } else
1c73ef66 806 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 807 switch (c->modrm_mod) {
808 case 0:
809 if (c->modrm_rm == 5)
810 c->modrm_ea += insn_fetch(s32, 4, c->eip);
811 break;
812 case 1:
813 c->modrm_ea += insn_fetch(s8, 1, c->eip);
814 break;
815 case 2:
816 c->modrm_ea += insn_fetch(s32, 4, c->eip);
817 break;
818 }
819 }
1c73ef66
AK		 820done:
821 return rc;
822}
823
824static int decode_abs(struct x86_emulate_ctxt *ctxt,
825 struct x86_emulate_ops *ops)
826{
827 struct decode_cache *c = &ctxt->decode;
828 int rc = 0;
829
830 switch (c->ad_bytes) {
831 case 2:
832 c->modrm_ea = insn_fetch(u16, 2, c->eip);
833 break;
834 case 4:
835 c->modrm_ea = insn_fetch(u32, 4, c->eip);
836 break;
837 case 8:
838 c->modrm_ea = insn_fetch(u64, 8, c->eip);
839 break;
840 }
841done:
842 return rc;
843}
844
6aa8b732 845int
8b4caf66 846x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 847{
e4e03ded 848 struct decode_cache *c = &ctxt->decode;
6aa8b732 849 int rc = 0;
6aa8b732 850 int mode = ctxt->mode;
e09d082c 851 int def_op_bytes, def_ad_bytes, group;
6aa8b732
AK		 852
853 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 854
e4e03ded 855 memset(c, 0, sizeof(struct decode_cache));
5fdbf976 856 c->eip = kvm_rip_read(ctxt->vcpu);
7a5b56df 857 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
ad312c7c 858 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 859
860 switch (mode) {
861 case X86EMUL_MODE_REAL:
862 case X86EMUL_MODE_PROT16:
f21b8bf4 863 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 864 break;
865 case X86EMUL_MODE_PROT32:
f21b8bf4 866 def_op_bytes = def_ad_bytes = 4;
6aa8b732 867 break;
05b3e0c2 868#ifdef CONFIG_X86_64
6aa8b732 869 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 870 def_op_bytes = 4;
871 def_ad_bytes = 8;
6aa8b732
AK		 872 break;
873#endif
874 default:
875 return -1;
876 }
877
f21b8bf4
AK		 878 c->op_bytes = def_op_bytes;
879 c->ad_bytes = def_ad_bytes;
880
6aa8b732 881 /* Legacy prefixes. */
b4c6abfe 882 for (;;) {
e4e03ded 883 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 884 case 0x66: /* operand-size override */
f21b8bf4
AK		 885 /* switch between 2/4 bytes */
886 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 887 break;
888 case 0x67: /* address-size override */
889 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 890 /* switch between 4/8 bytes */
f21b8bf4 891 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 892 else
e4e03ded 893 /* switch between 2/4 bytes */
f21b8bf4 894 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 895 break;
7a5b56df 896 case 0x26: /* ES override */
6aa8b732 897 case 0x2e: /* CS override */
7a5b56df 898 case 0x36: /* SS override */
6aa8b732 899 case 0x3e: /* DS override */
7a5b56df 900 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 901 break;
902 case 0x64: /* FS override */
6aa8b732 903 case 0x65: /* GS override */
7a5b56df 904 set_seg_override(c, c->b & 7);
6aa8b732 905 break;
b4c6abfe
LV		 906 case 0x40 ... 0x4f: /* REX */
907 if (mode != X86EMUL_MODE_PROT64)
908 goto done_prefixes;
33615aa9 909 c->rex_prefix = c->b;
b4c6abfe 910 continue;
6aa8b732 911 case 0xf0: /* LOCK */
e4e03ded 912 c->lock_prefix = 1;
6aa8b732 913 break;
ae6200ba 914 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 915 c->rep_prefix = REPNE_PREFIX;
916 break;
6aa8b732 917 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 918 c->rep_prefix = REPE_PREFIX;
6aa8b732 919 break;
6aa8b732
AK		 920 default:
921 goto done_prefixes;
922 }
b4c6abfe
LV		 923
924 /* Any legacy prefix after a REX prefix nullifies its effect. */
925
33615aa9 926 c->rex_prefix = 0;
6aa8b732
AK		 927 }
928
929done_prefixes:
930
931 /* REX prefix. */
1c73ef66 932 if (c->rex_prefix)
33615aa9 933 if (c->rex_prefix & 8)
e4e03ded 934 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 935
936 /* Opcode byte(s). */
e4e03ded
LV		 937 c->d = opcode_table[c->b];
938 if (c->d == 0) {
6aa8b732 939 /* Two-byte opcode? */
e4e03ded
LV		 940 if (c->b == 0x0f) {
941 c->twobyte = 1;
942 c->b = insn_fetch(u8, 1, c->eip);
943 c->d = twobyte_table[c->b];
6aa8b732 944 }
e09d082c 945 }
6aa8b732 946
e09d082c
AK		 947 if (c->d & Group) {
948 group = c->d & GroupMask;
949 c->modrm = insn_fetch(u8, 1, c->eip);
950 --c->eip;
951
952 group = (group << 3) + ((c->modrm >> 3) & 7);
953 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
954 c->d = group2_table[group];
955 else
956 c->d = group_table[group];
957 }
958
959 /* Unrecognised? */
960 if (c->d == 0) {
961 DPRINTF("Cannot emulate %02x\n", c->b);
962 return -1;
6aa8b732
AK		 963 }
964
6e3d5dfb
AK		 965 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
966 c->op_bytes = 8;
967
6aa8b732 968 /* ModRM and SIB bytes. */
1c73ef66
AK		 969 if (c->d & ModRM)
970 rc = decode_modrm(ctxt, ops);
971 else if (c->d & MemAbs)
972 rc = decode_abs(ctxt, ops);
973 if (rc)
974 goto done;
6aa8b732 975
7a5b56df
AK		 976 if (!c->has_seg_override)
977 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 978
7a5b56df
AK		 979 if (!(!c->twobyte && c->b == 0x8d))
980 c->modrm_ea += seg_override_base(ctxt, c);
c7e75a3d
AK		 981
982 if (c->ad_bytes != 8)
983 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 984 /*
985 * Decode and fetch the source operand: register, memory
986 * or immediate.
987 */
e4e03ded 988 switch (c->d & SrcMask) {
6aa8b732
AK		 989 case SrcNone:
990 break;
991 case SrcReg:
9f1ef3f8 992 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 993 break;
994 case SrcMem16:
e4e03ded 995 c->src.bytes = 2;
6aa8b732
AK		 996 goto srcmem_common;
997 case SrcMem32:
e4e03ded 998 c->src.bytes = 4;
6aa8b732
AK		 999 goto srcmem_common;
1000 case SrcMem:
e4e03ded
LV		 1001 c->src.bytes = (c->d & ByteOp) ? 1 :
1002 c->op_bytes;
b85b9ee9 1003 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1004 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1005 break;
d77c26fc 1006 srcmem_common:
4e62417b
AJ		 1007 /*
1008 * For instructions with a ModR/M byte, switch to register
1009 * access if Mod = 3.
1010 */
e4e03ded
LV		 1011 if ((c->d & ModRM) && c->modrm_mod == 3) {
1012 c->src.type = OP_REG;
66b85505 1013 c->src.val = c->modrm_val;
107d6d2e 1014 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1015 break;
1016 }
e4e03ded 1017 c->src.type = OP_MEM;
6aa8b732
AK		 1018 break;
1019 case SrcImm:
e4e03ded
LV		 1020 c->src.type = OP_IMM;
1021 c->src.ptr = (unsigned long *)c->eip;
1022 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1023 if (c->src.bytes == 8)
1024 c->src.bytes = 4;
6aa8b732 1025 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1026 switch (c->src.bytes) {
6aa8b732 1027 case 1:
e4e03ded 1028 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1029 break;
1030 case 2:
e4e03ded 1031 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1032 break;
1033 case 4:
e4e03ded 1034 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1035 break;
1036 }
1037 break;
1038 case SrcImmByte:
e4e03ded
LV		 1039 c->src.type = OP_IMM;
1040 c->src.ptr = (unsigned long *)c->eip;
1041 c->src.bytes = 1;
1042 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1043 break;
1044 }
1045
038e51de 1046 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1047 switch (c->d & DstMask) {
038e51de
AK		 1048 case ImplicitOps:
1049 /* Special instructions do their own operand decoding. */
8b4caf66 1050 return 0;
038e51de 1051 case DstReg:
9f1ef3f8 1052 decode_register_operand(&c->dst, c,
3c118e24 1053 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1054 break;
1055 case DstMem:
e4e03ded 1056 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1057 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1058 c->dst.type = OP_REG;
66b85505 1059 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1060 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1061 break;
1062 }
8b4caf66
LV		 1063 c->dst.type = OP_MEM;
1064 break;
9c9fddd0
GT		 1065 case DstAcc:
1066 c->dst.type = OP_REG;
1067 c->dst.bytes = c->op_bytes;
1068 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1069 switch (c->op_bytes) {
1070 case 1:
1071 c->dst.val = *(u8 *)c->dst.ptr;
1072 break;
1073 case 2:
1074 c->dst.val = *(u16 *)c->dst.ptr;
1075 break;
1076 case 4:
1077 c->dst.val = *(u32 *)c->dst.ptr;
1078 break;
1079 }
1080 c->dst.orig_val = c->dst.val;
1081 break;
8b4caf66
LV		 1082 }
1083
f5b4edcd
AK		 1084 if (c->rip_relative)
1085 c->modrm_ea += c->eip;
1086
8b4caf66
LV		 1087done:
1088 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1089}
1090
8cdbd2c9
LV		 1091static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1092{
1093 struct decode_cache *c = &ctxt->decode;
1094
1095 c->dst.type = OP_MEM;
1096 c->dst.bytes = c->op_bytes;
1097 c->dst.val = c->src.val;
7a957275 1098 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
7a5b56df 1099 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1100 c->regs[VCPU_REGS_RSP]);
1101}
1102
1103static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1104 struct x86_emulate_ops *ops)
1105{
1106 struct decode_cache *c = &ctxt->decode;
1107 int rc;
1108
7a5b56df 1109 rc = ops->read_std(register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1110 c->regs[VCPU_REGS_RSP]),
1111 &c->dst.val, c->dst.bytes, ctxt->vcpu);
1112 if (rc != 0)
1113 return rc;
1114
7a957275 1115 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->dst.bytes);
8cdbd2c9
LV		 1116
1117 return 0;
1118}
1119
05f086f8 1120static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1121{
05f086f8 1122 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1123 switch (c->modrm_reg) {
1124 case 0: /* rol */
05f086f8 1125 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1126 break;
1127 case 1: /* ror */
05f086f8 1128 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1129 break;
1130 case 2: /* rcl */
05f086f8 1131 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1132 break;
1133 case 3: /* rcr */
05f086f8 1134 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1135 break;
1136 case 4: /* sal/shl */
1137 case 6: /* sal/shl */
05f086f8 1138 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1139 break;
1140 case 5: /* shr */
05f086f8 1141 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1142 break;
1143 case 7: /* sar */
05f086f8 1144 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1145 break;
1146 }
1147}
1148
1149static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1150 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1151{
1152 struct decode_cache *c = &ctxt->decode;
1153 int rc = 0;
1154
1155 switch (c->modrm_reg) {
1156 case 0 ... 1: /* test */
05f086f8 1157 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1158 break;
1159 case 2: /* not */
1160 c->dst.val = ~c->dst.val;
1161 break;
1162 case 3: /* neg */
05f086f8 1163 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1164 break;
1165 default:
1166 DPRINTF("Cannot emulate %02x\n", c->b);
1167 rc = X86EMUL_UNHANDLEABLE;
1168 break;
1169 }
8cdbd2c9
LV		 1170 return rc;
1171}
1172
1173static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1174 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1175{
1176 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1177
1178 switch (c->modrm_reg) {
1179 case 0: /* inc */
05f086f8 1180 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1181 break;
1182 case 1: /* dec */
05f086f8 1183 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1184 break;
d19292e4
MG		 1185 case 2: /* call near abs */ {
1186 long int old_eip;
1187 old_eip = c->eip;
1188 c->eip = c->src.val;
1189 c->src.val = old_eip;
1190 emulate_push(ctxt);
1191 break;
1192 }
8cdbd2c9 1193 case 4: /* jmp abs */
fd60754e 1194 c->eip = c->src.val;
8cdbd2c9
LV		 1195 break;
1196 case 6: /* push */
fd60754e 1197 emulate_push(ctxt);
8cdbd2c9 1198 break;
8cdbd2c9
LV		 1199 }
1200 return 0;
1201}
1202
1203static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1204 struct x86_emulate_ops *ops,
e8d8d7fe 1205 unsigned long memop)
8cdbd2c9
LV		 1206{
1207 struct decode_cache *c = &ctxt->decode;
1208 u64 old, new;
1209 int rc;
1210
e8d8d7fe 1211 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
8cdbd2c9
LV		 1212 if (rc != 0)
1213 return rc;
1214
1215 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1216 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1217
1218 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1219 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1220 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1221
1222 } else {
1223 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1224 (u32) c->regs[VCPU_REGS_RBX];
1225
e8d8d7fe 1226 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
8cdbd2c9
LV		 1227 if (rc != 0)
1228 return rc;
05f086f8 1229 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1230 }
1231 return 0;
1232}
1233
1234static inline int writeback(struct x86_emulate_ctxt *ctxt,
1235 struct x86_emulate_ops *ops)
1236{
1237 int rc;
1238 struct decode_cache *c = &ctxt->decode;
1239
1240 switch (c->dst.type) {
1241 case OP_REG:
1242 /* The 4-byte case *is* correct:
1243 * in 64-bit mode we zero-extend.
1244 */
1245 switch (c->dst.bytes) {
1246 case 1:
1247 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1248 break;
1249 case 2:
1250 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1251 break;
1252 case 4:
1253 *c->dst.ptr = (u32)c->dst.val;
1254 break; /* 64b: zero-ext */
1255 case 8:
1256 *c->dst.ptr = c->dst.val;
1257 break;
1258 }
1259 break;
1260 case OP_MEM:
1261 if (c->lock_prefix)
1262 rc = ops->cmpxchg_emulated(
1263 (unsigned long)c->dst.ptr,
1264 &c->dst.orig_val,
1265 &c->dst.val,
1266 c->dst.bytes,
1267 ctxt->vcpu);
1268 else
1269 rc = ops->write_emulated(
1270 (unsigned long)c->dst.ptr,
1271 &c->dst.val,
1272 c->dst.bytes,
1273 ctxt->vcpu);
1274 if (rc != 0)
1275 return rc;
a01af5ec
LV		 1276 break;
1277 case OP_NONE:
1278 /* no writeback */
1279 break;
8cdbd2c9
LV		 1280 default:
1281 break;
1282 }
1283 return 0;
1284}
1285
8b4caf66 1286int
1be3aa47 1287x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 1288{
e8d8d7fe 1289 unsigned long memop = 0;
8b4caf66 1290 u64 msr_data;
3427318f 1291 unsigned long saved_eip = 0;
8b4caf66 1292 struct decode_cache *c = &ctxt->decode;
a6a3034c
MG		 1293 unsigned int port;
1294 int io_dir_in;
1be3aa47 1295 int rc = 0;
8b4caf66 1296
3427318f
LV		 1297 /* Shadow copy of register state. Committed on successful emulation.
1298 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1299 * modify them.
1300 */
1301
ad312c7c 1302 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f
LV		 1303 saved_eip = c->eip;
1304
c7e75a3d 1305 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
e8d8d7fe 1306 memop = c->modrm_ea;
8b4caf66 1307
b9fa9d6b
AK		 1308 if (c->rep_prefix && (c->d & String)) {
1309 /* All REP prefixes have the same first termination condition */
1310 if (c->regs[VCPU_REGS_RCX] == 0) {
5fdbf976 1311 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1312 goto done;
1313 }
1314 /* The second termination condition only applies for REPE
1315 * and REPNE. Test if the repeat string operation prefix is
1316 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1317 * corresponding termination condition according to:
1318 * - if REPE/REPZ and ZF = 0 then done
1319 * - if REPNE/REPNZ and ZF = 1 then done
1320 */
1321 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1322 (c->b == 0xae) || (c->b == 0xaf)) {
1323 if ((c->rep_prefix == REPE_PREFIX) &&
1324 ((ctxt->eflags & EFLG_ZF) == 0)) {
5fdbf976 1325 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1326 goto done;
1327 }
1328 if ((c->rep_prefix == REPNE_PREFIX) &&
1329 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
5fdbf976 1330 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1331 goto done;
1332 }
1333 }
1334 c->regs[VCPU_REGS_RCX]--;
5fdbf976 1335 c->eip = kvm_rip_read(ctxt->vcpu);
b9fa9d6b
AK		 1336 }
1337
8b4caf66 1338 if (c->src.type == OP_MEM) {
e8d8d7fe 1339 c->src.ptr = (unsigned long *)memop;
8b4caf66 1340 c->src.val = 0;
d77c26fc
MD		 1341 rc = ops->read_emulated((unsigned long)c->src.ptr,
1342 &c->src.val,
1343 c->src.bytes,
1344 ctxt->vcpu);
1345 if (rc != 0)
8b4caf66
LV		 1346 goto done;
1347 c->src.orig_val = c->src.val;
1348 }
1349
1350 if ((c->d & DstMask) == ImplicitOps)
1351 goto special_insn;
1352
1353
1354 if (c->dst.type == OP_MEM) {
e8d8d7fe 1355 c->dst.ptr = (unsigned long *)memop;
8b4caf66
LV		 1356 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1357 c->dst.val = 0;
e4e03ded
LV		 1358 if (c->d & BitOp) {
1359 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1360
e4e03ded
LV		 1361 c->dst.ptr = (void *)c->dst.ptr +
1362 (c->src.val & mask) / 8;
038e51de 1363 }
e4e03ded
LV		 1364 if (!(c->d & Mov) &&
1365 /* optimisation - avoid slow emulated read */
1366 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1367 &c->dst.val,
1368 c->dst.bytes, ctxt->vcpu)) != 0))
038e51de 1369 goto done;
038e51de 1370 }
e4e03ded 1371 c->dst.orig_val = c->dst.val;
038e51de 1372
018a98db
AK		 1373special_insn:
1374
e4e03ded 1375 if (c->twobyte)
6aa8b732
AK		 1376 goto twobyte_insn;
1377
e4e03ded 1378 switch (c->b) {
6aa8b732
AK		 1379 case 0x00 ... 0x05:
1380 add: /* add */
05f086f8 1381 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1382 break;
1383 case 0x08 ... 0x0d:
1384 or: /* or */
05f086f8 1385 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1386 break;
1387 case 0x10 ... 0x15:
1388 adc: /* adc */
05f086f8 1389 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1390 break;
1391 case 0x18 ... 0x1d:
1392 sbb: /* sbb */
05f086f8 1393 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1394 break;
19eb938e 1395 case 0x20 ... 0x23:
6aa8b732 1396 and: /* and */
05f086f8 1397 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732 1398 break;
19eb938e 1399 case 0x24: /* and al imm8 */
e4e03ded
LV		 1400 c->dst.type = OP_REG;
1401 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1402 c->dst.val = *(u8 *)c->dst.ptr;
1403 c->dst.bytes = 1;
1404 c->dst.orig_val = c->dst.val;
19eb938e
NK		 1405 goto and;
1406 case 0x25: /* and ax imm16, or eax imm32 */
e4e03ded
LV		 1407 c->dst.type = OP_REG;
1408 c->dst.bytes = c->op_bytes;
1409 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1410 if (c->op_bytes == 2)
1411 c->dst.val = *(u16 *)c->dst.ptr;
19eb938e 1412 else
e4e03ded
LV		 1413 c->dst.val = *(u32 *)c->dst.ptr;
1414 c->dst.orig_val = c->dst.val;
19eb938e 1415 goto and;
6aa8b732
AK		 1416 case 0x28 ... 0x2d:
1417 sub: /* sub */
05f086f8 1418 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1419 break;
1420 case 0x30 ... 0x35:
1421 xor: /* xor */
05f086f8 1422 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1423 break;
1424 case 0x38 ... 0x3d:
1425 cmp: /* cmp */
05f086f8 1426 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 1427 break;
33615aa9
AK		 1428 case 0x40 ... 0x47: /* inc r16/r32 */
1429 emulate_1op("inc", c->dst, ctxt->eflags);
1430 break;
1431 case 0x48 ... 0x4f: /* dec r16/r32 */
1432 emulate_1op("dec", c->dst, ctxt->eflags);
1433 break;
1434 case 0x50 ... 0x57: /* push reg */
1435 c->dst.type = OP_MEM;
1436 c->dst.bytes = c->op_bytes;
1437 c->dst.val = c->src.val;
7a957275 1438 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
33615aa9
AK		 1439 -c->op_bytes);
1440 c->dst.ptr = (void *) register_address(
7a5b56df 1441 c, ss_base(ctxt), c->regs[VCPU_REGS_RSP]);
33615aa9
AK		 1442 break;
1443 case 0x58 ... 0x5f: /* pop reg */
1444 pop_instruction:
7a5b56df 1445 if ((rc = ops->read_std(register_address(c, ss_base(ctxt),
33615aa9
AK		 1446 c->regs[VCPU_REGS_RSP]), c->dst.ptr,
1447 c->op_bytes, ctxt->vcpu)) != 0)
1448 goto done;
1449
7a957275 1450 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
33615aa9
AK		 1451 c->op_bytes);
1452 c->dst.type = OP_NONE; /* Disable writeback. */
1453 break;
6aa8b732 1454 case 0x63: /* movsxd */
8b4caf66 1455 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1456 goto cannot_emulate;
e4e03ded 1457 c->dst.val = (s32) c->src.val;
6aa8b732 1458 break;
91ed7a0e 1459 case 0x68: /* push imm */
018a98db 1460 case 0x6a: /* push imm8 */
018a98db
AK		 1461 emulate_push(ctxt);
1462 break;
1463 case 0x6c: /* insb */
1464 case 0x6d: /* insw/insd */
1465 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1466 1,
1467 (c->d & ByteOp) ? 1 : c->op_bytes,
1468 c->rep_prefix ?
e4706772 1469 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1470 (ctxt->eflags & EFLG_DF),
7a5b56df 1471 register_address(c, es_base(ctxt),
018a98db
AK		 1472 c->regs[VCPU_REGS_RDI]),
1473 c->rep_prefix,
1474 c->regs[VCPU_REGS_RDX]) == 0) {
1475 c->eip = saved_eip;
1476 return -1;
1477 }
1478 return 0;
1479 case 0x6e: /* outsb */
1480 case 0x6f: /* outsw/outsd */
1481 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1482 0,
1483 (c->d & ByteOp) ? 1 : c->op_bytes,
1484 c->rep_prefix ?
e4706772 1485 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1486 (ctxt->eflags & EFLG_DF),
7a5b56df
AK		 1487 register_address(c,
1488 seg_override_base(ctxt, c),
018a98db
AK		 1489 c->regs[VCPU_REGS_RSI]),
1490 c->rep_prefix,
1491 c->regs[VCPU_REGS_RDX]) == 0) {
1492 c->eip = saved_eip;
1493 return -1;
1494 }
1495 return 0;
1496 case 0x70 ... 0x7f: /* jcc (short) */ {
1497 int rel = insn_fetch(s8, 1, c->eip);
1498
1499 if (test_cc(c->b, ctxt->eflags))
7a957275 1500 jmp_rel(c, rel);
018a98db
AK		 1501 break;
1502 }
6aa8b732 1503 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 1504 switch (c->modrm_reg) {
6aa8b732
AK		 1505 case 0:
1506 goto add;
1507 case 1:
1508 goto or;
1509 case 2:
1510 goto adc;
1511 case 3:
1512 goto sbb;
1513 case 4:
1514 goto and;
1515 case 5:
1516 goto sub;
1517 case 6:
1518 goto xor;
1519 case 7:
1520 goto cmp;
1521 }
1522 break;
1523 case 0x84 ... 0x85:
05f086f8 1524 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1525 break;
1526 case 0x86 ... 0x87: /* xchg */
b13354f8 1527 xchg:
6aa8b732 1528 /* Write back the register source. */
e4e03ded 1529 switch (c->dst.bytes) {
6aa8b732 1530 case 1:
e4e03ded 1531 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 1532 break;
1533 case 2:
e4e03ded 1534 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 1535 break;
1536 case 4:
e4e03ded 1537 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 1538 break; /* 64b reg: zero-extend */
1539 case 8:
e4e03ded 1540 *c->src.ptr = c->dst.val;
6aa8b732
AK		 1541 break;
1542 }
1543 /*
1544 * Write back the memory destination with implicit LOCK
1545 * prefix.
1546 */
e4e03ded
LV		 1547 c->dst.val = c->src.val;
1548 c->lock_prefix = 1;
6aa8b732 1549 break;
6aa8b732 1550 case 0x88 ... 0x8b: /* mov */
7de75248 1551 goto mov;
38d5bc6d
GT		 1552 case 0x8c: { /* mov r/m, sreg */
1553 struct kvm_segment segreg;
1554
1555 if (c->modrm_reg <= 5)
1556 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
1557 else {
1558 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
1559 c->modrm);
1560 goto cannot_emulate;
1561 }
1562 c->dst.val = segreg.selector;
1563 break;
1564 }
7e0b54b1 1565 case 0x8d: /* lea r16/r32, m */
f9b7aab3 1566 c->dst.val = c->modrm_ea;
7e0b54b1 1567 break;
4257198a
GT		 1568 case 0x8e: { /* mov seg, r/m16 */
1569 uint16_t sel;
1570 int type_bits;
1571 int err;
1572
1573 sel = c->src.val;
1574 if (c->modrm_reg <= 5) {
1575 type_bits = (c->modrm_reg == 1) ? 9 : 1;
1576 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
1577 type_bits, c->modrm_reg);
1578 } else {
1579 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
1580 c->modrm);
1581 goto cannot_emulate;
1582 }
1583
1584 if (err < 0)
1585 goto cannot_emulate;
1586
1587 c->dst.type = OP_NONE; /* Disable writeback. */
1588 break;
1589 }
6aa8b732 1590 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 1591 rc = emulate_grp1a(ctxt, ops);
1592 if (rc != 0)
6aa8b732 1593 goto done;
6aa8b732 1594 break;
b13354f8
MG		 1595 case 0x90: /* nop / xchg r8,rax */
1596 if (!(c->rex_prefix & 1)) { /* nop */
1597 c->dst.type = OP_NONE;
1598 break;
1599 }
1600 case 0x91 ... 0x97: /* xchg reg,rax */
1601 c->src.type = c->dst.type = OP_REG;
1602 c->src.bytes = c->dst.bytes = c->op_bytes;
1603 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
1604 c->src.val = *(c->src.ptr);
1605 goto xchg;
fd2a7608 1606 case 0x9c: /* pushf */
05f086f8 1607 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 1608 emulate_push(ctxt);
1609 break;
535eabcf 1610 case 0x9d: /* popf */
05f086f8 1611 c->dst.ptr = (unsigned long *) &ctxt->eflags;
535eabcf 1612 goto pop_instruction;
018a98db
AK		 1613 case 0xa0 ... 0xa1: /* mov */
1614 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1615 c->dst.val = c->src.val;
1616 break;
1617 case 0xa2 ... 0xa3: /* mov */
1618 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1619 break;
6aa8b732 1620 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 1621 c->dst.type = OP_MEM;
1622 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1623 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1624 es_base(ctxt),
e4e03ded 1625 c->regs[VCPU_REGS_RDI]);
e4706772 1626 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 1627 seg_override_base(ctxt, c),
e4e03ded
LV		 1628 c->regs[VCPU_REGS_RSI]),
1629 &c->dst.val,
1630 c->dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1631 goto done;
7a957275 1632 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1633 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1634 : c->dst.bytes);
7a957275 1635 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1636 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1637 : c->dst.bytes);
6aa8b732
AK		 1638 break;
1639 case 0xa6 ... 0xa7: /* cmps */
d7e5117a
GT		 1640 c->src.type = OP_NONE; /* Disable writeback. */
1641 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1642 c->src.ptr = (unsigned long *)register_address(c,
7a5b56df 1643 seg_override_base(ctxt, c),
d7e5117a
GT		 1644 c->regs[VCPU_REGS_RSI]);
1645 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1646 &c->src.val,
1647 c->src.bytes,
1648 ctxt->vcpu)) != 0)
1649 goto done;
1650
1651 c->dst.type = OP_NONE; /* Disable writeback. */
1652 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1653 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1654 es_base(ctxt),
d7e5117a
GT		 1655 c->regs[VCPU_REGS_RDI]);
1656 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1657 &c->dst.val,
1658 c->dst.bytes,
1659 ctxt->vcpu)) != 0)
1660 goto done;
1661
1662 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1663
1664 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1665
7a957275 1666 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
d7e5117a
GT		 1667 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1668 : c->src.bytes);
7a957275 1669 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
d7e5117a
GT		 1670 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1671 : c->dst.bytes);
1672
1673 break;
6aa8b732 1674 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 1675 c->dst.type = OP_MEM;
1676 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1677 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1678 es_base(ctxt),
a7e6c88a 1679 c->regs[VCPU_REGS_RDI]);
e4e03ded 1680 c->dst.val = c->regs[VCPU_REGS_RAX];
7a957275 1681 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1682 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1683 : c->dst.bytes);
6aa8b732
AK		 1684 break;
1685 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 1686 c->dst.type = OP_REG;
1687 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1688 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
e4706772 1689 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 1690 seg_override_base(ctxt, c),
a7e6c88a
SY		 1691 c->regs[VCPU_REGS_RSI]),
1692 &c->dst.val,
1693 c->dst.bytes,
1694 ctxt->vcpu)) != 0)
6aa8b732 1695 goto done;
7a957275 1696 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1697 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1698 : c->dst.bytes);
6aa8b732
AK		 1699 break;
1700 case 0xae ... 0xaf: /* scas */
1701 DPRINTF("Urk! I don't handle SCAS.\n");
1702 goto cannot_emulate;
a5e2e82b 1703 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 1704 goto mov;
018a98db
AK		 1705 case 0xc0 ... 0xc1:
1706 emulate_grp2(ctxt);
1707 break;
111de5d6
AK		 1708 case 0xc3: /* ret */
1709 c->dst.ptr = &c->eip;
1710 goto pop_instruction;
018a98db
AK		 1711 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1712 mov:
1713 c->dst.val = c->src.val;
1714 break;
1715 case 0xd0 ... 0xd1: /* Grp2 */
1716 c->src.val = 1;
1717 emulate_grp2(ctxt);
1718 break;
1719 case 0xd2 ... 0xd3: /* Grp2 */
1720 c->src.val = c->regs[VCPU_REGS_RCX];
1721 emulate_grp2(ctxt);
1722 break;
a6a3034c
MG		 1723 case 0xe4: /* inb */
1724 case 0xe5: /* in */
1725 port = insn_fetch(u8, 1, c->eip);
1726 io_dir_in = 1;
1727 goto do_io;
1728 case 0xe6: /* outb */
1729 case 0xe7: /* out */
1730 port = insn_fetch(u8, 1, c->eip);
1731 io_dir_in = 0;
1732 goto do_io;
1a52e051
NK		 1733 case 0xe8: /* call (near) */ {
1734 long int rel;
e4e03ded 1735 switch (c->op_bytes) {
1a52e051 1736 case 2:
e4e03ded 1737 rel = insn_fetch(s16, 2, c->eip);
1a52e051
NK		 1738 break;
1739 case 4:
e4e03ded 1740 rel = insn_fetch(s32, 4, c->eip);
1a52e051 1741 break;
1a52e051
NK		 1742 default:
1743 DPRINTF("Call: Invalid op_bytes\n");
1744 goto cannot_emulate;
1745 }
e4e03ded 1746 c->src.val = (unsigned long) c->eip;
7a957275 1747 jmp_rel(c, rel);
e4e03ded 1748 c->op_bytes = c->ad_bytes;
8cdbd2c9
LV		 1749 emulate_push(ctxt);
1750 break;
1a52e051
NK		 1751 }
1752 case 0xe9: /* jmp rel */
954cd36f
GT		 1753 goto jmp;
1754 case 0xea: /* jmp far */ {
1755 uint32_t eip;
1756 uint16_t sel;
1757
1758 switch (c->op_bytes) {
1759 case 2:
1760 eip = insn_fetch(u16, 2, c->eip);
1761 break;
1762 case 4:
1763 eip = insn_fetch(u32, 4, c->eip);
1764 break;
1765 default:
1766 DPRINTF("jmp far: Invalid op_bytes\n");
1767 goto cannot_emulate;
1768 }
1769 sel = insn_fetch(u16, 2, c->eip);
1770 if (kvm_load_segment_descriptor(ctxt->vcpu, sel, 9, VCPU_SREG_CS) < 0) {
1771 DPRINTF("jmp far: Failed to load CS descriptor\n");
1772 goto cannot_emulate;
1773 }
1774
1775 c->eip = eip;
1776 break;
1777 }
1778 case 0xeb:
1779 jmp: /* jmp rel short */
7a957275 1780 jmp_rel(c, c->src.val);
a01af5ec 1781 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 1782 break;
a6a3034c
MG		 1783 case 0xec: /* in al,dx */
1784 case 0xed: /* in (e/r)ax,dx */
1785 port = c->regs[VCPU_REGS_RDX];
1786 io_dir_in = 1;
1787 goto do_io;
1788 case 0xee: /* out al,dx */
1789 case 0xef: /* out (e/r)ax,dx */
1790 port = c->regs[VCPU_REGS_RDX];
1791 io_dir_in = 0;
1792 do_io: if (kvm_emulate_pio(ctxt->vcpu, NULL, io_dir_in,
1793 (c->d & ByteOp) ? 1 : c->op_bytes,
1794 port) != 0) {
1795 c->eip = saved_eip;
1796 goto cannot_emulate;
1797 }
1798 return 0;
111de5d6 1799 case 0xf4: /* hlt */
ad312c7c 1800 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 1801 break;
111de5d6
AK		 1802 case 0xf5: /* cmc */
1803 /* complement carry flag from eflags reg */
1804 ctxt->eflags ^= EFLG_CF;
1805 c->dst.type = OP_NONE; /* Disable writeback. */
1806 break;
018a98db
AK		 1807 case 0xf6 ... 0xf7: /* Grp3 */
1808 rc = emulate_grp3(ctxt, ops);
1809 if (rc != 0)
1810 goto done;
1811 break;
111de5d6
AK		 1812 case 0xf8: /* clc */
1813 ctxt->eflags &= ~EFLG_CF;
1814 c->dst.type = OP_NONE; /* Disable writeback. */
1815 break;
1816 case 0xfa: /* cli */
1817 ctxt->eflags &= ~X86_EFLAGS_IF;
1818 c->dst.type = OP_NONE; /* Disable writeback. */
1819 break;
1820 case 0xfb: /* sti */
1821 ctxt->eflags |= X86_EFLAGS_IF;
1822 c->dst.type = OP_NONE; /* Disable writeback. */
1823 break;
fb4616f4
MG		 1824 case 0xfc: /* cld */
1825 ctxt->eflags &= ~EFLG_DF;
1826 c->dst.type = OP_NONE; /* Disable writeback. */
1827 break;
1828 case 0xfd: /* std */
1829 ctxt->eflags |= EFLG_DF;
1830 c->dst.type = OP_NONE; /* Disable writeback. */
1831 break;
018a98db
AK		 1832 case 0xfe ... 0xff: /* Grp4/Grp5 */
1833 rc = emulate_grp45(ctxt, ops);
1834 if (rc != 0)
1835 goto done;
1836 break;
6aa8b732 1837 }
018a98db
AK		 1838
1839writeback:
1840 rc = writeback(ctxt, ops);
1841 if (rc != 0)
1842 goto done;
1843
1844 /* Commit shadow register state. */
ad312c7c 1845 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
5fdbf976 1846 kvm_rip_write(ctxt->vcpu, c->eip);
018a98db
AK		 1847
1848done:
1849 if (rc == X86EMUL_UNHANDLEABLE) {
1850 c->eip = saved_eip;
1851 return -1;
1852 }
1853 return 0;
6aa8b732
AK		 1854
1855twobyte_insn:
e4e03ded 1856 switch (c->b) {
6aa8b732 1857 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 1858 switch (c->modrm_reg) {
6aa8b732
AK		 1859 u16 size;
1860 unsigned long address;
1861
aca7f966 1862 case 0: /* vmcall */
e4e03ded 1863 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 1864 goto cannot_emulate;
1865
7aa81cc0
AL		 1866 rc = kvm_fix_hypercall(ctxt->vcpu);
1867 if (rc)
1868 goto done;
1869
33e3885d 1870 /* Let the processor re-execute the fixed hypercall */
5fdbf976 1871 c->eip = kvm_rip_read(ctxt->vcpu);
16286d08
AK		 1872 /* Disable writeback. */
1873 c->dst.type = OP_NONE;
aca7f966 1874 break;
6aa8b732 1875 case 2: /* lgdt */
e4e03ded
LV		 1876 rc = read_descriptor(ctxt, ops, c->src.ptr,
1877 &size, &address, c->op_bytes);
6aa8b732
AK		 1878 if (rc)
1879 goto done;
1880 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 1881 /* Disable writeback. */
1882 c->dst.type = OP_NONE;
6aa8b732 1883 break;
aca7f966 1884 case 3: /* lidt/vmmcall */
e4e03ded 1885 if (c->modrm_mod == 3 && c->modrm_rm == 1) {
7aa81cc0
AL		 1886 rc = kvm_fix_hypercall(ctxt->vcpu);
1887 if (rc)
1888 goto done;
1889 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1890 } else {
e4e03ded 1891 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 1892 &size, &address,
e4e03ded 1893 c->op_bytes);
aca7f966
AL		 1894 if (rc)
1895 goto done;
1896 realmode_lidt(ctxt->vcpu, size, address);
1897 }
16286d08
AK		 1898 /* Disable writeback. */
1899 c->dst.type = OP_NONE;
6aa8b732
AK		 1900 break;
1901 case 4: /* smsw */
16286d08
AK		 1902 c->dst.bytes = 2;
1903 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
6aa8b732
AK		 1904 break;
1905 case 6: /* lmsw */
16286d08
AK		 1906 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
1907 &ctxt->eflags);
dc7457ea 1908 c->dst.type = OP_NONE;
6aa8b732
AK		 1909 break;
1910 case 7: /* invlpg*/
e8d8d7fe 1911 emulate_invlpg(ctxt->vcpu, memop);
16286d08
AK		 1912 /* Disable writeback. */
1913 c->dst.type = OP_NONE;
6aa8b732
AK		 1914 break;
1915 default:
1916 goto cannot_emulate;
1917 }
1918 break;
018a98db
AK		 1919 case 0x06:
1920 emulate_clts(ctxt->vcpu);
1921 c->dst.type = OP_NONE;
1922 break;
1923 case 0x08: /* invd */
1924 case 0x09: /* wbinvd */
1925 case 0x0d: /* GrpP (prefetch) */
1926 case 0x18: /* Grp16 (prefetch/nop) */
1927 c->dst.type = OP_NONE;
1928 break;
1929 case 0x20: /* mov cr, reg */
1930 if (c->modrm_mod != 3)
1931 goto cannot_emulate;
1932 c->regs[c->modrm_rm] =
1933 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1934 c->dst.type = OP_NONE; /* no writeback */
1935 break;
6aa8b732 1936 case 0x21: /* mov from dr to reg */
e4e03ded 1937 if (c->modrm_mod != 3)
6aa8b732 1938 goto cannot_emulate;
8cdbd2c9 1939 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 1940 if (rc)
1941 goto cannot_emulate;
1942 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1943 break;
018a98db
AK		 1944 case 0x22: /* mov reg, cr */
1945 if (c->modrm_mod != 3)
1946 goto cannot_emulate;
1947 realmode_set_cr(ctxt->vcpu,
1948 c->modrm_reg, c->modrm_val, &ctxt->eflags);
1949 c->dst.type = OP_NONE;
1950 break;
6aa8b732 1951 case 0x23: /* mov from reg to dr */
e4e03ded 1952 if (c->modrm_mod != 3)
6aa8b732 1953 goto cannot_emulate;
e4e03ded
LV		 1954 rc = emulator_set_dr(ctxt, c->modrm_reg,
1955 c->regs[c->modrm_rm]);
a01af5ec
LV		 1956 if (rc)
1957 goto cannot_emulate;
1958 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1959 break;
018a98db
AK		 1960 case 0x30:
1961 /* wrmsr */
1962 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1963 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1964 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
1965 if (rc) {
c1a5d4f9 1966 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 1967 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 1968 }
1969 rc = X86EMUL_CONTINUE;
1970 c->dst.type = OP_NONE;
1971 break;
1972 case 0x32:
1973 /* rdmsr */
1974 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
1975 if (rc) {
c1a5d4f9 1976 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 1977 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 1978 } else {
1979 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
1980 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
1981 }
1982 rc = X86EMUL_CONTINUE;
1983 c->dst.type = OP_NONE;
1984 break;
6aa8b732 1985 case 0x40 ... 0x4f: /* cmov */
e4e03ded 1986 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 1987 if (!test_cc(c->b, ctxt->eflags))
1988 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1989 break;
018a98db
AK		 1990 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1991 long int rel;
1992
1993 switch (c->op_bytes) {
1994 case 2:
1995 rel = insn_fetch(s16, 2, c->eip);
1996 break;
1997 case 4:
1998 rel = insn_fetch(s32, 4, c->eip);
1999 break;
2000 case 8:
2001 rel = insn_fetch(s64, 8, c->eip);
2002 break;
2003 default:
2004 DPRINTF("jnz: Invalid op_bytes\n");
2005 goto cannot_emulate;
2006 }
2007 if (test_cc(c->b, ctxt->eflags))
7a957275 2008 jmp_rel(c, rel);
018a98db
AK		 2009 c->dst.type = OP_NONE;
2010 break;
2011 }
7de75248
NK		 2012 case 0xa3:
2013 bt: /* bt */
e4f8e039 2014 c->dst.type = OP_NONE;
e4e03ded
LV		 2015 /* only subword offset */
2016 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2017 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248
NK		 2018 break;
2019 case 0xab:
2020 bts: /* bts */
e4e03ded
LV		 2021 /* only subword offset */
2022 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2023 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 2024 break;
2a7c5b8b
GC		 2025 case 0xae: /* clflush */
2026 break;
6aa8b732
AK		 2027 case 0xb0 ... 0xb1: /* cmpxchg */
2028 /*
2029 * Save real source value, then compare EAX against
2030 * destination.
2031 */
e4e03ded
LV		 2032 c->src.orig_val = c->src.val;
2033 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 2034 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2035 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 2036 /* Success: write back to memory. */
e4e03ded 2037 c->dst.val = c->src.orig_val;
6aa8b732
AK		 2038 } else {
2039 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 2040 c->dst.type = OP_REG;
2041 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2042 }
2043 break;
6aa8b732
AK		 2044 case 0xb3:
2045 btr: /* btr */
e4e03ded
LV		 2046 /* only subword offset */
2047 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2048 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 2049 break;
6aa8b732 2050 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 2051 c->dst.bytes = c->op_bytes;
2052 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
2053 : (u16) c->src.val;
6aa8b732 2054 break;
6aa8b732 2055 case 0xba: /* Grp8 */
e4e03ded 2056 switch (c->modrm_reg & 3) {
6aa8b732
AK		 2057 case 0:
2058 goto bt;
2059 case 1:
2060 goto bts;
2061 case 2:
2062 goto btr;
2063 case 3:
2064 goto btc;
2065 }
2066 break;
7de75248
NK		 2067 case 0xbb:
2068 btc: /* btc */
e4e03ded
LV		 2069 /* only subword offset */
2070 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2071 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 2072 break;
6aa8b732 2073 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 2074 c->dst.bytes = c->op_bytes;
2075 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
2076 (s16) c->src.val;
6aa8b732 2077 break;
a012e65a 2078 case 0xc3: /* movnti */
e4e03ded
LV		 2079 c->dst.bytes = c->op_bytes;
2080 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
2081 (u64) c->src.val;
a012e65a 2082 break;
6aa8b732 2083 case 0xc7: /* Grp9 (cmpxchg8b) */
e8d8d7fe 2084 rc = emulate_grp9(ctxt, ops, memop);
8cdbd2c9
LV		 2085 if (rc != 0)
2086 goto done;
018a98db 2087 c->dst.type = OP_NONE;
8cdbd2c9 2088 break;
6aa8b732
AK		 2089 }
2090 goto writeback;
2091
2092cannot_emulate:
e4e03ded 2093 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 2094 c->eip = saved_eip;
6aa8b732
AK		 2095 return -1;
2096}
Linux kernel - Deliverables
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