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KVM: x86 emulator: Add decoding of 16bit second immediate argument
[deliverable/linux.git] / arch / x86 / kvm / x86_emulate.c
CommitLineData
6aa8b732
AK		 1/******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
5fdbf976 29#include "kvm_cache_regs.h"
6aa8b732
AK		 30#define DPRINTF(x...) do {} while (0)
31#endif
6aa8b732 32#include <linux/module.h>
edf88417 33#include <asm/kvm_x86_emulate.h>
6aa8b732
AK		 34
35/*
36 * Opcode effective-address decode tables.
37 * Note that we only emulate instructions that have at least one memory
38 * operand (excluding implicit stack references). We assume that stack
39 * references and instruction fetches will never occur in special memory
40 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
41 * not be handled.
42 */
43
44/* Operand sizes: 8-bit operands or specified/overridden size. */
45#define ByteOp (1<<0) /* 8-bit operands. */
46/* Destination operand type. */
47#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
48#define DstReg (2<<1) /* Register operand. */
49#define DstMem (3<<1) /* Memory operand. */
9c9fddd0
GT		 50#define DstAcc (4<<1) /* Destination Accumulator */
51#define DstMask (7<<1)
6aa8b732 52/* Source operand type. */
9c9fddd0
GT		 53#define SrcNone (0<<4) /* No source operand. */
54#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
55#define SrcReg (1<<4) /* Register operand. */
56#define SrcMem (2<<4) /* Memory operand. */
57#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
58#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
59#define SrcImm (5<<4) /* Immediate operand. */
60#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 61#define SrcOne (7<<4) /* Implied '1' */
9c9fddd0 62#define SrcMask (7<<4)
6aa8b732 63/* Generic ModRM decode. */
9c9fddd0 64#define ModRM (1<<7)
6aa8b732 65/* Destination is only written; never read. */
9c9fddd0
GT		 66#define Mov (1<<8)
67#define BitOp (1<<9)
68#define MemAbs (1<<10) /* Memory operand is absolute displacement */
69#define String (1<<12) /* String instruction (rep capable) */
70#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 71#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
72#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
73#define GroupMask 0xff /* Group number stored in bits 0:7 */
0dc8d10f
GT		 74/* Source 2 operand type */
75#define Src2None (0<<29)
76#define Src2CL (1<<29)
77#define Src2ImmByte (2<<29)
78#define Src2One (3<<29)
a5f868bd 79#define Src2Imm16 (4<<29)
0dc8d10f 80#define Src2Mask (7<<29)
6aa8b732 81
43bb19cd 82enum {
1d6ad207 83 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 84 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
43bb19cd
AK		 85};
86
45ed60b3 87static u32 opcode_table[256] = {
6aa8b732
AK		 88 /* 0x00 - 0x07 */
89 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
90 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
291fd39b 91 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, 0, 0,
6aa8b732
AK		 92 /* 0x08 - 0x0F */
93 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
94 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
95 0, 0, 0, 0,
96 /* 0x10 - 0x17 */
97 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
98 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
99 0, 0, 0, 0,
100 /* 0x18 - 0x1F */
101 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
102 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
103 0, 0, 0, 0,
104 /* 0x20 - 0x27 */
105 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
106 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
aa3a816b 107 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732
AK		 108 /* 0x28 - 0x2F */
109 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
110 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
111 0, 0, 0, 0,
112 /* 0x30 - 0x37 */
113 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
114 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
115 0, 0, 0, 0,
116 /* 0x38 - 0x3F */
117 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
118 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
8a9fee67
GT		 119 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
120 0, 0,
d77a2507 121 /* 0x40 - 0x47 */
33615aa9 122 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 123 /* 0x48 - 0x4F */
33615aa9 124 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 125 /* 0x50 - 0x57 */
6e3d5dfb
AK		 126 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
127 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 128 /* 0x58 - 0x5F */
6e3d5dfb
AK		 129 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
130 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 131 /* 0x60 - 0x67 */
6aa8b732 132 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 133 0, 0, 0, 0,
134 /* 0x68 - 0x6F */
91ed7a0e 135 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
e70669ab
LV		 136 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
137 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4
NK		 138 /* 0x70 - 0x77 */
139 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
140 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
141 /* 0x78 - 0x7F */
142 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
143 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732 144 /* 0x80 - 0x87 */
1d6ad207
AK		 145 Group | Group1_80, Group | Group1_81,
146 Group | Group1_82, Group | Group1_83,
6aa8b732
AK		 147 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
148 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
149 /* 0x88 - 0x8F */
150 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
151 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
38d5bc6d 152 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
4257198a 153 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
b13354f8
MG		 154 /* 0x90 - 0x97 */
155 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
156 /* 0x98 - 0x9F */
6e3d5dfb 157 0, 0, 0, 0, ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 158 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 159 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
160 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
b9fa9d6b
AK		 161 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
162 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 163 /* 0xA8 - 0xAF */
b9fa9d6b
AK		 164 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
165 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
166 ByteOp | ImplicitOps | String, ImplicitOps | String,
a5e2e82b
MG		 167 /* 0xB0 - 0xB7 */
168 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
169 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
170 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
171 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
172 /* 0xB8 - 0xBF */
173 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
174 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
175 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
176 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
6aa8b732 177 /* 0xC0 - 0xC7 */
d9413cd7 178 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 179 0, ImplicitOps | Stack, 0, 0,
d9413cd7 180 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732 181 /* 0xC8 - 0xCF */
a77ab5ea 182 0, 0, 0, ImplicitOps | Stack, 0, 0, 0, 0,
6aa8b732
AK		 183 /* 0xD0 - 0xD7 */
184 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
185 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
186 0, 0, 0, 0,
187 /* 0xD8 - 0xDF */
188 0, 0, 0, 0, 0, 0, 0, 0,
098c937b 189 /* 0xE0 - 0xE7 */
a6a3034c
MG		 190 0, 0, 0, 0,
191 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
192 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
098c937b 193 /* 0xE8 - 0xEF */
954cd36f
GT		 194 ImplicitOps | Stack, SrcImm | ImplicitOps,
195 ImplicitOps, SrcImmByte | ImplicitOps,
a6a3034c
MG		 196 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
197 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
6aa8b732
AK		 198 /* 0xF0 - 0xF7 */
199 0, 0, 0, 0,
7d858a19 200 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 201 /* 0xF8 - 0xFF */
b284be57 202 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fb4616f4 203 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
6aa8b732
AK		 204};
205
45ed60b3 206static u32 twobyte_table[256] = {
6aa8b732 207 /* 0x00 - 0x0F */
d95058a1 208 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
651a3e29 209 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 210 /* 0x10 - 0x1F */
211 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
212 /* 0x20 - 0x2F */
213 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
214 0, 0, 0, 0, 0, 0, 0, 0,
215 /* 0x30 - 0x3F */
35f3f286 216 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 217 /* 0x40 - 0x47 */
218 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
219 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
220 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
221 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
222 /* 0x48 - 0x4F */
223 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
224 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
225 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
226 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
227 /* 0x50 - 0x5F */
228 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
229 /* 0x60 - 0x6F */
230 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
231 /* 0x70 - 0x7F */
232 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
233 /* 0x80 - 0x8F */
bbe9abbd
NK		 234 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
235 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
236 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
237 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 238 /* 0x90 - 0x9F */
239 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
240 /* 0xA0 - 0xA7 */
9bf8ea42
GT		 241 0, 0, 0, DstMem | SrcReg | ModRM | BitOp,
242 DstMem | SrcReg | Src2ImmByte | ModRM,
243 DstMem | SrcReg | Src2CL | ModRM, 0, 0,
6aa8b732 244 /* 0xA8 - 0xAF */
9bf8ea42
GT		 245 0, 0, 0, DstMem | SrcReg | ModRM | BitOp,
246 DstMem | SrcReg | Src2ImmByte | ModRM,
247 DstMem | SrcReg | Src2CL | ModRM,
248 ModRM, 0,
6aa8b732
AK		 249 /* 0xB0 - 0xB7 */
250 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 251 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 252 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
253 DstReg | SrcMem16 | ModRM | Mov,
254 /* 0xB8 - 0xBF */
038e51de 255 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 256 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
257 DstReg | SrcMem16 | ModRM | Mov,
258 /* 0xC0 - 0xCF */
a012e65a
SY		 259 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
260 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 261 /* 0xD0 - 0xDF */
262 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
263 /* 0xE0 - 0xEF */
264 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
265 /* 0xF0 - 0xFF */
266 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
267};
268
45ed60b3 269static u32 group_table[] = {
1d6ad207
AK		 270 [Group1_80*8] =
271 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
272 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
273 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
274 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
275 [Group1_81*8] =
276 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
277 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
278 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
279 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
280 [Group1_82*8] =
281 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
282 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
283 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
284 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
285 [Group1_83*8] =
286 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
287 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
288 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
289 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 290 [Group1A*8] =
291 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 292 [Group3_Byte*8] =
293 ByteOp | SrcImm | DstMem | ModRM, 0,
294 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
295 0, 0, 0, 0,
296 [Group3*8] =
41afa025 297 DstMem | SrcImm | ModRM, 0,
6eb06cb2 298 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
7d858a19 299 0, 0, 0, 0,
fd60754e
AK		 300 [Group4*8] =
301 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
302 0, 0, 0, 0, 0, 0,
303 [Group5*8] =
d19292e4
MG		 304 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
305 SrcMem | ModRM | Stack, 0,
ef46f18e 306 SrcMem | ModRM | Stack, 0, SrcMem | ModRM | Stack, 0,
d95058a1
AK		 307 [Group7*8] =
308 0, 0, ModRM | SrcMem, ModRM | SrcMem,
16286d08
AK		 309 SrcNone | ModRM | DstMem | Mov, 0,
310 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
e09d082c
AK		 311};
312
45ed60b3 313static u32 group2_table[] = {
d95058a1 314 [Group7*8] =
fbce554e 315 SrcNone | ModRM, 0, 0, SrcNone | ModRM,
16286d08
AK		 316 SrcNone | ModRM | DstMem | Mov, 0,
317 SrcMem16 | ModRM | Mov, 0,
e09d082c
AK		 318};
319
6aa8b732
AK		 320/* EFLAGS bit definitions. */
321#define EFLG_OF (1<<11)
322#define EFLG_DF (1<<10)
323#define EFLG_SF (1<<7)
324#define EFLG_ZF (1<<6)
325#define EFLG_AF (1<<4)
326#define EFLG_PF (1<<2)
327#define EFLG_CF (1<<0)
328
329/*
330 * Instruction emulation:
331 * Most instructions are emulated directly via a fragment of inline assembly
332 * code. This allows us to save/restore EFLAGS and thus very easily pick up
333 * any modified flags.
334 */
335
05b3e0c2 336#if defined(CONFIG_X86_64)
6aa8b732
AK		 337#define _LO32 "k" /* force 32-bit operand */
338#define _STK "%%rsp" /* stack pointer */
339#elif defined(__i386__)
340#define _LO32 "" /* force 32-bit operand */
341#define _STK "%%esp" /* stack pointer */
342#endif
343
344/*
345 * These EFLAGS bits are restored from saved value during emulation, and
346 * any changes are written back to the saved value after emulation.
347 */
348#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
349
350/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 351#define _PRE_EFLAGS(_sav, _msk, _tmp) \
352 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
353 "movl %"_sav",%"_LO32 _tmp"; " \
354 "push %"_tmp"; " \
355 "push %"_tmp"; " \
356 "movl %"_msk",%"_LO32 _tmp"; " \
357 "andl %"_LO32 _tmp",("_STK"); " \
358 "pushf; " \
359 "notl %"_LO32 _tmp"; " \
360 "andl %"_LO32 _tmp",("_STK"); " \
361 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
362 "pop %"_tmp"; " \
363 "orl %"_LO32 _tmp",("_STK"); " \
364 "popf; " \
365 "pop %"_sav"; "
6aa8b732
AK		 366
367/* After executing instruction: write-back necessary bits in EFLAGS. */
368#define _POST_EFLAGS(_sav, _msk, _tmp) \
369 /* _sav |= EFLAGS & _msk; */ \
370 "pushf; " \
371 "pop %"_tmp"; " \
372 "andl %"_msk",%"_LO32 _tmp"; " \
373 "orl %"_LO32 _tmp",%"_sav"; "
374
dda96d8f
AK		 375#ifdef CONFIG_X86_64
376#define ON64(x) x
377#else
378#define ON64(x)
379#endif
380
6b7ad61f
AK		 381#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
382 do { \
383 __asm__ __volatile__ ( \
384 _PRE_EFLAGS("0", "4", "2") \
385 _op _suffix " %"_x"3,%1; " \
386 _POST_EFLAGS("0", "4", "2") \
387 : "=m" (_eflags), "=m" ((_dst).val), \
388 "=&r" (_tmp) \
389 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 390 } while (0)
6b7ad61f
AK		 391
392
6aa8b732
AK		 393/* Raw emulation: instruction has two explicit operands. */
394#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 395 do { \
396 unsigned long _tmp; \
397 \
398 switch ((_dst).bytes) { \
399 case 2: \
400 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
401 break; \
402 case 4: \
403 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
404 break; \
405 case 8: \
406 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
407 break; \
408 } \
6aa8b732
AK		 409 } while (0)
410
411#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
412 do { \
6b7ad61f 413 unsigned long _tmp; \
d77c26fc 414 switch ((_dst).bytes) { \
6aa8b732 415 case 1: \
6b7ad61f 416 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 417 break; \
418 default: \
419 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
420 _wx, _wy, _lx, _ly, _qx, _qy); \
421 break; \
422 } \
423 } while (0)
424
425/* Source operand is byte-sized and may be restricted to just %cl. */
426#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
427 __emulate_2op(_op, _src, _dst, _eflags, \
428 "b", "c", "b", "c", "b", "c", "b", "c")
429
430/* Source operand is byte, word, long or quad sized. */
431#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
432 __emulate_2op(_op, _src, _dst, _eflags, \
433 "b", "q", "w", "r", _LO32, "r", "", "r")
434
435/* Source operand is word, long or quad sized. */
436#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
437 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
438 "w", "r", _LO32, "r", "", "r")
439
d175226a
GT		 440/* Instruction has three operands and one operand is stored in ECX register */
441#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
442 do { \
443 unsigned long _tmp; \
444 _type _clv = (_cl).val; \
445 _type _srcv = (_src).val; \
446 _type _dstv = (_dst).val; \
447 \
448 __asm__ __volatile__ ( \
449 _PRE_EFLAGS("0", "5", "2") \
450 _op _suffix " %4,%1 \n" \
451 _POST_EFLAGS("0", "5", "2") \
452 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
453 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
454 ); \
455 \
456 (_cl).val = (unsigned long) _clv; \
457 (_src).val = (unsigned long) _srcv; \
458 (_dst).val = (unsigned long) _dstv; \
459 } while (0)
460
461#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
462 do { \
463 switch ((_dst).bytes) { \
464 case 2: \
465 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
466 "w", unsigned short); \
467 break; \
468 case 4: \
469 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
470 "l", unsigned int); \
471 break; \
472 case 8: \
473 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
474 "q", unsigned long)); \
475 break; \
476 } \
477 } while (0)
478
dda96d8f 479#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 480 do { \
481 unsigned long _tmp; \
482 \
dda96d8f
AK		 483 __asm__ __volatile__ ( \
484 _PRE_EFLAGS("0", "3", "2") \
485 _op _suffix " %1; " \
486 _POST_EFLAGS("0", "3", "2") \
487 : "=m" (_eflags), "+m" ((_dst).val), \
488 "=&r" (_tmp) \
489 : "i" (EFLAGS_MASK)); \
490 } while (0)
491
492/* Instruction has only one explicit operand (no source operand). */
493#define emulate_1op(_op, _dst, _eflags) \
494 do { \
d77c26fc 495 switch ((_dst).bytes) { \
dda96d8f
AK		 496 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
497 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
498 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
499 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 500 } \
501 } while (0)
502
6aa8b732
AK		 503/* Fetch next part of the instruction being emulated. */
504#define insn_fetch(_type, _size, _eip) \
505({ unsigned long _x; \
62266869 506 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
d77c26fc 507 if (rc != 0) \
6aa8b732
AK		 508 goto done; \
509 (_eip) += (_size); \
510 (_type)_x; \
511})
512
ddcb2885
HH		 513static inline unsigned long ad_mask(struct decode_cache *c)
514{
515 return (1UL << (c->ad_bytes << 3)) - 1;
516}
517
6aa8b732 518/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 519static inline unsigned long
520address_mask(struct decode_cache *c, unsigned long reg)
521{
522 if (c->ad_bytes == sizeof(unsigned long))
523 return reg;
524 else
525 return reg & ad_mask(c);
526}
527
528static inline unsigned long
529register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
530{
531 return base + address_mask(c, reg);
532}
533
7a957275
HH		 534static inline void
535register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
536{
537 if (c->ad_bytes == sizeof(unsigned long))
538 *reg += inc;
539 else
540 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
541}
6aa8b732 542
7a957275
HH		 543static inline void jmp_rel(struct decode_cache *c, int rel)
544{
545 register_address_increment(c, &c->eip, rel);
546}
098c937b 547
7a5b56df
AK		 548static void set_seg_override(struct decode_cache *c, int seg)
549{
550 c->has_seg_override = true;
551 c->seg_override = seg;
552}
553
554static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
555{
556 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
557 return 0;
558
559 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
560}
561
562static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
563 struct decode_cache *c)
564{
565 if (!c->has_seg_override)
566 return 0;
567
568 return seg_base(ctxt, c->seg_override);
569}
570
571static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
572{
573 return seg_base(ctxt, VCPU_SREG_ES);
574}
575
576static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
577{
578 return seg_base(ctxt, VCPU_SREG_SS);
579}
580
62266869
AK		 581static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
582 struct x86_emulate_ops *ops,
583 unsigned long linear, u8 *dest)
584{
585 struct fetch_cache *fc = &ctxt->decode.fetch;
586 int rc;
587 int size;
588
589 if (linear < fc->start || linear >= fc->end) {
590 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
591 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
592 if (rc)
593 return rc;
594 fc->start = linear;
595 fc->end = linear + size;
596 }
597 *dest = fc->data[linear - fc->start];
598 return 0;
599}
600
601static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
602 struct x86_emulate_ops *ops,
603 unsigned long eip, void *dest, unsigned size)
604{
605 int rc = 0;
606
607 eip += ctxt->cs_base;
608 while (size--) {
609 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
610 if (rc)
611 return rc;
612 }
613 return 0;
614}
615
1e3c5cb0
RR		 616/*
617 * Given the 'reg' portion of a ModRM byte, and a register block, return a
618 * pointer into the block that addresses the relevant register.
619 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
620 */
621static void *decode_register(u8 modrm_reg, unsigned long *regs,
622 int highbyte_regs)
6aa8b732
AK		 623{
624 void *p;
625
626 p = &regs[modrm_reg];
627 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
628 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
629 return p;
630}
631
632static int read_descriptor(struct x86_emulate_ctxt *ctxt,
633 struct x86_emulate_ops *ops,
634 void *ptr,
635 u16 *size, unsigned long *address, int op_bytes)
636{
637 int rc;
638
639 if (op_bytes == 2)
640 op_bytes = 3;
641 *address = 0;
cebff02b
LV		 642 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
643 ctxt->vcpu);
6aa8b732
AK		 644 if (rc)
645 return rc;
cebff02b
LV		 646 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
647 ctxt->vcpu);
6aa8b732
AK		 648 return rc;
649}
650
bbe9abbd
NK		 651static int test_cc(unsigned int condition, unsigned int flags)
652{
653 int rc = 0;
654
655 switch ((condition & 15) >> 1) {
656 case 0: /* o */
657 rc |= (flags & EFLG_OF);
658 break;
659 case 1: /* b/c/nae */
660 rc |= (flags & EFLG_CF);
661 break;
662 case 2: /* z/e */
663 rc |= (flags & EFLG_ZF);
664 break;
665 case 3: /* be/na */
666 rc |= (flags & (EFLG_CF|EFLG_ZF));
667 break;
668 case 4: /* s */
669 rc |= (flags & EFLG_SF);
670 break;
671 case 5: /* p/pe */
672 rc |= (flags & EFLG_PF);
673 break;
674 case 7: /* le/ng */
675 rc |= (flags & EFLG_ZF);
676 /* fall through */
677 case 6: /* l/nge */
678 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
679 break;
680 }
681
682 /* Odd condition identifiers (lsb == 1) have inverted sense. */
683 return (!!rc ^ (condition & 1));
684}
685
3c118e24
AK		 686static void decode_register_operand(struct operand *op,
687 struct decode_cache *c,
3c118e24
AK		 688 int inhibit_bytereg)
689{
33615aa9 690 unsigned reg = c->modrm_reg;
9f1ef3f8 691 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 692
693 if (!(c->d & ModRM))
694 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 695 op->type = OP_REG;
696 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 697 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 698 op->val = *(u8 *)op->ptr;
699 op->bytes = 1;
700 } else {
33615aa9 701 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 702 op->bytes = c->op_bytes;
703 switch (op->bytes) {
704 case 2:
705 op->val = *(u16 *)op->ptr;
706 break;
707 case 4:
708 op->val = *(u32 *)op->ptr;
709 break;
710 case 8:
711 op->val = *(u64 *) op->ptr;
712 break;
713 }
714 }
715 op->orig_val = op->val;
716}
717
1c73ef66
AK		 718static int decode_modrm(struct x86_emulate_ctxt *ctxt,
719 struct x86_emulate_ops *ops)
720{
721 struct decode_cache *c = &ctxt->decode;
722 u8 sib;
f5b4edcd 723 int index_reg = 0, base_reg = 0, scale;
1c73ef66
AK		 724 int rc = 0;
725
726 if (c->rex_prefix) {
727 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
728 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
729 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
730 }
731
732 c->modrm = insn_fetch(u8, 1, c->eip);
733 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
734 c->modrm_reg |= (c->modrm & 0x38) >> 3;
735 c->modrm_rm |= (c->modrm & 0x07);
736 c->modrm_ea = 0;
737 c->use_modrm_ea = 1;
738
739 if (c->modrm_mod == 3) {
107d6d2e
AK		 740 c->modrm_ptr = decode_register(c->modrm_rm,
741 c->regs, c->d & ByteOp);
742 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 743 return rc;
744 }
745
746 if (c->ad_bytes == 2) {
747 unsigned bx = c->regs[VCPU_REGS_RBX];
748 unsigned bp = c->regs[VCPU_REGS_RBP];
749 unsigned si = c->regs[VCPU_REGS_RSI];
750 unsigned di = c->regs[VCPU_REGS_RDI];
751
752 /* 16-bit ModR/M decode. */
753 switch (c->modrm_mod) {
754 case 0:
755 if (c->modrm_rm == 6)
756 c->modrm_ea += insn_fetch(u16, 2, c->eip);
757 break;
758 case 1:
759 c->modrm_ea += insn_fetch(s8, 1, c->eip);
760 break;
761 case 2:
762 c->modrm_ea += insn_fetch(u16, 2, c->eip);
763 break;
764 }
765 switch (c->modrm_rm) {
766 case 0:
767 c->modrm_ea += bx + si;
768 break;
769 case 1:
770 c->modrm_ea += bx + di;
771 break;
772 case 2:
773 c->modrm_ea += bp + si;
774 break;
775 case 3:
776 c->modrm_ea += bp + di;
777 break;
778 case 4:
779 c->modrm_ea += si;
780 break;
781 case 5:
782 c->modrm_ea += di;
783 break;
784 case 6:
785 if (c->modrm_mod != 0)
786 c->modrm_ea += bp;
787 break;
788 case 7:
789 c->modrm_ea += bx;
790 break;
791 }
792 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
793 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 794 if (!c->has_seg_override)
795 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 796 c->modrm_ea = (u16)c->modrm_ea;
797 } else {
798 /* 32/64-bit ModR/M decode. */
84411d85 799 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 800 sib = insn_fetch(u8, 1, c->eip);
801 index_reg |= (sib >> 3) & 7;
802 base_reg |= sib & 7;
803 scale = sib >> 6;
804
dc71d0f1
AK		 805 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
806 c->modrm_ea += insn_fetch(s32, 4, c->eip);
807 else
1c73ef66 808 c->modrm_ea += c->regs[base_reg];
dc71d0f1 809 if (index_reg != 4)
1c73ef66 810 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 811 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
812 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 813 c->rip_relative = 1;
84411d85 814 } else
1c73ef66 815 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 816 switch (c->modrm_mod) {
817 case 0:
818 if (c->modrm_rm == 5)
819 c->modrm_ea += insn_fetch(s32, 4, c->eip);
820 break;
821 case 1:
822 c->modrm_ea += insn_fetch(s8, 1, c->eip);
823 break;
824 case 2:
825 c->modrm_ea += insn_fetch(s32, 4, c->eip);
826 break;
827 }
828 }
1c73ef66
AK		 829done:
830 return rc;
831}
832
833static int decode_abs(struct x86_emulate_ctxt *ctxt,
834 struct x86_emulate_ops *ops)
835{
836 struct decode_cache *c = &ctxt->decode;
837 int rc = 0;
838
839 switch (c->ad_bytes) {
840 case 2:
841 c->modrm_ea = insn_fetch(u16, 2, c->eip);
842 break;
843 case 4:
844 c->modrm_ea = insn_fetch(u32, 4, c->eip);
845 break;
846 case 8:
847 c->modrm_ea = insn_fetch(u64, 8, c->eip);
848 break;
849 }
850done:
851 return rc;
852}
853
6aa8b732 854int
8b4caf66 855x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 856{
e4e03ded 857 struct decode_cache *c = &ctxt->decode;
6aa8b732 858 int rc = 0;
6aa8b732 859 int mode = ctxt->mode;
e09d082c 860 int def_op_bytes, def_ad_bytes, group;
6aa8b732
AK		 861
862 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 863
e4e03ded 864 memset(c, 0, sizeof(struct decode_cache));
5fdbf976 865 c->eip = kvm_rip_read(ctxt->vcpu);
7a5b56df 866 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
ad312c7c 867 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 868
869 switch (mode) {
870 case X86EMUL_MODE_REAL:
871 case X86EMUL_MODE_PROT16:
f21b8bf4 872 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 873 break;
874 case X86EMUL_MODE_PROT32:
f21b8bf4 875 def_op_bytes = def_ad_bytes = 4;
6aa8b732 876 break;
05b3e0c2 877#ifdef CONFIG_X86_64
6aa8b732 878 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 879 def_op_bytes = 4;
880 def_ad_bytes = 8;
6aa8b732
AK		 881 break;
882#endif
883 default:
884 return -1;
885 }
886
f21b8bf4
AK		 887 c->op_bytes = def_op_bytes;
888 c->ad_bytes = def_ad_bytes;
889
6aa8b732 890 /* Legacy prefixes. */
b4c6abfe 891 for (;;) {
e4e03ded 892 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 893 case 0x66: /* operand-size override */
f21b8bf4
AK		 894 /* switch between 2/4 bytes */
895 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 896 break;
897 case 0x67: /* address-size override */
898 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 899 /* switch between 4/8 bytes */
f21b8bf4 900 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 901 else
e4e03ded 902 /* switch between 2/4 bytes */
f21b8bf4 903 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 904 break;
7a5b56df 905 case 0x26: /* ES override */
6aa8b732 906 case 0x2e: /* CS override */
7a5b56df 907 case 0x36: /* SS override */
6aa8b732 908 case 0x3e: /* DS override */
7a5b56df 909 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 910 break;
911 case 0x64: /* FS override */
6aa8b732 912 case 0x65: /* GS override */
7a5b56df 913 set_seg_override(c, c->b & 7);
6aa8b732 914 break;
b4c6abfe
LV		 915 case 0x40 ... 0x4f: /* REX */
916 if (mode != X86EMUL_MODE_PROT64)
917 goto done_prefixes;
33615aa9 918 c->rex_prefix = c->b;
b4c6abfe 919 continue;
6aa8b732 920 case 0xf0: /* LOCK */
e4e03ded 921 c->lock_prefix = 1;
6aa8b732 922 break;
ae6200ba 923 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 924 c->rep_prefix = REPNE_PREFIX;
925 break;
6aa8b732 926 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 927 c->rep_prefix = REPE_PREFIX;
6aa8b732 928 break;
6aa8b732
AK		 929 default:
930 goto done_prefixes;
931 }
b4c6abfe
LV		 932
933 /* Any legacy prefix after a REX prefix nullifies its effect. */
934
33615aa9 935 c->rex_prefix = 0;
6aa8b732
AK		 936 }
937
938done_prefixes:
939
940 /* REX prefix. */
1c73ef66 941 if (c->rex_prefix)
33615aa9 942 if (c->rex_prefix & 8)
e4e03ded 943 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 944
945 /* Opcode byte(s). */
e4e03ded
LV		 946 c->d = opcode_table[c->b];
947 if (c->d == 0) {
6aa8b732 948 /* Two-byte opcode? */
e4e03ded
LV		 949 if (c->b == 0x0f) {
950 c->twobyte = 1;
951 c->b = insn_fetch(u8, 1, c->eip);
952 c->d = twobyte_table[c->b];
6aa8b732 953 }
e09d082c 954 }
6aa8b732 955
e09d082c
AK		 956 if (c->d & Group) {
957 group = c->d & GroupMask;
958 c->modrm = insn_fetch(u8, 1, c->eip);
959 --c->eip;
960
961 group = (group << 3) + ((c->modrm >> 3) & 7);
962 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
963 c->d = group2_table[group];
964 else
965 c->d = group_table[group];
966 }
967
968 /* Unrecognised? */
969 if (c->d == 0) {
970 DPRINTF("Cannot emulate %02x\n", c->b);
971 return -1;
6aa8b732
AK		 972 }
973
6e3d5dfb
AK		 974 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
975 c->op_bytes = 8;
976
6aa8b732 977 /* ModRM and SIB bytes. */
1c73ef66
AK		 978 if (c->d & ModRM)
979 rc = decode_modrm(ctxt, ops);
980 else if (c->d & MemAbs)
981 rc = decode_abs(ctxt, ops);
982 if (rc)
983 goto done;
6aa8b732 984
7a5b56df
AK		 985 if (!c->has_seg_override)
986 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 987
7a5b56df
AK		 988 if (!(!c->twobyte && c->b == 0x8d))
989 c->modrm_ea += seg_override_base(ctxt, c);
c7e75a3d
AK		 990
991 if (c->ad_bytes != 8)
992 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 993 /*
994 * Decode and fetch the source operand: register, memory
995 * or immediate.
996 */
e4e03ded 997 switch (c->d & SrcMask) {
6aa8b732
AK		 998 case SrcNone:
999 break;
1000 case SrcReg:
9f1ef3f8 1001 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 1002 break;
1003 case SrcMem16:
e4e03ded 1004 c->src.bytes = 2;
6aa8b732
AK		 1005 goto srcmem_common;
1006 case SrcMem32:
e4e03ded 1007 c->src.bytes = 4;
6aa8b732
AK		 1008 goto srcmem_common;
1009 case SrcMem:
e4e03ded
LV		 1010 c->src.bytes = (c->d & ByteOp) ? 1 :
1011 c->op_bytes;
b85b9ee9 1012 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1013 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1014 break;
d77c26fc 1015 srcmem_common:
4e62417b
AJ		 1016 /*
1017 * For instructions with a ModR/M byte, switch to register
1018 * access if Mod = 3.
1019 */
e4e03ded
LV		 1020 if ((c->d & ModRM) && c->modrm_mod == 3) {
1021 c->src.type = OP_REG;
66b85505 1022 c->src.val = c->modrm_val;
107d6d2e 1023 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1024 break;
1025 }
e4e03ded 1026 c->src.type = OP_MEM;
6aa8b732
AK		 1027 break;
1028 case SrcImm:
e4e03ded
LV		 1029 c->src.type = OP_IMM;
1030 c->src.ptr = (unsigned long *)c->eip;
1031 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1032 if (c->src.bytes == 8)
1033 c->src.bytes = 4;
6aa8b732 1034 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1035 switch (c->src.bytes) {
6aa8b732 1036 case 1:
e4e03ded 1037 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1038 break;
1039 case 2:
e4e03ded 1040 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1041 break;
1042 case 4:
e4e03ded 1043 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1044 break;
1045 }
1046 break;
1047 case SrcImmByte:
e4e03ded
LV		 1048 c->src.type = OP_IMM;
1049 c->src.ptr = (unsigned long *)c->eip;
1050 c->src.bytes = 1;
1051 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732 1052 break;
bfcadf83
GT		 1053 case SrcOne:
1054 c->src.bytes = 1;
1055 c->src.val = 1;
1056 break;
6aa8b732
AK		 1057 }
1058
0dc8d10f
GT		 1059 /*
1060 * Decode and fetch the second source operand: register, memory
1061 * or immediate.
1062 */
1063 switch (c->d & Src2Mask) {
1064 case Src2None:
1065 break;
1066 case Src2CL:
1067 c->src2.bytes = 1;
1068 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1069 break;
1070 case Src2ImmByte:
1071 c->src2.type = OP_IMM;
1072 c->src2.ptr = (unsigned long *)c->eip;
1073 c->src2.bytes = 1;
1074 c->src2.val = insn_fetch(u8, 1, c->eip);
1075 break;
a5f868bd
GN		 1076 case Src2Imm16:
1077 c->src2.type = OP_IMM;
1078 c->src2.ptr = (unsigned long *)c->eip;
1079 c->src2.bytes = 2;
1080 c->src2.val = insn_fetch(u16, 2, c->eip);
1081 break;
0dc8d10f
GT		 1082 case Src2One:
1083 c->src2.bytes = 1;
1084 c->src2.val = 1;
1085 break;
1086 }
1087
038e51de 1088 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1089 switch (c->d & DstMask) {
038e51de
AK		 1090 case ImplicitOps:
1091 /* Special instructions do their own operand decoding. */
8b4caf66 1092 return 0;
038e51de 1093 case DstReg:
9f1ef3f8 1094 decode_register_operand(&c->dst, c,
3c118e24 1095 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1096 break;
1097 case DstMem:
e4e03ded 1098 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1099 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1100 c->dst.type = OP_REG;
66b85505 1101 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1102 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1103 break;
1104 }
8b4caf66
LV		 1105 c->dst.type = OP_MEM;
1106 break;
9c9fddd0
GT		 1107 case DstAcc:
1108 c->dst.type = OP_REG;
1109 c->dst.bytes = c->op_bytes;
1110 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1111 switch (c->op_bytes) {
1112 case 1:
1113 c->dst.val = *(u8 *)c->dst.ptr;
1114 break;
1115 case 2:
1116 c->dst.val = *(u16 *)c->dst.ptr;
1117 break;
1118 case 4:
1119 c->dst.val = *(u32 *)c->dst.ptr;
1120 break;
1121 }
1122 c->dst.orig_val = c->dst.val;
1123 break;
8b4caf66
LV		 1124 }
1125
f5b4edcd
AK		 1126 if (c->rip_relative)
1127 c->modrm_ea += c->eip;
1128
8b4caf66
LV		 1129done:
1130 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1131}
1132
8cdbd2c9
LV		 1133static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1134{
1135 struct decode_cache *c = &ctxt->decode;
1136
1137 c->dst.type = OP_MEM;
1138 c->dst.bytes = c->op_bytes;
1139 c->dst.val = c->src.val;
7a957275 1140 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
7a5b56df 1141 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1142 c->regs[VCPU_REGS_RSP]);
1143}
1144
faa5a3ae 1145static int emulate_pop(struct x86_emulate_ctxt *ctxt,
350f69dc
AK		 1146 struct x86_emulate_ops *ops,
1147 void *dest, int len)
8cdbd2c9
LV		 1148{
1149 struct decode_cache *c = &ctxt->decode;
1150 int rc;
1151
781d0edc
AK		 1152 rc = ops->read_emulated(register_address(c, ss_base(ctxt),
1153 c->regs[VCPU_REGS_RSP]),
350f69dc 1154 dest, len, ctxt->vcpu);
8cdbd2c9
LV		 1155 if (rc != 0)
1156 return rc;
1157
350f69dc 1158 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
faa5a3ae
AK		 1159 return rc;
1160}
8cdbd2c9 1161
faa5a3ae
AK		 1162static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1163 struct x86_emulate_ops *ops)
1164{
1165 struct decode_cache *c = &ctxt->decode;
1166 int rc;
1167
350f69dc 1168 rc = emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
faa5a3ae
AK		 1169 if (rc != 0)
1170 return rc;
8cdbd2c9
LV		 1171 return 0;
1172}
1173
05f086f8 1174static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1175{
05f086f8 1176 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1177 switch (c->modrm_reg) {
1178 case 0: /* rol */
05f086f8 1179 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1180 break;
1181 case 1: /* ror */
05f086f8 1182 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1183 break;
1184 case 2: /* rcl */
05f086f8 1185 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1186 break;
1187 case 3: /* rcr */
05f086f8 1188 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1189 break;
1190 case 4: /* sal/shl */
1191 case 6: /* sal/shl */
05f086f8 1192 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1193 break;
1194 case 5: /* shr */
05f086f8 1195 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1196 break;
1197 case 7: /* sar */
05f086f8 1198 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1199 break;
1200 }
1201}
1202
1203static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1204 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1205{
1206 struct decode_cache *c = &ctxt->decode;
1207 int rc = 0;
1208
1209 switch (c->modrm_reg) {
1210 case 0 ... 1: /* test */
05f086f8 1211 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1212 break;
1213 case 2: /* not */
1214 c->dst.val = ~c->dst.val;
1215 break;
1216 case 3: /* neg */
05f086f8 1217 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1218 break;
1219 default:
1220 DPRINTF("Cannot emulate %02x\n", c->b);
1221 rc = X86EMUL_UNHANDLEABLE;
1222 break;
1223 }
8cdbd2c9
LV		 1224 return rc;
1225}
1226
1227static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1228 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1229{
1230 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1231
1232 switch (c->modrm_reg) {
1233 case 0: /* inc */
05f086f8 1234 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1235 break;
1236 case 1: /* dec */
05f086f8 1237 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1238 break;
d19292e4
MG		 1239 case 2: /* call near abs */ {
1240 long int old_eip;
1241 old_eip = c->eip;
1242 c->eip = c->src.val;
1243 c->src.val = old_eip;
1244 emulate_push(ctxt);
1245 break;
1246 }
8cdbd2c9 1247 case 4: /* jmp abs */
fd60754e 1248 c->eip = c->src.val;
8cdbd2c9
LV		 1249 break;
1250 case 6: /* push */
fd60754e 1251 emulate_push(ctxt);
8cdbd2c9 1252 break;
8cdbd2c9
LV		 1253 }
1254 return 0;
1255}
1256
1257static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1258 struct x86_emulate_ops *ops,
e8d8d7fe 1259 unsigned long memop)
8cdbd2c9
LV		 1260{
1261 struct decode_cache *c = &ctxt->decode;
1262 u64 old, new;
1263 int rc;
1264
e8d8d7fe 1265 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
8cdbd2c9
LV		 1266 if (rc != 0)
1267 return rc;
1268
1269 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1270 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1271
1272 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1273 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1274 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1275
1276 } else {
1277 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1278 (u32) c->regs[VCPU_REGS_RBX];
1279
e8d8d7fe 1280 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
8cdbd2c9
LV		 1281 if (rc != 0)
1282 return rc;
05f086f8 1283 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1284 }
1285 return 0;
1286}
1287
a77ab5ea
AK		 1288static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1289 struct x86_emulate_ops *ops)
1290{
1291 struct decode_cache *c = &ctxt->decode;
1292 int rc;
1293 unsigned long cs;
1294
1295 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1296 if (rc)
1297 return rc;
1298 if (c->op_bytes == 4)
1299 c->eip = (u32)c->eip;
1300 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1301 if (rc)
1302 return rc;
1303 rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)cs, 1, VCPU_SREG_CS);
1304 return rc;
1305}
1306
8cdbd2c9
LV		 1307static inline int writeback(struct x86_emulate_ctxt *ctxt,
1308 struct x86_emulate_ops *ops)
1309{
1310 int rc;
1311 struct decode_cache *c = &ctxt->decode;
1312
1313 switch (c->dst.type) {
1314 case OP_REG:
1315 /* The 4-byte case *is* correct:
1316 * in 64-bit mode we zero-extend.
1317 */
1318 switch (c->dst.bytes) {
1319 case 1:
1320 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1321 break;
1322 case 2:
1323 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1324 break;
1325 case 4:
1326 *c->dst.ptr = (u32)c->dst.val;
1327 break; /* 64b: zero-ext */
1328 case 8:
1329 *c->dst.ptr = c->dst.val;
1330 break;
1331 }
1332 break;
1333 case OP_MEM:
1334 if (c->lock_prefix)
1335 rc = ops->cmpxchg_emulated(
1336 (unsigned long)c->dst.ptr,
1337 &c->dst.orig_val,
1338 &c->dst.val,
1339 c->dst.bytes,
1340 ctxt->vcpu);
1341 else
1342 rc = ops->write_emulated(
1343 (unsigned long)c->dst.ptr,
1344 &c->dst.val,
1345 c->dst.bytes,
1346 ctxt->vcpu);
1347 if (rc != 0)
1348 return rc;
a01af5ec
LV		 1349 break;
1350 case OP_NONE:
1351 /* no writeback */
1352 break;
8cdbd2c9
LV		 1353 default:
1354 break;
1355 }
1356 return 0;
1357}
1358
8b4caf66 1359int
1be3aa47 1360x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 1361{
e8d8d7fe 1362 unsigned long memop = 0;
8b4caf66 1363 u64 msr_data;
3427318f 1364 unsigned long saved_eip = 0;
8b4caf66 1365 struct decode_cache *c = &ctxt->decode;
a6a3034c
MG		 1366 unsigned int port;
1367 int io_dir_in;
1be3aa47 1368 int rc = 0;
8b4caf66 1369
3427318f
LV		 1370 /* Shadow copy of register state. Committed on successful emulation.
1371 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1372 * modify them.
1373 */
1374
ad312c7c 1375 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f
LV		 1376 saved_eip = c->eip;
1377
c7e75a3d 1378 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
e8d8d7fe 1379 memop = c->modrm_ea;
8b4caf66 1380
b9fa9d6b
AK		 1381 if (c->rep_prefix && (c->d & String)) {
1382 /* All REP prefixes have the same first termination condition */
1383 if (c->regs[VCPU_REGS_RCX] == 0) {
5fdbf976 1384 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1385 goto done;
1386 }
1387 /* The second termination condition only applies for REPE
1388 * and REPNE. Test if the repeat string operation prefix is
1389 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1390 * corresponding termination condition according to:
1391 * - if REPE/REPZ and ZF = 0 then done
1392 * - if REPNE/REPNZ and ZF = 1 then done
1393 */
1394 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1395 (c->b == 0xae) || (c->b == 0xaf)) {
1396 if ((c->rep_prefix == REPE_PREFIX) &&
1397 ((ctxt->eflags & EFLG_ZF) == 0)) {
5fdbf976 1398 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1399 goto done;
1400 }
1401 if ((c->rep_prefix == REPNE_PREFIX) &&
1402 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
5fdbf976 1403 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1404 goto done;
1405 }
1406 }
1407 c->regs[VCPU_REGS_RCX]--;
5fdbf976 1408 c->eip = kvm_rip_read(ctxt->vcpu);
b9fa9d6b
AK		 1409 }
1410
8b4caf66 1411 if (c->src.type == OP_MEM) {
e8d8d7fe 1412 c->src.ptr = (unsigned long *)memop;
8b4caf66 1413 c->src.val = 0;
d77c26fc
MD		 1414 rc = ops->read_emulated((unsigned long)c->src.ptr,
1415 &c->src.val,
1416 c->src.bytes,
1417 ctxt->vcpu);
1418 if (rc != 0)
8b4caf66
LV		 1419 goto done;
1420 c->src.orig_val = c->src.val;
1421 }
1422
1423 if ((c->d & DstMask) == ImplicitOps)
1424 goto special_insn;
1425
1426
1427 if (c->dst.type == OP_MEM) {
e8d8d7fe 1428 c->dst.ptr = (unsigned long *)memop;
8b4caf66
LV		 1429 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1430 c->dst.val = 0;
e4e03ded
LV		 1431 if (c->d & BitOp) {
1432 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1433
e4e03ded
LV		 1434 c->dst.ptr = (void *)c->dst.ptr +
1435 (c->src.val & mask) / 8;
038e51de 1436 }
e4e03ded
LV		 1437 if (!(c->d & Mov) &&
1438 /* optimisation - avoid slow emulated read */
1439 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1440 &c->dst.val,
1441 c->dst.bytes, ctxt->vcpu)) != 0))
038e51de 1442 goto done;
038e51de 1443 }
e4e03ded 1444 c->dst.orig_val = c->dst.val;
038e51de 1445
018a98db
AK		 1446special_insn:
1447
e4e03ded 1448 if (c->twobyte)
6aa8b732
AK		 1449 goto twobyte_insn;
1450
e4e03ded 1451 switch (c->b) {
6aa8b732
AK		 1452 case 0x00 ... 0x05:
1453 add: /* add */
05f086f8 1454 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1455 break;
1456 case 0x08 ... 0x0d:
1457 or: /* or */
05f086f8 1458 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1459 break;
1460 case 0x10 ... 0x15:
1461 adc: /* adc */
05f086f8 1462 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1463 break;
1464 case 0x18 ... 0x1d:
1465 sbb: /* sbb */
05f086f8 1466 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1467 break;
aa3a816b 1468 case 0x20 ... 0x25:
6aa8b732 1469 and: /* and */
05f086f8 1470 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1471 break;
1472 case 0x28 ... 0x2d:
1473 sub: /* sub */
05f086f8 1474 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1475 break;
1476 case 0x30 ... 0x35:
1477 xor: /* xor */
05f086f8 1478 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1479 break;
1480 case 0x38 ... 0x3d:
1481 cmp: /* cmp */
05f086f8 1482 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 1483 break;
33615aa9
AK		 1484 case 0x40 ... 0x47: /* inc r16/r32 */
1485 emulate_1op("inc", c->dst, ctxt->eflags);
1486 break;
1487 case 0x48 ... 0x4f: /* dec r16/r32 */
1488 emulate_1op("dec", c->dst, ctxt->eflags);
1489 break;
1490 case 0x50 ... 0x57: /* push reg */
2786b014 1491 emulate_push(ctxt);
33615aa9
AK		 1492 break;
1493 case 0x58 ... 0x5f: /* pop reg */
1494 pop_instruction:
350f69dc 1495 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
8a09b687 1496 if (rc != 0)
33615aa9 1497 goto done;
33615aa9 1498 break;
6aa8b732 1499 case 0x63: /* movsxd */
8b4caf66 1500 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1501 goto cannot_emulate;
e4e03ded 1502 c->dst.val = (s32) c->src.val;
6aa8b732 1503 break;
91ed7a0e 1504 case 0x68: /* push imm */
018a98db 1505 case 0x6a: /* push imm8 */
018a98db
AK		 1506 emulate_push(ctxt);
1507 break;
1508 case 0x6c: /* insb */
1509 case 0x6d: /* insw/insd */
1510 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1511 1,
1512 (c->d & ByteOp) ? 1 : c->op_bytes,
1513 c->rep_prefix ?
e4706772 1514 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1515 (ctxt->eflags & EFLG_DF),
7a5b56df 1516 register_address(c, es_base(ctxt),
018a98db
AK		 1517 c->regs[VCPU_REGS_RDI]),
1518 c->rep_prefix,
1519 c->regs[VCPU_REGS_RDX]) == 0) {
1520 c->eip = saved_eip;
1521 return -1;
1522 }
1523 return 0;
1524 case 0x6e: /* outsb */
1525 case 0x6f: /* outsw/outsd */
1526 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1527 0,
1528 (c->d & ByteOp) ? 1 : c->op_bytes,
1529 c->rep_prefix ?
e4706772 1530 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1531 (ctxt->eflags & EFLG_DF),
7a5b56df
AK		 1532 register_address(c,
1533 seg_override_base(ctxt, c),
018a98db
AK		 1534 c->regs[VCPU_REGS_RSI]),
1535 c->rep_prefix,
1536 c->regs[VCPU_REGS_RDX]) == 0) {
1537 c->eip = saved_eip;
1538 return -1;
1539 }
1540 return 0;
1541 case 0x70 ... 0x7f: /* jcc (short) */ {
1542 int rel = insn_fetch(s8, 1, c->eip);
1543
1544 if (test_cc(c->b, ctxt->eflags))
7a957275 1545 jmp_rel(c, rel);
018a98db
AK		 1546 break;
1547 }
6aa8b732 1548 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 1549 switch (c->modrm_reg) {
6aa8b732
AK		 1550 case 0:
1551 goto add;
1552 case 1:
1553 goto or;
1554 case 2:
1555 goto adc;
1556 case 3:
1557 goto sbb;
1558 case 4:
1559 goto and;
1560 case 5:
1561 goto sub;
1562 case 6:
1563 goto xor;
1564 case 7:
1565 goto cmp;
1566 }
1567 break;
1568 case 0x84 ... 0x85:
05f086f8 1569 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1570 break;
1571 case 0x86 ... 0x87: /* xchg */
b13354f8 1572 xchg:
6aa8b732 1573 /* Write back the register source. */
e4e03ded 1574 switch (c->dst.bytes) {
6aa8b732 1575 case 1:
e4e03ded 1576 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 1577 break;
1578 case 2:
e4e03ded 1579 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 1580 break;
1581 case 4:
e4e03ded 1582 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 1583 break; /* 64b reg: zero-extend */
1584 case 8:
e4e03ded 1585 *c->src.ptr = c->dst.val;
6aa8b732
AK		 1586 break;
1587 }
1588 /*
1589 * Write back the memory destination with implicit LOCK
1590 * prefix.
1591 */
e4e03ded
LV		 1592 c->dst.val = c->src.val;
1593 c->lock_prefix = 1;
6aa8b732 1594 break;
6aa8b732 1595 case 0x88 ... 0x8b: /* mov */
7de75248 1596 goto mov;
38d5bc6d
GT		 1597 case 0x8c: { /* mov r/m, sreg */
1598 struct kvm_segment segreg;
1599
1600 if (c->modrm_reg <= 5)
1601 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
1602 else {
1603 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
1604 c->modrm);
1605 goto cannot_emulate;
1606 }
1607 c->dst.val = segreg.selector;
1608 break;
1609 }
7e0b54b1 1610 case 0x8d: /* lea r16/r32, m */
f9b7aab3 1611 c->dst.val = c->modrm_ea;
7e0b54b1 1612 break;
4257198a
GT		 1613 case 0x8e: { /* mov seg, r/m16 */
1614 uint16_t sel;
1615 int type_bits;
1616 int err;
1617
1618 sel = c->src.val;
1619 if (c->modrm_reg <= 5) {
1620 type_bits = (c->modrm_reg == 1) ? 9 : 1;
1621 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
1622 type_bits, c->modrm_reg);
1623 } else {
1624 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
1625 c->modrm);
1626 goto cannot_emulate;
1627 }
1628
1629 if (err < 0)
1630 goto cannot_emulate;
1631
1632 c->dst.type = OP_NONE; /* Disable writeback. */
1633 break;
1634 }
6aa8b732 1635 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 1636 rc = emulate_grp1a(ctxt, ops);
1637 if (rc != 0)
6aa8b732 1638 goto done;
6aa8b732 1639 break;
b13354f8
MG		 1640 case 0x90: /* nop / xchg r8,rax */
1641 if (!(c->rex_prefix & 1)) { /* nop */
1642 c->dst.type = OP_NONE;
1643 break;
1644 }
1645 case 0x91 ... 0x97: /* xchg reg,rax */
1646 c->src.type = c->dst.type = OP_REG;
1647 c->src.bytes = c->dst.bytes = c->op_bytes;
1648 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
1649 c->src.val = *(c->src.ptr);
1650 goto xchg;
fd2a7608 1651 case 0x9c: /* pushf */
05f086f8 1652 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 1653 emulate_push(ctxt);
1654 break;
535eabcf 1655 case 0x9d: /* popf */
2b48cc75 1656 c->dst.type = OP_REG;
05f086f8 1657 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2b48cc75 1658 c->dst.bytes = c->op_bytes;
535eabcf 1659 goto pop_instruction;
018a98db
AK		 1660 case 0xa0 ... 0xa1: /* mov */
1661 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1662 c->dst.val = c->src.val;
1663 break;
1664 case 0xa2 ... 0xa3: /* mov */
1665 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1666 break;
6aa8b732 1667 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 1668 c->dst.type = OP_MEM;
1669 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1670 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1671 es_base(ctxt),
e4e03ded 1672 c->regs[VCPU_REGS_RDI]);
e4706772 1673 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 1674 seg_override_base(ctxt, c),
e4e03ded
LV		 1675 c->regs[VCPU_REGS_RSI]),
1676 &c->dst.val,
1677 c->dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1678 goto done;
7a957275 1679 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1680 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1681 : c->dst.bytes);
7a957275 1682 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1683 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1684 : c->dst.bytes);
6aa8b732
AK		 1685 break;
1686 case 0xa6 ... 0xa7: /* cmps */
d7e5117a
GT		 1687 c->src.type = OP_NONE; /* Disable writeback. */
1688 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1689 c->src.ptr = (unsigned long *)register_address(c,
7a5b56df 1690 seg_override_base(ctxt, c),
d7e5117a
GT		 1691 c->regs[VCPU_REGS_RSI]);
1692 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1693 &c->src.val,
1694 c->src.bytes,
1695 ctxt->vcpu)) != 0)
1696 goto done;
1697
1698 c->dst.type = OP_NONE; /* Disable writeback. */
1699 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1700 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1701 es_base(ctxt),
d7e5117a
GT		 1702 c->regs[VCPU_REGS_RDI]);
1703 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1704 &c->dst.val,
1705 c->dst.bytes,
1706 ctxt->vcpu)) != 0)
1707 goto done;
1708
1709 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1710
1711 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1712
7a957275 1713 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
d7e5117a
GT		 1714 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1715 : c->src.bytes);
7a957275 1716 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
d7e5117a
GT		 1717 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1718 : c->dst.bytes);
1719
1720 break;
6aa8b732 1721 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 1722 c->dst.type = OP_MEM;
1723 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1724 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1725 es_base(ctxt),
a7e6c88a 1726 c->regs[VCPU_REGS_RDI]);
e4e03ded 1727 c->dst.val = c->regs[VCPU_REGS_RAX];
7a957275 1728 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1729 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1730 : c->dst.bytes);
6aa8b732
AK		 1731 break;
1732 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 1733 c->dst.type = OP_REG;
1734 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1735 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
e4706772 1736 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 1737 seg_override_base(ctxt, c),
a7e6c88a
SY		 1738 c->regs[VCPU_REGS_RSI]),
1739 &c->dst.val,
1740 c->dst.bytes,
1741 ctxt->vcpu)) != 0)
6aa8b732 1742 goto done;
7a957275 1743 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1744 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1745 : c->dst.bytes);
6aa8b732
AK		 1746 break;
1747 case 0xae ... 0xaf: /* scas */
1748 DPRINTF("Urk! I don't handle SCAS.\n");
1749 goto cannot_emulate;
a5e2e82b 1750 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 1751 goto mov;
018a98db
AK		 1752 case 0xc0 ... 0xc1:
1753 emulate_grp2(ctxt);
1754 break;
111de5d6 1755 case 0xc3: /* ret */
cf5de4f8 1756 c->dst.type = OP_REG;
111de5d6 1757 c->dst.ptr = &c->eip;
cf5de4f8 1758 c->dst.bytes = c->op_bytes;
111de5d6 1759 goto pop_instruction;
018a98db
AK		 1760 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1761 mov:
1762 c->dst.val = c->src.val;
1763 break;
a77ab5ea
AK		 1764 case 0xcb: /* ret far */
1765 rc = emulate_ret_far(ctxt, ops);
1766 if (rc)
1767 goto done;
1768 break;
018a98db
AK		 1769 case 0xd0 ... 0xd1: /* Grp2 */
1770 c->src.val = 1;
1771 emulate_grp2(ctxt);
1772 break;
1773 case 0xd2 ... 0xd3: /* Grp2 */
1774 c->src.val = c->regs[VCPU_REGS_RCX];
1775 emulate_grp2(ctxt);
1776 break;
a6a3034c
MG		 1777 case 0xe4: /* inb */
1778 case 0xe5: /* in */
1779 port = insn_fetch(u8, 1, c->eip);
1780 io_dir_in = 1;
1781 goto do_io;
1782 case 0xe6: /* outb */
1783 case 0xe7: /* out */
1784 port = insn_fetch(u8, 1, c->eip);
1785 io_dir_in = 0;
1786 goto do_io;
1a52e051
NK		 1787 case 0xe8: /* call (near) */ {
1788 long int rel;
e4e03ded 1789 switch (c->op_bytes) {
1a52e051 1790 case 2:
e4e03ded 1791 rel = insn_fetch(s16, 2, c->eip);
1a52e051
NK		 1792 break;
1793 case 4:
e4e03ded 1794 rel = insn_fetch(s32, 4, c->eip);
1a52e051 1795 break;
1a52e051
NK		 1796 default:
1797 DPRINTF("Call: Invalid op_bytes\n");
1798 goto cannot_emulate;
1799 }
e4e03ded 1800 c->src.val = (unsigned long) c->eip;
7a957275 1801 jmp_rel(c, rel);
8cdbd2c9
LV		 1802 emulate_push(ctxt);
1803 break;
1a52e051
NK		 1804 }
1805 case 0xe9: /* jmp rel */
954cd36f
GT		 1806 goto jmp;
1807 case 0xea: /* jmp far */ {
1808 uint32_t eip;
1809 uint16_t sel;
1810
1811 switch (c->op_bytes) {
1812 case 2:
1813 eip = insn_fetch(u16, 2, c->eip);
1814 break;
1815 case 4:
1816 eip = insn_fetch(u32, 4, c->eip);
1817 break;
1818 default:
1819 DPRINTF("jmp far: Invalid op_bytes\n");
1820 goto cannot_emulate;
1821 }
1822 sel = insn_fetch(u16, 2, c->eip);
1823 if (kvm_load_segment_descriptor(ctxt->vcpu, sel, 9, VCPU_SREG_CS) < 0) {
1824 DPRINTF("jmp far: Failed to load CS descriptor\n");
1825 goto cannot_emulate;
1826 }
1827
1828 c->eip = eip;
1829 break;
1830 }
1831 case 0xeb:
1832 jmp: /* jmp rel short */
7a957275 1833 jmp_rel(c, c->src.val);
a01af5ec 1834 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 1835 break;
a6a3034c
MG		 1836 case 0xec: /* in al,dx */
1837 case 0xed: /* in (e/r)ax,dx */
1838 port = c->regs[VCPU_REGS_RDX];
1839 io_dir_in = 1;
1840 goto do_io;
1841 case 0xee: /* out al,dx */
1842 case 0xef: /* out (e/r)ax,dx */
1843 port = c->regs[VCPU_REGS_RDX];
1844 io_dir_in = 0;
1845 do_io: if (kvm_emulate_pio(ctxt->vcpu, NULL, io_dir_in,
1846 (c->d & ByteOp) ? 1 : c->op_bytes,
1847 port) != 0) {
1848 c->eip = saved_eip;
1849 goto cannot_emulate;
1850 }
e93f36bc 1851 break;
111de5d6 1852 case 0xf4: /* hlt */
ad312c7c 1853 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 1854 break;
111de5d6
AK		 1855 case 0xf5: /* cmc */
1856 /* complement carry flag from eflags reg */
1857 ctxt->eflags ^= EFLG_CF;
1858 c->dst.type = OP_NONE; /* Disable writeback. */
1859 break;
018a98db
AK		 1860 case 0xf6 ... 0xf7: /* Grp3 */
1861 rc = emulate_grp3(ctxt, ops);
1862 if (rc != 0)
1863 goto done;
1864 break;
111de5d6
AK		 1865 case 0xf8: /* clc */
1866 ctxt->eflags &= ~EFLG_CF;
1867 c->dst.type = OP_NONE; /* Disable writeback. */
1868 break;
1869 case 0xfa: /* cli */
1870 ctxt->eflags &= ~X86_EFLAGS_IF;
1871 c->dst.type = OP_NONE; /* Disable writeback. */
1872 break;
1873 case 0xfb: /* sti */
1874 ctxt->eflags |= X86_EFLAGS_IF;
1875 c->dst.type = OP_NONE; /* Disable writeback. */
1876 break;
fb4616f4
MG		 1877 case 0xfc: /* cld */
1878 ctxt->eflags &= ~EFLG_DF;
1879 c->dst.type = OP_NONE; /* Disable writeback. */
1880 break;
1881 case 0xfd: /* std */
1882 ctxt->eflags |= EFLG_DF;
1883 c->dst.type = OP_NONE; /* Disable writeback. */
1884 break;
018a98db
AK		 1885 case 0xfe ... 0xff: /* Grp4/Grp5 */
1886 rc = emulate_grp45(ctxt, ops);
1887 if (rc != 0)
1888 goto done;
1889 break;
6aa8b732 1890 }
018a98db
AK		 1891
1892writeback:
1893 rc = writeback(ctxt, ops);
1894 if (rc != 0)
1895 goto done;
1896
1897 /* Commit shadow register state. */
ad312c7c 1898 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
5fdbf976 1899 kvm_rip_write(ctxt->vcpu, c->eip);
018a98db
AK		 1900
1901done:
1902 if (rc == X86EMUL_UNHANDLEABLE) {
1903 c->eip = saved_eip;
1904 return -1;
1905 }
1906 return 0;
6aa8b732
AK		 1907
1908twobyte_insn:
e4e03ded 1909 switch (c->b) {
6aa8b732 1910 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 1911 switch (c->modrm_reg) {
6aa8b732
AK		 1912 u16 size;
1913 unsigned long address;
1914
aca7f966 1915 case 0: /* vmcall */
e4e03ded 1916 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 1917 goto cannot_emulate;
1918
7aa81cc0
AL		 1919 rc = kvm_fix_hypercall(ctxt->vcpu);
1920 if (rc)
1921 goto done;
1922
33e3885d 1923 /* Let the processor re-execute the fixed hypercall */
5fdbf976 1924 c->eip = kvm_rip_read(ctxt->vcpu);
16286d08
AK		 1925 /* Disable writeback. */
1926 c->dst.type = OP_NONE;
aca7f966 1927 break;
6aa8b732 1928 case 2: /* lgdt */
e4e03ded
LV		 1929 rc = read_descriptor(ctxt, ops, c->src.ptr,
1930 &size, &address, c->op_bytes);
6aa8b732
AK		 1931 if (rc)
1932 goto done;
1933 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 1934 /* Disable writeback. */
1935 c->dst.type = OP_NONE;
6aa8b732 1936 break;
aca7f966 1937 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 1938 if (c->modrm_mod == 3) {
1939 switch (c->modrm_rm) {
1940 case 1:
1941 rc = kvm_fix_hypercall(ctxt->vcpu);
1942 if (rc)
1943 goto done;
1944 break;
1945 default:
1946 goto cannot_emulate;
1947 }
aca7f966 1948 } else {
e4e03ded 1949 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 1950 &size, &address,
e4e03ded 1951 c->op_bytes);
aca7f966
AL		 1952 if (rc)
1953 goto done;
1954 realmode_lidt(ctxt->vcpu, size, address);
1955 }
16286d08
AK		 1956 /* Disable writeback. */
1957 c->dst.type = OP_NONE;
6aa8b732
AK		 1958 break;
1959 case 4: /* smsw */
16286d08
AK		 1960 c->dst.bytes = 2;
1961 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
6aa8b732
AK		 1962 break;
1963 case 6: /* lmsw */
16286d08
AK		 1964 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
1965 &ctxt->eflags);
dc7457ea 1966 c->dst.type = OP_NONE;
6aa8b732
AK		 1967 break;
1968 case 7: /* invlpg*/
e8d8d7fe 1969 emulate_invlpg(ctxt->vcpu, memop);
16286d08
AK		 1970 /* Disable writeback. */
1971 c->dst.type = OP_NONE;
6aa8b732
AK		 1972 break;
1973 default:
1974 goto cannot_emulate;
1975 }
1976 break;
018a98db
AK		 1977 case 0x06:
1978 emulate_clts(ctxt->vcpu);
1979 c->dst.type = OP_NONE;
1980 break;
1981 case 0x08: /* invd */
1982 case 0x09: /* wbinvd */
1983 case 0x0d: /* GrpP (prefetch) */
1984 case 0x18: /* Grp16 (prefetch/nop) */
1985 c->dst.type = OP_NONE;
1986 break;
1987 case 0x20: /* mov cr, reg */
1988 if (c->modrm_mod != 3)
1989 goto cannot_emulate;
1990 c->regs[c->modrm_rm] =
1991 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1992 c->dst.type = OP_NONE; /* no writeback */
1993 break;
6aa8b732 1994 case 0x21: /* mov from dr to reg */
e4e03ded 1995 if (c->modrm_mod != 3)
6aa8b732 1996 goto cannot_emulate;
8cdbd2c9 1997 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 1998 if (rc)
1999 goto cannot_emulate;
2000 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 2001 break;
018a98db
AK		 2002 case 0x22: /* mov reg, cr */
2003 if (c->modrm_mod != 3)
2004 goto cannot_emulate;
2005 realmode_set_cr(ctxt->vcpu,
2006 c->modrm_reg, c->modrm_val, &ctxt->eflags);
2007 c->dst.type = OP_NONE;
2008 break;
6aa8b732 2009 case 0x23: /* mov from reg to dr */
e4e03ded 2010 if (c->modrm_mod != 3)
6aa8b732 2011 goto cannot_emulate;
e4e03ded
LV		 2012 rc = emulator_set_dr(ctxt, c->modrm_reg,
2013 c->regs[c->modrm_rm]);
a01af5ec
LV		 2014 if (rc)
2015 goto cannot_emulate;
2016 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 2017 break;
018a98db
AK		 2018 case 0x30:
2019 /* wrmsr */
2020 msr_data = (u32)c->regs[VCPU_REGS_RAX]
2021 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
2022 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
2023 if (rc) {
c1a5d4f9 2024 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 2025 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 2026 }
2027 rc = X86EMUL_CONTINUE;
2028 c->dst.type = OP_NONE;
2029 break;
2030 case 0x32:
2031 /* rdmsr */
2032 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
2033 if (rc) {
c1a5d4f9 2034 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 2035 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 2036 } else {
2037 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
2038 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
2039 }
2040 rc = X86EMUL_CONTINUE;
2041 c->dst.type = OP_NONE;
2042 break;
6aa8b732 2043 case 0x40 ... 0x4f: /* cmov */
e4e03ded 2044 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 2045 if (!test_cc(c->b, ctxt->eflags))
2046 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 2047 break;
018a98db
AK		 2048 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
2049 long int rel;
2050
2051 switch (c->op_bytes) {
2052 case 2:
2053 rel = insn_fetch(s16, 2, c->eip);
2054 break;
2055 case 4:
2056 rel = insn_fetch(s32, 4, c->eip);
2057 break;
2058 case 8:
2059 rel = insn_fetch(s64, 8, c->eip);
2060 break;
2061 default:
2062 DPRINTF("jnz: Invalid op_bytes\n");
2063 goto cannot_emulate;
2064 }
2065 if (test_cc(c->b, ctxt->eflags))
7a957275 2066 jmp_rel(c, rel);
018a98db
AK		 2067 c->dst.type = OP_NONE;
2068 break;
2069 }
7de75248
NK		 2070 case 0xa3:
2071 bt: /* bt */
e4f8e039 2072 c->dst.type = OP_NONE;
e4e03ded
LV		 2073 /* only subword offset */
2074 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2075 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 2076 break;
9bf8ea42
GT		 2077 case 0xa4: /* shld imm8, r, r/m */
2078 case 0xa5: /* shld cl, r, r/m */
2079 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
2080 break;
7de75248
NK		 2081 case 0xab:
2082 bts: /* bts */
e4e03ded
LV		 2083 /* only subword offset */
2084 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2085 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 2086 break;
9bf8ea42
GT		 2087 case 0xac: /* shrd imm8, r, r/m */
2088 case 0xad: /* shrd cl, r, r/m */
2089 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
2090 break;
2a7c5b8b
GC		 2091 case 0xae: /* clflush */
2092 break;
6aa8b732
AK		 2093 case 0xb0 ... 0xb1: /* cmpxchg */
2094 /*
2095 * Save real source value, then compare EAX against
2096 * destination.
2097 */
e4e03ded
LV		 2098 c->src.orig_val = c->src.val;
2099 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 2100 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2101 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 2102 /* Success: write back to memory. */
e4e03ded 2103 c->dst.val = c->src.orig_val;
6aa8b732
AK		 2104 } else {
2105 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 2106 c->dst.type = OP_REG;
2107 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2108 }
2109 break;
6aa8b732
AK		 2110 case 0xb3:
2111 btr: /* btr */
e4e03ded
LV		 2112 /* only subword offset */
2113 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2114 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 2115 break;
6aa8b732 2116 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 2117 c->dst.bytes = c->op_bytes;
2118 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
2119 : (u16) c->src.val;
6aa8b732 2120 break;
6aa8b732 2121 case 0xba: /* Grp8 */
e4e03ded 2122 switch (c->modrm_reg & 3) {
6aa8b732
AK		 2123 case 0:
2124 goto bt;
2125 case 1:
2126 goto bts;
2127 case 2:
2128 goto btr;
2129 case 3:
2130 goto btc;
2131 }
2132 break;
7de75248
NK		 2133 case 0xbb:
2134 btc: /* btc */
e4e03ded
LV		 2135 /* only subword offset */
2136 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2137 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 2138 break;
6aa8b732 2139 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 2140 c->dst.bytes = c->op_bytes;
2141 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
2142 (s16) c->src.val;
6aa8b732 2143 break;
a012e65a 2144 case 0xc3: /* movnti */
e4e03ded
LV		 2145 c->dst.bytes = c->op_bytes;
2146 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
2147 (u64) c->src.val;
a012e65a 2148 break;
6aa8b732 2149 case 0xc7: /* Grp9 (cmpxchg8b) */
e8d8d7fe 2150 rc = emulate_grp9(ctxt, ops, memop);
8cdbd2c9
LV		 2151 if (rc != 0)
2152 goto done;
018a98db 2153 c->dst.type = OP_NONE;
8cdbd2c9 2154 break;
6aa8b732
AK		 2155 }
2156 goto writeback;
2157
2158cannot_emulate:
e4e03ded 2159 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 2160 c->eip = saved_eip;
6aa8b732
AK		 2161 return -1;
2162}
Linux kernel - Deliverables
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