projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: Prevent trace call into unloaded module text
[deliverable/linux.git] / arch / x86 / kvm / x86_emulate.c
CommitLineData
6aa8b732
AK		 1/******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
5fdbf976 29#include "kvm_cache_regs.h"
6aa8b732
AK		 30#define DPRINTF(x...) do {} while (0)
31#endif
6aa8b732 32#include <linux/module.h>
edf88417 33#include <asm/kvm_x86_emulate.h>
6aa8b732
AK		 34
35/*
36 * Opcode effective-address decode tables.
37 * Note that we only emulate instructions that have at least one memory
38 * operand (excluding implicit stack references). We assume that stack
39 * references and instruction fetches will never occur in special memory
40 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
41 * not be handled.
42 */
43
44/* Operand sizes: 8-bit operands or specified/overridden size. */
45#define ByteOp (1<<0) /* 8-bit operands. */
46/* Destination operand type. */
47#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
48#define DstReg (2<<1) /* Register operand. */
49#define DstMem (3<<1) /* Memory operand. */
9c9fddd0
GT		 50#define DstAcc (4<<1) /* Destination Accumulator */
51#define DstMask (7<<1)
6aa8b732 52/* Source operand type. */
9c9fddd0
GT		 53#define SrcNone (0<<4) /* No source operand. */
54#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
55#define SrcReg (1<<4) /* Register operand. */
56#define SrcMem (2<<4) /* Memory operand. */
57#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
58#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
59#define SrcImm (5<<4) /* Immediate operand. */
60#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
61#define SrcMask (7<<4)
6aa8b732 62/* Generic ModRM decode. */
9c9fddd0 63#define ModRM (1<<7)
6aa8b732 64/* Destination is only written; never read. */
9c9fddd0
GT		 65#define Mov (1<<8)
66#define BitOp (1<<9)
67#define MemAbs (1<<10) /* Memory operand is absolute displacement */
68#define String (1<<12) /* String instruction (rep capable) */
69#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 70#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
71#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
72#define GroupMask 0xff /* Group number stored in bits 0:7 */
6aa8b732 73
43bb19cd 74enum {
1d6ad207 75 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 76 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
43bb19cd
AK		 77};
78
c7e75a3d 79static u16 opcode_table[256] = {
6aa8b732
AK		 80 /* 0x00 - 0x07 */
81 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
82 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
291fd39b 83 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, 0, 0,
6aa8b732
AK		 84 /* 0x08 - 0x0F */
85 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
86 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
87 0, 0, 0, 0,
88 /* 0x10 - 0x17 */
89 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
90 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
91 0, 0, 0, 0,
92 /* 0x18 - 0x1F */
93 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
94 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
95 0, 0, 0, 0,
96 /* 0x20 - 0x27 */
97 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
98 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
aa3a816b 99 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732
AK		 100 /* 0x28 - 0x2F */
101 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
102 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
103 0, 0, 0, 0,
104 /* 0x30 - 0x37 */
105 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
106 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
107 0, 0, 0, 0,
108 /* 0x38 - 0x3F */
109 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
110 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
8a9fee67
GT		 111 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
112 0, 0,
d77a2507 113 /* 0x40 - 0x47 */
33615aa9 114 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 115 /* 0x48 - 0x4F */
33615aa9 116 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 117 /* 0x50 - 0x57 */
6e3d5dfb
AK		 118 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
119 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 120 /* 0x58 - 0x5F */
6e3d5dfb
AK		 121 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
122 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 123 /* 0x60 - 0x67 */
6aa8b732 124 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 125 0, 0, 0, 0,
126 /* 0x68 - 0x6F */
91ed7a0e 127 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
e70669ab
LV		 128 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
129 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4
NK		 130 /* 0x70 - 0x77 */
131 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
132 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
133 /* 0x78 - 0x7F */
134 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
135 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732 136 /* 0x80 - 0x87 */
1d6ad207
AK		 137 Group | Group1_80, Group | Group1_81,
138 Group | Group1_82, Group | Group1_83,
6aa8b732
AK		 139 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
140 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
141 /* 0x88 - 0x8F */
142 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
143 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
38d5bc6d 144 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
4257198a 145 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
b13354f8
MG		 146 /* 0x90 - 0x97 */
147 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
148 /* 0x98 - 0x9F */
6e3d5dfb 149 0, 0, 0, 0, ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 150 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 151 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
152 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
b9fa9d6b
AK		 153 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
154 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 155 /* 0xA8 - 0xAF */
b9fa9d6b
AK		 156 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
157 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
158 ByteOp | ImplicitOps | String, ImplicitOps | String,
a5e2e82b
MG		 159 /* 0xB0 - 0xB7 */
160 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
161 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
162 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
163 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
164 /* 0xB8 - 0xBF */
165 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
166 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
167 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
168 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
6aa8b732 169 /* 0xC0 - 0xC7 */
d9413cd7 170 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 171 0, ImplicitOps | Stack, 0, 0,
d9413cd7 172 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732
AK		 173 /* 0xC8 - 0xCF */
174 0, 0, 0, 0, 0, 0, 0, 0,
175 /* 0xD0 - 0xD7 */
176 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
177 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
178 0, 0, 0, 0,
179 /* 0xD8 - 0xDF */
180 0, 0, 0, 0, 0, 0, 0, 0,
098c937b 181 /* 0xE0 - 0xE7 */
a6a3034c
MG		 182 0, 0, 0, 0,
183 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
184 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
098c937b 185 /* 0xE8 - 0xEF */
954cd36f
GT		 186 ImplicitOps | Stack, SrcImm | ImplicitOps,
187 ImplicitOps, SrcImmByte | ImplicitOps,
a6a3034c
MG		 188 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
189 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
6aa8b732
AK		 190 /* 0xF0 - 0xF7 */
191 0, 0, 0, 0,
7d858a19 192 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 193 /* 0xF8 - 0xFF */
b284be57 194 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fb4616f4 195 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
6aa8b732
AK		 196};
197
038e51de 198static u16 twobyte_table[256] = {
6aa8b732 199 /* 0x00 - 0x0F */
d95058a1 200 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
651a3e29 201 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 202 /* 0x10 - 0x1F */
203 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
204 /* 0x20 - 0x2F */
205 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
206 0, 0, 0, 0, 0, 0, 0, 0,
207 /* 0x30 - 0x3F */
35f3f286 208 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 209 /* 0x40 - 0x47 */
210 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
211 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
212 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
213 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
214 /* 0x48 - 0x4F */
215 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
216 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
217 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
218 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
219 /* 0x50 - 0x5F */
220 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
221 /* 0x60 - 0x6F */
222 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
223 /* 0x70 - 0x7F */
224 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
225 /* 0x80 - 0x8F */
bbe9abbd
NK		 226 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
227 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
228 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
229 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 230 /* 0x90 - 0x9F */
231 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
232 /* 0xA0 - 0xA7 */
038e51de 233 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732 234 /* 0xA8 - 0xAF */
2a7c5b8b 235 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, ModRM, 0,
6aa8b732
AK		 236 /* 0xB0 - 0xB7 */
237 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 238 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 239 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
240 DstReg | SrcMem16 | ModRM | Mov,
241 /* 0xB8 - 0xBF */
038e51de 242 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 243 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
244 DstReg | SrcMem16 | ModRM | Mov,
245 /* 0xC0 - 0xCF */
a012e65a
SY		 246 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
247 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 248 /* 0xD0 - 0xDF */
249 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
250 /* 0xE0 - 0xEF */
251 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
252 /* 0xF0 - 0xFF */
253 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
254};
255
e09d082c 256static u16 group_table[] = {
1d6ad207
AK		 257 [Group1_80*8] =
258 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
259 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
260 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
261 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
262 [Group1_81*8] =
263 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
264 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
265 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
266 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
267 [Group1_82*8] =
268 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
269 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
270 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
271 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
272 [Group1_83*8] =
273 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
274 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
275 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
276 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 277 [Group1A*8] =
278 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 279 [Group3_Byte*8] =
280 ByteOp | SrcImm | DstMem | ModRM, 0,
281 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
282 0, 0, 0, 0,
283 [Group3*8] =
41afa025 284 DstMem | SrcImm | ModRM, 0,
6eb06cb2 285 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
7d858a19 286 0, 0, 0, 0,
fd60754e
AK		 287 [Group4*8] =
288 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
289 0, 0, 0, 0, 0, 0,
290 [Group5*8] =
d19292e4
MG		 291 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
292 SrcMem | ModRM | Stack, 0,
ef46f18e 293 SrcMem | ModRM | Stack, 0, SrcMem | ModRM | Stack, 0,
d95058a1
AK		 294 [Group7*8] =
295 0, 0, ModRM | SrcMem, ModRM | SrcMem,
16286d08
AK		 296 SrcNone | ModRM | DstMem | Mov, 0,
297 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
e09d082c
AK		 298};
299
300static u16 group2_table[] = {
d95058a1 301 [Group7*8] =
16286d08
AK		 302 SrcNone | ModRM, 0, 0, 0,
303 SrcNone | ModRM | DstMem | Mov, 0,
304 SrcMem16 | ModRM | Mov, 0,
e09d082c
AK		 305};
306
6aa8b732
AK		 307/* EFLAGS bit definitions. */
308#define EFLG_OF (1<<11)
309#define EFLG_DF (1<<10)
310#define EFLG_SF (1<<7)
311#define EFLG_ZF (1<<6)
312#define EFLG_AF (1<<4)
313#define EFLG_PF (1<<2)
314#define EFLG_CF (1<<0)
315
316/*
317 * Instruction emulation:
318 * Most instructions are emulated directly via a fragment of inline assembly
319 * code. This allows us to save/restore EFLAGS and thus very easily pick up
320 * any modified flags.
321 */
322
05b3e0c2 323#if defined(CONFIG_X86_64)
6aa8b732
AK		 324#define _LO32 "k" /* force 32-bit operand */
325#define _STK "%%rsp" /* stack pointer */
326#elif defined(__i386__)
327#define _LO32 "" /* force 32-bit operand */
328#define _STK "%%esp" /* stack pointer */
329#endif
330
331/*
332 * These EFLAGS bits are restored from saved value during emulation, and
333 * any changes are written back to the saved value after emulation.
334 */
335#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
336
337/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 338#define _PRE_EFLAGS(_sav, _msk, _tmp) \
339 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
340 "movl %"_sav",%"_LO32 _tmp"; " \
341 "push %"_tmp"; " \
342 "push %"_tmp"; " \
343 "movl %"_msk",%"_LO32 _tmp"; " \
344 "andl %"_LO32 _tmp",("_STK"); " \
345 "pushf; " \
346 "notl %"_LO32 _tmp"; " \
347 "andl %"_LO32 _tmp",("_STK"); " \
348 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
349 "pop %"_tmp"; " \
350 "orl %"_LO32 _tmp",("_STK"); " \
351 "popf; " \
352 "pop %"_sav"; "
6aa8b732
AK		 353
354/* After executing instruction: write-back necessary bits in EFLAGS. */
355#define _POST_EFLAGS(_sav, _msk, _tmp) \
356 /* _sav |= EFLAGS & _msk; */ \
357 "pushf; " \
358 "pop %"_tmp"; " \
359 "andl %"_msk",%"_LO32 _tmp"; " \
360 "orl %"_LO32 _tmp",%"_sav"; "
361
dda96d8f
AK		 362#ifdef CONFIG_X86_64
363#define ON64(x) x
364#else
365#define ON64(x)
366#endif
367
6b7ad61f
AK		 368#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
369 do { \
370 __asm__ __volatile__ ( \
371 _PRE_EFLAGS("0", "4", "2") \
372 _op _suffix " %"_x"3,%1; " \
373 _POST_EFLAGS("0", "4", "2") \
374 : "=m" (_eflags), "=m" ((_dst).val), \
375 "=&r" (_tmp) \
376 : _y ((_src).val), "i" (EFLAGS_MASK)); \
377 } while (0);
378
379
6aa8b732
AK		 380/* Raw emulation: instruction has two explicit operands. */
381#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 382 do { \
383 unsigned long _tmp; \
384 \
385 switch ((_dst).bytes) { \
386 case 2: \
387 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
388 break; \
389 case 4: \
390 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
391 break; \
392 case 8: \
393 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
394 break; \
395 } \
6aa8b732
AK		 396 } while (0)
397
398#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
399 do { \
6b7ad61f 400 unsigned long _tmp; \
d77c26fc 401 switch ((_dst).bytes) { \
6aa8b732 402 case 1: \
6b7ad61f 403 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 404 break; \
405 default: \
406 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
407 _wx, _wy, _lx, _ly, _qx, _qy); \
408 break; \
409 } \
410 } while (0)
411
412/* Source operand is byte-sized and may be restricted to just %cl. */
413#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
414 __emulate_2op(_op, _src, _dst, _eflags, \
415 "b", "c", "b", "c", "b", "c", "b", "c")
416
417/* Source operand is byte, word, long or quad sized. */
418#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
419 __emulate_2op(_op, _src, _dst, _eflags, \
420 "b", "q", "w", "r", _LO32, "r", "", "r")
421
422/* Source operand is word, long or quad sized. */
423#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
424 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
425 "w", "r", _LO32, "r", "", "r")
426
dda96d8f 427#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 428 do { \
429 unsigned long _tmp; \
430 \
dda96d8f
AK		 431 __asm__ __volatile__ ( \
432 _PRE_EFLAGS("0", "3", "2") \
433 _op _suffix " %1; " \
434 _POST_EFLAGS("0", "3", "2") \
435 : "=m" (_eflags), "+m" ((_dst).val), \
436 "=&r" (_tmp) \
437 : "i" (EFLAGS_MASK)); \
438 } while (0)
439
440/* Instruction has only one explicit operand (no source operand). */
441#define emulate_1op(_op, _dst, _eflags) \
442 do { \
d77c26fc 443 switch ((_dst).bytes) { \
dda96d8f
AK		 444 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
445 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
446 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
447 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 448 } \
449 } while (0)
450
6aa8b732
AK		 451/* Fetch next part of the instruction being emulated. */
452#define insn_fetch(_type, _size, _eip) \
453({ unsigned long _x; \
62266869 454 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
d77c26fc 455 if (rc != 0) \
6aa8b732
AK		 456 goto done; \
457 (_eip) += (_size); \
458 (_type)_x; \
459})
460
ddcb2885
HH		 461static inline unsigned long ad_mask(struct decode_cache *c)
462{
463 return (1UL << (c->ad_bytes << 3)) - 1;
464}
465
6aa8b732 466/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 467static inline unsigned long
468address_mask(struct decode_cache *c, unsigned long reg)
469{
470 if (c->ad_bytes == sizeof(unsigned long))
471 return reg;
472 else
473 return reg & ad_mask(c);
474}
475
476static inline unsigned long
477register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
478{
479 return base + address_mask(c, reg);
480}
481
7a957275
HH		 482static inline void
483register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
484{
485 if (c->ad_bytes == sizeof(unsigned long))
486 *reg += inc;
487 else
488 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
489}
6aa8b732 490
7a957275
HH		 491static inline void jmp_rel(struct decode_cache *c, int rel)
492{
493 register_address_increment(c, &c->eip, rel);
494}
098c937b 495
7a5b56df
AK		 496static void set_seg_override(struct decode_cache *c, int seg)
497{
498 c->has_seg_override = true;
499 c->seg_override = seg;
500}
501
502static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
503{
504 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
505 return 0;
506
507 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
508}
509
510static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
511 struct decode_cache *c)
512{
513 if (!c->has_seg_override)
514 return 0;
515
516 return seg_base(ctxt, c->seg_override);
517}
518
519static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
520{
521 return seg_base(ctxt, VCPU_SREG_ES);
522}
523
524static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
525{
526 return seg_base(ctxt, VCPU_SREG_SS);
527}
528
62266869
AK		 529static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
530 struct x86_emulate_ops *ops,
531 unsigned long linear, u8 *dest)
532{
533 struct fetch_cache *fc = &ctxt->decode.fetch;
534 int rc;
535 int size;
536
537 if (linear < fc->start || linear >= fc->end) {
538 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
539 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
540 if (rc)
541 return rc;
542 fc->start = linear;
543 fc->end = linear + size;
544 }
545 *dest = fc->data[linear - fc->start];
546 return 0;
547}
548
549static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
550 struct x86_emulate_ops *ops,
551 unsigned long eip, void *dest, unsigned size)
552{
553 int rc = 0;
554
555 eip += ctxt->cs_base;
556 while (size--) {
557 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
558 if (rc)
559 return rc;
560 }
561 return 0;
562}
563
1e3c5cb0
RR		 564/*
565 * Given the 'reg' portion of a ModRM byte, and a register block, return a
566 * pointer into the block that addresses the relevant register.
567 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
568 */
569static void *decode_register(u8 modrm_reg, unsigned long *regs,
570 int highbyte_regs)
6aa8b732
AK		 571{
572 void *p;
573
574 p = &regs[modrm_reg];
575 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
576 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
577 return p;
578}
579
580static int read_descriptor(struct x86_emulate_ctxt *ctxt,
581 struct x86_emulate_ops *ops,
582 void *ptr,
583 u16 *size, unsigned long *address, int op_bytes)
584{
585 int rc;
586
587 if (op_bytes == 2)
588 op_bytes = 3;
589 *address = 0;
cebff02b
LV		 590 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
591 ctxt->vcpu);
6aa8b732
AK		 592 if (rc)
593 return rc;
cebff02b
LV		 594 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
595 ctxt->vcpu);
6aa8b732
AK		 596 return rc;
597}
598
bbe9abbd
NK		 599static int test_cc(unsigned int condition, unsigned int flags)
600{
601 int rc = 0;
602
603 switch ((condition & 15) >> 1) {
604 case 0: /* o */
605 rc |= (flags & EFLG_OF);
606 break;
607 case 1: /* b/c/nae */
608 rc |= (flags & EFLG_CF);
609 break;
610 case 2: /* z/e */
611 rc |= (flags & EFLG_ZF);
612 break;
613 case 3: /* be/na */
614 rc |= (flags & (EFLG_CF|EFLG_ZF));
615 break;
616 case 4: /* s */
617 rc |= (flags & EFLG_SF);
618 break;
619 case 5: /* p/pe */
620 rc |= (flags & EFLG_PF);
621 break;
622 case 7: /* le/ng */
623 rc |= (flags & EFLG_ZF);
624 /* fall through */
625 case 6: /* l/nge */
626 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
627 break;
628 }
629
630 /* Odd condition identifiers (lsb == 1) have inverted sense. */
631 return (!!rc ^ (condition & 1));
632}
633
3c118e24
AK		 634static void decode_register_operand(struct operand *op,
635 struct decode_cache *c,
3c118e24
AK		 636 int inhibit_bytereg)
637{
33615aa9 638 unsigned reg = c->modrm_reg;
9f1ef3f8 639 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 640
641 if (!(c->d & ModRM))
642 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 643 op->type = OP_REG;
644 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 645 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 646 op->val = *(u8 *)op->ptr;
647 op->bytes = 1;
648 } else {
33615aa9 649 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 650 op->bytes = c->op_bytes;
651 switch (op->bytes) {
652 case 2:
653 op->val = *(u16 *)op->ptr;
654 break;
655 case 4:
656 op->val = *(u32 *)op->ptr;
657 break;
658 case 8:
659 op->val = *(u64 *) op->ptr;
660 break;
661 }
662 }
663 op->orig_val = op->val;
664}
665
1c73ef66
AK		 666static int decode_modrm(struct x86_emulate_ctxt *ctxt,
667 struct x86_emulate_ops *ops)
668{
669 struct decode_cache *c = &ctxt->decode;
670 u8 sib;
f5b4edcd 671 int index_reg = 0, base_reg = 0, scale;
1c73ef66
AK		 672 int rc = 0;
673
674 if (c->rex_prefix) {
675 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
676 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
677 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
678 }
679
680 c->modrm = insn_fetch(u8, 1, c->eip);
681 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
682 c->modrm_reg |= (c->modrm & 0x38) >> 3;
683 c->modrm_rm |= (c->modrm & 0x07);
684 c->modrm_ea = 0;
685 c->use_modrm_ea = 1;
686
687 if (c->modrm_mod == 3) {
107d6d2e
AK		 688 c->modrm_ptr = decode_register(c->modrm_rm,
689 c->regs, c->d & ByteOp);
690 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 691 return rc;
692 }
693
694 if (c->ad_bytes == 2) {
695 unsigned bx = c->regs[VCPU_REGS_RBX];
696 unsigned bp = c->regs[VCPU_REGS_RBP];
697 unsigned si = c->regs[VCPU_REGS_RSI];
698 unsigned di = c->regs[VCPU_REGS_RDI];
699
700 /* 16-bit ModR/M decode. */
701 switch (c->modrm_mod) {
702 case 0:
703 if (c->modrm_rm == 6)
704 c->modrm_ea += insn_fetch(u16, 2, c->eip);
705 break;
706 case 1:
707 c->modrm_ea += insn_fetch(s8, 1, c->eip);
708 break;
709 case 2:
710 c->modrm_ea += insn_fetch(u16, 2, c->eip);
711 break;
712 }
713 switch (c->modrm_rm) {
714 case 0:
715 c->modrm_ea += bx + si;
716 break;
717 case 1:
718 c->modrm_ea += bx + di;
719 break;
720 case 2:
721 c->modrm_ea += bp + si;
722 break;
723 case 3:
724 c->modrm_ea += bp + di;
725 break;
726 case 4:
727 c->modrm_ea += si;
728 break;
729 case 5:
730 c->modrm_ea += di;
731 break;
732 case 6:
733 if (c->modrm_mod != 0)
734 c->modrm_ea += bp;
735 break;
736 case 7:
737 c->modrm_ea += bx;
738 break;
739 }
740 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
741 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 742 if (!c->has_seg_override)
743 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 744 c->modrm_ea = (u16)c->modrm_ea;
745 } else {
746 /* 32/64-bit ModR/M decode. */
84411d85 747 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 748 sib = insn_fetch(u8, 1, c->eip);
749 index_reg |= (sib >> 3) & 7;
750 base_reg |= sib & 7;
751 scale = sib >> 6;
752
dc71d0f1
AK		 753 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
754 c->modrm_ea += insn_fetch(s32, 4, c->eip);
755 else
1c73ef66 756 c->modrm_ea += c->regs[base_reg];
dc71d0f1 757 if (index_reg != 4)
1c73ef66 758 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 759 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
760 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 761 c->rip_relative = 1;
84411d85 762 } else
1c73ef66 763 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 764 switch (c->modrm_mod) {
765 case 0:
766 if (c->modrm_rm == 5)
767 c->modrm_ea += insn_fetch(s32, 4, c->eip);
768 break;
769 case 1:
770 c->modrm_ea += insn_fetch(s8, 1, c->eip);
771 break;
772 case 2:
773 c->modrm_ea += insn_fetch(s32, 4, c->eip);
774 break;
775 }
776 }
1c73ef66
AK		 777done:
778 return rc;
779}
780
781static int decode_abs(struct x86_emulate_ctxt *ctxt,
782 struct x86_emulate_ops *ops)
783{
784 struct decode_cache *c = &ctxt->decode;
785 int rc = 0;
786
787 switch (c->ad_bytes) {
788 case 2:
789 c->modrm_ea = insn_fetch(u16, 2, c->eip);
790 break;
791 case 4:
792 c->modrm_ea = insn_fetch(u32, 4, c->eip);
793 break;
794 case 8:
795 c->modrm_ea = insn_fetch(u64, 8, c->eip);
796 break;
797 }
798done:
799 return rc;
800}
801
6aa8b732 802int
8b4caf66 803x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 804{
e4e03ded 805 struct decode_cache *c = &ctxt->decode;
6aa8b732 806 int rc = 0;
6aa8b732 807 int mode = ctxt->mode;
e09d082c 808 int def_op_bytes, def_ad_bytes, group;
6aa8b732
AK		 809
810 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 811
e4e03ded 812 memset(c, 0, sizeof(struct decode_cache));
5fdbf976 813 c->eip = kvm_rip_read(ctxt->vcpu);
7a5b56df 814 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
ad312c7c 815 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 816
817 switch (mode) {
818 case X86EMUL_MODE_REAL:
819 case X86EMUL_MODE_PROT16:
f21b8bf4 820 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 821 break;
822 case X86EMUL_MODE_PROT32:
f21b8bf4 823 def_op_bytes = def_ad_bytes = 4;
6aa8b732 824 break;
05b3e0c2 825#ifdef CONFIG_X86_64
6aa8b732 826 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 827 def_op_bytes = 4;
828 def_ad_bytes = 8;
6aa8b732
AK		 829 break;
830#endif
831 default:
832 return -1;
833 }
834
f21b8bf4
AK		 835 c->op_bytes = def_op_bytes;
836 c->ad_bytes = def_ad_bytes;
837
6aa8b732 838 /* Legacy prefixes. */
b4c6abfe 839 for (;;) {
e4e03ded 840 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 841 case 0x66: /* operand-size override */
f21b8bf4
AK		 842 /* switch between 2/4 bytes */
843 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 844 break;
845 case 0x67: /* address-size override */
846 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 847 /* switch between 4/8 bytes */
f21b8bf4 848 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 849 else
e4e03ded 850 /* switch between 2/4 bytes */
f21b8bf4 851 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 852 break;
7a5b56df 853 case 0x26: /* ES override */
6aa8b732 854 case 0x2e: /* CS override */
7a5b56df 855 case 0x36: /* SS override */
6aa8b732 856 case 0x3e: /* DS override */
7a5b56df 857 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 858 break;
859 case 0x64: /* FS override */
6aa8b732 860 case 0x65: /* GS override */
7a5b56df 861 set_seg_override(c, c->b & 7);
6aa8b732 862 break;
b4c6abfe
LV		 863 case 0x40 ... 0x4f: /* REX */
864 if (mode != X86EMUL_MODE_PROT64)
865 goto done_prefixes;
33615aa9 866 c->rex_prefix = c->b;
b4c6abfe 867 continue;
6aa8b732 868 case 0xf0: /* LOCK */
e4e03ded 869 c->lock_prefix = 1;
6aa8b732 870 break;
ae6200ba 871 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 872 c->rep_prefix = REPNE_PREFIX;
873 break;
6aa8b732 874 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 875 c->rep_prefix = REPE_PREFIX;
6aa8b732 876 break;
6aa8b732
AK		 877 default:
878 goto done_prefixes;
879 }
b4c6abfe
LV		 880
881 /* Any legacy prefix after a REX prefix nullifies its effect. */
882
33615aa9 883 c->rex_prefix = 0;
6aa8b732
AK		 884 }
885
886done_prefixes:
887
888 /* REX prefix. */
1c73ef66 889 if (c->rex_prefix)
33615aa9 890 if (c->rex_prefix & 8)
e4e03ded 891 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 892
893 /* Opcode byte(s). */
e4e03ded
LV		 894 c->d = opcode_table[c->b];
895 if (c->d == 0) {
6aa8b732 896 /* Two-byte opcode? */
e4e03ded
LV		 897 if (c->b == 0x0f) {
898 c->twobyte = 1;
899 c->b = insn_fetch(u8, 1, c->eip);
900 c->d = twobyte_table[c->b];
6aa8b732 901 }
e09d082c 902 }
6aa8b732 903
e09d082c
AK		 904 if (c->d & Group) {
905 group = c->d & GroupMask;
906 c->modrm = insn_fetch(u8, 1, c->eip);
907 --c->eip;
908
909 group = (group << 3) + ((c->modrm >> 3) & 7);
910 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
911 c->d = group2_table[group];
912 else
913 c->d = group_table[group];
914 }
915
916 /* Unrecognised? */
917 if (c->d == 0) {
918 DPRINTF("Cannot emulate %02x\n", c->b);
919 return -1;
6aa8b732
AK		 920 }
921
6e3d5dfb
AK		 922 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
923 c->op_bytes = 8;
924
6aa8b732 925 /* ModRM and SIB bytes. */
1c73ef66
AK		 926 if (c->d & ModRM)
927 rc = decode_modrm(ctxt, ops);
928 else if (c->d & MemAbs)
929 rc = decode_abs(ctxt, ops);
930 if (rc)
931 goto done;
6aa8b732 932
7a5b56df
AK		 933 if (!c->has_seg_override)
934 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 935
7a5b56df
AK		 936 if (!(!c->twobyte && c->b == 0x8d))
937 c->modrm_ea += seg_override_base(ctxt, c);
c7e75a3d
AK		 938
939 if (c->ad_bytes != 8)
940 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 941 /*
942 * Decode and fetch the source operand: register, memory
943 * or immediate.
944 */
e4e03ded 945 switch (c->d & SrcMask) {
6aa8b732
AK		 946 case SrcNone:
947 break;
948 case SrcReg:
9f1ef3f8 949 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 950 break;
951 case SrcMem16:
e4e03ded 952 c->src.bytes = 2;
6aa8b732
AK		 953 goto srcmem_common;
954 case SrcMem32:
e4e03ded 955 c->src.bytes = 4;
6aa8b732
AK		 956 goto srcmem_common;
957 case SrcMem:
e4e03ded
LV		 958 c->src.bytes = (c->d & ByteOp) ? 1 :
959 c->op_bytes;
b85b9ee9 960 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 961 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 962 break;
d77c26fc 963 srcmem_common:
4e62417b
AJ		 964 /*
965 * For instructions with a ModR/M byte, switch to register
966 * access if Mod = 3.
967 */
e4e03ded
LV		 968 if ((c->d & ModRM) && c->modrm_mod == 3) {
969 c->src.type = OP_REG;
66b85505 970 c->src.val = c->modrm_val;
107d6d2e 971 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 972 break;
973 }
e4e03ded 974 c->src.type = OP_MEM;
6aa8b732
AK		 975 break;
976 case SrcImm:
e4e03ded
LV		 977 c->src.type = OP_IMM;
978 c->src.ptr = (unsigned long *)c->eip;
979 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
980 if (c->src.bytes == 8)
981 c->src.bytes = 4;
6aa8b732 982 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 983 switch (c->src.bytes) {
6aa8b732 984 case 1:
e4e03ded 985 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 986 break;
987 case 2:
e4e03ded 988 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 989 break;
990 case 4:
e4e03ded 991 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 992 break;
993 }
994 break;
995 case SrcImmByte:
e4e03ded
LV		 996 c->src.type = OP_IMM;
997 c->src.ptr = (unsigned long *)c->eip;
998 c->src.bytes = 1;
999 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1000 break;
1001 }
1002
038e51de 1003 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1004 switch (c->d & DstMask) {
038e51de
AK		 1005 case ImplicitOps:
1006 /* Special instructions do their own operand decoding. */
8b4caf66 1007 return 0;
038e51de 1008 case DstReg:
9f1ef3f8 1009 decode_register_operand(&c->dst, c,
3c118e24 1010 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1011 break;
1012 case DstMem:
e4e03ded 1013 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1014 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1015 c->dst.type = OP_REG;
66b85505 1016 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1017 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1018 break;
1019 }
8b4caf66
LV		 1020 c->dst.type = OP_MEM;
1021 break;
9c9fddd0
GT		 1022 case DstAcc:
1023 c->dst.type = OP_REG;
1024 c->dst.bytes = c->op_bytes;
1025 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1026 switch (c->op_bytes) {
1027 case 1:
1028 c->dst.val = *(u8 *)c->dst.ptr;
1029 break;
1030 case 2:
1031 c->dst.val = *(u16 *)c->dst.ptr;
1032 break;
1033 case 4:
1034 c->dst.val = *(u32 *)c->dst.ptr;
1035 break;
1036 }
1037 c->dst.orig_val = c->dst.val;
1038 break;
8b4caf66
LV		 1039 }
1040
f5b4edcd
AK		 1041 if (c->rip_relative)
1042 c->modrm_ea += c->eip;
1043
8b4caf66
LV		 1044done:
1045 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1046}
1047
8cdbd2c9
LV		 1048static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1049{
1050 struct decode_cache *c = &ctxt->decode;
1051
1052 c->dst.type = OP_MEM;
1053 c->dst.bytes = c->op_bytes;
1054 c->dst.val = c->src.val;
7a957275 1055 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
7a5b56df 1056 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1057 c->regs[VCPU_REGS_RSP]);
1058}
1059
1060static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1061 struct x86_emulate_ops *ops)
1062{
1063 struct decode_cache *c = &ctxt->decode;
1064 int rc;
1065
7a5b56df 1066 rc = ops->read_std(register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1067 c->regs[VCPU_REGS_RSP]),
1068 &c->dst.val, c->dst.bytes, ctxt->vcpu);
1069 if (rc != 0)
1070 return rc;
1071
7a957275 1072 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->dst.bytes);
8cdbd2c9
LV		 1073
1074 return 0;
1075}
1076
05f086f8 1077static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1078{
05f086f8 1079 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1080 switch (c->modrm_reg) {
1081 case 0: /* rol */
05f086f8 1082 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1083 break;
1084 case 1: /* ror */
05f086f8 1085 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1086 break;
1087 case 2: /* rcl */
05f086f8 1088 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1089 break;
1090 case 3: /* rcr */
05f086f8 1091 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1092 break;
1093 case 4: /* sal/shl */
1094 case 6: /* sal/shl */
05f086f8 1095 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1096 break;
1097 case 5: /* shr */
05f086f8 1098 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1099 break;
1100 case 7: /* sar */
05f086f8 1101 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1102 break;
1103 }
1104}
1105
1106static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1107 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1108{
1109 struct decode_cache *c = &ctxt->decode;
1110 int rc = 0;
1111
1112 switch (c->modrm_reg) {
1113 case 0 ... 1: /* test */
05f086f8 1114 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1115 break;
1116 case 2: /* not */
1117 c->dst.val = ~c->dst.val;
1118 break;
1119 case 3: /* neg */
05f086f8 1120 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1121 break;
1122 default:
1123 DPRINTF("Cannot emulate %02x\n", c->b);
1124 rc = X86EMUL_UNHANDLEABLE;
1125 break;
1126 }
8cdbd2c9
LV		 1127 return rc;
1128}
1129
1130static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1131 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1132{
1133 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1134
1135 switch (c->modrm_reg) {
1136 case 0: /* inc */
05f086f8 1137 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1138 break;
1139 case 1: /* dec */
05f086f8 1140 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1141 break;
d19292e4
MG		 1142 case 2: /* call near abs */ {
1143 long int old_eip;
1144 old_eip = c->eip;
1145 c->eip = c->src.val;
1146 c->src.val = old_eip;
1147 emulate_push(ctxt);
1148 break;
1149 }
8cdbd2c9 1150 case 4: /* jmp abs */
fd60754e 1151 c->eip = c->src.val;
8cdbd2c9
LV		 1152 break;
1153 case 6: /* push */
fd60754e 1154 emulate_push(ctxt);
8cdbd2c9 1155 break;
8cdbd2c9
LV		 1156 }
1157 return 0;
1158}
1159
1160static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1161 struct x86_emulate_ops *ops,
e8d8d7fe 1162 unsigned long memop)
8cdbd2c9
LV		 1163{
1164 struct decode_cache *c = &ctxt->decode;
1165 u64 old, new;
1166 int rc;
1167
e8d8d7fe 1168 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
8cdbd2c9
LV		 1169 if (rc != 0)
1170 return rc;
1171
1172 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1173 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1174
1175 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1176 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1177 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1178
1179 } else {
1180 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1181 (u32) c->regs[VCPU_REGS_RBX];
1182
e8d8d7fe 1183 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
8cdbd2c9
LV		 1184 if (rc != 0)
1185 return rc;
05f086f8 1186 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1187 }
1188 return 0;
1189}
1190
1191static inline int writeback(struct x86_emulate_ctxt *ctxt,
1192 struct x86_emulate_ops *ops)
1193{
1194 int rc;
1195 struct decode_cache *c = &ctxt->decode;
1196
1197 switch (c->dst.type) {
1198 case OP_REG:
1199 /* The 4-byte case *is* correct:
1200 * in 64-bit mode we zero-extend.
1201 */
1202 switch (c->dst.bytes) {
1203 case 1:
1204 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1205 break;
1206 case 2:
1207 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1208 break;
1209 case 4:
1210 *c->dst.ptr = (u32)c->dst.val;
1211 break; /* 64b: zero-ext */
1212 case 8:
1213 *c->dst.ptr = c->dst.val;
1214 break;
1215 }
1216 break;
1217 case OP_MEM:
1218 if (c->lock_prefix)
1219 rc = ops->cmpxchg_emulated(
1220 (unsigned long)c->dst.ptr,
1221 &c->dst.orig_val,
1222 &c->dst.val,
1223 c->dst.bytes,
1224 ctxt->vcpu);
1225 else
1226 rc = ops->write_emulated(
1227 (unsigned long)c->dst.ptr,
1228 &c->dst.val,
1229 c->dst.bytes,
1230 ctxt->vcpu);
1231 if (rc != 0)
1232 return rc;
a01af5ec
LV		 1233 break;
1234 case OP_NONE:
1235 /* no writeback */
1236 break;
8cdbd2c9
LV		 1237 default:
1238 break;
1239 }
1240 return 0;
1241}
1242
8b4caf66 1243int
1be3aa47 1244x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 1245{
e8d8d7fe 1246 unsigned long memop = 0;
8b4caf66 1247 u64 msr_data;
3427318f 1248 unsigned long saved_eip = 0;
8b4caf66 1249 struct decode_cache *c = &ctxt->decode;
a6a3034c
MG		 1250 unsigned int port;
1251 int io_dir_in;
1be3aa47 1252 int rc = 0;
8b4caf66 1253
3427318f
LV		 1254 /* Shadow copy of register state. Committed on successful emulation.
1255 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1256 * modify them.
1257 */
1258
ad312c7c 1259 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f
LV		 1260 saved_eip = c->eip;
1261
c7e75a3d 1262 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
e8d8d7fe 1263 memop = c->modrm_ea;
8b4caf66 1264
b9fa9d6b
AK		 1265 if (c->rep_prefix && (c->d & String)) {
1266 /* All REP prefixes have the same first termination condition */
1267 if (c->regs[VCPU_REGS_RCX] == 0) {
5fdbf976 1268 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1269 goto done;
1270 }
1271 /* The second termination condition only applies for REPE
1272 * and REPNE. Test if the repeat string operation prefix is
1273 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1274 * corresponding termination condition according to:
1275 * - if REPE/REPZ and ZF = 0 then done
1276 * - if REPNE/REPNZ and ZF = 1 then done
1277 */
1278 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1279 (c->b == 0xae) || (c->b == 0xaf)) {
1280 if ((c->rep_prefix == REPE_PREFIX) &&
1281 ((ctxt->eflags & EFLG_ZF) == 0)) {
5fdbf976 1282 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1283 goto done;
1284 }
1285 if ((c->rep_prefix == REPNE_PREFIX) &&
1286 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
5fdbf976 1287 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1288 goto done;
1289 }
1290 }
1291 c->regs[VCPU_REGS_RCX]--;
5fdbf976 1292 c->eip = kvm_rip_read(ctxt->vcpu);
b9fa9d6b
AK		 1293 }
1294
8b4caf66 1295 if (c->src.type == OP_MEM) {
e8d8d7fe 1296 c->src.ptr = (unsigned long *)memop;
8b4caf66 1297 c->src.val = 0;
d77c26fc
MD		 1298 rc = ops->read_emulated((unsigned long)c->src.ptr,
1299 &c->src.val,
1300 c->src.bytes,
1301 ctxt->vcpu);
1302 if (rc != 0)
8b4caf66
LV		 1303 goto done;
1304 c->src.orig_val = c->src.val;
1305 }
1306
1307 if ((c->d & DstMask) == ImplicitOps)
1308 goto special_insn;
1309
1310
1311 if (c->dst.type == OP_MEM) {
e8d8d7fe 1312 c->dst.ptr = (unsigned long *)memop;
8b4caf66
LV		 1313 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1314 c->dst.val = 0;
e4e03ded
LV		 1315 if (c->d & BitOp) {
1316 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1317
e4e03ded
LV		 1318 c->dst.ptr = (void *)c->dst.ptr +
1319 (c->src.val & mask) / 8;
038e51de 1320 }
e4e03ded
LV		 1321 if (!(c->d & Mov) &&
1322 /* optimisation - avoid slow emulated read */
1323 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1324 &c->dst.val,
1325 c->dst.bytes, ctxt->vcpu)) != 0))
038e51de 1326 goto done;
038e51de 1327 }
e4e03ded 1328 c->dst.orig_val = c->dst.val;
038e51de 1329
018a98db
AK		 1330special_insn:
1331
e4e03ded 1332 if (c->twobyte)
6aa8b732
AK		 1333 goto twobyte_insn;
1334
e4e03ded 1335 switch (c->b) {
6aa8b732
AK		 1336 case 0x00 ... 0x05:
1337 add: /* add */
05f086f8 1338 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1339 break;
1340 case 0x08 ... 0x0d:
1341 or: /* or */
05f086f8 1342 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1343 break;
1344 case 0x10 ... 0x15:
1345 adc: /* adc */
05f086f8 1346 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1347 break;
1348 case 0x18 ... 0x1d:
1349 sbb: /* sbb */
05f086f8 1350 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1351 break;
aa3a816b 1352 case 0x20 ... 0x25:
6aa8b732 1353 and: /* and */
05f086f8 1354 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1355 break;
1356 case 0x28 ... 0x2d:
1357 sub: /* sub */
05f086f8 1358 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1359 break;
1360 case 0x30 ... 0x35:
1361 xor: /* xor */
05f086f8 1362 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1363 break;
1364 case 0x38 ... 0x3d:
1365 cmp: /* cmp */
05f086f8 1366 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 1367 break;
33615aa9
AK		 1368 case 0x40 ... 0x47: /* inc r16/r32 */
1369 emulate_1op("inc", c->dst, ctxt->eflags);
1370 break;
1371 case 0x48 ... 0x4f: /* dec r16/r32 */
1372 emulate_1op("dec", c->dst, ctxt->eflags);
1373 break;
1374 case 0x50 ... 0x57: /* push reg */
2786b014 1375 emulate_push(ctxt);
33615aa9
AK		 1376 break;
1377 case 0x58 ... 0x5f: /* pop reg */
1378 pop_instruction:
7a5b56df 1379 if ((rc = ops->read_std(register_address(c, ss_base(ctxt),
33615aa9
AK		 1380 c->regs[VCPU_REGS_RSP]), c->dst.ptr,
1381 c->op_bytes, ctxt->vcpu)) != 0)
1382 goto done;
1383
7a957275 1384 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
33615aa9
AK		 1385 c->op_bytes);
1386 c->dst.type = OP_NONE; /* Disable writeback. */
1387 break;
6aa8b732 1388 case 0x63: /* movsxd */
8b4caf66 1389 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1390 goto cannot_emulate;
e4e03ded 1391 c->dst.val = (s32) c->src.val;
6aa8b732 1392 break;
91ed7a0e 1393 case 0x68: /* push imm */
018a98db 1394 case 0x6a: /* push imm8 */
018a98db
AK		 1395 emulate_push(ctxt);
1396 break;
1397 case 0x6c: /* insb */
1398 case 0x6d: /* insw/insd */
1399 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1400 1,
1401 (c->d & ByteOp) ? 1 : c->op_bytes,
1402 c->rep_prefix ?
e4706772 1403 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1404 (ctxt->eflags & EFLG_DF),
7a5b56df 1405 register_address(c, es_base(ctxt),
018a98db
AK		 1406 c->regs[VCPU_REGS_RDI]),
1407 c->rep_prefix,
1408 c->regs[VCPU_REGS_RDX]) == 0) {
1409 c->eip = saved_eip;
1410 return -1;
1411 }
1412 return 0;
1413 case 0x6e: /* outsb */
1414 case 0x6f: /* outsw/outsd */
1415 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1416 0,
1417 (c->d & ByteOp) ? 1 : c->op_bytes,
1418 c->rep_prefix ?
e4706772 1419 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1420 (ctxt->eflags & EFLG_DF),
7a5b56df
AK		 1421 register_address(c,
1422 seg_override_base(ctxt, c),
018a98db
AK		 1423 c->regs[VCPU_REGS_RSI]),
1424 c->rep_prefix,
1425 c->regs[VCPU_REGS_RDX]) == 0) {
1426 c->eip = saved_eip;
1427 return -1;
1428 }
1429 return 0;
1430 case 0x70 ... 0x7f: /* jcc (short) */ {
1431 int rel = insn_fetch(s8, 1, c->eip);
1432
1433 if (test_cc(c->b, ctxt->eflags))
7a957275 1434 jmp_rel(c, rel);
018a98db
AK		 1435 break;
1436 }
6aa8b732 1437 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 1438 switch (c->modrm_reg) {
6aa8b732
AK		 1439 case 0:
1440 goto add;
1441 case 1:
1442 goto or;
1443 case 2:
1444 goto adc;
1445 case 3:
1446 goto sbb;
1447 case 4:
1448 goto and;
1449 case 5:
1450 goto sub;
1451 case 6:
1452 goto xor;
1453 case 7:
1454 goto cmp;
1455 }
1456 break;
1457 case 0x84 ... 0x85:
05f086f8 1458 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1459 break;
1460 case 0x86 ... 0x87: /* xchg */
b13354f8 1461 xchg:
6aa8b732 1462 /* Write back the register source. */
e4e03ded 1463 switch (c->dst.bytes) {
6aa8b732 1464 case 1:
e4e03ded 1465 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 1466 break;
1467 case 2:
e4e03ded 1468 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 1469 break;
1470 case 4:
e4e03ded 1471 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 1472 break; /* 64b reg: zero-extend */
1473 case 8:
e4e03ded 1474 *c->src.ptr = c->dst.val;
6aa8b732
AK		 1475 break;
1476 }
1477 /*
1478 * Write back the memory destination with implicit LOCK
1479 * prefix.
1480 */
e4e03ded
LV		 1481 c->dst.val = c->src.val;
1482 c->lock_prefix = 1;
6aa8b732 1483 break;
6aa8b732 1484 case 0x88 ... 0x8b: /* mov */
7de75248 1485 goto mov;
38d5bc6d
GT		 1486 case 0x8c: { /* mov r/m, sreg */
1487 struct kvm_segment segreg;
1488
1489 if (c->modrm_reg <= 5)
1490 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
1491 else {
1492 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
1493 c->modrm);
1494 goto cannot_emulate;
1495 }
1496 c->dst.val = segreg.selector;
1497 break;
1498 }
7e0b54b1 1499 case 0x8d: /* lea r16/r32, m */
f9b7aab3 1500 c->dst.val = c->modrm_ea;
7e0b54b1 1501 break;
4257198a
GT		 1502 case 0x8e: { /* mov seg, r/m16 */
1503 uint16_t sel;
1504 int type_bits;
1505 int err;
1506
1507 sel = c->src.val;
1508 if (c->modrm_reg <= 5) {
1509 type_bits = (c->modrm_reg == 1) ? 9 : 1;
1510 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
1511 type_bits, c->modrm_reg);
1512 } else {
1513 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
1514 c->modrm);
1515 goto cannot_emulate;
1516 }
1517
1518 if (err < 0)
1519 goto cannot_emulate;
1520
1521 c->dst.type = OP_NONE; /* Disable writeback. */
1522 break;
1523 }
6aa8b732 1524 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 1525 rc = emulate_grp1a(ctxt, ops);
1526 if (rc != 0)
6aa8b732 1527 goto done;
6aa8b732 1528 break;
b13354f8
MG		 1529 case 0x90: /* nop / xchg r8,rax */
1530 if (!(c->rex_prefix & 1)) { /* nop */
1531 c->dst.type = OP_NONE;
1532 break;
1533 }
1534 case 0x91 ... 0x97: /* xchg reg,rax */
1535 c->src.type = c->dst.type = OP_REG;
1536 c->src.bytes = c->dst.bytes = c->op_bytes;
1537 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
1538 c->src.val = *(c->src.ptr);
1539 goto xchg;
fd2a7608 1540 case 0x9c: /* pushf */
05f086f8 1541 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 1542 emulate_push(ctxt);
1543 break;
535eabcf 1544 case 0x9d: /* popf */
05f086f8 1545 c->dst.ptr = (unsigned long *) &ctxt->eflags;
535eabcf 1546 goto pop_instruction;
018a98db
AK		 1547 case 0xa0 ... 0xa1: /* mov */
1548 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1549 c->dst.val = c->src.val;
1550 break;
1551 case 0xa2 ... 0xa3: /* mov */
1552 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1553 break;
6aa8b732 1554 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 1555 c->dst.type = OP_MEM;
1556 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1557 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1558 es_base(ctxt),
e4e03ded 1559 c->regs[VCPU_REGS_RDI]);
e4706772 1560 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 1561 seg_override_base(ctxt, c),
e4e03ded
LV		 1562 c->regs[VCPU_REGS_RSI]),
1563 &c->dst.val,
1564 c->dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1565 goto done;
7a957275 1566 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1567 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1568 : c->dst.bytes);
7a957275 1569 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1570 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1571 : c->dst.bytes);
6aa8b732
AK		 1572 break;
1573 case 0xa6 ... 0xa7: /* cmps */
d7e5117a
GT		 1574 c->src.type = OP_NONE; /* Disable writeback. */
1575 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1576 c->src.ptr = (unsigned long *)register_address(c,
7a5b56df 1577 seg_override_base(ctxt, c),
d7e5117a
GT		 1578 c->regs[VCPU_REGS_RSI]);
1579 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1580 &c->src.val,
1581 c->src.bytes,
1582 ctxt->vcpu)) != 0)
1583 goto done;
1584
1585 c->dst.type = OP_NONE; /* Disable writeback. */
1586 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1587 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1588 es_base(ctxt),
d7e5117a
GT		 1589 c->regs[VCPU_REGS_RDI]);
1590 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1591 &c->dst.val,
1592 c->dst.bytes,
1593 ctxt->vcpu)) != 0)
1594 goto done;
1595
1596 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1597
1598 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1599
7a957275 1600 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
d7e5117a
GT		 1601 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1602 : c->src.bytes);
7a957275 1603 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
d7e5117a
GT		 1604 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1605 : c->dst.bytes);
1606
1607 break;
6aa8b732 1608 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 1609 c->dst.type = OP_MEM;
1610 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1611 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1612 es_base(ctxt),
a7e6c88a 1613 c->regs[VCPU_REGS_RDI]);
e4e03ded 1614 c->dst.val = c->regs[VCPU_REGS_RAX];
7a957275 1615 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1616 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1617 : c->dst.bytes);
6aa8b732
AK		 1618 break;
1619 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 1620 c->dst.type = OP_REG;
1621 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1622 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
e4706772 1623 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 1624 seg_override_base(ctxt, c),
a7e6c88a
SY		 1625 c->regs[VCPU_REGS_RSI]),
1626 &c->dst.val,
1627 c->dst.bytes,
1628 ctxt->vcpu)) != 0)
6aa8b732 1629 goto done;
7a957275 1630 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1631 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1632 : c->dst.bytes);
6aa8b732
AK		 1633 break;
1634 case 0xae ... 0xaf: /* scas */
1635 DPRINTF("Urk! I don't handle SCAS.\n");
1636 goto cannot_emulate;
a5e2e82b 1637 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 1638 goto mov;
018a98db
AK		 1639 case 0xc0 ... 0xc1:
1640 emulate_grp2(ctxt);
1641 break;
111de5d6
AK		 1642 case 0xc3: /* ret */
1643 c->dst.ptr = &c->eip;
1644 goto pop_instruction;
018a98db
AK		 1645 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1646 mov:
1647 c->dst.val = c->src.val;
1648 break;
1649 case 0xd0 ... 0xd1: /* Grp2 */
1650 c->src.val = 1;
1651 emulate_grp2(ctxt);
1652 break;
1653 case 0xd2 ... 0xd3: /* Grp2 */
1654 c->src.val = c->regs[VCPU_REGS_RCX];
1655 emulate_grp2(ctxt);
1656 break;
a6a3034c
MG		 1657 case 0xe4: /* inb */
1658 case 0xe5: /* in */
1659 port = insn_fetch(u8, 1, c->eip);
1660 io_dir_in = 1;
1661 goto do_io;
1662 case 0xe6: /* outb */
1663 case 0xe7: /* out */
1664 port = insn_fetch(u8, 1, c->eip);
1665 io_dir_in = 0;
1666 goto do_io;
1a52e051
NK		 1667 case 0xe8: /* call (near) */ {
1668 long int rel;
e4e03ded 1669 switch (c->op_bytes) {
1a52e051 1670 case 2:
e4e03ded 1671 rel = insn_fetch(s16, 2, c->eip);
1a52e051
NK		 1672 break;
1673 case 4:
e4e03ded 1674 rel = insn_fetch(s32, 4, c->eip);
1a52e051 1675 break;
1a52e051
NK		 1676 default:
1677 DPRINTF("Call: Invalid op_bytes\n");
1678 goto cannot_emulate;
1679 }
e4e03ded 1680 c->src.val = (unsigned long) c->eip;
7a957275 1681 jmp_rel(c, rel);
e4e03ded 1682 c->op_bytes = c->ad_bytes;
8cdbd2c9
LV		 1683 emulate_push(ctxt);
1684 break;
1a52e051
NK		 1685 }
1686 case 0xe9: /* jmp rel */
954cd36f
GT		 1687 goto jmp;
1688 case 0xea: /* jmp far */ {
1689 uint32_t eip;
1690 uint16_t sel;
1691
1692 switch (c->op_bytes) {
1693 case 2:
1694 eip = insn_fetch(u16, 2, c->eip);
1695 break;
1696 case 4:
1697 eip = insn_fetch(u32, 4, c->eip);
1698 break;
1699 default:
1700 DPRINTF("jmp far: Invalid op_bytes\n");
1701 goto cannot_emulate;
1702 }
1703 sel = insn_fetch(u16, 2, c->eip);
1704 if (kvm_load_segment_descriptor(ctxt->vcpu, sel, 9, VCPU_SREG_CS) < 0) {
1705 DPRINTF("jmp far: Failed to load CS descriptor\n");
1706 goto cannot_emulate;
1707 }
1708
1709 c->eip = eip;
1710 break;
1711 }
1712 case 0xeb:
1713 jmp: /* jmp rel short */
7a957275 1714 jmp_rel(c, c->src.val);
a01af5ec 1715 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 1716 break;
a6a3034c
MG		 1717 case 0xec: /* in al,dx */
1718 case 0xed: /* in (e/r)ax,dx */
1719 port = c->regs[VCPU_REGS_RDX];
1720 io_dir_in = 1;
1721 goto do_io;
1722 case 0xee: /* out al,dx */
1723 case 0xef: /* out (e/r)ax,dx */
1724 port = c->regs[VCPU_REGS_RDX];
1725 io_dir_in = 0;
1726 do_io: if (kvm_emulate_pio(ctxt->vcpu, NULL, io_dir_in,
1727 (c->d & ByteOp) ? 1 : c->op_bytes,
1728 port) != 0) {
1729 c->eip = saved_eip;
1730 goto cannot_emulate;
1731 }
e93f36bc 1732 break;
111de5d6 1733 case 0xf4: /* hlt */
ad312c7c 1734 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 1735 break;
111de5d6
AK		 1736 case 0xf5: /* cmc */
1737 /* complement carry flag from eflags reg */
1738 ctxt->eflags ^= EFLG_CF;
1739 c->dst.type = OP_NONE; /* Disable writeback. */
1740 break;
018a98db
AK		 1741 case 0xf6 ... 0xf7: /* Grp3 */
1742 rc = emulate_grp3(ctxt, ops);
1743 if (rc != 0)
1744 goto done;
1745 break;
111de5d6
AK		 1746 case 0xf8: /* clc */
1747 ctxt->eflags &= ~EFLG_CF;
1748 c->dst.type = OP_NONE; /* Disable writeback. */
1749 break;
1750 case 0xfa: /* cli */
1751 ctxt->eflags &= ~X86_EFLAGS_IF;
1752 c->dst.type = OP_NONE; /* Disable writeback. */
1753 break;
1754 case 0xfb: /* sti */
1755 ctxt->eflags |= X86_EFLAGS_IF;
1756 c->dst.type = OP_NONE; /* Disable writeback. */
1757 break;
fb4616f4
MG		 1758 case 0xfc: /* cld */
1759 ctxt->eflags &= ~EFLG_DF;
1760 c->dst.type = OP_NONE; /* Disable writeback. */
1761 break;
1762 case 0xfd: /* std */
1763 ctxt->eflags |= EFLG_DF;
1764 c->dst.type = OP_NONE; /* Disable writeback. */
1765 break;
018a98db
AK		 1766 case 0xfe ... 0xff: /* Grp4/Grp5 */
1767 rc = emulate_grp45(ctxt, ops);
1768 if (rc != 0)
1769 goto done;
1770 break;
6aa8b732 1771 }
018a98db
AK		 1772
1773writeback:
1774 rc = writeback(ctxt, ops);
1775 if (rc != 0)
1776 goto done;
1777
1778 /* Commit shadow register state. */
ad312c7c 1779 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
5fdbf976 1780 kvm_rip_write(ctxt->vcpu, c->eip);
018a98db
AK		 1781
1782done:
1783 if (rc == X86EMUL_UNHANDLEABLE) {
1784 c->eip = saved_eip;
1785 return -1;
1786 }
1787 return 0;
6aa8b732
AK		 1788
1789twobyte_insn:
e4e03ded 1790 switch (c->b) {
6aa8b732 1791 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 1792 switch (c->modrm_reg) {
6aa8b732
AK		 1793 u16 size;
1794 unsigned long address;
1795
aca7f966 1796 case 0: /* vmcall */
e4e03ded 1797 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 1798 goto cannot_emulate;
1799
7aa81cc0
AL		 1800 rc = kvm_fix_hypercall(ctxt->vcpu);
1801 if (rc)
1802 goto done;
1803
33e3885d 1804 /* Let the processor re-execute the fixed hypercall */
5fdbf976 1805 c->eip = kvm_rip_read(ctxt->vcpu);
16286d08
AK		 1806 /* Disable writeback. */
1807 c->dst.type = OP_NONE;
aca7f966 1808 break;
6aa8b732 1809 case 2: /* lgdt */
e4e03ded
LV		 1810 rc = read_descriptor(ctxt, ops, c->src.ptr,
1811 &size, &address, c->op_bytes);
6aa8b732
AK		 1812 if (rc)
1813 goto done;
1814 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 1815 /* Disable writeback. */
1816 c->dst.type = OP_NONE;
6aa8b732 1817 break;
aca7f966 1818 case 3: /* lidt/vmmcall */
e4e03ded 1819 if (c->modrm_mod == 3 && c->modrm_rm == 1) {
7aa81cc0
AL		 1820 rc = kvm_fix_hypercall(ctxt->vcpu);
1821 if (rc)
1822 goto done;
1823 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1824 } else {
e4e03ded 1825 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 1826 &size, &address,
e4e03ded 1827 c->op_bytes);
aca7f966
AL		 1828 if (rc)
1829 goto done;
1830 realmode_lidt(ctxt->vcpu, size, address);
1831 }
16286d08
AK		 1832 /* Disable writeback. */
1833 c->dst.type = OP_NONE;
6aa8b732
AK		 1834 break;
1835 case 4: /* smsw */
16286d08
AK		 1836 c->dst.bytes = 2;
1837 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
6aa8b732
AK		 1838 break;
1839 case 6: /* lmsw */
16286d08
AK		 1840 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
1841 &ctxt->eflags);
dc7457ea 1842 c->dst.type = OP_NONE;
6aa8b732
AK		 1843 break;
1844 case 7: /* invlpg*/
e8d8d7fe 1845 emulate_invlpg(ctxt->vcpu, memop);
16286d08
AK		 1846 /* Disable writeback. */
1847 c->dst.type = OP_NONE;
6aa8b732
AK		 1848 break;
1849 default:
1850 goto cannot_emulate;
1851 }
1852 break;
018a98db
AK		 1853 case 0x06:
1854 emulate_clts(ctxt->vcpu);
1855 c->dst.type = OP_NONE;
1856 break;
1857 case 0x08: /* invd */
1858 case 0x09: /* wbinvd */
1859 case 0x0d: /* GrpP (prefetch) */
1860 case 0x18: /* Grp16 (prefetch/nop) */
1861 c->dst.type = OP_NONE;
1862 break;
1863 case 0x20: /* mov cr, reg */
1864 if (c->modrm_mod != 3)
1865 goto cannot_emulate;
1866 c->regs[c->modrm_rm] =
1867 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1868 c->dst.type = OP_NONE; /* no writeback */
1869 break;
6aa8b732 1870 case 0x21: /* mov from dr to reg */
e4e03ded 1871 if (c->modrm_mod != 3)
6aa8b732 1872 goto cannot_emulate;
8cdbd2c9 1873 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 1874 if (rc)
1875 goto cannot_emulate;
1876 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1877 break;
018a98db
AK		 1878 case 0x22: /* mov reg, cr */
1879 if (c->modrm_mod != 3)
1880 goto cannot_emulate;
1881 realmode_set_cr(ctxt->vcpu,
1882 c->modrm_reg, c->modrm_val, &ctxt->eflags);
1883 c->dst.type = OP_NONE;
1884 break;
6aa8b732 1885 case 0x23: /* mov from reg to dr */
e4e03ded 1886 if (c->modrm_mod != 3)
6aa8b732 1887 goto cannot_emulate;
e4e03ded
LV		 1888 rc = emulator_set_dr(ctxt, c->modrm_reg,
1889 c->regs[c->modrm_rm]);
a01af5ec
LV		 1890 if (rc)
1891 goto cannot_emulate;
1892 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1893 break;
018a98db
AK		 1894 case 0x30:
1895 /* wrmsr */
1896 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1897 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1898 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
1899 if (rc) {
c1a5d4f9 1900 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 1901 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 1902 }
1903 rc = X86EMUL_CONTINUE;
1904 c->dst.type = OP_NONE;
1905 break;
1906 case 0x32:
1907 /* rdmsr */
1908 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
1909 if (rc) {
c1a5d4f9 1910 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 1911 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 1912 } else {
1913 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
1914 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
1915 }
1916 rc = X86EMUL_CONTINUE;
1917 c->dst.type = OP_NONE;
1918 break;
6aa8b732 1919 case 0x40 ... 0x4f: /* cmov */
e4e03ded 1920 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 1921 if (!test_cc(c->b, ctxt->eflags))
1922 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1923 break;
018a98db
AK		 1924 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1925 long int rel;
1926
1927 switch (c->op_bytes) {
1928 case 2:
1929 rel = insn_fetch(s16, 2, c->eip);
1930 break;
1931 case 4:
1932 rel = insn_fetch(s32, 4, c->eip);
1933 break;
1934 case 8:
1935 rel = insn_fetch(s64, 8, c->eip);
1936 break;
1937 default:
1938 DPRINTF("jnz: Invalid op_bytes\n");
1939 goto cannot_emulate;
1940 }
1941 if (test_cc(c->b, ctxt->eflags))
7a957275 1942 jmp_rel(c, rel);
018a98db
AK		 1943 c->dst.type = OP_NONE;
1944 break;
1945 }
7de75248
NK		 1946 case 0xa3:
1947 bt: /* bt */
e4f8e039 1948 c->dst.type = OP_NONE;
e4e03ded
LV		 1949 /* only subword offset */
1950 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1951 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248
NK		 1952 break;
1953 case 0xab:
1954 bts: /* bts */
e4e03ded
LV		 1955 /* only subword offset */
1956 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1957 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 1958 break;
2a7c5b8b
GC		 1959 case 0xae: /* clflush */
1960 break;
6aa8b732
AK		 1961 case 0xb0 ... 0xb1: /* cmpxchg */
1962 /*
1963 * Save real source value, then compare EAX against
1964 * destination.
1965 */
e4e03ded
LV		 1966 c->src.orig_val = c->src.val;
1967 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 1968 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1969 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 1970 /* Success: write back to memory. */
e4e03ded 1971 c->dst.val = c->src.orig_val;
6aa8b732
AK		 1972 } else {
1973 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 1974 c->dst.type = OP_REG;
1975 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 1976 }
1977 break;
6aa8b732
AK		 1978 case 0xb3:
1979 btr: /* btr */
e4e03ded
LV		 1980 /* only subword offset */
1981 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1982 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 1983 break;
6aa8b732 1984 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 1985 c->dst.bytes = c->op_bytes;
1986 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
1987 : (u16) c->src.val;
6aa8b732 1988 break;
6aa8b732 1989 case 0xba: /* Grp8 */
e4e03ded 1990 switch (c->modrm_reg & 3) {
6aa8b732
AK		 1991 case 0:
1992 goto bt;
1993 case 1:
1994 goto bts;
1995 case 2:
1996 goto btr;
1997 case 3:
1998 goto btc;
1999 }
2000 break;
7de75248
NK		 2001 case 0xbb:
2002 btc: /* btc */
e4e03ded
LV		 2003 /* only subword offset */
2004 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2005 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 2006 break;
6aa8b732 2007 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 2008 c->dst.bytes = c->op_bytes;
2009 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
2010 (s16) c->src.val;
6aa8b732 2011 break;
a012e65a 2012 case 0xc3: /* movnti */
e4e03ded
LV		 2013 c->dst.bytes = c->op_bytes;
2014 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
2015 (u64) c->src.val;
a012e65a 2016 break;
6aa8b732 2017 case 0xc7: /* Grp9 (cmpxchg8b) */
e8d8d7fe 2018 rc = emulate_grp9(ctxt, ops, memop);
8cdbd2c9
LV		 2019 if (rc != 0)
2020 goto done;
018a98db 2021 c->dst.type = OP_NONE;
8cdbd2c9 2022 break;
6aa8b732
AK		 2023 }
2024 goto writeback;
2025
2026cannot_emulate:
e4e03ded 2027 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 2028 c->eip = saved_eip;
6aa8b732
AK		 2029 return -1;
2030}
Linux kernel - Deliverables
This page took 0.366117 seconds and 5 git commands to generate.