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KVM: x86 emulator: add a new "implied 1" Src decode type
[deliverable/linux.git] / arch / x86 / kvm / x86_emulate.c
CommitLineData
6aa8b732
AK		 1/******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
5fdbf976 29#include "kvm_cache_regs.h"
6aa8b732
AK		 30#define DPRINTF(x...) do {} while (0)
31#endif
6aa8b732 32#include <linux/module.h>
edf88417 33#include <asm/kvm_x86_emulate.h>
6aa8b732
AK		 34
35/*
36 * Opcode effective-address decode tables.
37 * Note that we only emulate instructions that have at least one memory
38 * operand (excluding implicit stack references). We assume that stack
39 * references and instruction fetches will never occur in special memory
40 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
41 * not be handled.
42 */
43
44/* Operand sizes: 8-bit operands or specified/overridden size. */
45#define ByteOp (1<<0) /* 8-bit operands. */
46/* Destination operand type. */
47#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
48#define DstReg (2<<1) /* Register operand. */
49#define DstMem (3<<1) /* Memory operand. */
9c9fddd0
GT		 50#define DstAcc (4<<1) /* Destination Accumulator */
51#define DstMask (7<<1)
6aa8b732 52/* Source operand type. */
9c9fddd0
GT		 53#define SrcNone (0<<4) /* No source operand. */
54#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
55#define SrcReg (1<<4) /* Register operand. */
56#define SrcMem (2<<4) /* Memory operand. */
57#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
58#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
59#define SrcImm (5<<4) /* Immediate operand. */
60#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 61#define SrcOne (7<<4) /* Implied '1' */
9c9fddd0 62#define SrcMask (7<<4)
6aa8b732 63/* Generic ModRM decode. */
9c9fddd0 64#define ModRM (1<<7)
6aa8b732 65/* Destination is only written; never read. */
9c9fddd0
GT		 66#define Mov (1<<8)
67#define BitOp (1<<9)
68#define MemAbs (1<<10) /* Memory operand is absolute displacement */
69#define String (1<<12) /* String instruction (rep capable) */
70#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 71#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
72#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
73#define GroupMask 0xff /* Group number stored in bits 0:7 */
0dc8d10f
GT		 74/* Source 2 operand type */
75#define Src2None (0<<29)
76#define Src2CL (1<<29)
77#define Src2ImmByte (2<<29)
78#define Src2One (3<<29)
79#define Src2Mask (7<<29)
6aa8b732 80
43bb19cd 81enum {
1d6ad207 82 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 83 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
43bb19cd
AK		 84};
85
45ed60b3 86static u32 opcode_table[256] = {
6aa8b732
AK		 87 /* 0x00 - 0x07 */
88 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
89 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
291fd39b 90 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, 0, 0,
6aa8b732
AK		 91 /* 0x08 - 0x0F */
92 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
93 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94 0, 0, 0, 0,
95 /* 0x10 - 0x17 */
96 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
97 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
98 0, 0, 0, 0,
99 /* 0x18 - 0x1F */
100 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
101 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
102 0, 0, 0, 0,
103 /* 0x20 - 0x27 */
104 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
105 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
aa3a816b 106 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732
AK		 107 /* 0x28 - 0x2F */
108 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
109 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
110 0, 0, 0, 0,
111 /* 0x30 - 0x37 */
112 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
113 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
114 0, 0, 0, 0,
115 /* 0x38 - 0x3F */
116 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
117 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
8a9fee67
GT		 118 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
119 0, 0,
d77a2507 120 /* 0x40 - 0x47 */
33615aa9 121 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 122 /* 0x48 - 0x4F */
33615aa9 123 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 124 /* 0x50 - 0x57 */
6e3d5dfb
AK		 125 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
126 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 127 /* 0x58 - 0x5F */
6e3d5dfb
AK		 128 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
129 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 130 /* 0x60 - 0x67 */
6aa8b732 131 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 132 0, 0, 0, 0,
133 /* 0x68 - 0x6F */
91ed7a0e 134 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
e70669ab
LV		 135 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
136 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4
NK		 137 /* 0x70 - 0x77 */
138 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
139 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
140 /* 0x78 - 0x7F */
141 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
142 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732 143 /* 0x80 - 0x87 */
1d6ad207
AK		 144 Group | Group1_80, Group | Group1_81,
145 Group | Group1_82, Group | Group1_83,
6aa8b732
AK		 146 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
147 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
148 /* 0x88 - 0x8F */
149 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
150 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
38d5bc6d 151 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
4257198a 152 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
b13354f8
MG		 153 /* 0x90 - 0x97 */
154 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
155 /* 0x98 - 0x9F */
6e3d5dfb 156 0, 0, 0, 0, ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 157 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 158 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
159 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
b9fa9d6b
AK		 160 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
161 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 162 /* 0xA8 - 0xAF */
b9fa9d6b
AK		 163 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
164 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
165 ByteOp | ImplicitOps | String, ImplicitOps | String,
a5e2e82b
MG		 166 /* 0xB0 - 0xB7 */
167 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
168 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
169 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
170 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
171 /* 0xB8 - 0xBF */
172 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
173 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
174 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
175 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
6aa8b732 176 /* 0xC0 - 0xC7 */
d9413cd7 177 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 178 0, ImplicitOps | Stack, 0, 0,
d9413cd7 179 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732
AK		 180 /* 0xC8 - 0xCF */
181 0, 0, 0, 0, 0, 0, 0, 0,
182 /* 0xD0 - 0xD7 */
183 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
184 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
185 0, 0, 0, 0,
186 /* 0xD8 - 0xDF */
187 0, 0, 0, 0, 0, 0, 0, 0,
098c937b 188 /* 0xE0 - 0xE7 */
a6a3034c
MG		 189 0, 0, 0, 0,
190 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
191 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
098c937b 192 /* 0xE8 - 0xEF */
954cd36f
GT		 193 ImplicitOps | Stack, SrcImm | ImplicitOps,
194 ImplicitOps, SrcImmByte | ImplicitOps,
a6a3034c
MG		 195 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
196 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
6aa8b732
AK		 197 /* 0xF0 - 0xF7 */
198 0, 0, 0, 0,
7d858a19 199 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 200 /* 0xF8 - 0xFF */
b284be57 201 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fb4616f4 202 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
6aa8b732
AK		 203};
204
45ed60b3 205static u32 twobyte_table[256] = {
6aa8b732 206 /* 0x00 - 0x0F */
d95058a1 207 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
651a3e29 208 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 209 /* 0x10 - 0x1F */
210 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
211 /* 0x20 - 0x2F */
212 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
213 0, 0, 0, 0, 0, 0, 0, 0,
214 /* 0x30 - 0x3F */
35f3f286 215 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 216 /* 0x40 - 0x47 */
217 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
218 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
219 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
220 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
221 /* 0x48 - 0x4F */
222 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
223 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
224 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
225 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
226 /* 0x50 - 0x5F */
227 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
228 /* 0x60 - 0x6F */
229 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
230 /* 0x70 - 0x7F */
231 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
232 /* 0x80 - 0x8F */
bbe9abbd
NK		 233 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
234 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
235 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
236 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 237 /* 0x90 - 0x9F */
238 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
239 /* 0xA0 - 0xA7 */
038e51de 240 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732 241 /* 0xA8 - 0xAF */
2a7c5b8b 242 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, ModRM, 0,
6aa8b732
AK		 243 /* 0xB0 - 0xB7 */
244 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 245 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 246 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
247 DstReg | SrcMem16 | ModRM | Mov,
248 /* 0xB8 - 0xBF */
038e51de 249 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 250 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
251 DstReg | SrcMem16 | ModRM | Mov,
252 /* 0xC0 - 0xCF */
a012e65a
SY		 253 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
254 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 255 /* 0xD0 - 0xDF */
256 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
257 /* 0xE0 - 0xEF */
258 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
259 /* 0xF0 - 0xFF */
260 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
261};
262
45ed60b3 263static u32 group_table[] = {
1d6ad207
AK		 264 [Group1_80*8] =
265 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
266 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
267 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
268 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
269 [Group1_81*8] =
270 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
271 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
272 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
273 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
274 [Group1_82*8] =
275 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
276 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
277 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
278 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
279 [Group1_83*8] =
280 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
281 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
282 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
283 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 284 [Group1A*8] =
285 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 286 [Group3_Byte*8] =
287 ByteOp | SrcImm | DstMem | ModRM, 0,
288 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
289 0, 0, 0, 0,
290 [Group3*8] =
41afa025 291 DstMem | SrcImm | ModRM, 0,
6eb06cb2 292 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
7d858a19 293 0, 0, 0, 0,
fd60754e
AK		 294 [Group4*8] =
295 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
296 0, 0, 0, 0, 0, 0,
297 [Group5*8] =
d19292e4
MG		 298 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
299 SrcMem | ModRM | Stack, 0,
ef46f18e 300 SrcMem | ModRM | Stack, 0, SrcMem | ModRM | Stack, 0,
d95058a1
AK		 301 [Group7*8] =
302 0, 0, ModRM | SrcMem, ModRM | SrcMem,
16286d08
AK		 303 SrcNone | ModRM | DstMem | Mov, 0,
304 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
e09d082c
AK		 305};
306
45ed60b3 307static u32 group2_table[] = {
d95058a1 308 [Group7*8] =
16286d08
AK		 309 SrcNone | ModRM, 0, 0, 0,
310 SrcNone | ModRM | DstMem | Mov, 0,
311 SrcMem16 | ModRM | Mov, 0,
e09d082c
AK		 312};
313
6aa8b732
AK		 314/* EFLAGS bit definitions. */
315#define EFLG_OF (1<<11)
316#define EFLG_DF (1<<10)
317#define EFLG_SF (1<<7)
318#define EFLG_ZF (1<<6)
319#define EFLG_AF (1<<4)
320#define EFLG_PF (1<<2)
321#define EFLG_CF (1<<0)
322
323/*
324 * Instruction emulation:
325 * Most instructions are emulated directly via a fragment of inline assembly
326 * code. This allows us to save/restore EFLAGS and thus very easily pick up
327 * any modified flags.
328 */
329
05b3e0c2 330#if defined(CONFIG_X86_64)
6aa8b732
AK		 331#define _LO32 "k" /* force 32-bit operand */
332#define _STK "%%rsp" /* stack pointer */
333#elif defined(__i386__)
334#define _LO32 "" /* force 32-bit operand */
335#define _STK "%%esp" /* stack pointer */
336#endif
337
338/*
339 * These EFLAGS bits are restored from saved value during emulation, and
340 * any changes are written back to the saved value after emulation.
341 */
342#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
343
344/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 345#define _PRE_EFLAGS(_sav, _msk, _tmp) \
346 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
347 "movl %"_sav",%"_LO32 _tmp"; " \
348 "push %"_tmp"; " \
349 "push %"_tmp"; " \
350 "movl %"_msk",%"_LO32 _tmp"; " \
351 "andl %"_LO32 _tmp",("_STK"); " \
352 "pushf; " \
353 "notl %"_LO32 _tmp"; " \
354 "andl %"_LO32 _tmp",("_STK"); " \
355 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
356 "pop %"_tmp"; " \
357 "orl %"_LO32 _tmp",("_STK"); " \
358 "popf; " \
359 "pop %"_sav"; "
6aa8b732
AK		 360
361/* After executing instruction: write-back necessary bits in EFLAGS. */
362#define _POST_EFLAGS(_sav, _msk, _tmp) \
363 /* _sav |= EFLAGS & _msk; */ \
364 "pushf; " \
365 "pop %"_tmp"; " \
366 "andl %"_msk",%"_LO32 _tmp"; " \
367 "orl %"_LO32 _tmp",%"_sav"; "
368
dda96d8f
AK		 369#ifdef CONFIG_X86_64
370#define ON64(x) x
371#else
372#define ON64(x)
373#endif
374
6b7ad61f
AK		 375#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
376 do { \
377 __asm__ __volatile__ ( \
378 _PRE_EFLAGS("0", "4", "2") \
379 _op _suffix " %"_x"3,%1; " \
380 _POST_EFLAGS("0", "4", "2") \
381 : "=m" (_eflags), "=m" ((_dst).val), \
382 "=&r" (_tmp) \
383 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 384 } while (0)
6b7ad61f
AK		 385
386
6aa8b732
AK		 387/* Raw emulation: instruction has two explicit operands. */
388#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 389 do { \
390 unsigned long _tmp; \
391 \
392 switch ((_dst).bytes) { \
393 case 2: \
394 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
395 break; \
396 case 4: \
397 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
398 break; \
399 case 8: \
400 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
401 break; \
402 } \
6aa8b732
AK		 403 } while (0)
404
405#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
406 do { \
6b7ad61f 407 unsigned long _tmp; \
d77c26fc 408 switch ((_dst).bytes) { \
6aa8b732 409 case 1: \
6b7ad61f 410 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 411 break; \
412 default: \
413 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
414 _wx, _wy, _lx, _ly, _qx, _qy); \
415 break; \
416 } \
417 } while (0)
418
419/* Source operand is byte-sized and may be restricted to just %cl. */
420#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
421 __emulate_2op(_op, _src, _dst, _eflags, \
422 "b", "c", "b", "c", "b", "c", "b", "c")
423
424/* Source operand is byte, word, long or quad sized. */
425#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
426 __emulate_2op(_op, _src, _dst, _eflags, \
427 "b", "q", "w", "r", _LO32, "r", "", "r")
428
429/* Source operand is word, long or quad sized. */
430#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
431 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
432 "w", "r", _LO32, "r", "", "r")
433
dda96d8f 434#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 435 do { \
436 unsigned long _tmp; \
437 \
dda96d8f
AK		 438 __asm__ __volatile__ ( \
439 _PRE_EFLAGS("0", "3", "2") \
440 _op _suffix " %1; " \
441 _POST_EFLAGS("0", "3", "2") \
442 : "=m" (_eflags), "+m" ((_dst).val), \
443 "=&r" (_tmp) \
444 : "i" (EFLAGS_MASK)); \
445 } while (0)
446
447/* Instruction has only one explicit operand (no source operand). */
448#define emulate_1op(_op, _dst, _eflags) \
449 do { \
d77c26fc 450 switch ((_dst).bytes) { \
dda96d8f
AK		 451 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
452 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
453 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
454 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 455 } \
456 } while (0)
457
6aa8b732
AK		 458/* Fetch next part of the instruction being emulated. */
459#define insn_fetch(_type, _size, _eip) \
460({ unsigned long _x; \
62266869 461 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
d77c26fc 462 if (rc != 0) \
6aa8b732
AK		 463 goto done; \
464 (_eip) += (_size); \
465 (_type)_x; \
466})
467
ddcb2885
HH		 468static inline unsigned long ad_mask(struct decode_cache *c)
469{
470 return (1UL << (c->ad_bytes << 3)) - 1;
471}
472
6aa8b732 473/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 474static inline unsigned long
475address_mask(struct decode_cache *c, unsigned long reg)
476{
477 if (c->ad_bytes == sizeof(unsigned long))
478 return reg;
479 else
480 return reg & ad_mask(c);
481}
482
483static inline unsigned long
484register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
485{
486 return base + address_mask(c, reg);
487}
488
7a957275
HH		 489static inline void
490register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
491{
492 if (c->ad_bytes == sizeof(unsigned long))
493 *reg += inc;
494 else
495 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
496}
6aa8b732 497
7a957275
HH		 498static inline void jmp_rel(struct decode_cache *c, int rel)
499{
500 register_address_increment(c, &c->eip, rel);
501}
098c937b 502
7a5b56df
AK		 503static void set_seg_override(struct decode_cache *c, int seg)
504{
505 c->has_seg_override = true;
506 c->seg_override = seg;
507}
508
509static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
510{
511 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
512 return 0;
513
514 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
515}
516
517static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
518 struct decode_cache *c)
519{
520 if (!c->has_seg_override)
521 return 0;
522
523 return seg_base(ctxt, c->seg_override);
524}
525
526static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
527{
528 return seg_base(ctxt, VCPU_SREG_ES);
529}
530
531static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
532{
533 return seg_base(ctxt, VCPU_SREG_SS);
534}
535
62266869
AK		 536static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
537 struct x86_emulate_ops *ops,
538 unsigned long linear, u8 *dest)
539{
540 struct fetch_cache *fc = &ctxt->decode.fetch;
541 int rc;
542 int size;
543
544 if (linear < fc->start || linear >= fc->end) {
545 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
546 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
547 if (rc)
548 return rc;
549 fc->start = linear;
550 fc->end = linear + size;
551 }
552 *dest = fc->data[linear - fc->start];
553 return 0;
554}
555
556static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
557 struct x86_emulate_ops *ops,
558 unsigned long eip, void *dest, unsigned size)
559{
560 int rc = 0;
561
562 eip += ctxt->cs_base;
563 while (size--) {
564 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
565 if (rc)
566 return rc;
567 }
568 return 0;
569}
570
1e3c5cb0
RR		 571/*
572 * Given the 'reg' portion of a ModRM byte, and a register block, return a
573 * pointer into the block that addresses the relevant register.
574 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
575 */
576static void *decode_register(u8 modrm_reg, unsigned long *regs,
577 int highbyte_regs)
6aa8b732
AK		 578{
579 void *p;
580
581 p = &regs[modrm_reg];
582 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
583 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
584 return p;
585}
586
587static int read_descriptor(struct x86_emulate_ctxt *ctxt,
588 struct x86_emulate_ops *ops,
589 void *ptr,
590 u16 *size, unsigned long *address, int op_bytes)
591{
592 int rc;
593
594 if (op_bytes == 2)
595 op_bytes = 3;
596 *address = 0;
cebff02b
LV		 597 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
598 ctxt->vcpu);
6aa8b732
AK		 599 if (rc)
600 return rc;
cebff02b
LV		 601 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
602 ctxt->vcpu);
6aa8b732
AK		 603 return rc;
604}
605
bbe9abbd
NK		 606static int test_cc(unsigned int condition, unsigned int flags)
607{
608 int rc = 0;
609
610 switch ((condition & 15) >> 1) {
611 case 0: /* o */
612 rc |= (flags & EFLG_OF);
613 break;
614 case 1: /* b/c/nae */
615 rc |= (flags & EFLG_CF);
616 break;
617 case 2: /* z/e */
618 rc |= (flags & EFLG_ZF);
619 break;
620 case 3: /* be/na */
621 rc |= (flags & (EFLG_CF|EFLG_ZF));
622 break;
623 case 4: /* s */
624 rc |= (flags & EFLG_SF);
625 break;
626 case 5: /* p/pe */
627 rc |= (flags & EFLG_PF);
628 break;
629 case 7: /* le/ng */
630 rc |= (flags & EFLG_ZF);
631 /* fall through */
632 case 6: /* l/nge */
633 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
634 break;
635 }
636
637 /* Odd condition identifiers (lsb == 1) have inverted sense. */
638 return (!!rc ^ (condition & 1));
639}
640
3c118e24
AK		 641static void decode_register_operand(struct operand *op,
642 struct decode_cache *c,
3c118e24
AK		 643 int inhibit_bytereg)
644{
33615aa9 645 unsigned reg = c->modrm_reg;
9f1ef3f8 646 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 647
648 if (!(c->d & ModRM))
649 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 650 op->type = OP_REG;
651 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 652 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 653 op->val = *(u8 *)op->ptr;
654 op->bytes = 1;
655 } else {
33615aa9 656 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 657 op->bytes = c->op_bytes;
658 switch (op->bytes) {
659 case 2:
660 op->val = *(u16 *)op->ptr;
661 break;
662 case 4:
663 op->val = *(u32 *)op->ptr;
664 break;
665 case 8:
666 op->val = *(u64 *) op->ptr;
667 break;
668 }
669 }
670 op->orig_val = op->val;
671}
672
1c73ef66
AK		 673static int decode_modrm(struct x86_emulate_ctxt *ctxt,
674 struct x86_emulate_ops *ops)
675{
676 struct decode_cache *c = &ctxt->decode;
677 u8 sib;
f5b4edcd 678 int index_reg = 0, base_reg = 0, scale;
1c73ef66
AK		 679 int rc = 0;
680
681 if (c->rex_prefix) {
682 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
683 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
684 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
685 }
686
687 c->modrm = insn_fetch(u8, 1, c->eip);
688 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
689 c->modrm_reg |= (c->modrm & 0x38) >> 3;
690 c->modrm_rm |= (c->modrm & 0x07);
691 c->modrm_ea = 0;
692 c->use_modrm_ea = 1;
693
694 if (c->modrm_mod == 3) {
107d6d2e
AK		 695 c->modrm_ptr = decode_register(c->modrm_rm,
696 c->regs, c->d & ByteOp);
697 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 698 return rc;
699 }
700
701 if (c->ad_bytes == 2) {
702 unsigned bx = c->regs[VCPU_REGS_RBX];
703 unsigned bp = c->regs[VCPU_REGS_RBP];
704 unsigned si = c->regs[VCPU_REGS_RSI];
705 unsigned di = c->regs[VCPU_REGS_RDI];
706
707 /* 16-bit ModR/M decode. */
708 switch (c->modrm_mod) {
709 case 0:
710 if (c->modrm_rm == 6)
711 c->modrm_ea += insn_fetch(u16, 2, c->eip);
712 break;
713 case 1:
714 c->modrm_ea += insn_fetch(s8, 1, c->eip);
715 break;
716 case 2:
717 c->modrm_ea += insn_fetch(u16, 2, c->eip);
718 break;
719 }
720 switch (c->modrm_rm) {
721 case 0:
722 c->modrm_ea += bx + si;
723 break;
724 case 1:
725 c->modrm_ea += bx + di;
726 break;
727 case 2:
728 c->modrm_ea += bp + si;
729 break;
730 case 3:
731 c->modrm_ea += bp + di;
732 break;
733 case 4:
734 c->modrm_ea += si;
735 break;
736 case 5:
737 c->modrm_ea += di;
738 break;
739 case 6:
740 if (c->modrm_mod != 0)
741 c->modrm_ea += bp;
742 break;
743 case 7:
744 c->modrm_ea += bx;
745 break;
746 }
747 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
748 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 749 if (!c->has_seg_override)
750 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 751 c->modrm_ea = (u16)c->modrm_ea;
752 } else {
753 /* 32/64-bit ModR/M decode. */
84411d85 754 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 755 sib = insn_fetch(u8, 1, c->eip);
756 index_reg |= (sib >> 3) & 7;
757 base_reg |= sib & 7;
758 scale = sib >> 6;
759
dc71d0f1
AK		 760 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
761 c->modrm_ea += insn_fetch(s32, 4, c->eip);
762 else
1c73ef66 763 c->modrm_ea += c->regs[base_reg];
dc71d0f1 764 if (index_reg != 4)
1c73ef66 765 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 766 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
767 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 768 c->rip_relative = 1;
84411d85 769 } else
1c73ef66 770 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 771 switch (c->modrm_mod) {
772 case 0:
773 if (c->modrm_rm == 5)
774 c->modrm_ea += insn_fetch(s32, 4, c->eip);
775 break;
776 case 1:
777 c->modrm_ea += insn_fetch(s8, 1, c->eip);
778 break;
779 case 2:
780 c->modrm_ea += insn_fetch(s32, 4, c->eip);
781 break;
782 }
783 }
1c73ef66
AK		 784done:
785 return rc;
786}
787
788static int decode_abs(struct x86_emulate_ctxt *ctxt,
789 struct x86_emulate_ops *ops)
790{
791 struct decode_cache *c = &ctxt->decode;
792 int rc = 0;
793
794 switch (c->ad_bytes) {
795 case 2:
796 c->modrm_ea = insn_fetch(u16, 2, c->eip);
797 break;
798 case 4:
799 c->modrm_ea = insn_fetch(u32, 4, c->eip);
800 break;
801 case 8:
802 c->modrm_ea = insn_fetch(u64, 8, c->eip);
803 break;
804 }
805done:
806 return rc;
807}
808
6aa8b732 809int
8b4caf66 810x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 811{
e4e03ded 812 struct decode_cache *c = &ctxt->decode;
6aa8b732 813 int rc = 0;
6aa8b732 814 int mode = ctxt->mode;
e09d082c 815 int def_op_bytes, def_ad_bytes, group;
6aa8b732
AK		 816
817 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 818
e4e03ded 819 memset(c, 0, sizeof(struct decode_cache));
5fdbf976 820 c->eip = kvm_rip_read(ctxt->vcpu);
7a5b56df 821 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
ad312c7c 822 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 823
824 switch (mode) {
825 case X86EMUL_MODE_REAL:
826 case X86EMUL_MODE_PROT16:
f21b8bf4 827 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 828 break;
829 case X86EMUL_MODE_PROT32:
f21b8bf4 830 def_op_bytes = def_ad_bytes = 4;
6aa8b732 831 break;
05b3e0c2 832#ifdef CONFIG_X86_64
6aa8b732 833 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 834 def_op_bytes = 4;
835 def_ad_bytes = 8;
6aa8b732
AK		 836 break;
837#endif
838 default:
839 return -1;
840 }
841
f21b8bf4
AK		 842 c->op_bytes = def_op_bytes;
843 c->ad_bytes = def_ad_bytes;
844
6aa8b732 845 /* Legacy prefixes. */
b4c6abfe 846 for (;;) {
e4e03ded 847 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 848 case 0x66: /* operand-size override */
f21b8bf4
AK		 849 /* switch between 2/4 bytes */
850 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 851 break;
852 case 0x67: /* address-size override */
853 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 854 /* switch between 4/8 bytes */
f21b8bf4 855 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 856 else
e4e03ded 857 /* switch between 2/4 bytes */
f21b8bf4 858 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 859 break;
7a5b56df 860 case 0x26: /* ES override */
6aa8b732 861 case 0x2e: /* CS override */
7a5b56df 862 case 0x36: /* SS override */
6aa8b732 863 case 0x3e: /* DS override */
7a5b56df 864 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 865 break;
866 case 0x64: /* FS override */
6aa8b732 867 case 0x65: /* GS override */
7a5b56df 868 set_seg_override(c, c->b & 7);
6aa8b732 869 break;
b4c6abfe
LV		 870 case 0x40 ... 0x4f: /* REX */
871 if (mode != X86EMUL_MODE_PROT64)
872 goto done_prefixes;
33615aa9 873 c->rex_prefix = c->b;
b4c6abfe 874 continue;
6aa8b732 875 case 0xf0: /* LOCK */
e4e03ded 876 c->lock_prefix = 1;
6aa8b732 877 break;
ae6200ba 878 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 879 c->rep_prefix = REPNE_PREFIX;
880 break;
6aa8b732 881 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 882 c->rep_prefix = REPE_PREFIX;
6aa8b732 883 break;
6aa8b732
AK		 884 default:
885 goto done_prefixes;
886 }
b4c6abfe
LV		 887
888 /* Any legacy prefix after a REX prefix nullifies its effect. */
889
33615aa9 890 c->rex_prefix = 0;
6aa8b732
AK		 891 }
892
893done_prefixes:
894
895 /* REX prefix. */
1c73ef66 896 if (c->rex_prefix)
33615aa9 897 if (c->rex_prefix & 8)
e4e03ded 898 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 899
900 /* Opcode byte(s). */
e4e03ded
LV		 901 c->d = opcode_table[c->b];
902 if (c->d == 0) {
6aa8b732 903 /* Two-byte opcode? */
e4e03ded
LV		 904 if (c->b == 0x0f) {
905 c->twobyte = 1;
906 c->b = insn_fetch(u8, 1, c->eip);
907 c->d = twobyte_table[c->b];
6aa8b732 908 }
e09d082c 909 }
6aa8b732 910
e09d082c
AK		 911 if (c->d & Group) {
912 group = c->d & GroupMask;
913 c->modrm = insn_fetch(u8, 1, c->eip);
914 --c->eip;
915
916 group = (group << 3) + ((c->modrm >> 3) & 7);
917 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
918 c->d = group2_table[group];
919 else
920 c->d = group_table[group];
921 }
922
923 /* Unrecognised? */
924 if (c->d == 0) {
925 DPRINTF("Cannot emulate %02x\n", c->b);
926 return -1;
6aa8b732
AK		 927 }
928
6e3d5dfb
AK		 929 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
930 c->op_bytes = 8;
931
6aa8b732 932 /* ModRM and SIB bytes. */
1c73ef66
AK		 933 if (c->d & ModRM)
934 rc = decode_modrm(ctxt, ops);
935 else if (c->d & MemAbs)
936 rc = decode_abs(ctxt, ops);
937 if (rc)
938 goto done;
6aa8b732 939
7a5b56df
AK		 940 if (!c->has_seg_override)
941 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 942
7a5b56df
AK		 943 if (!(!c->twobyte && c->b == 0x8d))
944 c->modrm_ea += seg_override_base(ctxt, c);
c7e75a3d
AK		 945
946 if (c->ad_bytes != 8)
947 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 948 /*
949 * Decode and fetch the source operand: register, memory
950 * or immediate.
951 */
e4e03ded 952 switch (c->d & SrcMask) {
6aa8b732
AK		 953 case SrcNone:
954 break;
955 case SrcReg:
9f1ef3f8 956 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 957 break;
958 case SrcMem16:
e4e03ded 959 c->src.bytes = 2;
6aa8b732
AK		 960 goto srcmem_common;
961 case SrcMem32:
e4e03ded 962 c->src.bytes = 4;
6aa8b732
AK		 963 goto srcmem_common;
964 case SrcMem:
e4e03ded
LV		 965 c->src.bytes = (c->d & ByteOp) ? 1 :
966 c->op_bytes;
b85b9ee9 967 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 968 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 969 break;
d77c26fc 970 srcmem_common:
4e62417b
AJ		 971 /*
972 * For instructions with a ModR/M byte, switch to register
973 * access if Mod = 3.
974 */
e4e03ded
LV		 975 if ((c->d & ModRM) && c->modrm_mod == 3) {
976 c->src.type = OP_REG;
66b85505 977 c->src.val = c->modrm_val;
107d6d2e 978 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 979 break;
980 }
e4e03ded 981 c->src.type = OP_MEM;
6aa8b732
AK		 982 break;
983 case SrcImm:
e4e03ded
LV		 984 c->src.type = OP_IMM;
985 c->src.ptr = (unsigned long *)c->eip;
986 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
987 if (c->src.bytes == 8)
988 c->src.bytes = 4;
6aa8b732 989 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 990 switch (c->src.bytes) {
6aa8b732 991 case 1:
e4e03ded 992 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 993 break;
994 case 2:
e4e03ded 995 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 996 break;
997 case 4:
e4e03ded 998 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 999 break;
1000 }
1001 break;
1002 case SrcImmByte:
e4e03ded
LV		 1003 c->src.type = OP_IMM;
1004 c->src.ptr = (unsigned long *)c->eip;
1005 c->src.bytes = 1;
1006 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732 1007 break;
bfcadf83
GT		 1008 case SrcOne:
1009 c->src.bytes = 1;
1010 c->src.val = 1;
1011 break;
6aa8b732
AK		 1012 }
1013
0dc8d10f
GT		 1014 /*
1015 * Decode and fetch the second source operand: register, memory
1016 * or immediate.
1017 */
1018 switch (c->d & Src2Mask) {
1019 case Src2None:
1020 break;
1021 case Src2CL:
1022 c->src2.bytes = 1;
1023 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1024 break;
1025 case Src2ImmByte:
1026 c->src2.type = OP_IMM;
1027 c->src2.ptr = (unsigned long *)c->eip;
1028 c->src2.bytes = 1;
1029 c->src2.val = insn_fetch(u8, 1, c->eip);
1030 break;
1031 case Src2One:
1032 c->src2.bytes = 1;
1033 c->src2.val = 1;
1034 break;
1035 }
1036
038e51de 1037 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1038 switch (c->d & DstMask) {
038e51de
AK		 1039 case ImplicitOps:
1040 /* Special instructions do their own operand decoding. */
8b4caf66 1041 return 0;
038e51de 1042 case DstReg:
9f1ef3f8 1043 decode_register_operand(&c->dst, c,
3c118e24 1044 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1045 break;
1046 case DstMem:
e4e03ded 1047 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1048 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1049 c->dst.type = OP_REG;
66b85505 1050 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1051 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1052 break;
1053 }
8b4caf66
LV		 1054 c->dst.type = OP_MEM;
1055 break;
9c9fddd0
GT		 1056 case DstAcc:
1057 c->dst.type = OP_REG;
1058 c->dst.bytes = c->op_bytes;
1059 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1060 switch (c->op_bytes) {
1061 case 1:
1062 c->dst.val = *(u8 *)c->dst.ptr;
1063 break;
1064 case 2:
1065 c->dst.val = *(u16 *)c->dst.ptr;
1066 break;
1067 case 4:
1068 c->dst.val = *(u32 *)c->dst.ptr;
1069 break;
1070 }
1071 c->dst.orig_val = c->dst.val;
1072 break;
8b4caf66
LV		 1073 }
1074
f5b4edcd
AK		 1075 if (c->rip_relative)
1076 c->modrm_ea += c->eip;
1077
8b4caf66
LV		 1078done:
1079 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1080}
1081
8cdbd2c9
LV		 1082static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1083{
1084 struct decode_cache *c = &ctxt->decode;
1085
1086 c->dst.type = OP_MEM;
1087 c->dst.bytes = c->op_bytes;
1088 c->dst.val = c->src.val;
7a957275 1089 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
7a5b56df 1090 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1091 c->regs[VCPU_REGS_RSP]);
1092}
1093
faa5a3ae
AK		 1094static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1095 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1096{
1097 struct decode_cache *c = &ctxt->decode;
1098 int rc;
1099
781d0edc
AK		 1100 rc = ops->read_emulated(register_address(c, ss_base(ctxt),
1101 c->regs[VCPU_REGS_RSP]),
1102 &c->src.val, c->src.bytes, ctxt->vcpu);
8cdbd2c9
LV		 1103 if (rc != 0)
1104 return rc;
1105
faa5a3ae
AK		 1106 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.bytes);
1107 return rc;
1108}
8cdbd2c9 1109
faa5a3ae
AK		 1110static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1111 struct x86_emulate_ops *ops)
1112{
1113 struct decode_cache *c = &ctxt->decode;
1114 int rc;
1115
1116 c->src.bytes = c->dst.bytes;
1117 rc = emulate_pop(ctxt, ops);
1118 if (rc != 0)
1119 return rc;
1120 c->dst.val = c->src.val;
8cdbd2c9
LV		 1121 return 0;
1122}
1123
05f086f8 1124static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1125{
05f086f8 1126 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1127 switch (c->modrm_reg) {
1128 case 0: /* rol */
05f086f8 1129 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1130 break;
1131 case 1: /* ror */
05f086f8 1132 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1133 break;
1134 case 2: /* rcl */
05f086f8 1135 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1136 break;
1137 case 3: /* rcr */
05f086f8 1138 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1139 break;
1140 case 4: /* sal/shl */
1141 case 6: /* sal/shl */
05f086f8 1142 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1143 break;
1144 case 5: /* shr */
05f086f8 1145 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1146 break;
1147 case 7: /* sar */
05f086f8 1148 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1149 break;
1150 }
1151}
1152
1153static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1154 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1155{
1156 struct decode_cache *c = &ctxt->decode;
1157 int rc = 0;
1158
1159 switch (c->modrm_reg) {
1160 case 0 ... 1: /* test */
05f086f8 1161 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1162 break;
1163 case 2: /* not */
1164 c->dst.val = ~c->dst.val;
1165 break;
1166 case 3: /* neg */
05f086f8 1167 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1168 break;
1169 default:
1170 DPRINTF("Cannot emulate %02x\n", c->b);
1171 rc = X86EMUL_UNHANDLEABLE;
1172 break;
1173 }
8cdbd2c9
LV		 1174 return rc;
1175}
1176
1177static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1178 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1179{
1180 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1181
1182 switch (c->modrm_reg) {
1183 case 0: /* inc */
05f086f8 1184 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1185 break;
1186 case 1: /* dec */
05f086f8 1187 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1188 break;
d19292e4
MG		 1189 case 2: /* call near abs */ {
1190 long int old_eip;
1191 old_eip = c->eip;
1192 c->eip = c->src.val;
1193 c->src.val = old_eip;
1194 emulate_push(ctxt);
1195 break;
1196 }
8cdbd2c9 1197 case 4: /* jmp abs */
fd60754e 1198 c->eip = c->src.val;
8cdbd2c9
LV		 1199 break;
1200 case 6: /* push */
fd60754e 1201 emulate_push(ctxt);
8cdbd2c9 1202 break;
8cdbd2c9
LV		 1203 }
1204 return 0;
1205}
1206
1207static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1208 struct x86_emulate_ops *ops,
e8d8d7fe 1209 unsigned long memop)
8cdbd2c9
LV		 1210{
1211 struct decode_cache *c = &ctxt->decode;
1212 u64 old, new;
1213 int rc;
1214
e8d8d7fe 1215 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
8cdbd2c9
LV		 1216 if (rc != 0)
1217 return rc;
1218
1219 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1220 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1221
1222 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1223 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1224 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1225
1226 } else {
1227 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1228 (u32) c->regs[VCPU_REGS_RBX];
1229
e8d8d7fe 1230 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
8cdbd2c9
LV		 1231 if (rc != 0)
1232 return rc;
05f086f8 1233 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1234 }
1235 return 0;
1236}
1237
1238static inline int writeback(struct x86_emulate_ctxt *ctxt,
1239 struct x86_emulate_ops *ops)
1240{
1241 int rc;
1242 struct decode_cache *c = &ctxt->decode;
1243
1244 switch (c->dst.type) {
1245 case OP_REG:
1246 /* The 4-byte case *is* correct:
1247 * in 64-bit mode we zero-extend.
1248 */
1249 switch (c->dst.bytes) {
1250 case 1:
1251 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1252 break;
1253 case 2:
1254 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1255 break;
1256 case 4:
1257 *c->dst.ptr = (u32)c->dst.val;
1258 break; /* 64b: zero-ext */
1259 case 8:
1260 *c->dst.ptr = c->dst.val;
1261 break;
1262 }
1263 break;
1264 case OP_MEM:
1265 if (c->lock_prefix)
1266 rc = ops->cmpxchg_emulated(
1267 (unsigned long)c->dst.ptr,
1268 &c->dst.orig_val,
1269 &c->dst.val,
1270 c->dst.bytes,
1271 ctxt->vcpu);
1272 else
1273 rc = ops->write_emulated(
1274 (unsigned long)c->dst.ptr,
1275 &c->dst.val,
1276 c->dst.bytes,
1277 ctxt->vcpu);
1278 if (rc != 0)
1279 return rc;
a01af5ec
LV		 1280 break;
1281 case OP_NONE:
1282 /* no writeback */
1283 break;
8cdbd2c9
LV		 1284 default:
1285 break;
1286 }
1287 return 0;
1288}
1289
8b4caf66 1290int
1be3aa47 1291x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 1292{
e8d8d7fe 1293 unsigned long memop = 0;
8b4caf66 1294 u64 msr_data;
3427318f 1295 unsigned long saved_eip = 0;
8b4caf66 1296 struct decode_cache *c = &ctxt->decode;
a6a3034c
MG		 1297 unsigned int port;
1298 int io_dir_in;
1be3aa47 1299 int rc = 0;
8b4caf66 1300
3427318f
LV		 1301 /* Shadow copy of register state. Committed on successful emulation.
1302 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1303 * modify them.
1304 */
1305
ad312c7c 1306 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f
LV		 1307 saved_eip = c->eip;
1308
c7e75a3d 1309 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
e8d8d7fe 1310 memop = c->modrm_ea;
8b4caf66 1311
b9fa9d6b
AK		 1312 if (c->rep_prefix && (c->d & String)) {
1313 /* All REP prefixes have the same first termination condition */
1314 if (c->regs[VCPU_REGS_RCX] == 0) {
5fdbf976 1315 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1316 goto done;
1317 }
1318 /* The second termination condition only applies for REPE
1319 * and REPNE. Test if the repeat string operation prefix is
1320 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1321 * corresponding termination condition according to:
1322 * - if REPE/REPZ and ZF = 0 then done
1323 * - if REPNE/REPNZ and ZF = 1 then done
1324 */
1325 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1326 (c->b == 0xae) || (c->b == 0xaf)) {
1327 if ((c->rep_prefix == REPE_PREFIX) &&
1328 ((ctxt->eflags & EFLG_ZF) == 0)) {
5fdbf976 1329 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1330 goto done;
1331 }
1332 if ((c->rep_prefix == REPNE_PREFIX) &&
1333 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
5fdbf976 1334 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1335 goto done;
1336 }
1337 }
1338 c->regs[VCPU_REGS_RCX]--;
5fdbf976 1339 c->eip = kvm_rip_read(ctxt->vcpu);
b9fa9d6b
AK		 1340 }
1341
8b4caf66 1342 if (c->src.type == OP_MEM) {
e8d8d7fe 1343 c->src.ptr = (unsigned long *)memop;
8b4caf66 1344 c->src.val = 0;
d77c26fc
MD		 1345 rc = ops->read_emulated((unsigned long)c->src.ptr,
1346 &c->src.val,
1347 c->src.bytes,
1348 ctxt->vcpu);
1349 if (rc != 0)
8b4caf66
LV		 1350 goto done;
1351 c->src.orig_val = c->src.val;
1352 }
1353
1354 if ((c->d & DstMask) == ImplicitOps)
1355 goto special_insn;
1356
1357
1358 if (c->dst.type == OP_MEM) {
e8d8d7fe 1359 c->dst.ptr = (unsigned long *)memop;
8b4caf66
LV		 1360 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1361 c->dst.val = 0;
e4e03ded
LV		 1362 if (c->d & BitOp) {
1363 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1364
e4e03ded
LV		 1365 c->dst.ptr = (void *)c->dst.ptr +
1366 (c->src.val & mask) / 8;
038e51de 1367 }
e4e03ded
LV		 1368 if (!(c->d & Mov) &&
1369 /* optimisation - avoid slow emulated read */
1370 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1371 &c->dst.val,
1372 c->dst.bytes, ctxt->vcpu)) != 0))
038e51de 1373 goto done;
038e51de 1374 }
e4e03ded 1375 c->dst.orig_val = c->dst.val;
038e51de 1376
018a98db
AK		 1377special_insn:
1378
e4e03ded 1379 if (c->twobyte)
6aa8b732
AK		 1380 goto twobyte_insn;
1381
e4e03ded 1382 switch (c->b) {
6aa8b732
AK		 1383 case 0x00 ... 0x05:
1384 add: /* add */
05f086f8 1385 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1386 break;
1387 case 0x08 ... 0x0d:
1388 or: /* or */
05f086f8 1389 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1390 break;
1391 case 0x10 ... 0x15:
1392 adc: /* adc */
05f086f8 1393 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1394 break;
1395 case 0x18 ... 0x1d:
1396 sbb: /* sbb */
05f086f8 1397 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1398 break;
aa3a816b 1399 case 0x20 ... 0x25:
6aa8b732 1400 and: /* and */
05f086f8 1401 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1402 break;
1403 case 0x28 ... 0x2d:
1404 sub: /* sub */
05f086f8 1405 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1406 break;
1407 case 0x30 ... 0x35:
1408 xor: /* xor */
05f086f8 1409 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1410 break;
1411 case 0x38 ... 0x3d:
1412 cmp: /* cmp */
05f086f8 1413 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 1414 break;
33615aa9
AK		 1415 case 0x40 ... 0x47: /* inc r16/r32 */
1416 emulate_1op("inc", c->dst, ctxt->eflags);
1417 break;
1418 case 0x48 ... 0x4f: /* dec r16/r32 */
1419 emulate_1op("dec", c->dst, ctxt->eflags);
1420 break;
1421 case 0x50 ... 0x57: /* push reg */
2786b014 1422 emulate_push(ctxt);
33615aa9
AK		 1423 break;
1424 case 0x58 ... 0x5f: /* pop reg */
1425 pop_instruction:
8a09b687
AK		 1426 c->src.bytes = c->op_bytes;
1427 rc = emulate_pop(ctxt, ops);
1428 if (rc != 0)
33615aa9 1429 goto done;
8a09b687 1430 c->dst.val = c->src.val;
33615aa9 1431 break;
6aa8b732 1432 case 0x63: /* movsxd */
8b4caf66 1433 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1434 goto cannot_emulate;
e4e03ded 1435 c->dst.val = (s32) c->src.val;
6aa8b732 1436 break;
91ed7a0e 1437 case 0x68: /* push imm */
018a98db 1438 case 0x6a: /* push imm8 */
018a98db
AK		 1439 emulate_push(ctxt);
1440 break;
1441 case 0x6c: /* insb */
1442 case 0x6d: /* insw/insd */
1443 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1444 1,
1445 (c->d & ByteOp) ? 1 : c->op_bytes,
1446 c->rep_prefix ?
e4706772 1447 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1448 (ctxt->eflags & EFLG_DF),
7a5b56df 1449 register_address(c, es_base(ctxt),
018a98db
AK		 1450 c->regs[VCPU_REGS_RDI]),
1451 c->rep_prefix,
1452 c->regs[VCPU_REGS_RDX]) == 0) {
1453 c->eip = saved_eip;
1454 return -1;
1455 }
1456 return 0;
1457 case 0x6e: /* outsb */
1458 case 0x6f: /* outsw/outsd */
1459 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1460 0,
1461 (c->d & ByteOp) ? 1 : c->op_bytes,
1462 c->rep_prefix ?
e4706772 1463 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1464 (ctxt->eflags & EFLG_DF),
7a5b56df
AK		 1465 register_address(c,
1466 seg_override_base(ctxt, c),
018a98db
AK		 1467 c->regs[VCPU_REGS_RSI]),
1468 c->rep_prefix,
1469 c->regs[VCPU_REGS_RDX]) == 0) {
1470 c->eip = saved_eip;
1471 return -1;
1472 }
1473 return 0;
1474 case 0x70 ... 0x7f: /* jcc (short) */ {
1475 int rel = insn_fetch(s8, 1, c->eip);
1476
1477 if (test_cc(c->b, ctxt->eflags))
7a957275 1478 jmp_rel(c, rel);
018a98db
AK		 1479 break;
1480 }
6aa8b732 1481 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 1482 switch (c->modrm_reg) {
6aa8b732
AK		 1483 case 0:
1484 goto add;
1485 case 1:
1486 goto or;
1487 case 2:
1488 goto adc;
1489 case 3:
1490 goto sbb;
1491 case 4:
1492 goto and;
1493 case 5:
1494 goto sub;
1495 case 6:
1496 goto xor;
1497 case 7:
1498 goto cmp;
1499 }
1500 break;
1501 case 0x84 ... 0x85:
05f086f8 1502 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1503 break;
1504 case 0x86 ... 0x87: /* xchg */
b13354f8 1505 xchg:
6aa8b732 1506 /* Write back the register source. */
e4e03ded 1507 switch (c->dst.bytes) {
6aa8b732 1508 case 1:
e4e03ded 1509 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 1510 break;
1511 case 2:
e4e03ded 1512 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 1513 break;
1514 case 4:
e4e03ded 1515 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 1516 break; /* 64b reg: zero-extend */
1517 case 8:
e4e03ded 1518 *c->src.ptr = c->dst.val;
6aa8b732
AK		 1519 break;
1520 }
1521 /*
1522 * Write back the memory destination with implicit LOCK
1523 * prefix.
1524 */
e4e03ded
LV		 1525 c->dst.val = c->src.val;
1526 c->lock_prefix = 1;
6aa8b732 1527 break;
6aa8b732 1528 case 0x88 ... 0x8b: /* mov */
7de75248 1529 goto mov;
38d5bc6d
GT		 1530 case 0x8c: { /* mov r/m, sreg */
1531 struct kvm_segment segreg;
1532
1533 if (c->modrm_reg <= 5)
1534 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
1535 else {
1536 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
1537 c->modrm);
1538 goto cannot_emulate;
1539 }
1540 c->dst.val = segreg.selector;
1541 break;
1542 }
7e0b54b1 1543 case 0x8d: /* lea r16/r32, m */
f9b7aab3 1544 c->dst.val = c->modrm_ea;
7e0b54b1 1545 break;
4257198a
GT		 1546 case 0x8e: { /* mov seg, r/m16 */
1547 uint16_t sel;
1548 int type_bits;
1549 int err;
1550
1551 sel = c->src.val;
1552 if (c->modrm_reg <= 5) {
1553 type_bits = (c->modrm_reg == 1) ? 9 : 1;
1554 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
1555 type_bits, c->modrm_reg);
1556 } else {
1557 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
1558 c->modrm);
1559 goto cannot_emulate;
1560 }
1561
1562 if (err < 0)
1563 goto cannot_emulate;
1564
1565 c->dst.type = OP_NONE; /* Disable writeback. */
1566 break;
1567 }
6aa8b732 1568 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 1569 rc = emulate_grp1a(ctxt, ops);
1570 if (rc != 0)
6aa8b732 1571 goto done;
6aa8b732 1572 break;
b13354f8
MG		 1573 case 0x90: /* nop / xchg r8,rax */
1574 if (!(c->rex_prefix & 1)) { /* nop */
1575 c->dst.type = OP_NONE;
1576 break;
1577 }
1578 case 0x91 ... 0x97: /* xchg reg,rax */
1579 c->src.type = c->dst.type = OP_REG;
1580 c->src.bytes = c->dst.bytes = c->op_bytes;
1581 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
1582 c->src.val = *(c->src.ptr);
1583 goto xchg;
fd2a7608 1584 case 0x9c: /* pushf */
05f086f8 1585 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 1586 emulate_push(ctxt);
1587 break;
535eabcf 1588 case 0x9d: /* popf */
2b48cc75 1589 c->dst.type = OP_REG;
05f086f8 1590 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2b48cc75 1591 c->dst.bytes = c->op_bytes;
535eabcf 1592 goto pop_instruction;
018a98db
AK		 1593 case 0xa0 ... 0xa1: /* mov */
1594 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1595 c->dst.val = c->src.val;
1596 break;
1597 case 0xa2 ... 0xa3: /* mov */
1598 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1599 break;
6aa8b732 1600 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 1601 c->dst.type = OP_MEM;
1602 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1603 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1604 es_base(ctxt),
e4e03ded 1605 c->regs[VCPU_REGS_RDI]);
e4706772 1606 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 1607 seg_override_base(ctxt, c),
e4e03ded
LV		 1608 c->regs[VCPU_REGS_RSI]),
1609 &c->dst.val,
1610 c->dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1611 goto done;
7a957275 1612 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1613 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1614 : c->dst.bytes);
7a957275 1615 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1616 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1617 : c->dst.bytes);
6aa8b732
AK		 1618 break;
1619 case 0xa6 ... 0xa7: /* cmps */
d7e5117a
GT		 1620 c->src.type = OP_NONE; /* Disable writeback. */
1621 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1622 c->src.ptr = (unsigned long *)register_address(c,
7a5b56df 1623 seg_override_base(ctxt, c),
d7e5117a
GT		 1624 c->regs[VCPU_REGS_RSI]);
1625 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1626 &c->src.val,
1627 c->src.bytes,
1628 ctxt->vcpu)) != 0)
1629 goto done;
1630
1631 c->dst.type = OP_NONE; /* Disable writeback. */
1632 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1633 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1634 es_base(ctxt),
d7e5117a
GT		 1635 c->regs[VCPU_REGS_RDI]);
1636 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1637 &c->dst.val,
1638 c->dst.bytes,
1639 ctxt->vcpu)) != 0)
1640 goto done;
1641
1642 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1643
1644 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1645
7a957275 1646 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
d7e5117a
GT		 1647 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1648 : c->src.bytes);
7a957275 1649 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
d7e5117a
GT		 1650 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1651 : c->dst.bytes);
1652
1653 break;
6aa8b732 1654 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 1655 c->dst.type = OP_MEM;
1656 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1657 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1658 es_base(ctxt),
a7e6c88a 1659 c->regs[VCPU_REGS_RDI]);
e4e03ded 1660 c->dst.val = c->regs[VCPU_REGS_RAX];
7a957275 1661 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1662 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1663 : c->dst.bytes);
6aa8b732
AK		 1664 break;
1665 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 1666 c->dst.type = OP_REG;
1667 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1668 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
e4706772 1669 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 1670 seg_override_base(ctxt, c),
a7e6c88a
SY		 1671 c->regs[VCPU_REGS_RSI]),
1672 &c->dst.val,
1673 c->dst.bytes,
1674 ctxt->vcpu)) != 0)
6aa8b732 1675 goto done;
7a957275 1676 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1677 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1678 : c->dst.bytes);
6aa8b732
AK		 1679 break;
1680 case 0xae ... 0xaf: /* scas */
1681 DPRINTF("Urk! I don't handle SCAS.\n");
1682 goto cannot_emulate;
a5e2e82b 1683 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 1684 goto mov;
018a98db
AK		 1685 case 0xc0 ... 0xc1:
1686 emulate_grp2(ctxt);
1687 break;
111de5d6 1688 case 0xc3: /* ret */
cf5de4f8 1689 c->dst.type = OP_REG;
111de5d6 1690 c->dst.ptr = &c->eip;
cf5de4f8 1691 c->dst.bytes = c->op_bytes;
111de5d6 1692 goto pop_instruction;
018a98db
AK		 1693 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1694 mov:
1695 c->dst.val = c->src.val;
1696 break;
1697 case 0xd0 ... 0xd1: /* Grp2 */
1698 c->src.val = 1;
1699 emulate_grp2(ctxt);
1700 break;
1701 case 0xd2 ... 0xd3: /* Grp2 */
1702 c->src.val = c->regs[VCPU_REGS_RCX];
1703 emulate_grp2(ctxt);
1704 break;
a6a3034c
MG		 1705 case 0xe4: /* inb */
1706 case 0xe5: /* in */
1707 port = insn_fetch(u8, 1, c->eip);
1708 io_dir_in = 1;
1709 goto do_io;
1710 case 0xe6: /* outb */
1711 case 0xe7: /* out */
1712 port = insn_fetch(u8, 1, c->eip);
1713 io_dir_in = 0;
1714 goto do_io;
1a52e051
NK		 1715 case 0xe8: /* call (near) */ {
1716 long int rel;
e4e03ded 1717 switch (c->op_bytes) {
1a52e051 1718 case 2:
e4e03ded 1719 rel = insn_fetch(s16, 2, c->eip);
1a52e051
NK		 1720 break;
1721 case 4:
e4e03ded 1722 rel = insn_fetch(s32, 4, c->eip);
1a52e051 1723 break;
1a52e051
NK		 1724 default:
1725 DPRINTF("Call: Invalid op_bytes\n");
1726 goto cannot_emulate;
1727 }
e4e03ded 1728 c->src.val = (unsigned long) c->eip;
7a957275 1729 jmp_rel(c, rel);
e4e03ded 1730 c->op_bytes = c->ad_bytes;
8cdbd2c9
LV		 1731 emulate_push(ctxt);
1732 break;
1a52e051
NK		 1733 }
1734 case 0xe9: /* jmp rel */
954cd36f
GT		 1735 goto jmp;
1736 case 0xea: /* jmp far */ {
1737 uint32_t eip;
1738 uint16_t sel;
1739
1740 switch (c->op_bytes) {
1741 case 2:
1742 eip = insn_fetch(u16, 2, c->eip);
1743 break;
1744 case 4:
1745 eip = insn_fetch(u32, 4, c->eip);
1746 break;
1747 default:
1748 DPRINTF("jmp far: Invalid op_bytes\n");
1749 goto cannot_emulate;
1750 }
1751 sel = insn_fetch(u16, 2, c->eip);
1752 if (kvm_load_segment_descriptor(ctxt->vcpu, sel, 9, VCPU_SREG_CS) < 0) {
1753 DPRINTF("jmp far: Failed to load CS descriptor\n");
1754 goto cannot_emulate;
1755 }
1756
1757 c->eip = eip;
1758 break;
1759 }
1760 case 0xeb:
1761 jmp: /* jmp rel short */
7a957275 1762 jmp_rel(c, c->src.val);
a01af5ec 1763 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 1764 break;
a6a3034c
MG		 1765 case 0xec: /* in al,dx */
1766 case 0xed: /* in (e/r)ax,dx */
1767 port = c->regs[VCPU_REGS_RDX];
1768 io_dir_in = 1;
1769 goto do_io;
1770 case 0xee: /* out al,dx */
1771 case 0xef: /* out (e/r)ax,dx */
1772 port = c->regs[VCPU_REGS_RDX];
1773 io_dir_in = 0;
1774 do_io: if (kvm_emulate_pio(ctxt->vcpu, NULL, io_dir_in,
1775 (c->d & ByteOp) ? 1 : c->op_bytes,
1776 port) != 0) {
1777 c->eip = saved_eip;
1778 goto cannot_emulate;
1779 }
e93f36bc 1780 break;
111de5d6 1781 case 0xf4: /* hlt */
ad312c7c 1782 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 1783 break;
111de5d6
AK		 1784 case 0xf5: /* cmc */
1785 /* complement carry flag from eflags reg */
1786 ctxt->eflags ^= EFLG_CF;
1787 c->dst.type = OP_NONE; /* Disable writeback. */
1788 break;
018a98db
AK		 1789 case 0xf6 ... 0xf7: /* Grp3 */
1790 rc = emulate_grp3(ctxt, ops);
1791 if (rc != 0)
1792 goto done;
1793 break;
111de5d6
AK		 1794 case 0xf8: /* clc */
1795 ctxt->eflags &= ~EFLG_CF;
1796 c->dst.type = OP_NONE; /* Disable writeback. */
1797 break;
1798 case 0xfa: /* cli */
1799 ctxt->eflags &= ~X86_EFLAGS_IF;
1800 c->dst.type = OP_NONE; /* Disable writeback. */
1801 break;
1802 case 0xfb: /* sti */
1803 ctxt->eflags |= X86_EFLAGS_IF;
1804 c->dst.type = OP_NONE; /* Disable writeback. */
1805 break;
fb4616f4
MG		 1806 case 0xfc: /* cld */
1807 ctxt->eflags &= ~EFLG_DF;
1808 c->dst.type = OP_NONE; /* Disable writeback. */
1809 break;
1810 case 0xfd: /* std */
1811 ctxt->eflags |= EFLG_DF;
1812 c->dst.type = OP_NONE; /* Disable writeback. */
1813 break;
018a98db
AK		 1814 case 0xfe ... 0xff: /* Grp4/Grp5 */
1815 rc = emulate_grp45(ctxt, ops);
1816 if (rc != 0)
1817 goto done;
1818 break;
6aa8b732 1819 }
018a98db
AK		 1820
1821writeback:
1822 rc = writeback(ctxt, ops);
1823 if (rc != 0)
1824 goto done;
1825
1826 /* Commit shadow register state. */
ad312c7c 1827 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
5fdbf976 1828 kvm_rip_write(ctxt->vcpu, c->eip);
018a98db
AK		 1829
1830done:
1831 if (rc == X86EMUL_UNHANDLEABLE) {
1832 c->eip = saved_eip;
1833 return -1;
1834 }
1835 return 0;
6aa8b732
AK		 1836
1837twobyte_insn:
e4e03ded 1838 switch (c->b) {
6aa8b732 1839 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 1840 switch (c->modrm_reg) {
6aa8b732
AK		 1841 u16 size;
1842 unsigned long address;
1843
aca7f966 1844 case 0: /* vmcall */
e4e03ded 1845 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 1846 goto cannot_emulate;
1847
7aa81cc0
AL		 1848 rc = kvm_fix_hypercall(ctxt->vcpu);
1849 if (rc)
1850 goto done;
1851
33e3885d 1852 /* Let the processor re-execute the fixed hypercall */
5fdbf976 1853 c->eip = kvm_rip_read(ctxt->vcpu);
16286d08
AK		 1854 /* Disable writeback. */
1855 c->dst.type = OP_NONE;
aca7f966 1856 break;
6aa8b732 1857 case 2: /* lgdt */
e4e03ded
LV		 1858 rc = read_descriptor(ctxt, ops, c->src.ptr,
1859 &size, &address, c->op_bytes);
6aa8b732
AK		 1860 if (rc)
1861 goto done;
1862 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 1863 /* Disable writeback. */
1864 c->dst.type = OP_NONE;
6aa8b732 1865 break;
aca7f966 1866 case 3: /* lidt/vmmcall */
e4e03ded 1867 if (c->modrm_mod == 3 && c->modrm_rm == 1) {
7aa81cc0
AL		 1868 rc = kvm_fix_hypercall(ctxt->vcpu);
1869 if (rc)
1870 goto done;
1871 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1872 } else {
e4e03ded 1873 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 1874 &size, &address,
e4e03ded 1875 c->op_bytes);
aca7f966
AL		 1876 if (rc)
1877 goto done;
1878 realmode_lidt(ctxt->vcpu, size, address);
1879 }
16286d08
AK		 1880 /* Disable writeback. */
1881 c->dst.type = OP_NONE;
6aa8b732
AK		 1882 break;
1883 case 4: /* smsw */
16286d08
AK		 1884 c->dst.bytes = 2;
1885 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
6aa8b732
AK		 1886 break;
1887 case 6: /* lmsw */
16286d08
AK		 1888 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
1889 &ctxt->eflags);
dc7457ea 1890 c->dst.type = OP_NONE;
6aa8b732
AK		 1891 break;
1892 case 7: /* invlpg*/
e8d8d7fe 1893 emulate_invlpg(ctxt->vcpu, memop);
16286d08
AK		 1894 /* Disable writeback. */
1895 c->dst.type = OP_NONE;
6aa8b732
AK		 1896 break;
1897 default:
1898 goto cannot_emulate;
1899 }
1900 break;
018a98db
AK		 1901 case 0x06:
1902 emulate_clts(ctxt->vcpu);
1903 c->dst.type = OP_NONE;
1904 break;
1905 case 0x08: /* invd */
1906 case 0x09: /* wbinvd */
1907 case 0x0d: /* GrpP (prefetch) */
1908 case 0x18: /* Grp16 (prefetch/nop) */
1909 c->dst.type = OP_NONE;
1910 break;
1911 case 0x20: /* mov cr, reg */
1912 if (c->modrm_mod != 3)
1913 goto cannot_emulate;
1914 c->regs[c->modrm_rm] =
1915 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1916 c->dst.type = OP_NONE; /* no writeback */
1917 break;
6aa8b732 1918 case 0x21: /* mov from dr to reg */
e4e03ded 1919 if (c->modrm_mod != 3)
6aa8b732 1920 goto cannot_emulate;
8cdbd2c9 1921 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 1922 if (rc)
1923 goto cannot_emulate;
1924 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1925 break;
018a98db
AK		 1926 case 0x22: /* mov reg, cr */
1927 if (c->modrm_mod != 3)
1928 goto cannot_emulate;
1929 realmode_set_cr(ctxt->vcpu,
1930 c->modrm_reg, c->modrm_val, &ctxt->eflags);
1931 c->dst.type = OP_NONE;
1932 break;
6aa8b732 1933 case 0x23: /* mov from reg to dr */
e4e03ded 1934 if (c->modrm_mod != 3)
6aa8b732 1935 goto cannot_emulate;
e4e03ded
LV		 1936 rc = emulator_set_dr(ctxt, c->modrm_reg,
1937 c->regs[c->modrm_rm]);
a01af5ec
LV		 1938 if (rc)
1939 goto cannot_emulate;
1940 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1941 break;
018a98db
AK		 1942 case 0x30:
1943 /* wrmsr */
1944 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1945 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1946 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
1947 if (rc) {
c1a5d4f9 1948 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 1949 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 1950 }
1951 rc = X86EMUL_CONTINUE;
1952 c->dst.type = OP_NONE;
1953 break;
1954 case 0x32:
1955 /* rdmsr */
1956 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
1957 if (rc) {
c1a5d4f9 1958 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 1959 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 1960 } else {
1961 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
1962 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
1963 }
1964 rc = X86EMUL_CONTINUE;
1965 c->dst.type = OP_NONE;
1966 break;
6aa8b732 1967 case 0x40 ... 0x4f: /* cmov */
e4e03ded 1968 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 1969 if (!test_cc(c->b, ctxt->eflags))
1970 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1971 break;
018a98db
AK		 1972 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1973 long int rel;
1974
1975 switch (c->op_bytes) {
1976 case 2:
1977 rel = insn_fetch(s16, 2, c->eip);
1978 break;
1979 case 4:
1980 rel = insn_fetch(s32, 4, c->eip);
1981 break;
1982 case 8:
1983 rel = insn_fetch(s64, 8, c->eip);
1984 break;
1985 default:
1986 DPRINTF("jnz: Invalid op_bytes\n");
1987 goto cannot_emulate;
1988 }
1989 if (test_cc(c->b, ctxt->eflags))
7a957275 1990 jmp_rel(c, rel);
018a98db
AK		 1991 c->dst.type = OP_NONE;
1992 break;
1993 }
7de75248
NK		 1994 case 0xa3:
1995 bt: /* bt */
e4f8e039 1996 c->dst.type = OP_NONE;
e4e03ded
LV		 1997 /* only subword offset */
1998 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1999 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248
NK		 2000 break;
2001 case 0xab:
2002 bts: /* bts */
e4e03ded
LV		 2003 /* only subword offset */
2004 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2005 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 2006 break;
2a7c5b8b
GC		 2007 case 0xae: /* clflush */
2008 break;
6aa8b732
AK		 2009 case 0xb0 ... 0xb1: /* cmpxchg */
2010 /*
2011 * Save real source value, then compare EAX against
2012 * destination.
2013 */
e4e03ded
LV		 2014 c->src.orig_val = c->src.val;
2015 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 2016 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2017 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 2018 /* Success: write back to memory. */
e4e03ded 2019 c->dst.val = c->src.orig_val;
6aa8b732
AK		 2020 } else {
2021 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 2022 c->dst.type = OP_REG;
2023 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2024 }
2025 break;
6aa8b732
AK		 2026 case 0xb3:
2027 btr: /* btr */
e4e03ded
LV		 2028 /* only subword offset */
2029 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2030 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 2031 break;
6aa8b732 2032 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 2033 c->dst.bytes = c->op_bytes;
2034 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
2035 : (u16) c->src.val;
6aa8b732 2036 break;
6aa8b732 2037 case 0xba: /* Grp8 */
e4e03ded 2038 switch (c->modrm_reg & 3) {
6aa8b732
AK		 2039 case 0:
2040 goto bt;
2041 case 1:
2042 goto bts;
2043 case 2:
2044 goto btr;
2045 case 3:
2046 goto btc;
2047 }
2048 break;
7de75248
NK		 2049 case 0xbb:
2050 btc: /* btc */
e4e03ded
LV		 2051 /* only subword offset */
2052 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2053 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 2054 break;
6aa8b732 2055 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 2056 c->dst.bytes = c->op_bytes;
2057 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
2058 (s16) c->src.val;
6aa8b732 2059 break;
a012e65a 2060 case 0xc3: /* movnti */
e4e03ded
LV		 2061 c->dst.bytes = c->op_bytes;
2062 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
2063 (u64) c->src.val;
a012e65a 2064 break;
6aa8b732 2065 case 0xc7: /* Grp9 (cmpxchg8b) */
e8d8d7fe 2066 rc = emulate_grp9(ctxt, ops, memop);
8cdbd2c9
LV		 2067 if (rc != 0)
2068 goto done;
018a98db 2069 c->dst.type = OP_NONE;
8cdbd2c9 2070 break;
6aa8b732
AK		 2071 }
2072 goto writeback;
2073
2074cannot_emulate:
e4e03ded 2075 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 2076 c->eip = saved_eip;
6aa8b732
AK		 2077 return -1;
2078}
Linux kernel - Deliverables
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