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KVM: x86 emulator: Complete decoding of call near in decode stage
[deliverable/linux.git] / arch / x86 / kvm / x86_emulate.c
CommitLineData
6aa8b732
AK		 1/******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
5fdbf976 29#include "kvm_cache_regs.h"
6aa8b732
AK		 30#define DPRINTF(x...) do {} while (0)
31#endif
6aa8b732 32#include <linux/module.h>
edf88417 33#include <asm/kvm_x86_emulate.h>
6aa8b732
AK		 34
35/*
36 * Opcode effective-address decode tables.
37 * Note that we only emulate instructions that have at least one memory
38 * operand (excluding implicit stack references). We assume that stack
39 * references and instruction fetches will never occur in special memory
40 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
41 * not be handled.
42 */
43
44/* Operand sizes: 8-bit operands or specified/overridden size. */
45#define ByteOp (1<<0) /* 8-bit operands. */
46/* Destination operand type. */
47#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
48#define DstReg (2<<1) /* Register operand. */
49#define DstMem (3<<1) /* Memory operand. */
9c9fddd0
GT		 50#define DstAcc (4<<1) /* Destination Accumulator */
51#define DstMask (7<<1)
6aa8b732 52/* Source operand type. */
9c9fddd0
GT		 53#define SrcNone (0<<4) /* No source operand. */
54#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
55#define SrcReg (1<<4) /* Register operand. */
56#define SrcMem (2<<4) /* Memory operand. */
57#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
58#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
59#define SrcImm (5<<4) /* Immediate operand. */
60#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
bfcadf83 61#define SrcOne (7<<4) /* Implied '1' */
9c9fddd0 62#define SrcMask (7<<4)
6aa8b732 63/* Generic ModRM decode. */
9c9fddd0 64#define ModRM (1<<7)
6aa8b732 65/* Destination is only written; never read. */
9c9fddd0
GT		 66#define Mov (1<<8)
67#define BitOp (1<<9)
68#define MemAbs (1<<10) /* Memory operand is absolute displacement */
69#define String (1<<12) /* String instruction (rep capable) */
70#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 71#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
72#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
73#define GroupMask 0xff /* Group number stored in bits 0:7 */
0dc8d10f
GT		 74/* Source 2 operand type */
75#define Src2None (0<<29)
76#define Src2CL (1<<29)
77#define Src2ImmByte (2<<29)
78#define Src2One (3<<29)
a5f868bd 79#define Src2Imm16 (4<<29)
0dc8d10f 80#define Src2Mask (7<<29)
6aa8b732 81
43bb19cd 82enum {
1d6ad207 83 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 84 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
43bb19cd
AK		 85};
86
45ed60b3 87static u32 opcode_table[256] = {
6aa8b732
AK		 88 /* 0x00 - 0x07 */
89 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
90 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
291fd39b 91 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, 0, 0,
6aa8b732
AK		 92 /* 0x08 - 0x0F */
93 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
94 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
95 0, 0, 0, 0,
96 /* 0x10 - 0x17 */
97 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
98 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
99 0, 0, 0, 0,
100 /* 0x18 - 0x1F */
101 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
102 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
103 0, 0, 0, 0,
104 /* 0x20 - 0x27 */
105 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
106 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
aa3a816b 107 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732
AK		 108 /* 0x28 - 0x2F */
109 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
110 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
111 0, 0, 0, 0,
112 /* 0x30 - 0x37 */
113 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
114 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
115 0, 0, 0, 0,
116 /* 0x38 - 0x3F */
117 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
118 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
8a9fee67
GT		 119 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
120 0, 0,
d77a2507 121 /* 0x40 - 0x47 */
33615aa9 122 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 123 /* 0x48 - 0x4F */
33615aa9 124 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 125 /* 0x50 - 0x57 */
6e3d5dfb
AK		 126 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
127 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 128 /* 0x58 - 0x5F */
6e3d5dfb
AK		 129 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
130 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 131 /* 0x60 - 0x67 */
6aa8b732 132 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 133 0, 0, 0, 0,
134 /* 0x68 - 0x6F */
91ed7a0e 135 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
e70669ab
LV		 136 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
137 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4 138 /* 0x70 - 0x77 */
b2833e3c
GN		 139 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
140 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
55bebde4 141 /* 0x78 - 0x7F */
b2833e3c
GN		 142 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
143 SrcImmByte, SrcImmByte, SrcImmByte, SrcImmByte,
6aa8b732 144 /* 0x80 - 0x87 */
1d6ad207
AK		 145 Group | Group1_80, Group | Group1_81,
146 Group | Group1_82, Group | Group1_83,
6aa8b732
AK		 147 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
148 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
149 /* 0x88 - 0x8F */
150 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
151 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
38d5bc6d 152 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
4257198a 153 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
b13354f8
MG		 154 /* 0x90 - 0x97 */
155 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
156 /* 0x98 - 0x9F */
0654169e
GN		 157 0, 0, SrcImm | Src2Imm16, 0,
158 ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 159 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 160 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
161 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
b9fa9d6b
AK		 162 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
163 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 164 /* 0xA8 - 0xAF */
b9fa9d6b
AK		 165 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
166 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
167 ByteOp | ImplicitOps | String, ImplicitOps | String,
a5e2e82b
MG		 168 /* 0xB0 - 0xB7 */
169 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
170 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
171 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
172 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
173 /* 0xB8 - 0xBF */
174 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
175 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
176 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
177 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
6aa8b732 178 /* 0xC0 - 0xC7 */
d9413cd7 179 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 180 0, ImplicitOps | Stack, 0, 0,
d9413cd7 181 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732 182 /* 0xC8 - 0xCF */
a77ab5ea 183 0, 0, 0, ImplicitOps | Stack, 0, 0, 0, 0,
6aa8b732
AK		 184 /* 0xD0 - 0xD7 */
185 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
186 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
187 0, 0, 0, 0,
188 /* 0xD8 - 0xDF */
189 0, 0, 0, 0, 0, 0, 0, 0,
098c937b 190 /* 0xE0 - 0xE7 */
a6a3034c
MG		 191 0, 0, 0, 0,
192 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
193 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
098c937b 194 /* 0xE8 - 0xEF */
d53c4777 195 SrcImm | Stack, SrcImm | ImplicitOps,
782b877c 196 SrcImm | Src2Imm16, SrcImmByte | ImplicitOps,
a6a3034c
MG		 197 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
198 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
6aa8b732
AK		 199 /* 0xF0 - 0xF7 */
200 0, 0, 0, 0,
7d858a19 201 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 202 /* 0xF8 - 0xFF */
b284be57 203 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fb4616f4 204 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
6aa8b732
AK		 205};
206
45ed60b3 207static u32 twobyte_table[256] = {
6aa8b732 208 /* 0x00 - 0x0F */
d95058a1 209 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
651a3e29 210 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 211 /* 0x10 - 0x1F */
212 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
213 /* 0x20 - 0x2F */
214 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
215 0, 0, 0, 0, 0, 0, 0, 0,
216 /* 0x30 - 0x3F */
35f3f286 217 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 218 /* 0x40 - 0x47 */
219 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
220 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
221 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
222 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
223 /* 0x48 - 0x4F */
224 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
225 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
226 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
227 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
228 /* 0x50 - 0x5F */
229 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
230 /* 0x60 - 0x6F */
231 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
232 /* 0x70 - 0x7F */
233 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
234 /* 0x80 - 0x8F */
b2833e3c
GN		 235 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
236 SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm, SrcImm,
6aa8b732
AK		 237 /* 0x90 - 0x9F */
238 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
239 /* 0xA0 - 0xA7 */
9bf8ea42
GT		 240 0, 0, 0, DstMem | SrcReg | ModRM | BitOp,
241 DstMem | SrcReg | Src2ImmByte | ModRM,
242 DstMem | SrcReg | Src2CL | ModRM, 0, 0,
6aa8b732 243 /* 0xA8 - 0xAF */
9bf8ea42
GT		 244 0, 0, 0, DstMem | SrcReg | ModRM | BitOp,
245 DstMem | SrcReg | Src2ImmByte | ModRM,
246 DstMem | SrcReg | Src2CL | ModRM,
247 ModRM, 0,
6aa8b732
AK		 248 /* 0xB0 - 0xB7 */
249 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 250 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 251 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
252 DstReg | SrcMem16 | ModRM | Mov,
253 /* 0xB8 - 0xBF */
038e51de 254 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 255 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
256 DstReg | SrcMem16 | ModRM | Mov,
257 /* 0xC0 - 0xCF */
a012e65a
SY		 258 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
259 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 260 /* 0xD0 - 0xDF */
261 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
262 /* 0xE0 - 0xEF */
263 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
264 /* 0xF0 - 0xFF */
265 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
266};
267
45ed60b3 268static u32 group_table[] = {
1d6ad207
AK		 269 [Group1_80*8] =
270 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
271 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
272 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
273 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
274 [Group1_81*8] =
275 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
276 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
277 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
278 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
279 [Group1_82*8] =
280 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
281 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
282 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
283 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
284 [Group1_83*8] =
285 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
286 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
287 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
288 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 289 [Group1A*8] =
290 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 291 [Group3_Byte*8] =
292 ByteOp | SrcImm | DstMem | ModRM, 0,
293 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
294 0, 0, 0, 0,
295 [Group3*8] =
41afa025 296 DstMem | SrcImm | ModRM, 0,
6eb06cb2 297 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
7d858a19 298 0, 0, 0, 0,
fd60754e
AK		 299 [Group4*8] =
300 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
301 0, 0, 0, 0, 0, 0,
302 [Group5*8] =
d19292e4
MG		 303 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
304 SrcMem | ModRM | Stack, 0,
ef46f18e 305 SrcMem | ModRM | Stack, 0, SrcMem | ModRM | Stack, 0,
d95058a1
AK		 306 [Group7*8] =
307 0, 0, ModRM | SrcMem, ModRM | SrcMem,
16286d08
AK		 308 SrcNone | ModRM | DstMem | Mov, 0,
309 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
e09d082c
AK		 310};
311
45ed60b3 312static u32 group2_table[] = {
d95058a1 313 [Group7*8] =
fbce554e 314 SrcNone | ModRM, 0, 0, SrcNone | ModRM,
16286d08
AK		 315 SrcNone | ModRM | DstMem | Mov, 0,
316 SrcMem16 | ModRM | Mov, 0,
e09d082c
AK		 317};
318
6aa8b732
AK		 319/* EFLAGS bit definitions. */
320#define EFLG_OF (1<<11)
321#define EFLG_DF (1<<10)
322#define EFLG_SF (1<<7)
323#define EFLG_ZF (1<<6)
324#define EFLG_AF (1<<4)
325#define EFLG_PF (1<<2)
326#define EFLG_CF (1<<0)
327
328/*
329 * Instruction emulation:
330 * Most instructions are emulated directly via a fragment of inline assembly
331 * code. This allows us to save/restore EFLAGS and thus very easily pick up
332 * any modified flags.
333 */
334
05b3e0c2 335#if defined(CONFIG_X86_64)
6aa8b732
AK		 336#define _LO32 "k" /* force 32-bit operand */
337#define _STK "%%rsp" /* stack pointer */
338#elif defined(__i386__)
339#define _LO32 "" /* force 32-bit operand */
340#define _STK "%%esp" /* stack pointer */
341#endif
342
343/*
344 * These EFLAGS bits are restored from saved value during emulation, and
345 * any changes are written back to the saved value after emulation.
346 */
347#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
348
349/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 350#define _PRE_EFLAGS(_sav, _msk, _tmp) \
351 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
352 "movl %"_sav",%"_LO32 _tmp"; " \
353 "push %"_tmp"; " \
354 "push %"_tmp"; " \
355 "movl %"_msk",%"_LO32 _tmp"; " \
356 "andl %"_LO32 _tmp",("_STK"); " \
357 "pushf; " \
358 "notl %"_LO32 _tmp"; " \
359 "andl %"_LO32 _tmp",("_STK"); " \
360 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
361 "pop %"_tmp"; " \
362 "orl %"_LO32 _tmp",("_STK"); " \
363 "popf; " \
364 "pop %"_sav"; "
6aa8b732
AK		 365
366/* After executing instruction: write-back necessary bits in EFLAGS. */
367#define _POST_EFLAGS(_sav, _msk, _tmp) \
368 /* _sav |= EFLAGS & _msk; */ \
369 "pushf; " \
370 "pop %"_tmp"; " \
371 "andl %"_msk",%"_LO32 _tmp"; " \
372 "orl %"_LO32 _tmp",%"_sav"; "
373
dda96d8f
AK		 374#ifdef CONFIG_X86_64
375#define ON64(x) x
376#else
377#define ON64(x)
378#endif
379
6b7ad61f
AK		 380#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
381 do { \
382 __asm__ __volatile__ ( \
383 _PRE_EFLAGS("0", "4", "2") \
384 _op _suffix " %"_x"3,%1; " \
385 _POST_EFLAGS("0", "4", "2") \
386 : "=m" (_eflags), "=m" ((_dst).val), \
387 "=&r" (_tmp) \
388 : _y ((_src).val), "i" (EFLAGS_MASK)); \
f3fd92fb 389 } while (0)
6b7ad61f
AK		 390
391
6aa8b732
AK		 392/* Raw emulation: instruction has two explicit operands. */
393#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
6b7ad61f
AK		 394 do { \
395 unsigned long _tmp; \
396 \
397 switch ((_dst).bytes) { \
398 case 2: \
399 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
400 break; \
401 case 4: \
402 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
403 break; \
404 case 8: \
405 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
406 break; \
407 } \
6aa8b732
AK		 408 } while (0)
409
410#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
411 do { \
6b7ad61f 412 unsigned long _tmp; \
d77c26fc 413 switch ((_dst).bytes) { \
6aa8b732 414 case 1: \
6b7ad61f 415 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
6aa8b732
AK		 416 break; \
417 default: \
418 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
419 _wx, _wy, _lx, _ly, _qx, _qy); \
420 break; \
421 } \
422 } while (0)
423
424/* Source operand is byte-sized and may be restricted to just %cl. */
425#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
426 __emulate_2op(_op, _src, _dst, _eflags, \
427 "b", "c", "b", "c", "b", "c", "b", "c")
428
429/* Source operand is byte, word, long or quad sized. */
430#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
431 __emulate_2op(_op, _src, _dst, _eflags, \
432 "b", "q", "w", "r", _LO32, "r", "", "r")
433
434/* Source operand is word, long or quad sized. */
435#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
436 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
437 "w", "r", _LO32, "r", "", "r")
438
d175226a
GT		 439/* Instruction has three operands and one operand is stored in ECX register */
440#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
441 do { \
442 unsigned long _tmp; \
443 _type _clv = (_cl).val; \
444 _type _srcv = (_src).val; \
445 _type _dstv = (_dst).val; \
446 \
447 __asm__ __volatile__ ( \
448 _PRE_EFLAGS("0", "5", "2") \
449 _op _suffix " %4,%1 \n" \
450 _POST_EFLAGS("0", "5", "2") \
451 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
452 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
453 ); \
454 \
455 (_cl).val = (unsigned long) _clv; \
456 (_src).val = (unsigned long) _srcv; \
457 (_dst).val = (unsigned long) _dstv; \
458 } while (0)
459
460#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
461 do { \
462 switch ((_dst).bytes) { \
463 case 2: \
464 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
465 "w", unsigned short); \
466 break; \
467 case 4: \
468 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
469 "l", unsigned int); \
470 break; \
471 case 8: \
472 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
473 "q", unsigned long)); \
474 break; \
475 } \
476 } while (0)
477
dda96d8f 478#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 479 do { \
480 unsigned long _tmp; \
481 \
dda96d8f
AK		 482 __asm__ __volatile__ ( \
483 _PRE_EFLAGS("0", "3", "2") \
484 _op _suffix " %1; " \
485 _POST_EFLAGS("0", "3", "2") \
486 : "=m" (_eflags), "+m" ((_dst).val), \
487 "=&r" (_tmp) \
488 : "i" (EFLAGS_MASK)); \
489 } while (0)
490
491/* Instruction has only one explicit operand (no source operand). */
492#define emulate_1op(_op, _dst, _eflags) \
493 do { \
d77c26fc 494 switch ((_dst).bytes) { \
dda96d8f
AK		 495 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
496 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
497 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
498 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 499 } \
500 } while (0)
501
6aa8b732
AK		 502/* Fetch next part of the instruction being emulated. */
503#define insn_fetch(_type, _size, _eip) \
504({ unsigned long _x; \
62266869 505 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
d77c26fc 506 if (rc != 0) \
6aa8b732
AK		 507 goto done; \
508 (_eip) += (_size); \
509 (_type)_x; \
510})
511
ddcb2885
HH		 512static inline unsigned long ad_mask(struct decode_cache *c)
513{
514 return (1UL << (c->ad_bytes << 3)) - 1;
515}
516
6aa8b732 517/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 518static inline unsigned long
519address_mask(struct decode_cache *c, unsigned long reg)
520{
521 if (c->ad_bytes == sizeof(unsigned long))
522 return reg;
523 else
524 return reg & ad_mask(c);
525}
526
527static inline unsigned long
528register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
529{
530 return base + address_mask(c, reg);
531}
532
7a957275
HH		 533static inline void
534register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
535{
536 if (c->ad_bytes == sizeof(unsigned long))
537 *reg += inc;
538 else
539 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
540}
6aa8b732 541
7a957275
HH		 542static inline void jmp_rel(struct decode_cache *c, int rel)
543{
544 register_address_increment(c, &c->eip, rel);
545}
098c937b 546
7a5b56df
AK		 547static void set_seg_override(struct decode_cache *c, int seg)
548{
549 c->has_seg_override = true;
550 c->seg_override = seg;
551}
552
553static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
554{
555 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
556 return 0;
557
558 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
559}
560
561static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
562 struct decode_cache *c)
563{
564 if (!c->has_seg_override)
565 return 0;
566
567 return seg_base(ctxt, c->seg_override);
568}
569
570static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
571{
572 return seg_base(ctxt, VCPU_SREG_ES);
573}
574
575static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
576{
577 return seg_base(ctxt, VCPU_SREG_SS);
578}
579
62266869
AK		 580static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
581 struct x86_emulate_ops *ops,
582 unsigned long linear, u8 *dest)
583{
584 struct fetch_cache *fc = &ctxt->decode.fetch;
585 int rc;
586 int size;
587
588 if (linear < fc->start || linear >= fc->end) {
589 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
590 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
591 if (rc)
592 return rc;
593 fc->start = linear;
594 fc->end = linear + size;
595 }
596 *dest = fc->data[linear - fc->start];
597 return 0;
598}
599
600static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
601 struct x86_emulate_ops *ops,
602 unsigned long eip, void *dest, unsigned size)
603{
604 int rc = 0;
605
606 eip += ctxt->cs_base;
607 while (size--) {
608 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
609 if (rc)
610 return rc;
611 }
612 return 0;
613}
614
1e3c5cb0
RR		 615/*
616 * Given the 'reg' portion of a ModRM byte, and a register block, return a
617 * pointer into the block that addresses the relevant register.
618 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
619 */
620static void *decode_register(u8 modrm_reg, unsigned long *regs,
621 int highbyte_regs)
6aa8b732
AK		 622{
623 void *p;
624
625 p = &regs[modrm_reg];
626 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
627 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
628 return p;
629}
630
631static int read_descriptor(struct x86_emulate_ctxt *ctxt,
632 struct x86_emulate_ops *ops,
633 void *ptr,
634 u16 *size, unsigned long *address, int op_bytes)
635{
636 int rc;
637
638 if (op_bytes == 2)
639 op_bytes = 3;
640 *address = 0;
cebff02b
LV		 641 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
642 ctxt->vcpu);
6aa8b732
AK		 643 if (rc)
644 return rc;
cebff02b
LV		 645 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
646 ctxt->vcpu);
6aa8b732
AK		 647 return rc;
648}
649
bbe9abbd
NK		 650static int test_cc(unsigned int condition, unsigned int flags)
651{
652 int rc = 0;
653
654 switch ((condition & 15) >> 1) {
655 case 0: /* o */
656 rc |= (flags & EFLG_OF);
657 break;
658 case 1: /* b/c/nae */
659 rc |= (flags & EFLG_CF);
660 break;
661 case 2: /* z/e */
662 rc |= (flags & EFLG_ZF);
663 break;
664 case 3: /* be/na */
665 rc |= (flags & (EFLG_CF|EFLG_ZF));
666 break;
667 case 4: /* s */
668 rc |= (flags & EFLG_SF);
669 break;
670 case 5: /* p/pe */
671 rc |= (flags & EFLG_PF);
672 break;
673 case 7: /* le/ng */
674 rc |= (flags & EFLG_ZF);
675 /* fall through */
676 case 6: /* l/nge */
677 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
678 break;
679 }
680
681 /* Odd condition identifiers (lsb == 1) have inverted sense. */
682 return (!!rc ^ (condition & 1));
683}
684
3c118e24
AK		 685static void decode_register_operand(struct operand *op,
686 struct decode_cache *c,
3c118e24
AK		 687 int inhibit_bytereg)
688{
33615aa9 689 unsigned reg = c->modrm_reg;
9f1ef3f8 690 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 691
692 if (!(c->d & ModRM))
693 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 694 op->type = OP_REG;
695 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 696 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 697 op->val = *(u8 *)op->ptr;
698 op->bytes = 1;
699 } else {
33615aa9 700 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 701 op->bytes = c->op_bytes;
702 switch (op->bytes) {
703 case 2:
704 op->val = *(u16 *)op->ptr;
705 break;
706 case 4:
707 op->val = *(u32 *)op->ptr;
708 break;
709 case 8:
710 op->val = *(u64 *) op->ptr;
711 break;
712 }
713 }
714 op->orig_val = op->val;
715}
716
1c73ef66
AK		 717static int decode_modrm(struct x86_emulate_ctxt *ctxt,
718 struct x86_emulate_ops *ops)
719{
720 struct decode_cache *c = &ctxt->decode;
721 u8 sib;
f5b4edcd 722 int index_reg = 0, base_reg = 0, scale;
1c73ef66
AK		 723 int rc = 0;
724
725 if (c->rex_prefix) {
726 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
727 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
728 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
729 }
730
731 c->modrm = insn_fetch(u8, 1, c->eip);
732 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
733 c->modrm_reg |= (c->modrm & 0x38) >> 3;
734 c->modrm_rm |= (c->modrm & 0x07);
735 c->modrm_ea = 0;
736 c->use_modrm_ea = 1;
737
738 if (c->modrm_mod == 3) {
107d6d2e
AK		 739 c->modrm_ptr = decode_register(c->modrm_rm,
740 c->regs, c->d & ByteOp);
741 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 742 return rc;
743 }
744
745 if (c->ad_bytes == 2) {
746 unsigned bx = c->regs[VCPU_REGS_RBX];
747 unsigned bp = c->regs[VCPU_REGS_RBP];
748 unsigned si = c->regs[VCPU_REGS_RSI];
749 unsigned di = c->regs[VCPU_REGS_RDI];
750
751 /* 16-bit ModR/M decode. */
752 switch (c->modrm_mod) {
753 case 0:
754 if (c->modrm_rm == 6)
755 c->modrm_ea += insn_fetch(u16, 2, c->eip);
756 break;
757 case 1:
758 c->modrm_ea += insn_fetch(s8, 1, c->eip);
759 break;
760 case 2:
761 c->modrm_ea += insn_fetch(u16, 2, c->eip);
762 break;
763 }
764 switch (c->modrm_rm) {
765 case 0:
766 c->modrm_ea += bx + si;
767 break;
768 case 1:
769 c->modrm_ea += bx + di;
770 break;
771 case 2:
772 c->modrm_ea += bp + si;
773 break;
774 case 3:
775 c->modrm_ea += bp + di;
776 break;
777 case 4:
778 c->modrm_ea += si;
779 break;
780 case 5:
781 c->modrm_ea += di;
782 break;
783 case 6:
784 if (c->modrm_mod != 0)
785 c->modrm_ea += bp;
786 break;
787 case 7:
788 c->modrm_ea += bx;
789 break;
790 }
791 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
792 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 793 if (!c->has_seg_override)
794 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 795 c->modrm_ea = (u16)c->modrm_ea;
796 } else {
797 /* 32/64-bit ModR/M decode. */
84411d85 798 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 799 sib = insn_fetch(u8, 1, c->eip);
800 index_reg |= (sib >> 3) & 7;
801 base_reg |= sib & 7;
802 scale = sib >> 6;
803
dc71d0f1
AK		 804 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
805 c->modrm_ea += insn_fetch(s32, 4, c->eip);
806 else
1c73ef66 807 c->modrm_ea += c->regs[base_reg];
dc71d0f1 808 if (index_reg != 4)
1c73ef66 809 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 810 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
811 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 812 c->rip_relative = 1;
84411d85 813 } else
1c73ef66 814 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 815 switch (c->modrm_mod) {
816 case 0:
817 if (c->modrm_rm == 5)
818 c->modrm_ea += insn_fetch(s32, 4, c->eip);
819 break;
820 case 1:
821 c->modrm_ea += insn_fetch(s8, 1, c->eip);
822 break;
823 case 2:
824 c->modrm_ea += insn_fetch(s32, 4, c->eip);
825 break;
826 }
827 }
1c73ef66
AK		 828done:
829 return rc;
830}
831
832static int decode_abs(struct x86_emulate_ctxt *ctxt,
833 struct x86_emulate_ops *ops)
834{
835 struct decode_cache *c = &ctxt->decode;
836 int rc = 0;
837
838 switch (c->ad_bytes) {
839 case 2:
840 c->modrm_ea = insn_fetch(u16, 2, c->eip);
841 break;
842 case 4:
843 c->modrm_ea = insn_fetch(u32, 4, c->eip);
844 break;
845 case 8:
846 c->modrm_ea = insn_fetch(u64, 8, c->eip);
847 break;
848 }
849done:
850 return rc;
851}
852
6aa8b732 853int
8b4caf66 854x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 855{
e4e03ded 856 struct decode_cache *c = &ctxt->decode;
6aa8b732 857 int rc = 0;
6aa8b732 858 int mode = ctxt->mode;
e09d082c 859 int def_op_bytes, def_ad_bytes, group;
6aa8b732
AK		 860
861 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 862
e4e03ded 863 memset(c, 0, sizeof(struct decode_cache));
5fdbf976 864 c->eip = kvm_rip_read(ctxt->vcpu);
7a5b56df 865 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
ad312c7c 866 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 867
868 switch (mode) {
869 case X86EMUL_MODE_REAL:
870 case X86EMUL_MODE_PROT16:
f21b8bf4 871 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 872 break;
873 case X86EMUL_MODE_PROT32:
f21b8bf4 874 def_op_bytes = def_ad_bytes = 4;
6aa8b732 875 break;
05b3e0c2 876#ifdef CONFIG_X86_64
6aa8b732 877 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 878 def_op_bytes = 4;
879 def_ad_bytes = 8;
6aa8b732
AK		 880 break;
881#endif
882 default:
883 return -1;
884 }
885
f21b8bf4
AK		 886 c->op_bytes = def_op_bytes;
887 c->ad_bytes = def_ad_bytes;
888
6aa8b732 889 /* Legacy prefixes. */
b4c6abfe 890 for (;;) {
e4e03ded 891 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 892 case 0x66: /* operand-size override */
f21b8bf4
AK		 893 /* switch between 2/4 bytes */
894 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 895 break;
896 case 0x67: /* address-size override */
897 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 898 /* switch between 4/8 bytes */
f21b8bf4 899 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 900 else
e4e03ded 901 /* switch between 2/4 bytes */
f21b8bf4 902 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 903 break;
7a5b56df 904 case 0x26: /* ES override */
6aa8b732 905 case 0x2e: /* CS override */
7a5b56df 906 case 0x36: /* SS override */
6aa8b732 907 case 0x3e: /* DS override */
7a5b56df 908 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 909 break;
910 case 0x64: /* FS override */
6aa8b732 911 case 0x65: /* GS override */
7a5b56df 912 set_seg_override(c, c->b & 7);
6aa8b732 913 break;
b4c6abfe
LV		 914 case 0x40 ... 0x4f: /* REX */
915 if (mode != X86EMUL_MODE_PROT64)
916 goto done_prefixes;
33615aa9 917 c->rex_prefix = c->b;
b4c6abfe 918 continue;
6aa8b732 919 case 0xf0: /* LOCK */
e4e03ded 920 c->lock_prefix = 1;
6aa8b732 921 break;
ae6200ba 922 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 923 c->rep_prefix = REPNE_PREFIX;
924 break;
6aa8b732 925 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 926 c->rep_prefix = REPE_PREFIX;
6aa8b732 927 break;
6aa8b732
AK		 928 default:
929 goto done_prefixes;
930 }
b4c6abfe
LV		 931
932 /* Any legacy prefix after a REX prefix nullifies its effect. */
933
33615aa9 934 c->rex_prefix = 0;
6aa8b732
AK		 935 }
936
937done_prefixes:
938
939 /* REX prefix. */
1c73ef66 940 if (c->rex_prefix)
33615aa9 941 if (c->rex_prefix & 8)
e4e03ded 942 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 943
944 /* Opcode byte(s). */
e4e03ded
LV		 945 c->d = opcode_table[c->b];
946 if (c->d == 0) {
6aa8b732 947 /* Two-byte opcode? */
e4e03ded
LV		 948 if (c->b == 0x0f) {
949 c->twobyte = 1;
950 c->b = insn_fetch(u8, 1, c->eip);
951 c->d = twobyte_table[c->b];
6aa8b732 952 }
e09d082c 953 }
6aa8b732 954
e09d082c
AK		 955 if (c->d & Group) {
956 group = c->d & GroupMask;
957 c->modrm = insn_fetch(u8, 1, c->eip);
958 --c->eip;
959
960 group = (group << 3) + ((c->modrm >> 3) & 7);
961 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
962 c->d = group2_table[group];
963 else
964 c->d = group_table[group];
965 }
966
967 /* Unrecognised? */
968 if (c->d == 0) {
969 DPRINTF("Cannot emulate %02x\n", c->b);
970 return -1;
6aa8b732
AK		 971 }
972
6e3d5dfb
AK		 973 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
974 c->op_bytes = 8;
975
6aa8b732 976 /* ModRM and SIB bytes. */
1c73ef66
AK		 977 if (c->d & ModRM)
978 rc = decode_modrm(ctxt, ops);
979 else if (c->d & MemAbs)
980 rc = decode_abs(ctxt, ops);
981 if (rc)
982 goto done;
6aa8b732 983
7a5b56df
AK		 984 if (!c->has_seg_override)
985 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 986
7a5b56df
AK		 987 if (!(!c->twobyte && c->b == 0x8d))
988 c->modrm_ea += seg_override_base(ctxt, c);
c7e75a3d
AK		 989
990 if (c->ad_bytes != 8)
991 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 992 /*
993 * Decode and fetch the source operand: register, memory
994 * or immediate.
995 */
e4e03ded 996 switch (c->d & SrcMask) {
6aa8b732
AK		 997 case SrcNone:
998 break;
999 case SrcReg:
9f1ef3f8 1000 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 1001 break;
1002 case SrcMem16:
e4e03ded 1003 c->src.bytes = 2;
6aa8b732
AK		 1004 goto srcmem_common;
1005 case SrcMem32:
e4e03ded 1006 c->src.bytes = 4;
6aa8b732
AK		 1007 goto srcmem_common;
1008 case SrcMem:
e4e03ded
LV		 1009 c->src.bytes = (c->d & ByteOp) ? 1 :
1010 c->op_bytes;
b85b9ee9 1011 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 1012 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1013 break;
d77c26fc 1014 srcmem_common:
4e62417b
AJ		 1015 /*
1016 * For instructions with a ModR/M byte, switch to register
1017 * access if Mod = 3.
1018 */
e4e03ded
LV		 1019 if ((c->d & ModRM) && c->modrm_mod == 3) {
1020 c->src.type = OP_REG;
66b85505 1021 c->src.val = c->modrm_val;
107d6d2e 1022 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1023 break;
1024 }
e4e03ded 1025 c->src.type = OP_MEM;
6aa8b732
AK		 1026 break;
1027 case SrcImm:
e4e03ded
LV		 1028 c->src.type = OP_IMM;
1029 c->src.ptr = (unsigned long *)c->eip;
1030 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1031 if (c->src.bytes == 8)
1032 c->src.bytes = 4;
6aa8b732 1033 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1034 switch (c->src.bytes) {
6aa8b732 1035 case 1:
e4e03ded 1036 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1037 break;
1038 case 2:
e4e03ded 1039 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1040 break;
1041 case 4:
e4e03ded 1042 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1043 break;
1044 }
1045 break;
1046 case SrcImmByte:
e4e03ded
LV		 1047 c->src.type = OP_IMM;
1048 c->src.ptr = (unsigned long *)c->eip;
1049 c->src.bytes = 1;
1050 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732 1051 break;
bfcadf83
GT		 1052 case SrcOne:
1053 c->src.bytes = 1;
1054 c->src.val = 1;
1055 break;
6aa8b732
AK		 1056 }
1057
0dc8d10f
GT		 1058 /*
1059 * Decode and fetch the second source operand: register, memory
1060 * or immediate.
1061 */
1062 switch (c->d & Src2Mask) {
1063 case Src2None:
1064 break;
1065 case Src2CL:
1066 c->src2.bytes = 1;
1067 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1068 break;
1069 case Src2ImmByte:
1070 c->src2.type = OP_IMM;
1071 c->src2.ptr = (unsigned long *)c->eip;
1072 c->src2.bytes = 1;
1073 c->src2.val = insn_fetch(u8, 1, c->eip);
1074 break;
a5f868bd
GN		 1075 case Src2Imm16:
1076 c->src2.type = OP_IMM;
1077 c->src2.ptr = (unsigned long *)c->eip;
1078 c->src2.bytes = 2;
1079 c->src2.val = insn_fetch(u16, 2, c->eip);
1080 break;
0dc8d10f
GT		 1081 case Src2One:
1082 c->src2.bytes = 1;
1083 c->src2.val = 1;
1084 break;
1085 }
1086
038e51de 1087 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1088 switch (c->d & DstMask) {
038e51de
AK		 1089 case ImplicitOps:
1090 /* Special instructions do their own operand decoding. */
8b4caf66 1091 return 0;
038e51de 1092 case DstReg:
9f1ef3f8 1093 decode_register_operand(&c->dst, c,
3c118e24 1094 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1095 break;
1096 case DstMem:
e4e03ded 1097 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1098 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1099 c->dst.type = OP_REG;
66b85505 1100 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1101 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1102 break;
1103 }
8b4caf66
LV		 1104 c->dst.type = OP_MEM;
1105 break;
9c9fddd0
GT		 1106 case DstAcc:
1107 c->dst.type = OP_REG;
1108 c->dst.bytes = c->op_bytes;
1109 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1110 switch (c->op_bytes) {
1111 case 1:
1112 c->dst.val = *(u8 *)c->dst.ptr;
1113 break;
1114 case 2:
1115 c->dst.val = *(u16 *)c->dst.ptr;
1116 break;
1117 case 4:
1118 c->dst.val = *(u32 *)c->dst.ptr;
1119 break;
1120 }
1121 c->dst.orig_val = c->dst.val;
1122 break;
8b4caf66
LV		 1123 }
1124
f5b4edcd
AK		 1125 if (c->rip_relative)
1126 c->modrm_ea += c->eip;
1127
8b4caf66
LV		 1128done:
1129 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1130}
1131
8cdbd2c9
LV		 1132static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1133{
1134 struct decode_cache *c = &ctxt->decode;
1135
1136 c->dst.type = OP_MEM;
1137 c->dst.bytes = c->op_bytes;
1138 c->dst.val = c->src.val;
7a957275 1139 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
7a5b56df 1140 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1141 c->regs[VCPU_REGS_RSP]);
1142}
1143
faa5a3ae 1144static int emulate_pop(struct x86_emulate_ctxt *ctxt,
350f69dc
AK		 1145 struct x86_emulate_ops *ops,
1146 void *dest, int len)
8cdbd2c9
LV		 1147{
1148 struct decode_cache *c = &ctxt->decode;
1149 int rc;
1150
781d0edc
AK		 1151 rc = ops->read_emulated(register_address(c, ss_base(ctxt),
1152 c->regs[VCPU_REGS_RSP]),
350f69dc 1153 dest, len, ctxt->vcpu);
8cdbd2c9
LV		 1154 if (rc != 0)
1155 return rc;
1156
350f69dc 1157 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
faa5a3ae
AK		 1158 return rc;
1159}
8cdbd2c9 1160
faa5a3ae
AK		 1161static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1162 struct x86_emulate_ops *ops)
1163{
1164 struct decode_cache *c = &ctxt->decode;
1165 int rc;
1166
350f69dc 1167 rc = emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
faa5a3ae
AK		 1168 if (rc != 0)
1169 return rc;
8cdbd2c9
LV		 1170 return 0;
1171}
1172
05f086f8 1173static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1174{
05f086f8 1175 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1176 switch (c->modrm_reg) {
1177 case 0: /* rol */
05f086f8 1178 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1179 break;
1180 case 1: /* ror */
05f086f8 1181 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1182 break;
1183 case 2: /* rcl */
05f086f8 1184 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1185 break;
1186 case 3: /* rcr */
05f086f8 1187 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1188 break;
1189 case 4: /* sal/shl */
1190 case 6: /* sal/shl */
05f086f8 1191 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1192 break;
1193 case 5: /* shr */
05f086f8 1194 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1195 break;
1196 case 7: /* sar */
05f086f8 1197 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1198 break;
1199 }
1200}
1201
1202static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1203 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1204{
1205 struct decode_cache *c = &ctxt->decode;
1206 int rc = 0;
1207
1208 switch (c->modrm_reg) {
1209 case 0 ... 1: /* test */
05f086f8 1210 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1211 break;
1212 case 2: /* not */
1213 c->dst.val = ~c->dst.val;
1214 break;
1215 case 3: /* neg */
05f086f8 1216 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1217 break;
1218 default:
1219 DPRINTF("Cannot emulate %02x\n", c->b);
1220 rc = X86EMUL_UNHANDLEABLE;
1221 break;
1222 }
8cdbd2c9
LV		 1223 return rc;
1224}
1225
1226static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1227 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1228{
1229 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1230
1231 switch (c->modrm_reg) {
1232 case 0: /* inc */
05f086f8 1233 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1234 break;
1235 case 1: /* dec */
05f086f8 1236 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1237 break;
d19292e4
MG		 1238 case 2: /* call near abs */ {
1239 long int old_eip;
1240 old_eip = c->eip;
1241 c->eip = c->src.val;
1242 c->src.val = old_eip;
1243 emulate_push(ctxt);
1244 break;
1245 }
8cdbd2c9 1246 case 4: /* jmp abs */
fd60754e 1247 c->eip = c->src.val;
8cdbd2c9
LV		 1248 break;
1249 case 6: /* push */
fd60754e 1250 emulate_push(ctxt);
8cdbd2c9 1251 break;
8cdbd2c9
LV		 1252 }
1253 return 0;
1254}
1255
1256static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1257 struct x86_emulate_ops *ops,
e8d8d7fe 1258 unsigned long memop)
8cdbd2c9
LV		 1259{
1260 struct decode_cache *c = &ctxt->decode;
1261 u64 old, new;
1262 int rc;
1263
e8d8d7fe 1264 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
8cdbd2c9
LV		 1265 if (rc != 0)
1266 return rc;
1267
1268 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1269 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1270
1271 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1272 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1273 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1274
1275 } else {
1276 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1277 (u32) c->regs[VCPU_REGS_RBX];
1278
e8d8d7fe 1279 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
8cdbd2c9
LV		 1280 if (rc != 0)
1281 return rc;
05f086f8 1282 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1283 }
1284 return 0;
1285}
1286
a77ab5ea
AK		 1287static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1288 struct x86_emulate_ops *ops)
1289{
1290 struct decode_cache *c = &ctxt->decode;
1291 int rc;
1292 unsigned long cs;
1293
1294 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1295 if (rc)
1296 return rc;
1297 if (c->op_bytes == 4)
1298 c->eip = (u32)c->eip;
1299 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1300 if (rc)
1301 return rc;
1302 rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)cs, 1, VCPU_SREG_CS);
1303 return rc;
1304}
1305
8cdbd2c9
LV		 1306static inline int writeback(struct x86_emulate_ctxt *ctxt,
1307 struct x86_emulate_ops *ops)
1308{
1309 int rc;
1310 struct decode_cache *c = &ctxt->decode;
1311
1312 switch (c->dst.type) {
1313 case OP_REG:
1314 /* The 4-byte case *is* correct:
1315 * in 64-bit mode we zero-extend.
1316 */
1317 switch (c->dst.bytes) {
1318 case 1:
1319 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1320 break;
1321 case 2:
1322 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1323 break;
1324 case 4:
1325 *c->dst.ptr = (u32)c->dst.val;
1326 break; /* 64b: zero-ext */
1327 case 8:
1328 *c->dst.ptr = c->dst.val;
1329 break;
1330 }
1331 break;
1332 case OP_MEM:
1333 if (c->lock_prefix)
1334 rc = ops->cmpxchg_emulated(
1335 (unsigned long)c->dst.ptr,
1336 &c->dst.orig_val,
1337 &c->dst.val,
1338 c->dst.bytes,
1339 ctxt->vcpu);
1340 else
1341 rc = ops->write_emulated(
1342 (unsigned long)c->dst.ptr,
1343 &c->dst.val,
1344 c->dst.bytes,
1345 ctxt->vcpu);
1346 if (rc != 0)
1347 return rc;
a01af5ec
LV		 1348 break;
1349 case OP_NONE:
1350 /* no writeback */
1351 break;
8cdbd2c9
LV		 1352 default:
1353 break;
1354 }
1355 return 0;
1356}
1357
8b4caf66 1358int
1be3aa47 1359x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 1360{
e8d8d7fe 1361 unsigned long memop = 0;
8b4caf66 1362 u64 msr_data;
3427318f 1363 unsigned long saved_eip = 0;
8b4caf66 1364 struct decode_cache *c = &ctxt->decode;
a6a3034c
MG		 1365 unsigned int port;
1366 int io_dir_in;
1be3aa47 1367 int rc = 0;
8b4caf66 1368
3427318f
LV		 1369 /* Shadow copy of register state. Committed on successful emulation.
1370 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1371 * modify them.
1372 */
1373
ad312c7c 1374 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f
LV		 1375 saved_eip = c->eip;
1376
c7e75a3d 1377 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
e8d8d7fe 1378 memop = c->modrm_ea;
8b4caf66 1379
b9fa9d6b
AK		 1380 if (c->rep_prefix && (c->d & String)) {
1381 /* All REP prefixes have the same first termination condition */
1382 if (c->regs[VCPU_REGS_RCX] == 0) {
5fdbf976 1383 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1384 goto done;
1385 }
1386 /* The second termination condition only applies for REPE
1387 * and REPNE. Test if the repeat string operation prefix is
1388 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1389 * corresponding termination condition according to:
1390 * - if REPE/REPZ and ZF = 0 then done
1391 * - if REPNE/REPNZ and ZF = 1 then done
1392 */
1393 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1394 (c->b == 0xae) || (c->b == 0xaf)) {
1395 if ((c->rep_prefix == REPE_PREFIX) &&
1396 ((ctxt->eflags & EFLG_ZF) == 0)) {
5fdbf976 1397 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1398 goto done;
1399 }
1400 if ((c->rep_prefix == REPNE_PREFIX) &&
1401 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
5fdbf976 1402 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1403 goto done;
1404 }
1405 }
1406 c->regs[VCPU_REGS_RCX]--;
5fdbf976 1407 c->eip = kvm_rip_read(ctxt->vcpu);
b9fa9d6b
AK		 1408 }
1409
8b4caf66 1410 if (c->src.type == OP_MEM) {
e8d8d7fe 1411 c->src.ptr = (unsigned long *)memop;
8b4caf66 1412 c->src.val = 0;
d77c26fc
MD		 1413 rc = ops->read_emulated((unsigned long)c->src.ptr,
1414 &c->src.val,
1415 c->src.bytes,
1416 ctxt->vcpu);
1417 if (rc != 0)
8b4caf66
LV		 1418 goto done;
1419 c->src.orig_val = c->src.val;
1420 }
1421
1422 if ((c->d & DstMask) == ImplicitOps)
1423 goto special_insn;
1424
1425
1426 if (c->dst.type == OP_MEM) {
e8d8d7fe 1427 c->dst.ptr = (unsigned long *)memop;
8b4caf66
LV		 1428 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1429 c->dst.val = 0;
e4e03ded
LV		 1430 if (c->d & BitOp) {
1431 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1432
e4e03ded
LV		 1433 c->dst.ptr = (void *)c->dst.ptr +
1434 (c->src.val & mask) / 8;
038e51de 1435 }
e4e03ded
LV		 1436 if (!(c->d & Mov) &&
1437 /* optimisation - avoid slow emulated read */
1438 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1439 &c->dst.val,
1440 c->dst.bytes, ctxt->vcpu)) != 0))
038e51de 1441 goto done;
038e51de 1442 }
e4e03ded 1443 c->dst.orig_val = c->dst.val;
038e51de 1444
018a98db
AK		 1445special_insn:
1446
e4e03ded 1447 if (c->twobyte)
6aa8b732
AK		 1448 goto twobyte_insn;
1449
e4e03ded 1450 switch (c->b) {
6aa8b732
AK		 1451 case 0x00 ... 0x05:
1452 add: /* add */
05f086f8 1453 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1454 break;
1455 case 0x08 ... 0x0d:
1456 or: /* or */
05f086f8 1457 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1458 break;
1459 case 0x10 ... 0x15:
1460 adc: /* adc */
05f086f8 1461 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1462 break;
1463 case 0x18 ... 0x1d:
1464 sbb: /* sbb */
05f086f8 1465 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1466 break;
aa3a816b 1467 case 0x20 ... 0x25:
6aa8b732 1468 and: /* and */
05f086f8 1469 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1470 break;
1471 case 0x28 ... 0x2d:
1472 sub: /* sub */
05f086f8 1473 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1474 break;
1475 case 0x30 ... 0x35:
1476 xor: /* xor */
05f086f8 1477 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1478 break;
1479 case 0x38 ... 0x3d:
1480 cmp: /* cmp */
05f086f8 1481 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 1482 break;
33615aa9
AK		 1483 case 0x40 ... 0x47: /* inc r16/r32 */
1484 emulate_1op("inc", c->dst, ctxt->eflags);
1485 break;
1486 case 0x48 ... 0x4f: /* dec r16/r32 */
1487 emulate_1op("dec", c->dst, ctxt->eflags);
1488 break;
1489 case 0x50 ... 0x57: /* push reg */
2786b014 1490 emulate_push(ctxt);
33615aa9
AK		 1491 break;
1492 case 0x58 ... 0x5f: /* pop reg */
1493 pop_instruction:
350f69dc 1494 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
8a09b687 1495 if (rc != 0)
33615aa9 1496 goto done;
33615aa9 1497 break;
6aa8b732 1498 case 0x63: /* movsxd */
8b4caf66 1499 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1500 goto cannot_emulate;
e4e03ded 1501 c->dst.val = (s32) c->src.val;
6aa8b732 1502 break;
91ed7a0e 1503 case 0x68: /* push imm */
018a98db 1504 case 0x6a: /* push imm8 */
018a98db
AK		 1505 emulate_push(ctxt);
1506 break;
1507 case 0x6c: /* insb */
1508 case 0x6d: /* insw/insd */
1509 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1510 1,
1511 (c->d & ByteOp) ? 1 : c->op_bytes,
1512 c->rep_prefix ?
e4706772 1513 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1514 (ctxt->eflags & EFLG_DF),
7a5b56df 1515 register_address(c, es_base(ctxt),
018a98db
AK		 1516 c->regs[VCPU_REGS_RDI]),
1517 c->rep_prefix,
1518 c->regs[VCPU_REGS_RDX]) == 0) {
1519 c->eip = saved_eip;
1520 return -1;
1521 }
1522 return 0;
1523 case 0x6e: /* outsb */
1524 case 0x6f: /* outsw/outsd */
1525 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1526 0,
1527 (c->d & ByteOp) ? 1 : c->op_bytes,
1528 c->rep_prefix ?
e4706772 1529 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1530 (ctxt->eflags & EFLG_DF),
7a5b56df
AK		 1531 register_address(c,
1532 seg_override_base(ctxt, c),
018a98db
AK		 1533 c->regs[VCPU_REGS_RSI]),
1534 c->rep_prefix,
1535 c->regs[VCPU_REGS_RDX]) == 0) {
1536 c->eip = saved_eip;
1537 return -1;
1538 }
1539 return 0;
b2833e3c 1540 case 0x70 ... 0x7f: /* jcc (short) */
018a98db 1541 if (test_cc(c->b, ctxt->eflags))
b2833e3c 1542 jmp_rel(c, c->src.val);
018a98db 1543 break;
6aa8b732 1544 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 1545 switch (c->modrm_reg) {
6aa8b732
AK		 1546 case 0:
1547 goto add;
1548 case 1:
1549 goto or;
1550 case 2:
1551 goto adc;
1552 case 3:
1553 goto sbb;
1554 case 4:
1555 goto and;
1556 case 5:
1557 goto sub;
1558 case 6:
1559 goto xor;
1560 case 7:
1561 goto cmp;
1562 }
1563 break;
1564 case 0x84 ... 0x85:
05f086f8 1565 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1566 break;
1567 case 0x86 ... 0x87: /* xchg */
b13354f8 1568 xchg:
6aa8b732 1569 /* Write back the register source. */
e4e03ded 1570 switch (c->dst.bytes) {
6aa8b732 1571 case 1:
e4e03ded 1572 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 1573 break;
1574 case 2:
e4e03ded 1575 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 1576 break;
1577 case 4:
e4e03ded 1578 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 1579 break; /* 64b reg: zero-extend */
1580 case 8:
e4e03ded 1581 *c->src.ptr = c->dst.val;
6aa8b732
AK		 1582 break;
1583 }
1584 /*
1585 * Write back the memory destination with implicit LOCK
1586 * prefix.
1587 */
e4e03ded
LV		 1588 c->dst.val = c->src.val;
1589 c->lock_prefix = 1;
6aa8b732 1590 break;
6aa8b732 1591 case 0x88 ... 0x8b: /* mov */
7de75248 1592 goto mov;
38d5bc6d
GT		 1593 case 0x8c: { /* mov r/m, sreg */
1594 struct kvm_segment segreg;
1595
1596 if (c->modrm_reg <= 5)
1597 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
1598 else {
1599 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
1600 c->modrm);
1601 goto cannot_emulate;
1602 }
1603 c->dst.val = segreg.selector;
1604 break;
1605 }
7e0b54b1 1606 case 0x8d: /* lea r16/r32, m */
f9b7aab3 1607 c->dst.val = c->modrm_ea;
7e0b54b1 1608 break;
4257198a
GT		 1609 case 0x8e: { /* mov seg, r/m16 */
1610 uint16_t sel;
1611 int type_bits;
1612 int err;
1613
1614 sel = c->src.val;
1615 if (c->modrm_reg <= 5) {
1616 type_bits = (c->modrm_reg == 1) ? 9 : 1;
1617 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
1618 type_bits, c->modrm_reg);
1619 } else {
1620 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
1621 c->modrm);
1622 goto cannot_emulate;
1623 }
1624
1625 if (err < 0)
1626 goto cannot_emulate;
1627
1628 c->dst.type = OP_NONE; /* Disable writeback. */
1629 break;
1630 }
6aa8b732 1631 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 1632 rc = emulate_grp1a(ctxt, ops);
1633 if (rc != 0)
6aa8b732 1634 goto done;
6aa8b732 1635 break;
b13354f8
MG		 1636 case 0x90: /* nop / xchg r8,rax */
1637 if (!(c->rex_prefix & 1)) { /* nop */
1638 c->dst.type = OP_NONE;
1639 break;
1640 }
1641 case 0x91 ... 0x97: /* xchg reg,rax */
1642 c->src.type = c->dst.type = OP_REG;
1643 c->src.bytes = c->dst.bytes = c->op_bytes;
1644 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
1645 c->src.val = *(c->src.ptr);
1646 goto xchg;
fd2a7608 1647 case 0x9c: /* pushf */
05f086f8 1648 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 1649 emulate_push(ctxt);
1650 break;
535eabcf 1651 case 0x9d: /* popf */
2b48cc75 1652 c->dst.type = OP_REG;
05f086f8 1653 c->dst.ptr = (unsigned long *) &ctxt->eflags;
2b48cc75 1654 c->dst.bytes = c->op_bytes;
535eabcf 1655 goto pop_instruction;
018a98db
AK		 1656 case 0xa0 ... 0xa1: /* mov */
1657 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1658 c->dst.val = c->src.val;
1659 break;
1660 case 0xa2 ... 0xa3: /* mov */
1661 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1662 break;
6aa8b732 1663 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 1664 c->dst.type = OP_MEM;
1665 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1666 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1667 es_base(ctxt),
e4e03ded 1668 c->regs[VCPU_REGS_RDI]);
e4706772 1669 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 1670 seg_override_base(ctxt, c),
e4e03ded
LV		 1671 c->regs[VCPU_REGS_RSI]),
1672 &c->dst.val,
1673 c->dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1674 goto done;
7a957275 1675 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1676 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1677 : c->dst.bytes);
7a957275 1678 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1679 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1680 : c->dst.bytes);
6aa8b732
AK		 1681 break;
1682 case 0xa6 ... 0xa7: /* cmps */
d7e5117a
GT		 1683 c->src.type = OP_NONE; /* Disable writeback. */
1684 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1685 c->src.ptr = (unsigned long *)register_address(c,
7a5b56df 1686 seg_override_base(ctxt, c),
d7e5117a
GT		 1687 c->regs[VCPU_REGS_RSI]);
1688 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1689 &c->src.val,
1690 c->src.bytes,
1691 ctxt->vcpu)) != 0)
1692 goto done;
1693
1694 c->dst.type = OP_NONE; /* Disable writeback. */
1695 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1696 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1697 es_base(ctxt),
d7e5117a
GT		 1698 c->regs[VCPU_REGS_RDI]);
1699 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1700 &c->dst.val,
1701 c->dst.bytes,
1702 ctxt->vcpu)) != 0)
1703 goto done;
1704
1705 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1706
1707 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1708
7a957275 1709 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
d7e5117a
GT		 1710 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1711 : c->src.bytes);
7a957275 1712 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
d7e5117a
GT		 1713 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1714 : c->dst.bytes);
1715
1716 break;
6aa8b732 1717 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 1718 c->dst.type = OP_MEM;
1719 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1720 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1721 es_base(ctxt),
a7e6c88a 1722 c->regs[VCPU_REGS_RDI]);
e4e03ded 1723 c->dst.val = c->regs[VCPU_REGS_RAX];
7a957275 1724 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1725 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1726 : c->dst.bytes);
6aa8b732
AK		 1727 break;
1728 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 1729 c->dst.type = OP_REG;
1730 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1731 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
e4706772 1732 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 1733 seg_override_base(ctxt, c),
a7e6c88a
SY		 1734 c->regs[VCPU_REGS_RSI]),
1735 &c->dst.val,
1736 c->dst.bytes,
1737 ctxt->vcpu)) != 0)
6aa8b732 1738 goto done;
7a957275 1739 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1740 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1741 : c->dst.bytes);
6aa8b732
AK		 1742 break;
1743 case 0xae ... 0xaf: /* scas */
1744 DPRINTF("Urk! I don't handle SCAS.\n");
1745 goto cannot_emulate;
a5e2e82b 1746 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 1747 goto mov;
018a98db
AK		 1748 case 0xc0 ... 0xc1:
1749 emulate_grp2(ctxt);
1750 break;
111de5d6 1751 case 0xc3: /* ret */
cf5de4f8 1752 c->dst.type = OP_REG;
111de5d6 1753 c->dst.ptr = &c->eip;
cf5de4f8 1754 c->dst.bytes = c->op_bytes;
111de5d6 1755 goto pop_instruction;
018a98db
AK		 1756 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1757 mov:
1758 c->dst.val = c->src.val;
1759 break;
a77ab5ea
AK		 1760 case 0xcb: /* ret far */
1761 rc = emulate_ret_far(ctxt, ops);
1762 if (rc)
1763 goto done;
1764 break;
018a98db
AK		 1765 case 0xd0 ... 0xd1: /* Grp2 */
1766 c->src.val = 1;
1767 emulate_grp2(ctxt);
1768 break;
1769 case 0xd2 ... 0xd3: /* Grp2 */
1770 c->src.val = c->regs[VCPU_REGS_RCX];
1771 emulate_grp2(ctxt);
1772 break;
a6a3034c
MG		 1773 case 0xe4: /* inb */
1774 case 0xe5: /* in */
1775 port = insn_fetch(u8, 1, c->eip);
1776 io_dir_in = 1;
1777 goto do_io;
1778 case 0xe6: /* outb */
1779 case 0xe7: /* out */
1780 port = insn_fetch(u8, 1, c->eip);
1781 io_dir_in = 0;
1782 goto do_io;
1a52e051 1783 case 0xe8: /* call (near) */ {
d53c4777 1784 long int rel = c->src.val;
e4e03ded 1785 c->src.val = (unsigned long) c->eip;
7a957275 1786 jmp_rel(c, rel);
8cdbd2c9
LV		 1787 emulate_push(ctxt);
1788 break;
1a52e051
NK		 1789 }
1790 case 0xe9: /* jmp rel */
954cd36f 1791 goto jmp;
782b877c
GN		 1792 case 0xea: /* jmp far */
1793 if (kvm_load_segment_descriptor(ctxt->vcpu, c->src2.val, 9,
1794 VCPU_SREG_CS) < 0) {
954cd36f
GT		 1795 DPRINTF("jmp far: Failed to load CS descriptor\n");
1796 goto cannot_emulate;
1797 }
1798
782b877c 1799 c->eip = c->src.val;
954cd36f 1800 break;
954cd36f
GT		 1801 case 0xeb:
1802 jmp: /* jmp rel short */
7a957275 1803 jmp_rel(c, c->src.val);
a01af5ec 1804 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 1805 break;
a6a3034c
MG		 1806 case 0xec: /* in al,dx */
1807 case 0xed: /* in (e/r)ax,dx */
1808 port = c->regs[VCPU_REGS_RDX];
1809 io_dir_in = 1;
1810 goto do_io;
1811 case 0xee: /* out al,dx */
1812 case 0xef: /* out (e/r)ax,dx */
1813 port = c->regs[VCPU_REGS_RDX];
1814 io_dir_in = 0;
1815 do_io: if (kvm_emulate_pio(ctxt->vcpu, NULL, io_dir_in,
1816 (c->d & ByteOp) ? 1 : c->op_bytes,
1817 port) != 0) {
1818 c->eip = saved_eip;
1819 goto cannot_emulate;
1820 }
e93f36bc 1821 break;
111de5d6 1822 case 0xf4: /* hlt */
ad312c7c 1823 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 1824 break;
111de5d6
AK		 1825 case 0xf5: /* cmc */
1826 /* complement carry flag from eflags reg */
1827 ctxt->eflags ^= EFLG_CF;
1828 c->dst.type = OP_NONE; /* Disable writeback. */
1829 break;
018a98db
AK		 1830 case 0xf6 ... 0xf7: /* Grp3 */
1831 rc = emulate_grp3(ctxt, ops);
1832 if (rc != 0)
1833 goto done;
1834 break;
111de5d6
AK		 1835 case 0xf8: /* clc */
1836 ctxt->eflags &= ~EFLG_CF;
1837 c->dst.type = OP_NONE; /* Disable writeback. */
1838 break;
1839 case 0xfa: /* cli */
1840 ctxt->eflags &= ~X86_EFLAGS_IF;
1841 c->dst.type = OP_NONE; /* Disable writeback. */
1842 break;
1843 case 0xfb: /* sti */
1844 ctxt->eflags |= X86_EFLAGS_IF;
1845 c->dst.type = OP_NONE; /* Disable writeback. */
1846 break;
fb4616f4
MG		 1847 case 0xfc: /* cld */
1848 ctxt->eflags &= ~EFLG_DF;
1849 c->dst.type = OP_NONE; /* Disable writeback. */
1850 break;
1851 case 0xfd: /* std */
1852 ctxt->eflags |= EFLG_DF;
1853 c->dst.type = OP_NONE; /* Disable writeback. */
1854 break;
018a98db
AK		 1855 case 0xfe ... 0xff: /* Grp4/Grp5 */
1856 rc = emulate_grp45(ctxt, ops);
1857 if (rc != 0)
1858 goto done;
1859 break;
6aa8b732 1860 }
018a98db
AK		 1861
1862writeback:
1863 rc = writeback(ctxt, ops);
1864 if (rc != 0)
1865 goto done;
1866
1867 /* Commit shadow register state. */
ad312c7c 1868 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
5fdbf976 1869 kvm_rip_write(ctxt->vcpu, c->eip);
018a98db
AK		 1870
1871done:
1872 if (rc == X86EMUL_UNHANDLEABLE) {
1873 c->eip = saved_eip;
1874 return -1;
1875 }
1876 return 0;
6aa8b732
AK		 1877
1878twobyte_insn:
e4e03ded 1879 switch (c->b) {
6aa8b732 1880 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 1881 switch (c->modrm_reg) {
6aa8b732
AK		 1882 u16 size;
1883 unsigned long address;
1884
aca7f966 1885 case 0: /* vmcall */
e4e03ded 1886 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 1887 goto cannot_emulate;
1888
7aa81cc0
AL		 1889 rc = kvm_fix_hypercall(ctxt->vcpu);
1890 if (rc)
1891 goto done;
1892
33e3885d 1893 /* Let the processor re-execute the fixed hypercall */
5fdbf976 1894 c->eip = kvm_rip_read(ctxt->vcpu);
16286d08
AK		 1895 /* Disable writeback. */
1896 c->dst.type = OP_NONE;
aca7f966 1897 break;
6aa8b732 1898 case 2: /* lgdt */
e4e03ded
LV		 1899 rc = read_descriptor(ctxt, ops, c->src.ptr,
1900 &size, &address, c->op_bytes);
6aa8b732
AK		 1901 if (rc)
1902 goto done;
1903 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 1904 /* Disable writeback. */
1905 c->dst.type = OP_NONE;
6aa8b732 1906 break;
aca7f966 1907 case 3: /* lidt/vmmcall */
2b3d2a20
AK		 1908 if (c->modrm_mod == 3) {
1909 switch (c->modrm_rm) {
1910 case 1:
1911 rc = kvm_fix_hypercall(ctxt->vcpu);
1912 if (rc)
1913 goto done;
1914 break;
1915 default:
1916 goto cannot_emulate;
1917 }
aca7f966 1918 } else {
e4e03ded 1919 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 1920 &size, &address,
e4e03ded 1921 c->op_bytes);
aca7f966
AL		 1922 if (rc)
1923 goto done;
1924 realmode_lidt(ctxt->vcpu, size, address);
1925 }
16286d08
AK		 1926 /* Disable writeback. */
1927 c->dst.type = OP_NONE;
6aa8b732
AK		 1928 break;
1929 case 4: /* smsw */
16286d08
AK		 1930 c->dst.bytes = 2;
1931 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
6aa8b732
AK		 1932 break;
1933 case 6: /* lmsw */
16286d08
AK		 1934 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
1935 &ctxt->eflags);
dc7457ea 1936 c->dst.type = OP_NONE;
6aa8b732
AK		 1937 break;
1938 case 7: /* invlpg*/
e8d8d7fe 1939 emulate_invlpg(ctxt->vcpu, memop);
16286d08
AK		 1940 /* Disable writeback. */
1941 c->dst.type = OP_NONE;
6aa8b732
AK		 1942 break;
1943 default:
1944 goto cannot_emulate;
1945 }
1946 break;
018a98db
AK		 1947 case 0x06:
1948 emulate_clts(ctxt->vcpu);
1949 c->dst.type = OP_NONE;
1950 break;
1951 case 0x08: /* invd */
1952 case 0x09: /* wbinvd */
1953 case 0x0d: /* GrpP (prefetch) */
1954 case 0x18: /* Grp16 (prefetch/nop) */
1955 c->dst.type = OP_NONE;
1956 break;
1957 case 0x20: /* mov cr, reg */
1958 if (c->modrm_mod != 3)
1959 goto cannot_emulate;
1960 c->regs[c->modrm_rm] =
1961 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1962 c->dst.type = OP_NONE; /* no writeback */
1963 break;
6aa8b732 1964 case 0x21: /* mov from dr to reg */
e4e03ded 1965 if (c->modrm_mod != 3)
6aa8b732 1966 goto cannot_emulate;
8cdbd2c9 1967 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 1968 if (rc)
1969 goto cannot_emulate;
1970 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1971 break;
018a98db
AK		 1972 case 0x22: /* mov reg, cr */
1973 if (c->modrm_mod != 3)
1974 goto cannot_emulate;
1975 realmode_set_cr(ctxt->vcpu,
1976 c->modrm_reg, c->modrm_val, &ctxt->eflags);
1977 c->dst.type = OP_NONE;
1978 break;
6aa8b732 1979 case 0x23: /* mov from reg to dr */
e4e03ded 1980 if (c->modrm_mod != 3)
6aa8b732 1981 goto cannot_emulate;
e4e03ded
LV		 1982 rc = emulator_set_dr(ctxt, c->modrm_reg,
1983 c->regs[c->modrm_rm]);
a01af5ec
LV		 1984 if (rc)
1985 goto cannot_emulate;
1986 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1987 break;
018a98db
AK		 1988 case 0x30:
1989 /* wrmsr */
1990 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1991 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1992 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
1993 if (rc) {
c1a5d4f9 1994 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 1995 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 1996 }
1997 rc = X86EMUL_CONTINUE;
1998 c->dst.type = OP_NONE;
1999 break;
2000 case 0x32:
2001 /* rdmsr */
2002 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
2003 if (rc) {
c1a5d4f9 2004 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 2005 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 2006 } else {
2007 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
2008 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
2009 }
2010 rc = X86EMUL_CONTINUE;
2011 c->dst.type = OP_NONE;
2012 break;
6aa8b732 2013 case 0x40 ... 0x4f: /* cmov */
e4e03ded 2014 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 2015 if (!test_cc(c->b, ctxt->eflags))
2016 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 2017 break;
b2833e3c 2018 case 0x80 ... 0x8f: /* jnz rel, etc*/
018a98db 2019 if (test_cc(c->b, ctxt->eflags))
b2833e3c 2020 jmp_rel(c, c->src.val);
018a98db
AK		 2021 c->dst.type = OP_NONE;
2022 break;
7de75248
NK		 2023 case 0xa3:
2024 bt: /* bt */
e4f8e039 2025 c->dst.type = OP_NONE;
e4e03ded
LV		 2026 /* only subword offset */
2027 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2028 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248 2029 break;
9bf8ea42
GT		 2030 case 0xa4: /* shld imm8, r, r/m */
2031 case 0xa5: /* shld cl, r, r/m */
2032 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
2033 break;
7de75248
NK		 2034 case 0xab:
2035 bts: /* bts */
e4e03ded
LV		 2036 /* only subword offset */
2037 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2038 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 2039 break;
9bf8ea42
GT		 2040 case 0xac: /* shrd imm8, r, r/m */
2041 case 0xad: /* shrd cl, r, r/m */
2042 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
2043 break;
2a7c5b8b
GC		 2044 case 0xae: /* clflush */
2045 break;
6aa8b732
AK		 2046 case 0xb0 ... 0xb1: /* cmpxchg */
2047 /*
2048 * Save real source value, then compare EAX against
2049 * destination.
2050 */
e4e03ded
LV		 2051 c->src.orig_val = c->src.val;
2052 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 2053 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2054 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 2055 /* Success: write back to memory. */
e4e03ded 2056 c->dst.val = c->src.orig_val;
6aa8b732
AK		 2057 } else {
2058 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 2059 c->dst.type = OP_REG;
2060 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 2061 }
2062 break;
6aa8b732
AK		 2063 case 0xb3:
2064 btr: /* btr */
e4e03ded
LV		 2065 /* only subword offset */
2066 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2067 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 2068 break;
6aa8b732 2069 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 2070 c->dst.bytes = c->op_bytes;
2071 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
2072 : (u16) c->src.val;
6aa8b732 2073 break;
6aa8b732 2074 case 0xba: /* Grp8 */
e4e03ded 2075 switch (c->modrm_reg & 3) {
6aa8b732
AK		 2076 case 0:
2077 goto bt;
2078 case 1:
2079 goto bts;
2080 case 2:
2081 goto btr;
2082 case 3:
2083 goto btc;
2084 }
2085 break;
7de75248
NK		 2086 case 0xbb:
2087 btc: /* btc */
e4e03ded
LV		 2088 /* only subword offset */
2089 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2090 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 2091 break;
6aa8b732 2092 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 2093 c->dst.bytes = c->op_bytes;
2094 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
2095 (s16) c->src.val;
6aa8b732 2096 break;
a012e65a 2097 case 0xc3: /* movnti */
e4e03ded
LV		 2098 c->dst.bytes = c->op_bytes;
2099 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
2100 (u64) c->src.val;
a012e65a 2101 break;
6aa8b732 2102 case 0xc7: /* Grp9 (cmpxchg8b) */
e8d8d7fe 2103 rc = emulate_grp9(ctxt, ops, memop);
8cdbd2c9
LV		 2104 if (rc != 0)
2105 goto done;
018a98db 2106 c->dst.type = OP_NONE;
8cdbd2c9 2107 break;
6aa8b732
AK		 2108 }
2109 goto writeback;
2110
2111cannot_emulate:
e4e03ded 2112 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 2113 c->eip = saved_eip;
6aa8b732
AK		 2114 return -1;
2115}
Linux kernel - Deliverables
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