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KVM: x86 emulator: simplify sib decoding
[deliverable/linux.git] / arch / x86 / kvm / x86_emulate.c
CommitLineData
6aa8b732
AK		 1/******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
6aa8b732
AK		 29#define DPRINTF(x...) do {} while (0)
30#endif
6aa8b732 31#include <linux/module.h>
edf88417 32#include <asm/kvm_x86_emulate.h>
6aa8b732
AK		 33
34/*
35 * Opcode effective-address decode tables.
36 * Note that we only emulate instructions that have at least one memory
37 * operand (excluding implicit stack references). We assume that stack
38 * references and instruction fetches will never occur in special memory
39 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
40 * not be handled.
41 */
42
43/* Operand sizes: 8-bit operands or specified/overridden size. */
44#define ByteOp (1<<0) /* 8-bit operands. */
45/* Destination operand type. */
46#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
47#define DstReg (2<<1) /* Register operand. */
48#define DstMem (3<<1) /* Memory operand. */
49#define DstMask (3<<1)
50/* Source operand type. */
51#define SrcNone (0<<3) /* No source operand. */
52#define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */
53#define SrcReg (1<<3) /* Register operand. */
54#define SrcMem (2<<3) /* Memory operand. */
55#define SrcMem16 (3<<3) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<3) /* Memory operand (32-bit). */
57#define SrcImm (5<<3) /* Immediate operand. */
58#define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */
59#define SrcMask (7<<3)
60/* Generic ModRM decode. */
61#define ModRM (1<<6)
62/* Destination is only written; never read. */
63#define Mov (1<<7)
038e51de 64#define BitOp (1<<8)
c7e75a3d 65#define MemAbs (1<<9) /* Memory operand is absolute displacement */
b9fa9d6b 66#define String (1<<10) /* String instruction (rep capable) */
6e3d5dfb 67#define Stack (1<<11) /* Stack instruction (push/pop) */
e09d082c
AK		 68#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
69#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
70#define GroupMask 0xff /* Group number stored in bits 0:7 */
6aa8b732 71
43bb19cd 72enum {
1d6ad207 73 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 74 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
43bb19cd
AK		 75};
76
c7e75a3d 77static u16 opcode_table[256] = {
6aa8b732
AK		 78 /* 0x00 - 0x07 */
79 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
80 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
81 0, 0, 0, 0,
82 /* 0x08 - 0x0F */
83 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
84 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
85 0, 0, 0, 0,
86 /* 0x10 - 0x17 */
87 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
88 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
89 0, 0, 0, 0,
90 /* 0x18 - 0x1F */
91 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
92 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
93 0, 0, 0, 0,
94 /* 0x20 - 0x27 */
95 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
96 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
19eb938e 97 SrcImmByte, SrcImm, 0, 0,
6aa8b732
AK		 98 /* 0x28 - 0x2F */
99 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
100 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
101 0, 0, 0, 0,
102 /* 0x30 - 0x37 */
103 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
104 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
105 0, 0, 0, 0,
106 /* 0x38 - 0x3F */
107 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
108 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
109 0, 0, 0, 0,
d77a2507 110 /* 0x40 - 0x47 */
33615aa9 111 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 112 /* 0x48 - 0x4F */
33615aa9 113 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 114 /* 0x50 - 0x57 */
6e3d5dfb
AK		 115 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
116 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 117 /* 0x58 - 0x5F */
6e3d5dfb
AK		 118 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
119 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 120 /* 0x60 - 0x67 */
6aa8b732 121 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 122 0, 0, 0, 0,
123 /* 0x68 - 0x6F */
91ed7a0e 124 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
e70669ab
LV		 125 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
126 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4
NK		 127 /* 0x70 - 0x77 */
128 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
129 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
130 /* 0x78 - 0x7F */
131 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
132 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732 133 /* 0x80 - 0x87 */
1d6ad207
AK		 134 Group | Group1_80, Group | Group1_81,
135 Group | Group1_82, Group | Group1_83,
6aa8b732
AK		 136 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
137 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
138 /* 0x88 - 0x8F */
139 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
140 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
38d5bc6d 141 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
4257198a 142 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
b13354f8
MG		 143 /* 0x90 - 0x97 */
144 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
145 /* 0x98 - 0x9F */
6e3d5dfb 146 0, 0, 0, 0, ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 147 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 148 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
149 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
b9fa9d6b
AK		 150 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
151 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 152 /* 0xA8 - 0xAF */
b9fa9d6b
AK		 153 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
154 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
155 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 156 /* 0xB0 - 0xBF */
615ac125
GT		 157 0, 0, 0, 0, 0, 0, 0, 0,
158 DstReg | SrcImm | Mov, 0, 0, 0, 0, 0, 0, 0,
6aa8b732 159 /* 0xC0 - 0xC7 */
d9413cd7 160 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 161 0, ImplicitOps | Stack, 0, 0,
d9413cd7 162 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732
AK		 163 /* 0xC8 - 0xCF */
164 0, 0, 0, 0, 0, 0, 0, 0,
165 /* 0xD0 - 0xD7 */
166 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
167 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
168 0, 0, 0, 0,
169 /* 0xD8 - 0xDF */
170 0, 0, 0, 0, 0, 0, 0, 0,
098c937b
NK		 171 /* 0xE0 - 0xE7 */
172 0, 0, 0, 0, 0, 0, 0, 0,
173 /* 0xE8 - 0xEF */
954cd36f
GT		 174 ImplicitOps | Stack, SrcImm | ImplicitOps,
175 ImplicitOps, SrcImmByte | ImplicitOps,
6e3d5dfb 176 0, 0, 0, 0,
6aa8b732
AK		 177 /* 0xF0 - 0xF7 */
178 0, 0, 0, 0,
7d858a19 179 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 180 /* 0xF8 - 0xFF */
b284be57 181 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fd60754e 182 0, 0, Group | Group4, Group | Group5,
6aa8b732
AK		 183};
184
038e51de 185static u16 twobyte_table[256] = {
6aa8b732 186 /* 0x00 - 0x0F */
d95058a1 187 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
651a3e29 188 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 189 /* 0x10 - 0x1F */
190 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
191 /* 0x20 - 0x2F */
192 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
193 0, 0, 0, 0, 0, 0, 0, 0,
194 /* 0x30 - 0x3F */
35f3f286 195 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 196 /* 0x40 - 0x47 */
197 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
198 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
199 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
200 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
201 /* 0x48 - 0x4F */
202 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
203 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
204 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
205 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
206 /* 0x50 - 0x5F */
207 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
208 /* 0x60 - 0x6F */
209 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
210 /* 0x70 - 0x7F */
211 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
212 /* 0x80 - 0x8F */
bbe9abbd
NK		 213 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
214 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
215 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
216 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 217 /* 0x90 - 0x9F */
218 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
219 /* 0xA0 - 0xA7 */
038e51de 220 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732 221 /* 0xA8 - 0xAF */
038e51de 222 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732
AK		 223 /* 0xB0 - 0xB7 */
224 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 225 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 226 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
227 DstReg | SrcMem16 | ModRM | Mov,
228 /* 0xB8 - 0xBF */
038e51de 229 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 230 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
231 DstReg | SrcMem16 | ModRM | Mov,
232 /* 0xC0 - 0xCF */
a012e65a
SY		 233 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
234 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 235 /* 0xD0 - 0xDF */
236 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
237 /* 0xE0 - 0xEF */
238 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
239 /* 0xF0 - 0xFF */
240 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
241};
242
e09d082c 243static u16 group_table[] = {
1d6ad207
AK		 244 [Group1_80*8] =
245 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
246 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
247 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
248 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
249 [Group1_81*8] =
250 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
251 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
252 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
253 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
254 [Group1_82*8] =
255 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
256 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
257 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
258 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
259 [Group1_83*8] =
260 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
261 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
262 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
263 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 264 [Group1A*8] =
265 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 266 [Group3_Byte*8] =
267 ByteOp | SrcImm | DstMem | ModRM, 0,
268 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
269 0, 0, 0, 0,
270 [Group3*8] =
271 DstMem | SrcImm | ModRM | SrcImm, 0,
272 DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
273 0, 0, 0, 0,
fd60754e
AK		 274 [Group4*8] =
275 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
276 0, 0, 0, 0, 0, 0,
277 [Group5*8] =
278 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM, 0, 0,
279 SrcMem | ModRM, 0, SrcMem | ModRM | Stack, 0,
d95058a1
AK		 280 [Group7*8] =
281 0, 0, ModRM | SrcMem, ModRM | SrcMem,
16286d08
AK		 282 SrcNone | ModRM | DstMem | Mov, 0,
283 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
e09d082c
AK		 284};
285
286static u16 group2_table[] = {
d95058a1 287 [Group7*8] =
16286d08
AK		 288 SrcNone | ModRM, 0, 0, 0,
289 SrcNone | ModRM | DstMem | Mov, 0,
290 SrcMem16 | ModRM | Mov, 0,
e09d082c
AK		 291};
292
6aa8b732
AK		 293/* EFLAGS bit definitions. */
294#define EFLG_OF (1<<11)
295#define EFLG_DF (1<<10)
296#define EFLG_SF (1<<7)
297#define EFLG_ZF (1<<6)
298#define EFLG_AF (1<<4)
299#define EFLG_PF (1<<2)
300#define EFLG_CF (1<<0)
301
302/*
303 * Instruction emulation:
304 * Most instructions are emulated directly via a fragment of inline assembly
305 * code. This allows us to save/restore EFLAGS and thus very easily pick up
306 * any modified flags.
307 */
308
05b3e0c2 309#if defined(CONFIG_X86_64)
6aa8b732
AK		 310#define _LO32 "k" /* force 32-bit operand */
311#define _STK "%%rsp" /* stack pointer */
312#elif defined(__i386__)
313#define _LO32 "" /* force 32-bit operand */
314#define _STK "%%esp" /* stack pointer */
315#endif
316
317/*
318 * These EFLAGS bits are restored from saved value during emulation, and
319 * any changes are written back to the saved value after emulation.
320 */
321#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
322
323/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 324#define _PRE_EFLAGS(_sav, _msk, _tmp) \
325 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
326 "movl %"_sav",%"_LO32 _tmp"; " \
327 "push %"_tmp"; " \
328 "push %"_tmp"; " \
329 "movl %"_msk",%"_LO32 _tmp"; " \
330 "andl %"_LO32 _tmp",("_STK"); " \
331 "pushf; " \
332 "notl %"_LO32 _tmp"; " \
333 "andl %"_LO32 _tmp",("_STK"); " \
334 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
335 "pop %"_tmp"; " \
336 "orl %"_LO32 _tmp",("_STK"); " \
337 "popf; " \
338 "pop %"_sav"; "
6aa8b732
AK		 339
340/* After executing instruction: write-back necessary bits in EFLAGS. */
341#define _POST_EFLAGS(_sav, _msk, _tmp) \
342 /* _sav |= EFLAGS & _msk; */ \
343 "pushf; " \
344 "pop %"_tmp"; " \
345 "andl %"_msk",%"_LO32 _tmp"; " \
346 "orl %"_LO32 _tmp",%"_sav"; "
347
348/* Raw emulation: instruction has two explicit operands. */
349#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
350 do { \
351 unsigned long _tmp; \
352 \
353 switch ((_dst).bytes) { \
354 case 2: \
355 __asm__ __volatile__ ( \
d77c26fc 356 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 357 _op"w %"_wx"3,%1; " \
d77c26fc 358 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 359 : "=m" (_eflags), "=m" ((_dst).val), \
360 "=&r" (_tmp) \
d77c26fc 361 : _wy ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 362 break; \
363 case 4: \
364 __asm__ __volatile__ ( \
d77c26fc 365 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 366 _op"l %"_lx"3,%1; " \
d77c26fc 367 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 368 : "=m" (_eflags), "=m" ((_dst).val), \
369 "=&r" (_tmp) \
d77c26fc 370 : _ly ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 371 break; \
372 case 8: \
373 __emulate_2op_8byte(_op, _src, _dst, \
374 _eflags, _qx, _qy); \
375 break; \
376 } \
377 } while (0)
378
379#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
380 do { \
77cd337f 381 unsigned long __tmp; \
d77c26fc 382 switch ((_dst).bytes) { \
6aa8b732
AK		 383 case 1: \
384 __asm__ __volatile__ ( \
d77c26fc 385 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 386 _op"b %"_bx"3,%1; " \
d77c26fc 387 _POST_EFLAGS("0", "4", "2") \
6aa8b732 388 : "=m" (_eflags), "=m" ((_dst).val), \
77cd337f 389 "=&r" (__tmp) \
d77c26fc 390 : _by ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 391 break; \
392 default: \
393 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
394 _wx, _wy, _lx, _ly, _qx, _qy); \
395 break; \
396 } \
397 } while (0)
398
399/* Source operand is byte-sized and may be restricted to just %cl. */
400#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
401 __emulate_2op(_op, _src, _dst, _eflags, \
402 "b", "c", "b", "c", "b", "c", "b", "c")
403
404/* Source operand is byte, word, long or quad sized. */
405#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
406 __emulate_2op(_op, _src, _dst, _eflags, \
407 "b", "q", "w", "r", _LO32, "r", "", "r")
408
409/* Source operand is word, long or quad sized. */
410#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
411 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
412 "w", "r", _LO32, "r", "", "r")
413
414/* Instruction has only one explicit operand (no source operand). */
415#define emulate_1op(_op, _dst, _eflags) \
416 do { \
417 unsigned long _tmp; \
418 \
d77c26fc 419 switch ((_dst).bytes) { \
6aa8b732
AK		 420 case 1: \
421 __asm__ __volatile__ ( \
d77c26fc 422 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 423 _op"b %1; " \
d77c26fc 424 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 425 : "=m" (_eflags), "=m" ((_dst).val), \
426 "=&r" (_tmp) \
d77c26fc 427 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 428 break; \
429 case 2: \
430 __asm__ __volatile__ ( \
d77c26fc 431 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 432 _op"w %1; " \
d77c26fc 433 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 434 : "=m" (_eflags), "=m" ((_dst).val), \
435 "=&r" (_tmp) \
d77c26fc 436 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 437 break; \
438 case 4: \
439 __asm__ __volatile__ ( \
d77c26fc 440 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 441 _op"l %1; " \
d77c26fc 442 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 443 : "=m" (_eflags), "=m" ((_dst).val), \
444 "=&r" (_tmp) \
d77c26fc 445 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 446 break; \
447 case 8: \
448 __emulate_1op_8byte(_op, _dst, _eflags); \
449 break; \
450 } \
451 } while (0)
452
453/* Emulate an instruction with quadword operands (x86/64 only). */
05b3e0c2 454#if defined(CONFIG_X86_64)
6aa8b732
AK		 455#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
456 do { \
457 __asm__ __volatile__ ( \
d77c26fc 458 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 459 _op"q %"_qx"3,%1; " \
d77c26fc 460 _POST_EFLAGS("0", "4", "2") \
6aa8b732 461 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
d77c26fc 462 : _qy ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 463 } while (0)
464
465#define __emulate_1op_8byte(_op, _dst, _eflags) \
466 do { \
467 __asm__ __volatile__ ( \
d77c26fc 468 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 469 _op"q %1; " \
d77c26fc 470 _POST_EFLAGS("0", "3", "2") \
6aa8b732 471 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
d77c26fc 472 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 473 } while (0)
474
475#elif defined(__i386__)
476#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
477#define __emulate_1op_8byte(_op, _dst, _eflags)
478#endif /* __i386__ */
479
480/* Fetch next part of the instruction being emulated. */
481#define insn_fetch(_type, _size, _eip) \
482({ unsigned long _x; \
62266869 483 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
d77c26fc 484 if (rc != 0) \
6aa8b732
AK		 485 goto done; \
486 (_eip) += (_size); \
487 (_type)_x; \
488})
489
ddcb2885
HH		 490static inline unsigned long ad_mask(struct decode_cache *c)
491{
492 return (1UL << (c->ad_bytes << 3)) - 1;
493}
494
6aa8b732 495/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 496static inline unsigned long
497address_mask(struct decode_cache *c, unsigned long reg)
498{
499 if (c->ad_bytes == sizeof(unsigned long))
500 return reg;
501 else
502 return reg & ad_mask(c);
503}
504
505static inline unsigned long
506register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
507{
508 return base + address_mask(c, reg);
509}
510
7a957275
HH		 511static inline void
512register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
513{
514 if (c->ad_bytes == sizeof(unsigned long))
515 *reg += inc;
516 else
517 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
518}
6aa8b732 519
7a957275
HH		 520static inline void jmp_rel(struct decode_cache *c, int rel)
521{
522 register_address_increment(c, &c->eip, rel);
523}
098c937b 524
62266869
AK		 525static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
526 struct x86_emulate_ops *ops,
527 unsigned long linear, u8 *dest)
528{
529 struct fetch_cache *fc = &ctxt->decode.fetch;
530 int rc;
531 int size;
532
533 if (linear < fc->start || linear >= fc->end) {
534 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
535 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
536 if (rc)
537 return rc;
538 fc->start = linear;
539 fc->end = linear + size;
540 }
541 *dest = fc->data[linear - fc->start];
542 return 0;
543}
544
545static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
546 struct x86_emulate_ops *ops,
547 unsigned long eip, void *dest, unsigned size)
548{
549 int rc = 0;
550
551 eip += ctxt->cs_base;
552 while (size--) {
553 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
554 if (rc)
555 return rc;
556 }
557 return 0;
558}
559
1e3c5cb0
RR		 560/*
561 * Given the 'reg' portion of a ModRM byte, and a register block, return a
562 * pointer into the block that addresses the relevant register.
563 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
564 */
565static void *decode_register(u8 modrm_reg, unsigned long *regs,
566 int highbyte_regs)
6aa8b732
AK		 567{
568 void *p;
569
570 p = &regs[modrm_reg];
571 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
572 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
573 return p;
574}
575
576static int read_descriptor(struct x86_emulate_ctxt *ctxt,
577 struct x86_emulate_ops *ops,
578 void *ptr,
579 u16 *size, unsigned long *address, int op_bytes)
580{
581 int rc;
582
583 if (op_bytes == 2)
584 op_bytes = 3;
585 *address = 0;
cebff02b
LV		 586 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
587 ctxt->vcpu);
6aa8b732
AK		 588 if (rc)
589 return rc;
cebff02b
LV		 590 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
591 ctxt->vcpu);
6aa8b732
AK		 592 return rc;
593}
594
bbe9abbd
NK		 595static int test_cc(unsigned int condition, unsigned int flags)
596{
597 int rc = 0;
598
599 switch ((condition & 15) >> 1) {
600 case 0: /* o */
601 rc |= (flags & EFLG_OF);
602 break;
603 case 1: /* b/c/nae */
604 rc |= (flags & EFLG_CF);
605 break;
606 case 2: /* z/e */
607 rc |= (flags & EFLG_ZF);
608 break;
609 case 3: /* be/na */
610 rc |= (flags & (EFLG_CF|EFLG_ZF));
611 break;
612 case 4: /* s */
613 rc |= (flags & EFLG_SF);
614 break;
615 case 5: /* p/pe */
616 rc |= (flags & EFLG_PF);
617 break;
618 case 7: /* le/ng */
619 rc |= (flags & EFLG_ZF);
620 /* fall through */
621 case 6: /* l/nge */
622 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
623 break;
624 }
625
626 /* Odd condition identifiers (lsb == 1) have inverted sense. */
627 return (!!rc ^ (condition & 1));
628}
629
3c118e24
AK		 630static void decode_register_operand(struct operand *op,
631 struct decode_cache *c,
3c118e24
AK		 632 int inhibit_bytereg)
633{
33615aa9 634 unsigned reg = c->modrm_reg;
9f1ef3f8 635 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 636
637 if (!(c->d & ModRM))
638 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 639 op->type = OP_REG;
640 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 641 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 642 op->val = *(u8 *)op->ptr;
643 op->bytes = 1;
644 } else {
33615aa9 645 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 646 op->bytes = c->op_bytes;
647 switch (op->bytes) {
648 case 2:
649 op->val = *(u16 *)op->ptr;
650 break;
651 case 4:
652 op->val = *(u32 *)op->ptr;
653 break;
654 case 8:
655 op->val = *(u64 *) op->ptr;
656 break;
657 }
658 }
659 op->orig_val = op->val;
660}
661
1c73ef66
AK		 662static int decode_modrm(struct x86_emulate_ctxt *ctxt,
663 struct x86_emulate_ops *ops)
664{
665 struct decode_cache *c = &ctxt->decode;
666 u8 sib;
667 int index_reg = 0, base_reg = 0, scale, rip_relative = 0;
668 int rc = 0;
669
670 if (c->rex_prefix) {
671 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
672 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
673 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
674 }
675
676 c->modrm = insn_fetch(u8, 1, c->eip);
677 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
678 c->modrm_reg |= (c->modrm & 0x38) >> 3;
679 c->modrm_rm |= (c->modrm & 0x07);
680 c->modrm_ea = 0;
681 c->use_modrm_ea = 1;
682
683 if (c->modrm_mod == 3) {
107d6d2e
AK		 684 c->modrm_ptr = decode_register(c->modrm_rm,
685 c->regs, c->d & ByteOp);
686 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 687 return rc;
688 }
689
690 if (c->ad_bytes == 2) {
691 unsigned bx = c->regs[VCPU_REGS_RBX];
692 unsigned bp = c->regs[VCPU_REGS_RBP];
693 unsigned si = c->regs[VCPU_REGS_RSI];
694 unsigned di = c->regs[VCPU_REGS_RDI];
695
696 /* 16-bit ModR/M decode. */
697 switch (c->modrm_mod) {
698 case 0:
699 if (c->modrm_rm == 6)
700 c->modrm_ea += insn_fetch(u16, 2, c->eip);
701 break;
702 case 1:
703 c->modrm_ea += insn_fetch(s8, 1, c->eip);
704 break;
705 case 2:
706 c->modrm_ea += insn_fetch(u16, 2, c->eip);
707 break;
708 }
709 switch (c->modrm_rm) {
710 case 0:
711 c->modrm_ea += bx + si;
712 break;
713 case 1:
714 c->modrm_ea += bx + di;
715 break;
716 case 2:
717 c->modrm_ea += bp + si;
718 break;
719 case 3:
720 c->modrm_ea += bp + di;
721 break;
722 case 4:
723 c->modrm_ea += si;
724 break;
725 case 5:
726 c->modrm_ea += di;
727 break;
728 case 6:
729 if (c->modrm_mod != 0)
730 c->modrm_ea += bp;
731 break;
732 case 7:
733 c->modrm_ea += bx;
734 break;
735 }
736 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
737 (c->modrm_rm == 6 && c->modrm_mod != 0))
738 if (!c->override_base)
739 c->override_base = &ctxt->ss_base;
740 c->modrm_ea = (u16)c->modrm_ea;
741 } else {
742 /* 32/64-bit ModR/M decode. */
743 switch (c->modrm_rm) {
744 case 4:
745 case 12:
746 sib = insn_fetch(u8, 1, c->eip);
747 index_reg |= (sib >> 3) & 7;
748 base_reg |= sib & 7;
749 scale = sib >> 6;
750
dc71d0f1
AK		 751 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
752 c->modrm_ea += insn_fetch(s32, 4, c->eip);
753 else
1c73ef66 754 c->modrm_ea += c->regs[base_reg];
dc71d0f1 755 if (index_reg != 4)
1c73ef66 756 c->modrm_ea += c->regs[index_reg] << scale;
1c73ef66
AK		 757 break;
758 case 5:
8684c0af 759 case 13:
1c73ef66
AK		 760 if (c->modrm_mod != 0)
761 c->modrm_ea += c->regs[c->modrm_rm];
762 else if (ctxt->mode == X86EMUL_MODE_PROT64)
763 rip_relative = 1;
764 break;
765 default:
766 c->modrm_ea += c->regs[c->modrm_rm];
767 break;
768 }
769 switch (c->modrm_mod) {
770 case 0:
771 if (c->modrm_rm == 5)
772 c->modrm_ea += insn_fetch(s32, 4, c->eip);
773 break;
774 case 1:
775 c->modrm_ea += insn_fetch(s8, 1, c->eip);
776 break;
777 case 2:
778 c->modrm_ea += insn_fetch(s32, 4, c->eip);
779 break;
780 }
781 }
782 if (rip_relative) {
783 c->modrm_ea += c->eip;
784 switch (c->d & SrcMask) {
785 case SrcImmByte:
786 c->modrm_ea += 1;
787 break;
788 case SrcImm:
789 if (c->d & ByteOp)
790 c->modrm_ea += 1;
791 else
792 if (c->op_bytes == 8)
793 c->modrm_ea += 4;
794 else
795 c->modrm_ea += c->op_bytes;
796 }
797 }
798done:
799 return rc;
800}
801
802static int decode_abs(struct x86_emulate_ctxt *ctxt,
803 struct x86_emulate_ops *ops)
804{
805 struct decode_cache *c = &ctxt->decode;
806 int rc = 0;
807
808 switch (c->ad_bytes) {
809 case 2:
810 c->modrm_ea = insn_fetch(u16, 2, c->eip);
811 break;
812 case 4:
813 c->modrm_ea = insn_fetch(u32, 4, c->eip);
814 break;
815 case 8:
816 c->modrm_ea = insn_fetch(u64, 8, c->eip);
817 break;
818 }
819done:
820 return rc;
821}
822
6aa8b732 823int
8b4caf66 824x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 825{
e4e03ded 826 struct decode_cache *c = &ctxt->decode;
6aa8b732 827 int rc = 0;
6aa8b732 828 int mode = ctxt->mode;
e09d082c 829 int def_op_bytes, def_ad_bytes, group;
6aa8b732
AK		 830
831 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 832
e4e03ded 833 memset(c, 0, sizeof(struct decode_cache));
ad312c7c
ZX		 834 c->eip = ctxt->vcpu->arch.rip;
835 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 836
837 switch (mode) {
838 case X86EMUL_MODE_REAL:
839 case X86EMUL_MODE_PROT16:
f21b8bf4 840 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 841 break;
842 case X86EMUL_MODE_PROT32:
f21b8bf4 843 def_op_bytes = def_ad_bytes = 4;
6aa8b732 844 break;
05b3e0c2 845#ifdef CONFIG_X86_64
6aa8b732 846 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 847 def_op_bytes = 4;
848 def_ad_bytes = 8;
6aa8b732
AK		 849 break;
850#endif
851 default:
852 return -1;
853 }
854
f21b8bf4
AK		 855 c->op_bytes = def_op_bytes;
856 c->ad_bytes = def_ad_bytes;
857
6aa8b732 858 /* Legacy prefixes. */
b4c6abfe 859 for (;;) {
e4e03ded 860 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 861 case 0x66: /* operand-size override */
f21b8bf4
AK		 862 /* switch between 2/4 bytes */
863 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 864 break;
865 case 0x67: /* address-size override */
866 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 867 /* switch between 4/8 bytes */
f21b8bf4 868 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 869 else
e4e03ded 870 /* switch between 2/4 bytes */
f21b8bf4 871 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732
AK		 872 break;
873 case 0x2e: /* CS override */
e4e03ded 874 c->override_base = &ctxt->cs_base;
6aa8b732
AK		 875 break;
876 case 0x3e: /* DS override */
e4e03ded 877 c->override_base = &ctxt->ds_base;
6aa8b732
AK		 878 break;
879 case 0x26: /* ES override */
e4e03ded 880 c->override_base = &ctxt->es_base;
6aa8b732
AK		 881 break;
882 case 0x64: /* FS override */
e4e03ded 883 c->override_base = &ctxt->fs_base;
6aa8b732
AK		 884 break;
885 case 0x65: /* GS override */
e4e03ded 886 c->override_base = &ctxt->gs_base;
6aa8b732
AK		 887 break;
888 case 0x36: /* SS override */
e4e03ded 889 c->override_base = &ctxt->ss_base;
6aa8b732 890 break;
b4c6abfe
LV		 891 case 0x40 ... 0x4f: /* REX */
892 if (mode != X86EMUL_MODE_PROT64)
893 goto done_prefixes;
33615aa9 894 c->rex_prefix = c->b;
b4c6abfe 895 continue;
6aa8b732 896 case 0xf0: /* LOCK */
e4e03ded 897 c->lock_prefix = 1;
6aa8b732 898 break;
ae6200ba 899 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 900 c->rep_prefix = REPNE_PREFIX;
901 break;
6aa8b732 902 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 903 c->rep_prefix = REPE_PREFIX;
6aa8b732 904 break;
6aa8b732
AK		 905 default:
906 goto done_prefixes;
907 }
b4c6abfe
LV		 908
909 /* Any legacy prefix after a REX prefix nullifies its effect. */
910
33615aa9 911 c->rex_prefix = 0;
6aa8b732
AK		 912 }
913
914done_prefixes:
915
916 /* REX prefix. */
1c73ef66 917 if (c->rex_prefix)
33615aa9 918 if (c->rex_prefix & 8)
e4e03ded 919 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 920
921 /* Opcode byte(s). */
e4e03ded
LV		 922 c->d = opcode_table[c->b];
923 if (c->d == 0) {
6aa8b732 924 /* Two-byte opcode? */
e4e03ded
LV		 925 if (c->b == 0x0f) {
926 c->twobyte = 1;
927 c->b = insn_fetch(u8, 1, c->eip);
928 c->d = twobyte_table[c->b];
6aa8b732 929 }
e09d082c 930 }
6aa8b732 931
e09d082c
AK		 932 if (c->d & Group) {
933 group = c->d & GroupMask;
934 c->modrm = insn_fetch(u8, 1, c->eip);
935 --c->eip;
936
937 group = (group << 3) + ((c->modrm >> 3) & 7);
938 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
939 c->d = group2_table[group];
940 else
941 c->d = group_table[group];
942 }
943
944 /* Unrecognised? */
945 if (c->d == 0) {
946 DPRINTF("Cannot emulate %02x\n", c->b);
947 return -1;
6aa8b732
AK		 948 }
949
6e3d5dfb
AK		 950 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
951 c->op_bytes = 8;
952
6aa8b732 953 /* ModRM and SIB bytes. */
1c73ef66
AK		 954 if (c->d & ModRM)
955 rc = decode_modrm(ctxt, ops);
956 else if (c->d & MemAbs)
957 rc = decode_abs(ctxt, ops);
958 if (rc)
959 goto done;
6aa8b732 960
c7e75a3d
AK		 961 if (!c->override_base)
962 c->override_base = &ctxt->ds_base;
963 if (mode == X86EMUL_MODE_PROT64 &&
964 c->override_base != &ctxt->fs_base &&
965 c->override_base != &ctxt->gs_base)
966 c->override_base = NULL;
967
968 if (c->override_base)
969 c->modrm_ea += *c->override_base;
970
971 if (c->ad_bytes != 8)
972 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 973 /*
974 * Decode and fetch the source operand: register, memory
975 * or immediate.
976 */
e4e03ded 977 switch (c->d & SrcMask) {
6aa8b732
AK		 978 case SrcNone:
979 break;
980 case SrcReg:
9f1ef3f8 981 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 982 break;
983 case SrcMem16:
e4e03ded 984 c->src.bytes = 2;
6aa8b732
AK		 985 goto srcmem_common;
986 case SrcMem32:
e4e03ded 987 c->src.bytes = 4;
6aa8b732
AK		 988 goto srcmem_common;
989 case SrcMem:
e4e03ded
LV		 990 c->src.bytes = (c->d & ByteOp) ? 1 :
991 c->op_bytes;
b85b9ee9 992 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 993 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 994 break;
d77c26fc 995 srcmem_common:
4e62417b
AJ		 996 /*
997 * For instructions with a ModR/M byte, switch to register
998 * access if Mod = 3.
999 */
e4e03ded
LV		 1000 if ((c->d & ModRM) && c->modrm_mod == 3) {
1001 c->src.type = OP_REG;
66b85505 1002 c->src.val = c->modrm_val;
107d6d2e 1003 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 1004 break;
1005 }
e4e03ded 1006 c->src.type = OP_MEM;
6aa8b732
AK		 1007 break;
1008 case SrcImm:
e4e03ded
LV		 1009 c->src.type = OP_IMM;
1010 c->src.ptr = (unsigned long *)c->eip;
1011 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1012 if (c->src.bytes == 8)
1013 c->src.bytes = 4;
6aa8b732 1014 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1015 switch (c->src.bytes) {
6aa8b732 1016 case 1:
e4e03ded 1017 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1018 break;
1019 case 2:
e4e03ded 1020 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1021 break;
1022 case 4:
e4e03ded 1023 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1024 break;
1025 }
1026 break;
1027 case SrcImmByte:
e4e03ded
LV		 1028 c->src.type = OP_IMM;
1029 c->src.ptr = (unsigned long *)c->eip;
1030 c->src.bytes = 1;
1031 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1032 break;
1033 }
1034
038e51de 1035 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1036 switch (c->d & DstMask) {
038e51de
AK		 1037 case ImplicitOps:
1038 /* Special instructions do their own operand decoding. */
8b4caf66 1039 return 0;
038e51de 1040 case DstReg:
9f1ef3f8 1041 decode_register_operand(&c->dst, c,
3c118e24 1042 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1043 break;
1044 case DstMem:
e4e03ded 1045 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1046 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1047 c->dst.type = OP_REG;
66b85505 1048 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1049 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1050 break;
1051 }
8b4caf66
LV		 1052 c->dst.type = OP_MEM;
1053 break;
1054 }
1055
1056done:
1057 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1058}
1059
8cdbd2c9
LV		 1060static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1061{
1062 struct decode_cache *c = &ctxt->decode;
1063
1064 c->dst.type = OP_MEM;
1065 c->dst.bytes = c->op_bytes;
1066 c->dst.val = c->src.val;
7a957275 1067 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
e4706772 1068 c->dst.ptr = (void *) register_address(c, ctxt->ss_base,
8cdbd2c9
LV		 1069 c->regs[VCPU_REGS_RSP]);
1070}
1071
1072static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1073 struct x86_emulate_ops *ops)
1074{
1075 struct decode_cache *c = &ctxt->decode;
1076 int rc;
1077
e4706772 1078 rc = ops->read_std(register_address(c, ctxt->ss_base,
8cdbd2c9
LV		 1079 c->regs[VCPU_REGS_RSP]),
1080 &c->dst.val, c->dst.bytes, ctxt->vcpu);
1081 if (rc != 0)
1082 return rc;
1083
7a957275 1084 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->dst.bytes);
8cdbd2c9
LV		 1085
1086 return 0;
1087}
1088
05f086f8 1089static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1090{
05f086f8 1091 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1092 switch (c->modrm_reg) {
1093 case 0: /* rol */
05f086f8 1094 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1095 break;
1096 case 1: /* ror */
05f086f8 1097 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1098 break;
1099 case 2: /* rcl */
05f086f8 1100 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1101 break;
1102 case 3: /* rcr */
05f086f8 1103 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1104 break;
1105 case 4: /* sal/shl */
1106 case 6: /* sal/shl */
05f086f8 1107 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1108 break;
1109 case 5: /* shr */
05f086f8 1110 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1111 break;
1112 case 7: /* sar */
05f086f8 1113 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1114 break;
1115 }
1116}
1117
1118static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1119 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1120{
1121 struct decode_cache *c = &ctxt->decode;
1122 int rc = 0;
1123
1124 switch (c->modrm_reg) {
1125 case 0 ... 1: /* test */
05f086f8 1126 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1127 break;
1128 case 2: /* not */
1129 c->dst.val = ~c->dst.val;
1130 break;
1131 case 3: /* neg */
05f086f8 1132 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1133 break;
1134 default:
1135 DPRINTF("Cannot emulate %02x\n", c->b);
1136 rc = X86EMUL_UNHANDLEABLE;
1137 break;
1138 }
8cdbd2c9
LV		 1139 return rc;
1140}
1141
1142static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1143 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1144{
1145 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1146
1147 switch (c->modrm_reg) {
1148 case 0: /* inc */
05f086f8 1149 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1150 break;
1151 case 1: /* dec */
05f086f8 1152 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1153 break;
1154 case 4: /* jmp abs */
fd60754e 1155 c->eip = c->src.val;
8cdbd2c9
LV		 1156 break;
1157 case 6: /* push */
fd60754e 1158 emulate_push(ctxt);
8cdbd2c9 1159 break;
8cdbd2c9
LV		 1160 }
1161 return 0;
1162}
1163
1164static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1165 struct x86_emulate_ops *ops,
e8d8d7fe 1166 unsigned long memop)
8cdbd2c9
LV		 1167{
1168 struct decode_cache *c = &ctxt->decode;
1169 u64 old, new;
1170 int rc;
1171
e8d8d7fe 1172 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
8cdbd2c9
LV		 1173 if (rc != 0)
1174 return rc;
1175
1176 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1177 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1178
1179 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1180 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1181 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1182
1183 } else {
1184 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1185 (u32) c->regs[VCPU_REGS_RBX];
1186
e8d8d7fe 1187 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
8cdbd2c9
LV		 1188 if (rc != 0)
1189 return rc;
05f086f8 1190 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1191 }
1192 return 0;
1193}
1194
1195static inline int writeback(struct x86_emulate_ctxt *ctxt,
1196 struct x86_emulate_ops *ops)
1197{
1198 int rc;
1199 struct decode_cache *c = &ctxt->decode;
1200
1201 switch (c->dst.type) {
1202 case OP_REG:
1203 /* The 4-byte case *is* correct:
1204 * in 64-bit mode we zero-extend.
1205 */
1206 switch (c->dst.bytes) {
1207 case 1:
1208 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1209 break;
1210 case 2:
1211 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1212 break;
1213 case 4:
1214 *c->dst.ptr = (u32)c->dst.val;
1215 break; /* 64b: zero-ext */
1216 case 8:
1217 *c->dst.ptr = c->dst.val;
1218 break;
1219 }
1220 break;
1221 case OP_MEM:
1222 if (c->lock_prefix)
1223 rc = ops->cmpxchg_emulated(
1224 (unsigned long)c->dst.ptr,
1225 &c->dst.orig_val,
1226 &c->dst.val,
1227 c->dst.bytes,
1228 ctxt->vcpu);
1229 else
1230 rc = ops->write_emulated(
1231 (unsigned long)c->dst.ptr,
1232 &c->dst.val,
1233 c->dst.bytes,
1234 ctxt->vcpu);
1235 if (rc != 0)
1236 return rc;
a01af5ec
LV		 1237 break;
1238 case OP_NONE:
1239 /* no writeback */
1240 break;
8cdbd2c9
LV		 1241 default:
1242 break;
1243 }
1244 return 0;
1245}
1246
8b4caf66 1247int
1be3aa47 1248x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 1249{
e8d8d7fe 1250 unsigned long memop = 0;
8b4caf66 1251 u64 msr_data;
3427318f 1252 unsigned long saved_eip = 0;
8b4caf66 1253 struct decode_cache *c = &ctxt->decode;
1be3aa47 1254 int rc = 0;
8b4caf66 1255
3427318f
LV		 1256 /* Shadow copy of register state. Committed on successful emulation.
1257 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1258 * modify them.
1259 */
1260
ad312c7c 1261 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f
LV		 1262 saved_eip = c->eip;
1263
c7e75a3d 1264 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
e8d8d7fe 1265 memop = c->modrm_ea;
8b4caf66 1266
b9fa9d6b
AK		 1267 if (c->rep_prefix && (c->d & String)) {
1268 /* All REP prefixes have the same first termination condition */
1269 if (c->regs[VCPU_REGS_RCX] == 0) {
ad312c7c 1270 ctxt->vcpu->arch.rip = c->eip;
b9fa9d6b
AK		 1271 goto done;
1272 }
1273 /* The second termination condition only applies for REPE
1274 * and REPNE. Test if the repeat string operation prefix is
1275 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1276 * corresponding termination condition according to:
1277 * - if REPE/REPZ and ZF = 0 then done
1278 * - if REPNE/REPNZ and ZF = 1 then done
1279 */
1280 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1281 (c->b == 0xae) || (c->b == 0xaf)) {
1282 if ((c->rep_prefix == REPE_PREFIX) &&
1283 ((ctxt->eflags & EFLG_ZF) == 0)) {
ad312c7c 1284 ctxt->vcpu->arch.rip = c->eip;
b9fa9d6b
AK		 1285 goto done;
1286 }
1287 if ((c->rep_prefix == REPNE_PREFIX) &&
1288 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
ad312c7c 1289 ctxt->vcpu->arch.rip = c->eip;
b9fa9d6b
AK		 1290 goto done;
1291 }
1292 }
1293 c->regs[VCPU_REGS_RCX]--;
ad312c7c 1294 c->eip = ctxt->vcpu->arch.rip;
b9fa9d6b
AK		 1295 }
1296
8b4caf66 1297 if (c->src.type == OP_MEM) {
e8d8d7fe 1298 c->src.ptr = (unsigned long *)memop;
8b4caf66 1299 c->src.val = 0;
d77c26fc
MD		 1300 rc = ops->read_emulated((unsigned long)c->src.ptr,
1301 &c->src.val,
1302 c->src.bytes,
1303 ctxt->vcpu);
1304 if (rc != 0)
8b4caf66
LV		 1305 goto done;
1306 c->src.orig_val = c->src.val;
1307 }
1308
1309 if ((c->d & DstMask) == ImplicitOps)
1310 goto special_insn;
1311
1312
1313 if (c->dst.type == OP_MEM) {
e8d8d7fe 1314 c->dst.ptr = (unsigned long *)memop;
8b4caf66
LV		 1315 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1316 c->dst.val = 0;
e4e03ded
LV		 1317 if (c->d & BitOp) {
1318 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1319
e4e03ded
LV		 1320 c->dst.ptr = (void *)c->dst.ptr +
1321 (c->src.val & mask) / 8;
038e51de 1322 }
e4e03ded
LV		 1323 if (!(c->d & Mov) &&
1324 /* optimisation - avoid slow emulated read */
1325 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1326 &c->dst.val,
1327 c->dst.bytes, ctxt->vcpu)) != 0))
038e51de 1328 goto done;
038e51de 1329 }
e4e03ded 1330 c->dst.orig_val = c->dst.val;
038e51de 1331
018a98db
AK		 1332special_insn:
1333
e4e03ded 1334 if (c->twobyte)
6aa8b732
AK		 1335 goto twobyte_insn;
1336
e4e03ded 1337 switch (c->b) {
6aa8b732
AK		 1338 case 0x00 ... 0x05:
1339 add: /* add */
05f086f8 1340 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1341 break;
1342 case 0x08 ... 0x0d:
1343 or: /* or */
05f086f8 1344 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1345 break;
1346 case 0x10 ... 0x15:
1347 adc: /* adc */
05f086f8 1348 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1349 break;
1350 case 0x18 ... 0x1d:
1351 sbb: /* sbb */
05f086f8 1352 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1353 break;
19eb938e 1354 case 0x20 ... 0x23:
6aa8b732 1355 and: /* and */
05f086f8 1356 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732 1357 break;
19eb938e 1358 case 0x24: /* and al imm8 */
e4e03ded
LV		 1359 c->dst.type = OP_REG;
1360 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1361 c->dst.val = *(u8 *)c->dst.ptr;
1362 c->dst.bytes = 1;
1363 c->dst.orig_val = c->dst.val;
19eb938e
NK		 1364 goto and;
1365 case 0x25: /* and ax imm16, or eax imm32 */
e4e03ded
LV		 1366 c->dst.type = OP_REG;
1367 c->dst.bytes = c->op_bytes;
1368 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1369 if (c->op_bytes == 2)
1370 c->dst.val = *(u16 *)c->dst.ptr;
19eb938e 1371 else
e4e03ded
LV		 1372 c->dst.val = *(u32 *)c->dst.ptr;
1373 c->dst.orig_val = c->dst.val;
19eb938e 1374 goto and;
6aa8b732
AK		 1375 case 0x28 ... 0x2d:
1376 sub: /* sub */
05f086f8 1377 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1378 break;
1379 case 0x30 ... 0x35:
1380 xor: /* xor */
05f086f8 1381 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1382 break;
1383 case 0x38 ... 0x3d:
1384 cmp: /* cmp */
05f086f8 1385 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 1386 break;
33615aa9
AK		 1387 case 0x40 ... 0x47: /* inc r16/r32 */
1388 emulate_1op("inc", c->dst, ctxt->eflags);
1389 break;
1390 case 0x48 ... 0x4f: /* dec r16/r32 */
1391 emulate_1op("dec", c->dst, ctxt->eflags);
1392 break;
1393 case 0x50 ... 0x57: /* push reg */
1394 c->dst.type = OP_MEM;
1395 c->dst.bytes = c->op_bytes;
1396 c->dst.val = c->src.val;
7a957275 1397 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
33615aa9
AK		 1398 -c->op_bytes);
1399 c->dst.ptr = (void *) register_address(
e4706772 1400 c, ctxt->ss_base, c->regs[VCPU_REGS_RSP]);
33615aa9
AK		 1401 break;
1402 case 0x58 ... 0x5f: /* pop reg */
1403 pop_instruction:
e4706772 1404 if ((rc = ops->read_std(register_address(c, ctxt->ss_base,
33615aa9
AK		 1405 c->regs[VCPU_REGS_RSP]), c->dst.ptr,
1406 c->op_bytes, ctxt->vcpu)) != 0)
1407 goto done;
1408
7a957275 1409 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
33615aa9
AK		 1410 c->op_bytes);
1411 c->dst.type = OP_NONE; /* Disable writeback. */
1412 break;
6aa8b732 1413 case 0x63: /* movsxd */
8b4caf66 1414 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1415 goto cannot_emulate;
e4e03ded 1416 c->dst.val = (s32) c->src.val;
6aa8b732 1417 break;
91ed7a0e 1418 case 0x68: /* push imm */
018a98db 1419 case 0x6a: /* push imm8 */
018a98db
AK		 1420 emulate_push(ctxt);
1421 break;
1422 case 0x6c: /* insb */
1423 case 0x6d: /* insw/insd */
1424 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1425 1,
1426 (c->d & ByteOp) ? 1 : c->op_bytes,
1427 c->rep_prefix ?
e4706772 1428 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1429 (ctxt->eflags & EFLG_DF),
e4706772 1430 register_address(c, ctxt->es_base,
018a98db
AK		 1431 c->regs[VCPU_REGS_RDI]),
1432 c->rep_prefix,
1433 c->regs[VCPU_REGS_RDX]) == 0) {
1434 c->eip = saved_eip;
1435 return -1;
1436 }
1437 return 0;
1438 case 0x6e: /* outsb */
1439 case 0x6f: /* outsw/outsd */
1440 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1441 0,
1442 (c->d & ByteOp) ? 1 : c->op_bytes,
1443 c->rep_prefix ?
e4706772 1444 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1445 (ctxt->eflags & EFLG_DF),
e4706772 1446 register_address(c, c->override_base ?
018a98db
AK		 1447 *c->override_base :
1448 ctxt->ds_base,
1449 c->regs[VCPU_REGS_RSI]),
1450 c->rep_prefix,
1451 c->regs[VCPU_REGS_RDX]) == 0) {
1452 c->eip = saved_eip;
1453 return -1;
1454 }
1455 return 0;
1456 case 0x70 ... 0x7f: /* jcc (short) */ {
1457 int rel = insn_fetch(s8, 1, c->eip);
1458
1459 if (test_cc(c->b, ctxt->eflags))
7a957275 1460 jmp_rel(c, rel);
018a98db
AK		 1461 break;
1462 }
6aa8b732 1463 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 1464 switch (c->modrm_reg) {
6aa8b732
AK		 1465 case 0:
1466 goto add;
1467 case 1:
1468 goto or;
1469 case 2:
1470 goto adc;
1471 case 3:
1472 goto sbb;
1473 case 4:
1474 goto and;
1475 case 5:
1476 goto sub;
1477 case 6:
1478 goto xor;
1479 case 7:
1480 goto cmp;
1481 }
1482 break;
1483 case 0x84 ... 0x85:
05f086f8 1484 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1485 break;
1486 case 0x86 ... 0x87: /* xchg */
b13354f8 1487 xchg:
6aa8b732 1488 /* Write back the register source. */
e4e03ded 1489 switch (c->dst.bytes) {
6aa8b732 1490 case 1:
e4e03ded 1491 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 1492 break;
1493 case 2:
e4e03ded 1494 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 1495 break;
1496 case 4:
e4e03ded 1497 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 1498 break; /* 64b reg: zero-extend */
1499 case 8:
e4e03ded 1500 *c->src.ptr = c->dst.val;
6aa8b732
AK		 1501 break;
1502 }
1503 /*
1504 * Write back the memory destination with implicit LOCK
1505 * prefix.
1506 */
e4e03ded
LV		 1507 c->dst.val = c->src.val;
1508 c->lock_prefix = 1;
6aa8b732 1509 break;
6aa8b732 1510 case 0x88 ... 0x8b: /* mov */
7de75248 1511 goto mov;
38d5bc6d
GT		 1512 case 0x8c: { /* mov r/m, sreg */
1513 struct kvm_segment segreg;
1514
1515 if (c->modrm_reg <= 5)
1516 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
1517 else {
1518 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
1519 c->modrm);
1520 goto cannot_emulate;
1521 }
1522 c->dst.val = segreg.selector;
1523 break;
1524 }
7e0b54b1 1525 case 0x8d: /* lea r16/r32, m */
f9b7aab3 1526 c->dst.val = c->modrm_ea;
7e0b54b1 1527 break;
4257198a
GT		 1528 case 0x8e: { /* mov seg, r/m16 */
1529 uint16_t sel;
1530 int type_bits;
1531 int err;
1532
1533 sel = c->src.val;
1534 if (c->modrm_reg <= 5) {
1535 type_bits = (c->modrm_reg == 1) ? 9 : 1;
1536 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
1537 type_bits, c->modrm_reg);
1538 } else {
1539 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
1540 c->modrm);
1541 goto cannot_emulate;
1542 }
1543
1544 if (err < 0)
1545 goto cannot_emulate;
1546
1547 c->dst.type = OP_NONE; /* Disable writeback. */
1548 break;
1549 }
6aa8b732 1550 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 1551 rc = emulate_grp1a(ctxt, ops);
1552 if (rc != 0)
6aa8b732 1553 goto done;
6aa8b732 1554 break;
b13354f8
MG		 1555 case 0x90: /* nop / xchg r8,rax */
1556 if (!(c->rex_prefix & 1)) { /* nop */
1557 c->dst.type = OP_NONE;
1558 break;
1559 }
1560 case 0x91 ... 0x97: /* xchg reg,rax */
1561 c->src.type = c->dst.type = OP_REG;
1562 c->src.bytes = c->dst.bytes = c->op_bytes;
1563 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
1564 c->src.val = *(c->src.ptr);
1565 goto xchg;
fd2a7608 1566 case 0x9c: /* pushf */
05f086f8 1567 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 1568 emulate_push(ctxt);
1569 break;
535eabcf 1570 case 0x9d: /* popf */
05f086f8 1571 c->dst.ptr = (unsigned long *) &ctxt->eflags;
535eabcf 1572 goto pop_instruction;
018a98db
AK		 1573 case 0xa0 ... 0xa1: /* mov */
1574 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1575 c->dst.val = c->src.val;
1576 break;
1577 case 0xa2 ... 0xa3: /* mov */
1578 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1579 break;
6aa8b732 1580 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 1581 c->dst.type = OP_MEM;
1582 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1583 c->dst.ptr = (unsigned long *)register_address(c,
e4e03ded
LV		 1584 ctxt->es_base,
1585 c->regs[VCPU_REGS_RDI]);
e4706772 1586 if ((rc = ops->read_emulated(register_address(c,
e4e03ded
LV		 1587 c->override_base ? *c->override_base :
1588 ctxt->ds_base,
1589 c->regs[VCPU_REGS_RSI]),
1590 &c->dst.val,
1591 c->dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1592 goto done;
7a957275 1593 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1594 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1595 : c->dst.bytes);
7a957275 1596 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1597 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1598 : c->dst.bytes);
6aa8b732
AK		 1599 break;
1600 case 0xa6 ... 0xa7: /* cmps */
d7e5117a
GT		 1601 c->src.type = OP_NONE; /* Disable writeback. */
1602 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1603 c->src.ptr = (unsigned long *)register_address(c,
d7e5117a
GT		 1604 c->override_base ? *c->override_base :
1605 ctxt->ds_base,
1606 c->regs[VCPU_REGS_RSI]);
1607 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1608 &c->src.val,
1609 c->src.bytes,
1610 ctxt->vcpu)) != 0)
1611 goto done;
1612
1613 c->dst.type = OP_NONE; /* Disable writeback. */
1614 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1615 c->dst.ptr = (unsigned long *)register_address(c,
d7e5117a
GT		 1616 ctxt->es_base,
1617 c->regs[VCPU_REGS_RDI]);
1618 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1619 &c->dst.val,
1620 c->dst.bytes,
1621 ctxt->vcpu)) != 0)
1622 goto done;
1623
1624 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1625
1626 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1627
7a957275 1628 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
d7e5117a
GT		 1629 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1630 : c->src.bytes);
7a957275 1631 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
d7e5117a
GT		 1632 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1633 : c->dst.bytes);
1634
1635 break;
6aa8b732 1636 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 1637 c->dst.type = OP_MEM;
1638 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1639 c->dst.ptr = (unsigned long *)register_address(c,
a7e6c88a
SY		 1640 ctxt->es_base,
1641 c->regs[VCPU_REGS_RDI]);
e4e03ded 1642 c->dst.val = c->regs[VCPU_REGS_RAX];
7a957275 1643 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1644 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1645 : c->dst.bytes);
6aa8b732
AK		 1646 break;
1647 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 1648 c->dst.type = OP_REG;
1649 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1650 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
e4706772 1651 if ((rc = ops->read_emulated(register_address(c,
a7e6c88a
SY		 1652 c->override_base ? *c->override_base :
1653 ctxt->ds_base,
1654 c->regs[VCPU_REGS_RSI]),
1655 &c->dst.val,
1656 c->dst.bytes,
1657 ctxt->vcpu)) != 0)
6aa8b732 1658 goto done;
7a957275 1659 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1660 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1661 : c->dst.bytes);
6aa8b732
AK		 1662 break;
1663 case 0xae ... 0xaf: /* scas */
1664 DPRINTF("Urk! I don't handle SCAS.\n");
1665 goto cannot_emulate;
615ac125
GT		 1666 case 0xb8: /* mov r, imm */
1667 goto mov;
018a98db
AK		 1668 case 0xc0 ... 0xc1:
1669 emulate_grp2(ctxt);
1670 break;
111de5d6
AK		 1671 case 0xc3: /* ret */
1672 c->dst.ptr = &c->eip;
1673 goto pop_instruction;
018a98db
AK		 1674 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1675 mov:
1676 c->dst.val = c->src.val;
1677 break;
1678 case 0xd0 ... 0xd1: /* Grp2 */
1679 c->src.val = 1;
1680 emulate_grp2(ctxt);
1681 break;
1682 case 0xd2 ... 0xd3: /* Grp2 */
1683 c->src.val = c->regs[VCPU_REGS_RCX];
1684 emulate_grp2(ctxt);
1685 break;
1a52e051
NK		 1686 case 0xe8: /* call (near) */ {
1687 long int rel;
e4e03ded 1688 switch (c->op_bytes) {
1a52e051 1689 case 2:
e4e03ded 1690 rel = insn_fetch(s16, 2, c->eip);
1a52e051
NK		 1691 break;
1692 case 4:
e4e03ded 1693 rel = insn_fetch(s32, 4, c->eip);
1a52e051 1694 break;
1a52e051
NK		 1695 default:
1696 DPRINTF("Call: Invalid op_bytes\n");
1697 goto cannot_emulate;
1698 }
e4e03ded 1699 c->src.val = (unsigned long) c->eip;
7a957275 1700 jmp_rel(c, rel);
e4e03ded 1701 c->op_bytes = c->ad_bytes;
8cdbd2c9
LV		 1702 emulate_push(ctxt);
1703 break;
1a52e051
NK		 1704 }
1705 case 0xe9: /* jmp rel */
954cd36f
GT		 1706 goto jmp;
1707 case 0xea: /* jmp far */ {
1708 uint32_t eip;
1709 uint16_t sel;
1710
1711 switch (c->op_bytes) {
1712 case 2:
1713 eip = insn_fetch(u16, 2, c->eip);
1714 break;
1715 case 4:
1716 eip = insn_fetch(u32, 4, c->eip);
1717 break;
1718 default:
1719 DPRINTF("jmp far: Invalid op_bytes\n");
1720 goto cannot_emulate;
1721 }
1722 sel = insn_fetch(u16, 2, c->eip);
1723 if (kvm_load_segment_descriptor(ctxt->vcpu, sel, 9, VCPU_SREG_CS) < 0) {
1724 DPRINTF("jmp far: Failed to load CS descriptor\n");
1725 goto cannot_emulate;
1726 }
1727
1728 c->eip = eip;
1729 break;
1730 }
1731 case 0xeb:
1732 jmp: /* jmp rel short */
7a957275 1733 jmp_rel(c, c->src.val);
a01af5ec 1734 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 1735 break;
111de5d6 1736 case 0xf4: /* hlt */
ad312c7c 1737 ctxt->vcpu->arch.halt_request = 1;
111de5d6
AK		 1738 goto done;
1739 case 0xf5: /* cmc */
1740 /* complement carry flag from eflags reg */
1741 ctxt->eflags ^= EFLG_CF;
1742 c->dst.type = OP_NONE; /* Disable writeback. */
1743 break;
018a98db
AK		 1744 case 0xf6 ... 0xf7: /* Grp3 */
1745 rc = emulate_grp3(ctxt, ops);
1746 if (rc != 0)
1747 goto done;
1748 break;
111de5d6
AK		 1749 case 0xf8: /* clc */
1750 ctxt->eflags &= ~EFLG_CF;
1751 c->dst.type = OP_NONE; /* Disable writeback. */
1752 break;
1753 case 0xfa: /* cli */
1754 ctxt->eflags &= ~X86_EFLAGS_IF;
1755 c->dst.type = OP_NONE; /* Disable writeback. */
1756 break;
1757 case 0xfb: /* sti */
1758 ctxt->eflags |= X86_EFLAGS_IF;
1759 c->dst.type = OP_NONE; /* Disable writeback. */
1760 break;
018a98db
AK		 1761 case 0xfe ... 0xff: /* Grp4/Grp5 */
1762 rc = emulate_grp45(ctxt, ops);
1763 if (rc != 0)
1764 goto done;
1765 break;
6aa8b732 1766 }
018a98db
AK		 1767
1768writeback:
1769 rc = writeback(ctxt, ops);
1770 if (rc != 0)
1771 goto done;
1772
1773 /* Commit shadow register state. */
ad312c7c
ZX		 1774 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
1775 ctxt->vcpu->arch.rip = c->eip;
018a98db
AK		 1776
1777done:
1778 if (rc == X86EMUL_UNHANDLEABLE) {
1779 c->eip = saved_eip;
1780 return -1;
1781 }
1782 return 0;
6aa8b732
AK		 1783
1784twobyte_insn:
e4e03ded 1785 switch (c->b) {
6aa8b732 1786 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 1787 switch (c->modrm_reg) {
6aa8b732
AK		 1788 u16 size;
1789 unsigned long address;
1790
aca7f966 1791 case 0: /* vmcall */
e4e03ded 1792 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 1793 goto cannot_emulate;
1794
7aa81cc0
AL		 1795 rc = kvm_fix_hypercall(ctxt->vcpu);
1796 if (rc)
1797 goto done;
1798
33e3885d
AK		 1799 /* Let the processor re-execute the fixed hypercall */
1800 c->eip = ctxt->vcpu->arch.rip;
16286d08
AK		 1801 /* Disable writeback. */
1802 c->dst.type = OP_NONE;
aca7f966 1803 break;
6aa8b732 1804 case 2: /* lgdt */
e4e03ded
LV		 1805 rc = read_descriptor(ctxt, ops, c->src.ptr,
1806 &size, &address, c->op_bytes);
6aa8b732
AK		 1807 if (rc)
1808 goto done;
1809 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 1810 /* Disable writeback. */
1811 c->dst.type = OP_NONE;
6aa8b732 1812 break;
aca7f966 1813 case 3: /* lidt/vmmcall */
e4e03ded 1814 if (c->modrm_mod == 3 && c->modrm_rm == 1) {
7aa81cc0
AL		 1815 rc = kvm_fix_hypercall(ctxt->vcpu);
1816 if (rc)
1817 goto done;
1818 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1819 } else {
e4e03ded 1820 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 1821 &size, &address,
e4e03ded 1822 c->op_bytes);
aca7f966
AL		 1823 if (rc)
1824 goto done;
1825 realmode_lidt(ctxt->vcpu, size, address);
1826 }
16286d08
AK		 1827 /* Disable writeback. */
1828 c->dst.type = OP_NONE;
6aa8b732
AK		 1829 break;
1830 case 4: /* smsw */
16286d08
AK		 1831 c->dst.bytes = 2;
1832 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
6aa8b732
AK		 1833 break;
1834 case 6: /* lmsw */
16286d08
AK		 1835 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
1836 &ctxt->eflags);
dc7457ea 1837 c->dst.type = OP_NONE;
6aa8b732
AK		 1838 break;
1839 case 7: /* invlpg*/
e8d8d7fe 1840 emulate_invlpg(ctxt->vcpu, memop);
16286d08
AK		 1841 /* Disable writeback. */
1842 c->dst.type = OP_NONE;
6aa8b732
AK		 1843 break;
1844 default:
1845 goto cannot_emulate;
1846 }
1847 break;
018a98db
AK		 1848 case 0x06:
1849 emulate_clts(ctxt->vcpu);
1850 c->dst.type = OP_NONE;
1851 break;
1852 case 0x08: /* invd */
1853 case 0x09: /* wbinvd */
1854 case 0x0d: /* GrpP (prefetch) */
1855 case 0x18: /* Grp16 (prefetch/nop) */
1856 c->dst.type = OP_NONE;
1857 break;
1858 case 0x20: /* mov cr, reg */
1859 if (c->modrm_mod != 3)
1860 goto cannot_emulate;
1861 c->regs[c->modrm_rm] =
1862 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1863 c->dst.type = OP_NONE; /* no writeback */
1864 break;
6aa8b732 1865 case 0x21: /* mov from dr to reg */
e4e03ded 1866 if (c->modrm_mod != 3)
6aa8b732 1867 goto cannot_emulate;
8cdbd2c9 1868 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 1869 if (rc)
1870 goto cannot_emulate;
1871 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1872 break;
018a98db
AK		 1873 case 0x22: /* mov reg, cr */
1874 if (c->modrm_mod != 3)
1875 goto cannot_emulate;
1876 realmode_set_cr(ctxt->vcpu,
1877 c->modrm_reg, c->modrm_val, &ctxt->eflags);
1878 c->dst.type = OP_NONE;
1879 break;
6aa8b732 1880 case 0x23: /* mov from reg to dr */
e4e03ded 1881 if (c->modrm_mod != 3)
6aa8b732 1882 goto cannot_emulate;
e4e03ded
LV		 1883 rc = emulator_set_dr(ctxt, c->modrm_reg,
1884 c->regs[c->modrm_rm]);
a01af5ec
LV		 1885 if (rc)
1886 goto cannot_emulate;
1887 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1888 break;
018a98db
AK		 1889 case 0x30:
1890 /* wrmsr */
1891 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1892 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1893 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
1894 if (rc) {
c1a5d4f9 1895 kvm_inject_gp(ctxt->vcpu, 0);
ad312c7c 1896 c->eip = ctxt->vcpu->arch.rip;
018a98db
AK		 1897 }
1898 rc = X86EMUL_CONTINUE;
1899 c->dst.type = OP_NONE;
1900 break;
1901 case 0x32:
1902 /* rdmsr */
1903 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
1904 if (rc) {
c1a5d4f9 1905 kvm_inject_gp(ctxt->vcpu, 0);
ad312c7c 1906 c->eip = ctxt->vcpu->arch.rip;
018a98db
AK		 1907 } else {
1908 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
1909 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
1910 }
1911 rc = X86EMUL_CONTINUE;
1912 c->dst.type = OP_NONE;
1913 break;
6aa8b732 1914 case 0x40 ... 0x4f: /* cmov */
e4e03ded 1915 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 1916 if (!test_cc(c->b, ctxt->eflags))
1917 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1918 break;
018a98db
AK		 1919 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1920 long int rel;
1921
1922 switch (c->op_bytes) {
1923 case 2:
1924 rel = insn_fetch(s16, 2, c->eip);
1925 break;
1926 case 4:
1927 rel = insn_fetch(s32, 4, c->eip);
1928 break;
1929 case 8:
1930 rel = insn_fetch(s64, 8, c->eip);
1931 break;
1932 default:
1933 DPRINTF("jnz: Invalid op_bytes\n");
1934 goto cannot_emulate;
1935 }
1936 if (test_cc(c->b, ctxt->eflags))
7a957275 1937 jmp_rel(c, rel);
018a98db
AK		 1938 c->dst.type = OP_NONE;
1939 break;
1940 }
7de75248
NK		 1941 case 0xa3:
1942 bt: /* bt */
e4f8e039 1943 c->dst.type = OP_NONE;
e4e03ded
LV		 1944 /* only subword offset */
1945 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1946 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248
NK		 1947 break;
1948 case 0xab:
1949 bts: /* bts */
e4e03ded
LV		 1950 /* only subword offset */
1951 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1952 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 1953 break;
6aa8b732
AK		 1954 case 0xb0 ... 0xb1: /* cmpxchg */
1955 /*
1956 * Save real source value, then compare EAX against
1957 * destination.
1958 */
e4e03ded
LV		 1959 c->src.orig_val = c->src.val;
1960 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 1961 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1962 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 1963 /* Success: write back to memory. */
e4e03ded 1964 c->dst.val = c->src.orig_val;
6aa8b732
AK		 1965 } else {
1966 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 1967 c->dst.type = OP_REG;
1968 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 1969 }
1970 break;
6aa8b732
AK		 1971 case 0xb3:
1972 btr: /* btr */
e4e03ded
LV		 1973 /* only subword offset */
1974 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1975 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 1976 break;
6aa8b732 1977 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 1978 c->dst.bytes = c->op_bytes;
1979 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
1980 : (u16) c->src.val;
6aa8b732 1981 break;
6aa8b732 1982 case 0xba: /* Grp8 */
e4e03ded 1983 switch (c->modrm_reg & 3) {
6aa8b732
AK		 1984 case 0:
1985 goto bt;
1986 case 1:
1987 goto bts;
1988 case 2:
1989 goto btr;
1990 case 3:
1991 goto btc;
1992 }
1993 break;
7de75248
NK		 1994 case 0xbb:
1995 btc: /* btc */
e4e03ded
LV		 1996 /* only subword offset */
1997 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1998 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 1999 break;
6aa8b732 2000 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 2001 c->dst.bytes = c->op_bytes;
2002 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
2003 (s16) c->src.val;
6aa8b732 2004 break;
a012e65a 2005 case 0xc3: /* movnti */
e4e03ded
LV		 2006 c->dst.bytes = c->op_bytes;
2007 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
2008 (u64) c->src.val;
a012e65a 2009 break;
6aa8b732 2010 case 0xc7: /* Grp9 (cmpxchg8b) */
e8d8d7fe 2011 rc = emulate_grp9(ctxt, ops, memop);
8cdbd2c9
LV		 2012 if (rc != 0)
2013 goto done;
018a98db 2014 c->dst.type = OP_NONE;
8cdbd2c9 2015 break;
6aa8b732
AK		 2016 }
2017 goto writeback;
2018
2019cannot_emulate:
e4e03ded 2020 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 2021 c->eip = saved_eip;
6aa8b732
AK		 2022 return -1;
2023}
Linux kernel - Deliverables
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