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KVM: x86 emulator: reduce duplication in one operand emulation thunks
[deliverable/linux.git] / arch / x86 / kvm / x86_emulate.c
CommitLineData
6aa8b732
AK		 1/******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
5fdbf976 29#include "kvm_cache_regs.h"
6aa8b732
AK		 30#define DPRINTF(x...) do {} while (0)
31#endif
6aa8b732 32#include <linux/module.h>
edf88417 33#include <asm/kvm_x86_emulate.h>
6aa8b732
AK		 34
35/*
36 * Opcode effective-address decode tables.
37 * Note that we only emulate instructions that have at least one memory
38 * operand (excluding implicit stack references). We assume that stack
39 * references and instruction fetches will never occur in special memory
40 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
41 * not be handled.
42 */
43
44/* Operand sizes: 8-bit operands or specified/overridden size. */
45#define ByteOp (1<<0) /* 8-bit operands. */
46/* Destination operand type. */
47#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
48#define DstReg (2<<1) /* Register operand. */
49#define DstMem (3<<1) /* Memory operand. */
9c9fddd0
GT		 50#define DstAcc (4<<1) /* Destination Accumulator */
51#define DstMask (7<<1)
6aa8b732 52/* Source operand type. */
9c9fddd0
GT		 53#define SrcNone (0<<4) /* No source operand. */
54#define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
55#define SrcReg (1<<4) /* Register operand. */
56#define SrcMem (2<<4) /* Memory operand. */
57#define SrcMem16 (3<<4) /* Memory operand (16-bit). */
58#define SrcMem32 (4<<4) /* Memory operand (32-bit). */
59#define SrcImm (5<<4) /* Immediate operand. */
60#define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
61#define SrcMask (7<<4)
6aa8b732 62/* Generic ModRM decode. */
9c9fddd0 63#define ModRM (1<<7)
6aa8b732 64/* Destination is only written; never read. */
9c9fddd0
GT		 65#define Mov (1<<8)
66#define BitOp (1<<9)
67#define MemAbs (1<<10) /* Memory operand is absolute displacement */
68#define String (1<<12) /* String instruction (rep capable) */
69#define Stack (1<<13) /* Stack instruction (push/pop) */
e09d082c
AK		 70#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
71#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
72#define GroupMask 0xff /* Group number stored in bits 0:7 */
6aa8b732 73
43bb19cd 74enum {
1d6ad207 75 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 76 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
43bb19cd
AK		 77};
78
c7e75a3d 79static u16 opcode_table[256] = {
6aa8b732
AK		 80 /* 0x00 - 0x07 */
81 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
82 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
291fd39b 83 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, 0, 0,
6aa8b732
AK		 84 /* 0x08 - 0x0F */
85 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
86 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
87 0, 0, 0, 0,
88 /* 0x10 - 0x17 */
89 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
90 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
91 0, 0, 0, 0,
92 /* 0x18 - 0x1F */
93 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
94 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
95 0, 0, 0, 0,
96 /* 0x20 - 0x27 */
97 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
98 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
aa3a816b 99 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
6aa8b732
AK		 100 /* 0x28 - 0x2F */
101 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
102 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
103 0, 0, 0, 0,
104 /* 0x30 - 0x37 */
105 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
106 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
107 0, 0, 0, 0,
108 /* 0x38 - 0x3F */
109 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
110 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
8a9fee67
GT		 111 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
112 0, 0,
d77a2507 113 /* 0x40 - 0x47 */
33615aa9 114 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 115 /* 0x48 - 0x4F */
33615aa9 116 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 117 /* 0x50 - 0x57 */
6e3d5dfb
AK		 118 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
119 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 120 /* 0x58 - 0x5F */
6e3d5dfb
AK		 121 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
122 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 123 /* 0x60 - 0x67 */
6aa8b732 124 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 125 0, 0, 0, 0,
126 /* 0x68 - 0x6F */
91ed7a0e 127 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
e70669ab
LV		 128 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
129 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4
NK		 130 /* 0x70 - 0x77 */
131 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
132 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
133 /* 0x78 - 0x7F */
134 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
135 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732 136 /* 0x80 - 0x87 */
1d6ad207
AK		 137 Group | Group1_80, Group | Group1_81,
138 Group | Group1_82, Group | Group1_83,
6aa8b732
AK		 139 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
140 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
141 /* 0x88 - 0x8F */
142 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
143 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
38d5bc6d 144 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
4257198a 145 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
b13354f8
MG		 146 /* 0x90 - 0x97 */
147 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
148 /* 0x98 - 0x9F */
6e3d5dfb 149 0, 0, 0, 0, ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 150 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 151 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
152 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
b9fa9d6b
AK		 153 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
154 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 155 /* 0xA8 - 0xAF */
b9fa9d6b
AK		 156 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
157 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
158 ByteOp | ImplicitOps | String, ImplicitOps | String,
a5e2e82b
MG		 159 /* 0xB0 - 0xB7 */
160 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
161 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
162 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
163 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
164 /* 0xB8 - 0xBF */
165 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
166 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
167 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
168 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
6aa8b732 169 /* 0xC0 - 0xC7 */
d9413cd7 170 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 171 0, ImplicitOps | Stack, 0, 0,
d9413cd7 172 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732
AK		 173 /* 0xC8 - 0xCF */
174 0, 0, 0, 0, 0, 0, 0, 0,
175 /* 0xD0 - 0xD7 */
176 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
177 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
178 0, 0, 0, 0,
179 /* 0xD8 - 0xDF */
180 0, 0, 0, 0, 0, 0, 0, 0,
098c937b 181 /* 0xE0 - 0xE7 */
a6a3034c
MG		 182 0, 0, 0, 0,
183 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
184 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
098c937b 185 /* 0xE8 - 0xEF */
954cd36f
GT		 186 ImplicitOps | Stack, SrcImm | ImplicitOps,
187 ImplicitOps, SrcImmByte | ImplicitOps,
a6a3034c
MG		 188 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
189 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
6aa8b732
AK		 190 /* 0xF0 - 0xF7 */
191 0, 0, 0, 0,
7d858a19 192 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 193 /* 0xF8 - 0xFF */
b284be57 194 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fb4616f4 195 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
6aa8b732
AK		 196};
197
038e51de 198static u16 twobyte_table[256] = {
6aa8b732 199 /* 0x00 - 0x0F */
d95058a1 200 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
651a3e29 201 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 202 /* 0x10 - 0x1F */
203 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
204 /* 0x20 - 0x2F */
205 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
206 0, 0, 0, 0, 0, 0, 0, 0,
207 /* 0x30 - 0x3F */
35f3f286 208 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 209 /* 0x40 - 0x47 */
210 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
211 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
212 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
213 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
214 /* 0x48 - 0x4F */
215 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
216 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
217 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
218 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
219 /* 0x50 - 0x5F */
220 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
221 /* 0x60 - 0x6F */
222 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
223 /* 0x70 - 0x7F */
224 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
225 /* 0x80 - 0x8F */
bbe9abbd
NK		 226 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
227 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
228 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
229 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 230 /* 0x90 - 0x9F */
231 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
232 /* 0xA0 - 0xA7 */
038e51de 233 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732 234 /* 0xA8 - 0xAF */
2a7c5b8b 235 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, ModRM, 0,
6aa8b732
AK		 236 /* 0xB0 - 0xB7 */
237 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 238 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 239 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
240 DstReg | SrcMem16 | ModRM | Mov,
241 /* 0xB8 - 0xBF */
038e51de 242 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 243 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
244 DstReg | SrcMem16 | ModRM | Mov,
245 /* 0xC0 - 0xCF */
a012e65a
SY		 246 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
247 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 248 /* 0xD0 - 0xDF */
249 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
250 /* 0xE0 - 0xEF */
251 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
252 /* 0xF0 - 0xFF */
253 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
254};
255
e09d082c 256static u16 group_table[] = {
1d6ad207
AK		 257 [Group1_80*8] =
258 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
259 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
260 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
261 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
262 [Group1_81*8] =
263 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
264 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
265 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
266 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
267 [Group1_82*8] =
268 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
269 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
270 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
271 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
272 [Group1_83*8] =
273 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
274 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
275 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
276 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 277 [Group1A*8] =
278 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 279 [Group3_Byte*8] =
280 ByteOp | SrcImm | DstMem | ModRM, 0,
281 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
282 0, 0, 0, 0,
283 [Group3*8] =
41afa025 284 DstMem | SrcImm | ModRM, 0,
6eb06cb2 285 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
7d858a19 286 0, 0, 0, 0,
fd60754e
AK		 287 [Group4*8] =
288 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
289 0, 0, 0, 0, 0, 0,
290 [Group5*8] =
d19292e4
MG		 291 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
292 SrcMem | ModRM | Stack, 0,
ef46f18e 293 SrcMem | ModRM | Stack, 0, SrcMem | ModRM | Stack, 0,
d95058a1
AK		 294 [Group7*8] =
295 0, 0, ModRM | SrcMem, ModRM | SrcMem,
16286d08
AK		 296 SrcNone | ModRM | DstMem | Mov, 0,
297 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
e09d082c
AK		 298};
299
300static u16 group2_table[] = {
d95058a1 301 [Group7*8] =
16286d08
AK		 302 SrcNone | ModRM, 0, 0, 0,
303 SrcNone | ModRM | DstMem | Mov, 0,
304 SrcMem16 | ModRM | Mov, 0,
e09d082c
AK		 305};
306
6aa8b732
AK		 307/* EFLAGS bit definitions. */
308#define EFLG_OF (1<<11)
309#define EFLG_DF (1<<10)
310#define EFLG_SF (1<<7)
311#define EFLG_ZF (1<<6)
312#define EFLG_AF (1<<4)
313#define EFLG_PF (1<<2)
314#define EFLG_CF (1<<0)
315
316/*
317 * Instruction emulation:
318 * Most instructions are emulated directly via a fragment of inline assembly
319 * code. This allows us to save/restore EFLAGS and thus very easily pick up
320 * any modified flags.
321 */
322
05b3e0c2 323#if defined(CONFIG_X86_64)
6aa8b732
AK		 324#define _LO32 "k" /* force 32-bit operand */
325#define _STK "%%rsp" /* stack pointer */
326#elif defined(__i386__)
327#define _LO32 "" /* force 32-bit operand */
328#define _STK "%%esp" /* stack pointer */
329#endif
330
331/*
332 * These EFLAGS bits are restored from saved value during emulation, and
333 * any changes are written back to the saved value after emulation.
334 */
335#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
336
337/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 338#define _PRE_EFLAGS(_sav, _msk, _tmp) \
339 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
340 "movl %"_sav",%"_LO32 _tmp"; " \
341 "push %"_tmp"; " \
342 "push %"_tmp"; " \
343 "movl %"_msk",%"_LO32 _tmp"; " \
344 "andl %"_LO32 _tmp",("_STK"); " \
345 "pushf; " \
346 "notl %"_LO32 _tmp"; " \
347 "andl %"_LO32 _tmp",("_STK"); " \
348 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
349 "pop %"_tmp"; " \
350 "orl %"_LO32 _tmp",("_STK"); " \
351 "popf; " \
352 "pop %"_sav"; "
6aa8b732
AK		 353
354/* After executing instruction: write-back necessary bits in EFLAGS. */
355#define _POST_EFLAGS(_sav, _msk, _tmp) \
356 /* _sav |= EFLAGS & _msk; */ \
357 "pushf; " \
358 "pop %"_tmp"; " \
359 "andl %"_msk",%"_LO32 _tmp"; " \
360 "orl %"_LO32 _tmp",%"_sav"; "
361
dda96d8f
AK		 362#ifdef CONFIG_X86_64
363#define ON64(x) x
364#else
365#define ON64(x)
366#endif
367
6aa8b732
AK		 368/* Raw emulation: instruction has two explicit operands. */
369#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
370 do { \
371 unsigned long _tmp; \
372 \
373 switch ((_dst).bytes) { \
374 case 2: \
375 __asm__ __volatile__ ( \
d77c26fc 376 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 377 _op"w %"_wx"3,%1; " \
d77c26fc 378 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 379 : "=m" (_eflags), "=m" ((_dst).val), \
380 "=&r" (_tmp) \
d77c26fc 381 : _wy ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 382 break; \
383 case 4: \
384 __asm__ __volatile__ ( \
d77c26fc 385 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 386 _op"l %"_lx"3,%1; " \
d77c26fc 387 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 388 : "=m" (_eflags), "=m" ((_dst).val), \
389 "=&r" (_tmp) \
d77c26fc 390 : _ly ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 391 break; \
392 case 8: \
393 __emulate_2op_8byte(_op, _src, _dst, \
394 _eflags, _qx, _qy); \
395 break; \
396 } \
397 } while (0)
398
399#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
400 do { \
77cd337f 401 unsigned long __tmp; \
d77c26fc 402 switch ((_dst).bytes) { \
6aa8b732
AK		 403 case 1: \
404 __asm__ __volatile__ ( \
d77c26fc 405 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 406 _op"b %"_bx"3,%1; " \
d77c26fc 407 _POST_EFLAGS("0", "4", "2") \
6aa8b732 408 : "=m" (_eflags), "=m" ((_dst).val), \
77cd337f 409 "=&r" (__tmp) \
d77c26fc 410 : _by ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 411 break; \
412 default: \
413 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
414 _wx, _wy, _lx, _ly, _qx, _qy); \
415 break; \
416 } \
417 } while (0)
418
419/* Source operand is byte-sized and may be restricted to just %cl. */
420#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
421 __emulate_2op(_op, _src, _dst, _eflags, \
422 "b", "c", "b", "c", "b", "c", "b", "c")
423
424/* Source operand is byte, word, long or quad sized. */
425#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
426 __emulate_2op(_op, _src, _dst, _eflags, \
427 "b", "q", "w", "r", _LO32, "r", "", "r")
428
429/* Source operand is word, long or quad sized. */
430#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
431 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
432 "w", "r", _LO32, "r", "", "r")
433
dda96d8f 434#define __emulate_1op(_op, _dst, _eflags, _suffix) \
6aa8b732
AK		 435 do { \
436 unsigned long _tmp; \
437 \
dda96d8f
AK		 438 __asm__ __volatile__ ( \
439 _PRE_EFLAGS("0", "3", "2") \
440 _op _suffix " %1; " \
441 _POST_EFLAGS("0", "3", "2") \
442 : "=m" (_eflags), "+m" ((_dst).val), \
443 "=&r" (_tmp) \
444 : "i" (EFLAGS_MASK)); \
445 } while (0)
446
447/* Instruction has only one explicit operand (no source operand). */
448#define emulate_1op(_op, _dst, _eflags) \
449 do { \
d77c26fc 450 switch ((_dst).bytes) { \
dda96d8f
AK		 451 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
452 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
453 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
454 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
6aa8b732
AK		 455 } \
456 } while (0)
457
458/* Emulate an instruction with quadword operands (x86/64 only). */
05b3e0c2 459#if defined(CONFIG_X86_64)
6aa8b732
AK		 460#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
461 do { \
462 __asm__ __volatile__ ( \
d77c26fc 463 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 464 _op"q %"_qx"3,%1; " \
d77c26fc 465 _POST_EFLAGS("0", "4", "2") \
6aa8b732 466 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
d77c26fc 467 : _qy ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 468 } while (0)
469
6aa8b732
AK		 470#elif defined(__i386__)
471#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
6aa8b732
AK		 472#endif /* __i386__ */
473
474/* Fetch next part of the instruction being emulated. */
475#define insn_fetch(_type, _size, _eip) \
476({ unsigned long _x; \
62266869 477 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
d77c26fc 478 if (rc != 0) \
6aa8b732
AK		 479 goto done; \
480 (_eip) += (_size); \
481 (_type)_x; \
482})
483
ddcb2885
HH		 484static inline unsigned long ad_mask(struct decode_cache *c)
485{
486 return (1UL << (c->ad_bytes << 3)) - 1;
487}
488
6aa8b732 489/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 490static inline unsigned long
491address_mask(struct decode_cache *c, unsigned long reg)
492{
493 if (c->ad_bytes == sizeof(unsigned long))
494 return reg;
495 else
496 return reg & ad_mask(c);
497}
498
499static inline unsigned long
500register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
501{
502 return base + address_mask(c, reg);
503}
504
7a957275
HH		 505static inline void
506register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
507{
508 if (c->ad_bytes == sizeof(unsigned long))
509 *reg += inc;
510 else
511 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
512}
6aa8b732 513
7a957275
HH		 514static inline void jmp_rel(struct decode_cache *c, int rel)
515{
516 register_address_increment(c, &c->eip, rel);
517}
098c937b 518
7a5b56df
AK		 519static void set_seg_override(struct decode_cache *c, int seg)
520{
521 c->has_seg_override = true;
522 c->seg_override = seg;
523}
524
525static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
526{
527 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
528 return 0;
529
530 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
531}
532
533static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
534 struct decode_cache *c)
535{
536 if (!c->has_seg_override)
537 return 0;
538
539 return seg_base(ctxt, c->seg_override);
540}
541
542static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
543{
544 return seg_base(ctxt, VCPU_SREG_ES);
545}
546
547static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
548{
549 return seg_base(ctxt, VCPU_SREG_SS);
550}
551
62266869
AK		 552static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
553 struct x86_emulate_ops *ops,
554 unsigned long linear, u8 *dest)
555{
556 struct fetch_cache *fc = &ctxt->decode.fetch;
557 int rc;
558 int size;
559
560 if (linear < fc->start || linear >= fc->end) {
561 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
562 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
563 if (rc)
564 return rc;
565 fc->start = linear;
566 fc->end = linear + size;
567 }
568 *dest = fc->data[linear - fc->start];
569 return 0;
570}
571
572static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
573 struct x86_emulate_ops *ops,
574 unsigned long eip, void *dest, unsigned size)
575{
576 int rc = 0;
577
578 eip += ctxt->cs_base;
579 while (size--) {
580 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
581 if (rc)
582 return rc;
583 }
584 return 0;
585}
586
1e3c5cb0
RR		 587/*
588 * Given the 'reg' portion of a ModRM byte, and a register block, return a
589 * pointer into the block that addresses the relevant register.
590 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
591 */
592static void *decode_register(u8 modrm_reg, unsigned long *regs,
593 int highbyte_regs)
6aa8b732
AK		 594{
595 void *p;
596
597 p = &regs[modrm_reg];
598 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
599 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
600 return p;
601}
602
603static int read_descriptor(struct x86_emulate_ctxt *ctxt,
604 struct x86_emulate_ops *ops,
605 void *ptr,
606 u16 *size, unsigned long *address, int op_bytes)
607{
608 int rc;
609
610 if (op_bytes == 2)
611 op_bytes = 3;
612 *address = 0;
cebff02b
LV		 613 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
614 ctxt->vcpu);
6aa8b732
AK		 615 if (rc)
616 return rc;
cebff02b
LV		 617 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
618 ctxt->vcpu);
6aa8b732
AK		 619 return rc;
620}
621
bbe9abbd
NK		 622static int test_cc(unsigned int condition, unsigned int flags)
623{
624 int rc = 0;
625
626 switch ((condition & 15) >> 1) {
627 case 0: /* o */
628 rc |= (flags & EFLG_OF);
629 break;
630 case 1: /* b/c/nae */
631 rc |= (flags & EFLG_CF);
632 break;
633 case 2: /* z/e */
634 rc |= (flags & EFLG_ZF);
635 break;
636 case 3: /* be/na */
637 rc |= (flags & (EFLG_CF|EFLG_ZF));
638 break;
639 case 4: /* s */
640 rc |= (flags & EFLG_SF);
641 break;
642 case 5: /* p/pe */
643 rc |= (flags & EFLG_PF);
644 break;
645 case 7: /* le/ng */
646 rc |= (flags & EFLG_ZF);
647 /* fall through */
648 case 6: /* l/nge */
649 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
650 break;
651 }
652
653 /* Odd condition identifiers (lsb == 1) have inverted sense. */
654 return (!!rc ^ (condition & 1));
655}
656
3c118e24
AK		 657static void decode_register_operand(struct operand *op,
658 struct decode_cache *c,
3c118e24
AK		 659 int inhibit_bytereg)
660{
33615aa9 661 unsigned reg = c->modrm_reg;
9f1ef3f8 662 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 663
664 if (!(c->d & ModRM))
665 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 666 op->type = OP_REG;
667 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 668 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 669 op->val = *(u8 *)op->ptr;
670 op->bytes = 1;
671 } else {
33615aa9 672 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 673 op->bytes = c->op_bytes;
674 switch (op->bytes) {
675 case 2:
676 op->val = *(u16 *)op->ptr;
677 break;
678 case 4:
679 op->val = *(u32 *)op->ptr;
680 break;
681 case 8:
682 op->val = *(u64 *) op->ptr;
683 break;
684 }
685 }
686 op->orig_val = op->val;
687}
688
1c73ef66
AK		 689static int decode_modrm(struct x86_emulate_ctxt *ctxt,
690 struct x86_emulate_ops *ops)
691{
692 struct decode_cache *c = &ctxt->decode;
693 u8 sib;
f5b4edcd 694 int index_reg = 0, base_reg = 0, scale;
1c73ef66
AK		 695 int rc = 0;
696
697 if (c->rex_prefix) {
698 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
699 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
700 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
701 }
702
703 c->modrm = insn_fetch(u8, 1, c->eip);
704 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
705 c->modrm_reg |= (c->modrm & 0x38) >> 3;
706 c->modrm_rm |= (c->modrm & 0x07);
707 c->modrm_ea = 0;
708 c->use_modrm_ea = 1;
709
710 if (c->modrm_mod == 3) {
107d6d2e
AK		 711 c->modrm_ptr = decode_register(c->modrm_rm,
712 c->regs, c->d & ByteOp);
713 c->modrm_val = *(unsigned long *)c->modrm_ptr;
1c73ef66
AK		 714 return rc;
715 }
716
717 if (c->ad_bytes == 2) {
718 unsigned bx = c->regs[VCPU_REGS_RBX];
719 unsigned bp = c->regs[VCPU_REGS_RBP];
720 unsigned si = c->regs[VCPU_REGS_RSI];
721 unsigned di = c->regs[VCPU_REGS_RDI];
722
723 /* 16-bit ModR/M decode. */
724 switch (c->modrm_mod) {
725 case 0:
726 if (c->modrm_rm == 6)
727 c->modrm_ea += insn_fetch(u16, 2, c->eip);
728 break;
729 case 1:
730 c->modrm_ea += insn_fetch(s8, 1, c->eip);
731 break;
732 case 2:
733 c->modrm_ea += insn_fetch(u16, 2, c->eip);
734 break;
735 }
736 switch (c->modrm_rm) {
737 case 0:
738 c->modrm_ea += bx + si;
739 break;
740 case 1:
741 c->modrm_ea += bx + di;
742 break;
743 case 2:
744 c->modrm_ea += bp + si;
745 break;
746 case 3:
747 c->modrm_ea += bp + di;
748 break;
749 case 4:
750 c->modrm_ea += si;
751 break;
752 case 5:
753 c->modrm_ea += di;
754 break;
755 case 6:
756 if (c->modrm_mod != 0)
757 c->modrm_ea += bp;
758 break;
759 case 7:
760 c->modrm_ea += bx;
761 break;
762 }
763 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
764 (c->modrm_rm == 6 && c->modrm_mod != 0))
7a5b56df
AK		 765 if (!c->has_seg_override)
766 set_seg_override(c, VCPU_SREG_SS);
1c73ef66
AK		 767 c->modrm_ea = (u16)c->modrm_ea;
768 } else {
769 /* 32/64-bit ModR/M decode. */
84411d85 770 if ((c->modrm_rm & 7) == 4) {
1c73ef66
AK		 771 sib = insn_fetch(u8, 1, c->eip);
772 index_reg |= (sib >> 3) & 7;
773 base_reg |= sib & 7;
774 scale = sib >> 6;
775
dc71d0f1
AK		 776 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
777 c->modrm_ea += insn_fetch(s32, 4, c->eip);
778 else
1c73ef66 779 c->modrm_ea += c->regs[base_reg];
dc71d0f1 780 if (index_reg != 4)
1c73ef66 781 c->modrm_ea += c->regs[index_reg] << scale;
84411d85
AK		 782 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
783 if (ctxt->mode == X86EMUL_MODE_PROT64)
f5b4edcd 784 c->rip_relative = 1;
84411d85 785 } else
1c73ef66 786 c->modrm_ea += c->regs[c->modrm_rm];
1c73ef66
AK		 787 switch (c->modrm_mod) {
788 case 0:
789 if (c->modrm_rm == 5)
790 c->modrm_ea += insn_fetch(s32, 4, c->eip);
791 break;
792 case 1:
793 c->modrm_ea += insn_fetch(s8, 1, c->eip);
794 break;
795 case 2:
796 c->modrm_ea += insn_fetch(s32, 4, c->eip);
797 break;
798 }
799 }
1c73ef66
AK		 800done:
801 return rc;
802}
803
804static int decode_abs(struct x86_emulate_ctxt *ctxt,
805 struct x86_emulate_ops *ops)
806{
807 struct decode_cache *c = &ctxt->decode;
808 int rc = 0;
809
810 switch (c->ad_bytes) {
811 case 2:
812 c->modrm_ea = insn_fetch(u16, 2, c->eip);
813 break;
814 case 4:
815 c->modrm_ea = insn_fetch(u32, 4, c->eip);
816 break;
817 case 8:
818 c->modrm_ea = insn_fetch(u64, 8, c->eip);
819 break;
820 }
821done:
822 return rc;
823}
824
6aa8b732 825int
8b4caf66 826x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 827{
e4e03ded 828 struct decode_cache *c = &ctxt->decode;
6aa8b732 829 int rc = 0;
6aa8b732 830 int mode = ctxt->mode;
e09d082c 831 int def_op_bytes, def_ad_bytes, group;
6aa8b732
AK		 832
833 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 834
e4e03ded 835 memset(c, 0, sizeof(struct decode_cache));
5fdbf976 836 c->eip = kvm_rip_read(ctxt->vcpu);
7a5b56df 837 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
ad312c7c 838 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 839
840 switch (mode) {
841 case X86EMUL_MODE_REAL:
842 case X86EMUL_MODE_PROT16:
f21b8bf4 843 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 844 break;
845 case X86EMUL_MODE_PROT32:
f21b8bf4 846 def_op_bytes = def_ad_bytes = 4;
6aa8b732 847 break;
05b3e0c2 848#ifdef CONFIG_X86_64
6aa8b732 849 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 850 def_op_bytes = 4;
851 def_ad_bytes = 8;
6aa8b732
AK		 852 break;
853#endif
854 default:
855 return -1;
856 }
857
f21b8bf4
AK		 858 c->op_bytes = def_op_bytes;
859 c->ad_bytes = def_ad_bytes;
860
6aa8b732 861 /* Legacy prefixes. */
b4c6abfe 862 for (;;) {
e4e03ded 863 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 864 case 0x66: /* operand-size override */
f21b8bf4
AK		 865 /* switch between 2/4 bytes */
866 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 867 break;
868 case 0x67: /* address-size override */
869 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 870 /* switch between 4/8 bytes */
f21b8bf4 871 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 872 else
e4e03ded 873 /* switch between 2/4 bytes */
f21b8bf4 874 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732 875 break;
7a5b56df 876 case 0x26: /* ES override */
6aa8b732 877 case 0x2e: /* CS override */
7a5b56df 878 case 0x36: /* SS override */
6aa8b732 879 case 0x3e: /* DS override */
7a5b56df 880 set_seg_override(c, (c->b >> 3) & 3);
6aa8b732
AK		 881 break;
882 case 0x64: /* FS override */
6aa8b732 883 case 0x65: /* GS override */
7a5b56df 884 set_seg_override(c, c->b & 7);
6aa8b732 885 break;
b4c6abfe
LV		 886 case 0x40 ... 0x4f: /* REX */
887 if (mode != X86EMUL_MODE_PROT64)
888 goto done_prefixes;
33615aa9 889 c->rex_prefix = c->b;
b4c6abfe 890 continue;
6aa8b732 891 case 0xf0: /* LOCK */
e4e03ded 892 c->lock_prefix = 1;
6aa8b732 893 break;
ae6200ba 894 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 895 c->rep_prefix = REPNE_PREFIX;
896 break;
6aa8b732 897 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 898 c->rep_prefix = REPE_PREFIX;
6aa8b732 899 break;
6aa8b732
AK		 900 default:
901 goto done_prefixes;
902 }
b4c6abfe
LV		 903
904 /* Any legacy prefix after a REX prefix nullifies its effect. */
905
33615aa9 906 c->rex_prefix = 0;
6aa8b732
AK		 907 }
908
909done_prefixes:
910
911 /* REX prefix. */
1c73ef66 912 if (c->rex_prefix)
33615aa9 913 if (c->rex_prefix & 8)
e4e03ded 914 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 915
916 /* Opcode byte(s). */
e4e03ded
LV		 917 c->d = opcode_table[c->b];
918 if (c->d == 0) {
6aa8b732 919 /* Two-byte opcode? */
e4e03ded
LV		 920 if (c->b == 0x0f) {
921 c->twobyte = 1;
922 c->b = insn_fetch(u8, 1, c->eip);
923 c->d = twobyte_table[c->b];
6aa8b732 924 }
e09d082c 925 }
6aa8b732 926
e09d082c
AK		 927 if (c->d & Group) {
928 group = c->d & GroupMask;
929 c->modrm = insn_fetch(u8, 1, c->eip);
930 --c->eip;
931
932 group = (group << 3) + ((c->modrm >> 3) & 7);
933 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
934 c->d = group2_table[group];
935 else
936 c->d = group_table[group];
937 }
938
939 /* Unrecognised? */
940 if (c->d == 0) {
941 DPRINTF("Cannot emulate %02x\n", c->b);
942 return -1;
6aa8b732
AK		 943 }
944
6e3d5dfb
AK		 945 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
946 c->op_bytes = 8;
947
6aa8b732 948 /* ModRM and SIB bytes. */
1c73ef66
AK		 949 if (c->d & ModRM)
950 rc = decode_modrm(ctxt, ops);
951 else if (c->d & MemAbs)
952 rc = decode_abs(ctxt, ops);
953 if (rc)
954 goto done;
6aa8b732 955
7a5b56df
AK		 956 if (!c->has_seg_override)
957 set_seg_override(c, VCPU_SREG_DS);
c7e75a3d 958
7a5b56df
AK		 959 if (!(!c->twobyte && c->b == 0x8d))
960 c->modrm_ea += seg_override_base(ctxt, c);
c7e75a3d
AK		 961
962 if (c->ad_bytes != 8)
963 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 964 /*
965 * Decode and fetch the source operand: register, memory
966 * or immediate.
967 */
e4e03ded 968 switch (c->d & SrcMask) {
6aa8b732
AK		 969 case SrcNone:
970 break;
971 case SrcReg:
9f1ef3f8 972 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 973 break;
974 case SrcMem16:
e4e03ded 975 c->src.bytes = 2;
6aa8b732
AK		 976 goto srcmem_common;
977 case SrcMem32:
e4e03ded 978 c->src.bytes = 4;
6aa8b732
AK		 979 goto srcmem_common;
980 case SrcMem:
e4e03ded
LV		 981 c->src.bytes = (c->d & ByteOp) ? 1 :
982 c->op_bytes;
b85b9ee9 983 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 984 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 985 break;
d77c26fc 986 srcmem_common:
4e62417b
AJ		 987 /*
988 * For instructions with a ModR/M byte, switch to register
989 * access if Mod = 3.
990 */
e4e03ded
LV		 991 if ((c->d & ModRM) && c->modrm_mod == 3) {
992 c->src.type = OP_REG;
66b85505 993 c->src.val = c->modrm_val;
107d6d2e 994 c->src.ptr = c->modrm_ptr;
4e62417b
AJ		 995 break;
996 }
e4e03ded 997 c->src.type = OP_MEM;
6aa8b732
AK		 998 break;
999 case SrcImm:
e4e03ded
LV		 1000 c->src.type = OP_IMM;
1001 c->src.ptr = (unsigned long *)c->eip;
1002 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1003 if (c->src.bytes == 8)
1004 c->src.bytes = 4;
6aa8b732 1005 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1006 switch (c->src.bytes) {
6aa8b732 1007 case 1:
e4e03ded 1008 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1009 break;
1010 case 2:
e4e03ded 1011 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1012 break;
1013 case 4:
e4e03ded 1014 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1015 break;
1016 }
1017 break;
1018 case SrcImmByte:
e4e03ded
LV		 1019 c->src.type = OP_IMM;
1020 c->src.ptr = (unsigned long *)c->eip;
1021 c->src.bytes = 1;
1022 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1023 break;
1024 }
1025
038e51de 1026 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1027 switch (c->d & DstMask) {
038e51de
AK		 1028 case ImplicitOps:
1029 /* Special instructions do their own operand decoding. */
8b4caf66 1030 return 0;
038e51de 1031 case DstReg:
9f1ef3f8 1032 decode_register_operand(&c->dst, c,
3c118e24 1033 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1034 break;
1035 case DstMem:
e4e03ded 1036 if ((c->d & ModRM) && c->modrm_mod == 3) {
89c69638 1037 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4e03ded 1038 c->dst.type = OP_REG;
66b85505 1039 c->dst.val = c->dst.orig_val = c->modrm_val;
107d6d2e 1040 c->dst.ptr = c->modrm_ptr;
4e62417b
AJ		 1041 break;
1042 }
8b4caf66
LV		 1043 c->dst.type = OP_MEM;
1044 break;
9c9fddd0
GT		 1045 case DstAcc:
1046 c->dst.type = OP_REG;
1047 c->dst.bytes = c->op_bytes;
1048 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1049 switch (c->op_bytes) {
1050 case 1:
1051 c->dst.val = *(u8 *)c->dst.ptr;
1052 break;
1053 case 2:
1054 c->dst.val = *(u16 *)c->dst.ptr;
1055 break;
1056 case 4:
1057 c->dst.val = *(u32 *)c->dst.ptr;
1058 break;
1059 }
1060 c->dst.orig_val = c->dst.val;
1061 break;
8b4caf66
LV		 1062 }
1063
f5b4edcd
AK		 1064 if (c->rip_relative)
1065 c->modrm_ea += c->eip;
1066
8b4caf66
LV		 1067done:
1068 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1069}
1070
8cdbd2c9
LV		 1071static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1072{
1073 struct decode_cache *c = &ctxt->decode;
1074
1075 c->dst.type = OP_MEM;
1076 c->dst.bytes = c->op_bytes;
1077 c->dst.val = c->src.val;
7a957275 1078 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
7a5b56df 1079 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1080 c->regs[VCPU_REGS_RSP]);
1081}
1082
1083static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1084 struct x86_emulate_ops *ops)
1085{
1086 struct decode_cache *c = &ctxt->decode;
1087 int rc;
1088
7a5b56df 1089 rc = ops->read_std(register_address(c, ss_base(ctxt),
8cdbd2c9
LV		 1090 c->regs[VCPU_REGS_RSP]),
1091 &c->dst.val, c->dst.bytes, ctxt->vcpu);
1092 if (rc != 0)
1093 return rc;
1094
7a957275 1095 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->dst.bytes);
8cdbd2c9
LV		 1096
1097 return 0;
1098}
1099
05f086f8 1100static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1101{
05f086f8 1102 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1103 switch (c->modrm_reg) {
1104 case 0: /* rol */
05f086f8 1105 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1106 break;
1107 case 1: /* ror */
05f086f8 1108 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1109 break;
1110 case 2: /* rcl */
05f086f8 1111 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1112 break;
1113 case 3: /* rcr */
05f086f8 1114 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1115 break;
1116 case 4: /* sal/shl */
1117 case 6: /* sal/shl */
05f086f8 1118 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1119 break;
1120 case 5: /* shr */
05f086f8 1121 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1122 break;
1123 case 7: /* sar */
05f086f8 1124 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1125 break;
1126 }
1127}
1128
1129static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1130 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1131{
1132 struct decode_cache *c = &ctxt->decode;
1133 int rc = 0;
1134
1135 switch (c->modrm_reg) {
1136 case 0 ... 1: /* test */
05f086f8 1137 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1138 break;
1139 case 2: /* not */
1140 c->dst.val = ~c->dst.val;
1141 break;
1142 case 3: /* neg */
05f086f8 1143 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1144 break;
1145 default:
1146 DPRINTF("Cannot emulate %02x\n", c->b);
1147 rc = X86EMUL_UNHANDLEABLE;
1148 break;
1149 }
8cdbd2c9
LV		 1150 return rc;
1151}
1152
1153static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1154 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1155{
1156 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1157
1158 switch (c->modrm_reg) {
1159 case 0: /* inc */
05f086f8 1160 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1161 break;
1162 case 1: /* dec */
05f086f8 1163 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9 1164 break;
d19292e4
MG		 1165 case 2: /* call near abs */ {
1166 long int old_eip;
1167 old_eip = c->eip;
1168 c->eip = c->src.val;
1169 c->src.val = old_eip;
1170 emulate_push(ctxt);
1171 break;
1172 }
8cdbd2c9 1173 case 4: /* jmp abs */
fd60754e 1174 c->eip = c->src.val;
8cdbd2c9
LV		 1175 break;
1176 case 6: /* push */
fd60754e 1177 emulate_push(ctxt);
8cdbd2c9 1178 break;
8cdbd2c9
LV		 1179 }
1180 return 0;
1181}
1182
1183static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1184 struct x86_emulate_ops *ops,
e8d8d7fe 1185 unsigned long memop)
8cdbd2c9
LV		 1186{
1187 struct decode_cache *c = &ctxt->decode;
1188 u64 old, new;
1189 int rc;
1190
e8d8d7fe 1191 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
8cdbd2c9
LV		 1192 if (rc != 0)
1193 return rc;
1194
1195 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1196 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1197
1198 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1199 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1200 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1201
1202 } else {
1203 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1204 (u32) c->regs[VCPU_REGS_RBX];
1205
e8d8d7fe 1206 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
8cdbd2c9
LV		 1207 if (rc != 0)
1208 return rc;
05f086f8 1209 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1210 }
1211 return 0;
1212}
1213
1214static inline int writeback(struct x86_emulate_ctxt *ctxt,
1215 struct x86_emulate_ops *ops)
1216{
1217 int rc;
1218 struct decode_cache *c = &ctxt->decode;
1219
1220 switch (c->dst.type) {
1221 case OP_REG:
1222 /* The 4-byte case *is* correct:
1223 * in 64-bit mode we zero-extend.
1224 */
1225 switch (c->dst.bytes) {
1226 case 1:
1227 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1228 break;
1229 case 2:
1230 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1231 break;
1232 case 4:
1233 *c->dst.ptr = (u32)c->dst.val;
1234 break; /* 64b: zero-ext */
1235 case 8:
1236 *c->dst.ptr = c->dst.val;
1237 break;
1238 }
1239 break;
1240 case OP_MEM:
1241 if (c->lock_prefix)
1242 rc = ops->cmpxchg_emulated(
1243 (unsigned long)c->dst.ptr,
1244 &c->dst.orig_val,
1245 &c->dst.val,
1246 c->dst.bytes,
1247 ctxt->vcpu);
1248 else
1249 rc = ops->write_emulated(
1250 (unsigned long)c->dst.ptr,
1251 &c->dst.val,
1252 c->dst.bytes,
1253 ctxt->vcpu);
1254 if (rc != 0)
1255 return rc;
a01af5ec
LV		 1256 break;
1257 case OP_NONE:
1258 /* no writeback */
1259 break;
8cdbd2c9
LV		 1260 default:
1261 break;
1262 }
1263 return 0;
1264}
1265
8b4caf66 1266int
1be3aa47 1267x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 1268{
e8d8d7fe 1269 unsigned long memop = 0;
8b4caf66 1270 u64 msr_data;
3427318f 1271 unsigned long saved_eip = 0;
8b4caf66 1272 struct decode_cache *c = &ctxt->decode;
a6a3034c
MG		 1273 unsigned int port;
1274 int io_dir_in;
1be3aa47 1275 int rc = 0;
8b4caf66 1276
3427318f
LV		 1277 /* Shadow copy of register state. Committed on successful emulation.
1278 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1279 * modify them.
1280 */
1281
ad312c7c 1282 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f
LV		 1283 saved_eip = c->eip;
1284
c7e75a3d 1285 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
e8d8d7fe 1286 memop = c->modrm_ea;
8b4caf66 1287
b9fa9d6b
AK		 1288 if (c->rep_prefix && (c->d & String)) {
1289 /* All REP prefixes have the same first termination condition */
1290 if (c->regs[VCPU_REGS_RCX] == 0) {
5fdbf976 1291 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1292 goto done;
1293 }
1294 /* The second termination condition only applies for REPE
1295 * and REPNE. Test if the repeat string operation prefix is
1296 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1297 * corresponding termination condition according to:
1298 * - if REPE/REPZ and ZF = 0 then done
1299 * - if REPNE/REPNZ and ZF = 1 then done
1300 */
1301 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1302 (c->b == 0xae) || (c->b == 0xaf)) {
1303 if ((c->rep_prefix == REPE_PREFIX) &&
1304 ((ctxt->eflags & EFLG_ZF) == 0)) {
5fdbf976 1305 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1306 goto done;
1307 }
1308 if ((c->rep_prefix == REPNE_PREFIX) &&
1309 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
5fdbf976 1310 kvm_rip_write(ctxt->vcpu, c->eip);
b9fa9d6b
AK		 1311 goto done;
1312 }
1313 }
1314 c->regs[VCPU_REGS_RCX]--;
5fdbf976 1315 c->eip = kvm_rip_read(ctxt->vcpu);
b9fa9d6b
AK		 1316 }
1317
8b4caf66 1318 if (c->src.type == OP_MEM) {
e8d8d7fe 1319 c->src.ptr = (unsigned long *)memop;
8b4caf66 1320 c->src.val = 0;
d77c26fc
MD		 1321 rc = ops->read_emulated((unsigned long)c->src.ptr,
1322 &c->src.val,
1323 c->src.bytes,
1324 ctxt->vcpu);
1325 if (rc != 0)
8b4caf66
LV		 1326 goto done;
1327 c->src.orig_val = c->src.val;
1328 }
1329
1330 if ((c->d & DstMask) == ImplicitOps)
1331 goto special_insn;
1332
1333
1334 if (c->dst.type == OP_MEM) {
e8d8d7fe 1335 c->dst.ptr = (unsigned long *)memop;
8b4caf66
LV		 1336 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1337 c->dst.val = 0;
e4e03ded
LV		 1338 if (c->d & BitOp) {
1339 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1340
e4e03ded
LV		 1341 c->dst.ptr = (void *)c->dst.ptr +
1342 (c->src.val & mask) / 8;
038e51de 1343 }
e4e03ded
LV		 1344 if (!(c->d & Mov) &&
1345 /* optimisation - avoid slow emulated read */
1346 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1347 &c->dst.val,
1348 c->dst.bytes, ctxt->vcpu)) != 0))
038e51de 1349 goto done;
038e51de 1350 }
e4e03ded 1351 c->dst.orig_val = c->dst.val;
038e51de 1352
018a98db
AK		 1353special_insn:
1354
e4e03ded 1355 if (c->twobyte)
6aa8b732
AK		 1356 goto twobyte_insn;
1357
e4e03ded 1358 switch (c->b) {
6aa8b732
AK		 1359 case 0x00 ... 0x05:
1360 add: /* add */
05f086f8 1361 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1362 break;
1363 case 0x08 ... 0x0d:
1364 or: /* or */
05f086f8 1365 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1366 break;
1367 case 0x10 ... 0x15:
1368 adc: /* adc */
05f086f8 1369 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1370 break;
1371 case 0x18 ... 0x1d:
1372 sbb: /* sbb */
05f086f8 1373 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1374 break;
aa3a816b 1375 case 0x20 ... 0x25:
6aa8b732 1376 and: /* and */
05f086f8 1377 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1378 break;
1379 case 0x28 ... 0x2d:
1380 sub: /* sub */
05f086f8 1381 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1382 break;
1383 case 0x30 ... 0x35:
1384 xor: /* xor */
05f086f8 1385 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1386 break;
1387 case 0x38 ... 0x3d:
1388 cmp: /* cmp */
05f086f8 1389 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 1390 break;
33615aa9
AK		 1391 case 0x40 ... 0x47: /* inc r16/r32 */
1392 emulate_1op("inc", c->dst, ctxt->eflags);
1393 break;
1394 case 0x48 ... 0x4f: /* dec r16/r32 */
1395 emulate_1op("dec", c->dst, ctxt->eflags);
1396 break;
1397 case 0x50 ... 0x57: /* push reg */
2786b014 1398 emulate_push(ctxt);
33615aa9
AK		 1399 break;
1400 case 0x58 ... 0x5f: /* pop reg */
1401 pop_instruction:
7a5b56df 1402 if ((rc = ops->read_std(register_address(c, ss_base(ctxt),
33615aa9
AK		 1403 c->regs[VCPU_REGS_RSP]), c->dst.ptr,
1404 c->op_bytes, ctxt->vcpu)) != 0)
1405 goto done;
1406
7a957275 1407 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
33615aa9
AK		 1408 c->op_bytes);
1409 c->dst.type = OP_NONE; /* Disable writeback. */
1410 break;
6aa8b732 1411 case 0x63: /* movsxd */
8b4caf66 1412 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1413 goto cannot_emulate;
e4e03ded 1414 c->dst.val = (s32) c->src.val;
6aa8b732 1415 break;
91ed7a0e 1416 case 0x68: /* push imm */
018a98db 1417 case 0x6a: /* push imm8 */
018a98db
AK		 1418 emulate_push(ctxt);
1419 break;
1420 case 0x6c: /* insb */
1421 case 0x6d: /* insw/insd */
1422 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1423 1,
1424 (c->d & ByteOp) ? 1 : c->op_bytes,
1425 c->rep_prefix ?
e4706772 1426 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1427 (ctxt->eflags & EFLG_DF),
7a5b56df 1428 register_address(c, es_base(ctxt),
018a98db
AK		 1429 c->regs[VCPU_REGS_RDI]),
1430 c->rep_prefix,
1431 c->regs[VCPU_REGS_RDX]) == 0) {
1432 c->eip = saved_eip;
1433 return -1;
1434 }
1435 return 0;
1436 case 0x6e: /* outsb */
1437 case 0x6f: /* outsw/outsd */
1438 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1439 0,
1440 (c->d & ByteOp) ? 1 : c->op_bytes,
1441 c->rep_prefix ?
e4706772 1442 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1443 (ctxt->eflags & EFLG_DF),
7a5b56df
AK		 1444 register_address(c,
1445 seg_override_base(ctxt, c),
018a98db
AK		 1446 c->regs[VCPU_REGS_RSI]),
1447 c->rep_prefix,
1448 c->regs[VCPU_REGS_RDX]) == 0) {
1449 c->eip = saved_eip;
1450 return -1;
1451 }
1452 return 0;
1453 case 0x70 ... 0x7f: /* jcc (short) */ {
1454 int rel = insn_fetch(s8, 1, c->eip);
1455
1456 if (test_cc(c->b, ctxt->eflags))
7a957275 1457 jmp_rel(c, rel);
018a98db
AK		 1458 break;
1459 }
6aa8b732 1460 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 1461 switch (c->modrm_reg) {
6aa8b732
AK		 1462 case 0:
1463 goto add;
1464 case 1:
1465 goto or;
1466 case 2:
1467 goto adc;
1468 case 3:
1469 goto sbb;
1470 case 4:
1471 goto and;
1472 case 5:
1473 goto sub;
1474 case 6:
1475 goto xor;
1476 case 7:
1477 goto cmp;
1478 }
1479 break;
1480 case 0x84 ... 0x85:
05f086f8 1481 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1482 break;
1483 case 0x86 ... 0x87: /* xchg */
b13354f8 1484 xchg:
6aa8b732 1485 /* Write back the register source. */
e4e03ded 1486 switch (c->dst.bytes) {
6aa8b732 1487 case 1:
e4e03ded 1488 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 1489 break;
1490 case 2:
e4e03ded 1491 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 1492 break;
1493 case 4:
e4e03ded 1494 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 1495 break; /* 64b reg: zero-extend */
1496 case 8:
e4e03ded 1497 *c->src.ptr = c->dst.val;
6aa8b732
AK		 1498 break;
1499 }
1500 /*
1501 * Write back the memory destination with implicit LOCK
1502 * prefix.
1503 */
e4e03ded
LV		 1504 c->dst.val = c->src.val;
1505 c->lock_prefix = 1;
6aa8b732 1506 break;
6aa8b732 1507 case 0x88 ... 0x8b: /* mov */
7de75248 1508 goto mov;
38d5bc6d
GT		 1509 case 0x8c: { /* mov r/m, sreg */
1510 struct kvm_segment segreg;
1511
1512 if (c->modrm_reg <= 5)
1513 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
1514 else {
1515 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
1516 c->modrm);
1517 goto cannot_emulate;
1518 }
1519 c->dst.val = segreg.selector;
1520 break;
1521 }
7e0b54b1 1522 case 0x8d: /* lea r16/r32, m */
f9b7aab3 1523 c->dst.val = c->modrm_ea;
7e0b54b1 1524 break;
4257198a
GT		 1525 case 0x8e: { /* mov seg, r/m16 */
1526 uint16_t sel;
1527 int type_bits;
1528 int err;
1529
1530 sel = c->src.val;
1531 if (c->modrm_reg <= 5) {
1532 type_bits = (c->modrm_reg == 1) ? 9 : 1;
1533 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
1534 type_bits, c->modrm_reg);
1535 } else {
1536 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
1537 c->modrm);
1538 goto cannot_emulate;
1539 }
1540
1541 if (err < 0)
1542 goto cannot_emulate;
1543
1544 c->dst.type = OP_NONE; /* Disable writeback. */
1545 break;
1546 }
6aa8b732 1547 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 1548 rc = emulate_grp1a(ctxt, ops);
1549 if (rc != 0)
6aa8b732 1550 goto done;
6aa8b732 1551 break;
b13354f8
MG		 1552 case 0x90: /* nop / xchg r8,rax */
1553 if (!(c->rex_prefix & 1)) { /* nop */
1554 c->dst.type = OP_NONE;
1555 break;
1556 }
1557 case 0x91 ... 0x97: /* xchg reg,rax */
1558 c->src.type = c->dst.type = OP_REG;
1559 c->src.bytes = c->dst.bytes = c->op_bytes;
1560 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
1561 c->src.val = *(c->src.ptr);
1562 goto xchg;
fd2a7608 1563 case 0x9c: /* pushf */
05f086f8 1564 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 1565 emulate_push(ctxt);
1566 break;
535eabcf 1567 case 0x9d: /* popf */
05f086f8 1568 c->dst.ptr = (unsigned long *) &ctxt->eflags;
535eabcf 1569 goto pop_instruction;
018a98db
AK		 1570 case 0xa0 ... 0xa1: /* mov */
1571 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1572 c->dst.val = c->src.val;
1573 break;
1574 case 0xa2 ... 0xa3: /* mov */
1575 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1576 break;
6aa8b732 1577 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 1578 c->dst.type = OP_MEM;
1579 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1580 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1581 es_base(ctxt),
e4e03ded 1582 c->regs[VCPU_REGS_RDI]);
e4706772 1583 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 1584 seg_override_base(ctxt, c),
e4e03ded
LV		 1585 c->regs[VCPU_REGS_RSI]),
1586 &c->dst.val,
1587 c->dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1588 goto done;
7a957275 1589 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1590 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1591 : c->dst.bytes);
7a957275 1592 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1593 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1594 : c->dst.bytes);
6aa8b732
AK		 1595 break;
1596 case 0xa6 ... 0xa7: /* cmps */
d7e5117a
GT		 1597 c->src.type = OP_NONE; /* Disable writeback. */
1598 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1599 c->src.ptr = (unsigned long *)register_address(c,
7a5b56df 1600 seg_override_base(ctxt, c),
d7e5117a
GT		 1601 c->regs[VCPU_REGS_RSI]);
1602 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1603 &c->src.val,
1604 c->src.bytes,
1605 ctxt->vcpu)) != 0)
1606 goto done;
1607
1608 c->dst.type = OP_NONE; /* Disable writeback. */
1609 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1610 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1611 es_base(ctxt),
d7e5117a
GT		 1612 c->regs[VCPU_REGS_RDI]);
1613 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1614 &c->dst.val,
1615 c->dst.bytes,
1616 ctxt->vcpu)) != 0)
1617 goto done;
1618
1619 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1620
1621 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1622
7a957275 1623 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
d7e5117a
GT		 1624 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1625 : c->src.bytes);
7a957275 1626 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
d7e5117a
GT		 1627 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1628 : c->dst.bytes);
1629
1630 break;
6aa8b732 1631 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 1632 c->dst.type = OP_MEM;
1633 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1634 c->dst.ptr = (unsigned long *)register_address(c,
7a5b56df 1635 es_base(ctxt),
a7e6c88a 1636 c->regs[VCPU_REGS_RDI]);
e4e03ded 1637 c->dst.val = c->regs[VCPU_REGS_RAX];
7a957275 1638 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
05f086f8 1639 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1640 : c->dst.bytes);
6aa8b732
AK		 1641 break;
1642 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 1643 c->dst.type = OP_REG;
1644 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1645 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
e4706772 1646 if ((rc = ops->read_emulated(register_address(c,
7a5b56df 1647 seg_override_base(ctxt, c),
a7e6c88a
SY		 1648 c->regs[VCPU_REGS_RSI]),
1649 &c->dst.val,
1650 c->dst.bytes,
1651 ctxt->vcpu)) != 0)
6aa8b732 1652 goto done;
7a957275 1653 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
05f086f8 1654 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1655 : c->dst.bytes);
6aa8b732
AK		 1656 break;
1657 case 0xae ... 0xaf: /* scas */
1658 DPRINTF("Urk! I don't handle SCAS.\n");
1659 goto cannot_emulate;
a5e2e82b 1660 case 0xb0 ... 0xbf: /* mov r, imm */
615ac125 1661 goto mov;
018a98db
AK		 1662 case 0xc0 ... 0xc1:
1663 emulate_grp2(ctxt);
1664 break;
111de5d6
AK		 1665 case 0xc3: /* ret */
1666 c->dst.ptr = &c->eip;
1667 goto pop_instruction;
018a98db
AK		 1668 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1669 mov:
1670 c->dst.val = c->src.val;
1671 break;
1672 case 0xd0 ... 0xd1: /* Grp2 */
1673 c->src.val = 1;
1674 emulate_grp2(ctxt);
1675 break;
1676 case 0xd2 ... 0xd3: /* Grp2 */
1677 c->src.val = c->regs[VCPU_REGS_RCX];
1678 emulate_grp2(ctxt);
1679 break;
a6a3034c
MG		 1680 case 0xe4: /* inb */
1681 case 0xe5: /* in */
1682 port = insn_fetch(u8, 1, c->eip);
1683 io_dir_in = 1;
1684 goto do_io;
1685 case 0xe6: /* outb */
1686 case 0xe7: /* out */
1687 port = insn_fetch(u8, 1, c->eip);
1688 io_dir_in = 0;
1689 goto do_io;
1a52e051
NK		 1690 case 0xe8: /* call (near) */ {
1691 long int rel;
e4e03ded 1692 switch (c->op_bytes) {
1a52e051 1693 case 2:
e4e03ded 1694 rel = insn_fetch(s16, 2, c->eip);
1a52e051
NK		 1695 break;
1696 case 4:
e4e03ded 1697 rel = insn_fetch(s32, 4, c->eip);
1a52e051 1698 break;
1a52e051
NK		 1699 default:
1700 DPRINTF("Call: Invalid op_bytes\n");
1701 goto cannot_emulate;
1702 }
e4e03ded 1703 c->src.val = (unsigned long) c->eip;
7a957275 1704 jmp_rel(c, rel);
e4e03ded 1705 c->op_bytes = c->ad_bytes;
8cdbd2c9
LV		 1706 emulate_push(ctxt);
1707 break;
1a52e051
NK		 1708 }
1709 case 0xe9: /* jmp rel */
954cd36f
GT		 1710 goto jmp;
1711 case 0xea: /* jmp far */ {
1712 uint32_t eip;
1713 uint16_t sel;
1714
1715 switch (c->op_bytes) {
1716 case 2:
1717 eip = insn_fetch(u16, 2, c->eip);
1718 break;
1719 case 4:
1720 eip = insn_fetch(u32, 4, c->eip);
1721 break;
1722 default:
1723 DPRINTF("jmp far: Invalid op_bytes\n");
1724 goto cannot_emulate;
1725 }
1726 sel = insn_fetch(u16, 2, c->eip);
1727 if (kvm_load_segment_descriptor(ctxt->vcpu, sel, 9, VCPU_SREG_CS) < 0) {
1728 DPRINTF("jmp far: Failed to load CS descriptor\n");
1729 goto cannot_emulate;
1730 }
1731
1732 c->eip = eip;
1733 break;
1734 }
1735 case 0xeb:
1736 jmp: /* jmp rel short */
7a957275 1737 jmp_rel(c, c->src.val);
a01af5ec 1738 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 1739 break;
a6a3034c
MG		 1740 case 0xec: /* in al,dx */
1741 case 0xed: /* in (e/r)ax,dx */
1742 port = c->regs[VCPU_REGS_RDX];
1743 io_dir_in = 1;
1744 goto do_io;
1745 case 0xee: /* out al,dx */
1746 case 0xef: /* out (e/r)ax,dx */
1747 port = c->regs[VCPU_REGS_RDX];
1748 io_dir_in = 0;
1749 do_io: if (kvm_emulate_pio(ctxt->vcpu, NULL, io_dir_in,
1750 (c->d & ByteOp) ? 1 : c->op_bytes,
1751 port) != 0) {
1752 c->eip = saved_eip;
1753 goto cannot_emulate;
1754 }
e93f36bc 1755 break;
111de5d6 1756 case 0xf4: /* hlt */
ad312c7c 1757 ctxt->vcpu->arch.halt_request = 1;
19fdfa0d 1758 break;
111de5d6
AK		 1759 case 0xf5: /* cmc */
1760 /* complement carry flag from eflags reg */
1761 ctxt->eflags ^= EFLG_CF;
1762 c->dst.type = OP_NONE; /* Disable writeback. */
1763 break;
018a98db
AK		 1764 case 0xf6 ... 0xf7: /* Grp3 */
1765 rc = emulate_grp3(ctxt, ops);
1766 if (rc != 0)
1767 goto done;
1768 break;
111de5d6
AK		 1769 case 0xf8: /* clc */
1770 ctxt->eflags &= ~EFLG_CF;
1771 c->dst.type = OP_NONE; /* Disable writeback. */
1772 break;
1773 case 0xfa: /* cli */
1774 ctxt->eflags &= ~X86_EFLAGS_IF;
1775 c->dst.type = OP_NONE; /* Disable writeback. */
1776 break;
1777 case 0xfb: /* sti */
1778 ctxt->eflags |= X86_EFLAGS_IF;
1779 c->dst.type = OP_NONE; /* Disable writeback. */
1780 break;
fb4616f4
MG		 1781 case 0xfc: /* cld */
1782 ctxt->eflags &= ~EFLG_DF;
1783 c->dst.type = OP_NONE; /* Disable writeback. */
1784 break;
1785 case 0xfd: /* std */
1786 ctxt->eflags |= EFLG_DF;
1787 c->dst.type = OP_NONE; /* Disable writeback. */
1788 break;
018a98db
AK		 1789 case 0xfe ... 0xff: /* Grp4/Grp5 */
1790 rc = emulate_grp45(ctxt, ops);
1791 if (rc != 0)
1792 goto done;
1793 break;
6aa8b732 1794 }
018a98db
AK		 1795
1796writeback:
1797 rc = writeback(ctxt, ops);
1798 if (rc != 0)
1799 goto done;
1800
1801 /* Commit shadow register state. */
ad312c7c 1802 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
5fdbf976 1803 kvm_rip_write(ctxt->vcpu, c->eip);
018a98db
AK		 1804
1805done:
1806 if (rc == X86EMUL_UNHANDLEABLE) {
1807 c->eip = saved_eip;
1808 return -1;
1809 }
1810 return 0;
6aa8b732
AK		 1811
1812twobyte_insn:
e4e03ded 1813 switch (c->b) {
6aa8b732 1814 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 1815 switch (c->modrm_reg) {
6aa8b732
AK		 1816 u16 size;
1817 unsigned long address;
1818
aca7f966 1819 case 0: /* vmcall */
e4e03ded 1820 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 1821 goto cannot_emulate;
1822
7aa81cc0
AL		 1823 rc = kvm_fix_hypercall(ctxt->vcpu);
1824 if (rc)
1825 goto done;
1826
33e3885d 1827 /* Let the processor re-execute the fixed hypercall */
5fdbf976 1828 c->eip = kvm_rip_read(ctxt->vcpu);
16286d08
AK		 1829 /* Disable writeback. */
1830 c->dst.type = OP_NONE;
aca7f966 1831 break;
6aa8b732 1832 case 2: /* lgdt */
e4e03ded
LV		 1833 rc = read_descriptor(ctxt, ops, c->src.ptr,
1834 &size, &address, c->op_bytes);
6aa8b732
AK		 1835 if (rc)
1836 goto done;
1837 realmode_lgdt(ctxt->vcpu, size, address);
16286d08
AK		 1838 /* Disable writeback. */
1839 c->dst.type = OP_NONE;
6aa8b732 1840 break;
aca7f966 1841 case 3: /* lidt/vmmcall */
e4e03ded 1842 if (c->modrm_mod == 3 && c->modrm_rm == 1) {
7aa81cc0
AL		 1843 rc = kvm_fix_hypercall(ctxt->vcpu);
1844 if (rc)
1845 goto done;
1846 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1847 } else {
e4e03ded 1848 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 1849 &size, &address,
e4e03ded 1850 c->op_bytes);
aca7f966
AL		 1851 if (rc)
1852 goto done;
1853 realmode_lidt(ctxt->vcpu, size, address);
1854 }
16286d08
AK		 1855 /* Disable writeback. */
1856 c->dst.type = OP_NONE;
6aa8b732
AK		 1857 break;
1858 case 4: /* smsw */
16286d08
AK		 1859 c->dst.bytes = 2;
1860 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
6aa8b732
AK		 1861 break;
1862 case 6: /* lmsw */
16286d08
AK		 1863 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
1864 &ctxt->eflags);
dc7457ea 1865 c->dst.type = OP_NONE;
6aa8b732
AK		 1866 break;
1867 case 7: /* invlpg*/
e8d8d7fe 1868 emulate_invlpg(ctxt->vcpu, memop);
16286d08
AK		 1869 /* Disable writeback. */
1870 c->dst.type = OP_NONE;
6aa8b732
AK		 1871 break;
1872 default:
1873 goto cannot_emulate;
1874 }
1875 break;
018a98db
AK		 1876 case 0x06:
1877 emulate_clts(ctxt->vcpu);
1878 c->dst.type = OP_NONE;
1879 break;
1880 case 0x08: /* invd */
1881 case 0x09: /* wbinvd */
1882 case 0x0d: /* GrpP (prefetch) */
1883 case 0x18: /* Grp16 (prefetch/nop) */
1884 c->dst.type = OP_NONE;
1885 break;
1886 case 0x20: /* mov cr, reg */
1887 if (c->modrm_mod != 3)
1888 goto cannot_emulate;
1889 c->regs[c->modrm_rm] =
1890 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1891 c->dst.type = OP_NONE; /* no writeback */
1892 break;
6aa8b732 1893 case 0x21: /* mov from dr to reg */
e4e03ded 1894 if (c->modrm_mod != 3)
6aa8b732 1895 goto cannot_emulate;
8cdbd2c9 1896 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 1897 if (rc)
1898 goto cannot_emulate;
1899 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1900 break;
018a98db
AK		 1901 case 0x22: /* mov reg, cr */
1902 if (c->modrm_mod != 3)
1903 goto cannot_emulate;
1904 realmode_set_cr(ctxt->vcpu,
1905 c->modrm_reg, c->modrm_val, &ctxt->eflags);
1906 c->dst.type = OP_NONE;
1907 break;
6aa8b732 1908 case 0x23: /* mov from reg to dr */
e4e03ded 1909 if (c->modrm_mod != 3)
6aa8b732 1910 goto cannot_emulate;
e4e03ded
LV		 1911 rc = emulator_set_dr(ctxt, c->modrm_reg,
1912 c->regs[c->modrm_rm]);
a01af5ec
LV		 1913 if (rc)
1914 goto cannot_emulate;
1915 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1916 break;
018a98db
AK		 1917 case 0x30:
1918 /* wrmsr */
1919 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1920 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1921 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
1922 if (rc) {
c1a5d4f9 1923 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 1924 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 1925 }
1926 rc = X86EMUL_CONTINUE;
1927 c->dst.type = OP_NONE;
1928 break;
1929 case 0x32:
1930 /* rdmsr */
1931 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
1932 if (rc) {
c1a5d4f9 1933 kvm_inject_gp(ctxt->vcpu, 0);
5fdbf976 1934 c->eip = kvm_rip_read(ctxt->vcpu);
018a98db
AK		 1935 } else {
1936 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
1937 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
1938 }
1939 rc = X86EMUL_CONTINUE;
1940 c->dst.type = OP_NONE;
1941 break;
6aa8b732 1942 case 0x40 ... 0x4f: /* cmov */
e4e03ded 1943 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 1944 if (!test_cc(c->b, ctxt->eflags))
1945 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1946 break;
018a98db
AK		 1947 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1948 long int rel;
1949
1950 switch (c->op_bytes) {
1951 case 2:
1952 rel = insn_fetch(s16, 2, c->eip);
1953 break;
1954 case 4:
1955 rel = insn_fetch(s32, 4, c->eip);
1956 break;
1957 case 8:
1958 rel = insn_fetch(s64, 8, c->eip);
1959 break;
1960 default:
1961 DPRINTF("jnz: Invalid op_bytes\n");
1962 goto cannot_emulate;
1963 }
1964 if (test_cc(c->b, ctxt->eflags))
7a957275 1965 jmp_rel(c, rel);
018a98db
AK		 1966 c->dst.type = OP_NONE;
1967 break;
1968 }
7de75248
NK		 1969 case 0xa3:
1970 bt: /* bt */
e4f8e039 1971 c->dst.type = OP_NONE;
e4e03ded
LV		 1972 /* only subword offset */
1973 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1974 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248
NK		 1975 break;
1976 case 0xab:
1977 bts: /* bts */
e4e03ded
LV		 1978 /* only subword offset */
1979 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1980 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 1981 break;
2a7c5b8b
GC		 1982 case 0xae: /* clflush */
1983 break;
6aa8b732
AK		 1984 case 0xb0 ... 0xb1: /* cmpxchg */
1985 /*
1986 * Save real source value, then compare EAX against
1987 * destination.
1988 */
e4e03ded
LV		 1989 c->src.orig_val = c->src.val;
1990 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 1991 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1992 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 1993 /* Success: write back to memory. */
e4e03ded 1994 c->dst.val = c->src.orig_val;
6aa8b732
AK		 1995 } else {
1996 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 1997 c->dst.type = OP_REG;
1998 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 1999 }
2000 break;
6aa8b732
AK		 2001 case 0xb3:
2002 btr: /* btr */
e4e03ded
LV		 2003 /* only subword offset */
2004 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2005 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 2006 break;
6aa8b732 2007 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 2008 c->dst.bytes = c->op_bytes;
2009 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
2010 : (u16) c->src.val;
6aa8b732 2011 break;
6aa8b732 2012 case 0xba: /* Grp8 */
e4e03ded 2013 switch (c->modrm_reg & 3) {
6aa8b732
AK		 2014 case 0:
2015 goto bt;
2016 case 1:
2017 goto bts;
2018 case 2:
2019 goto btr;
2020 case 3:
2021 goto btc;
2022 }
2023 break;
7de75248
NK		 2024 case 0xbb:
2025 btc: /* btc */
e4e03ded
LV		 2026 /* only subword offset */
2027 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 2028 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 2029 break;
6aa8b732 2030 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 2031 c->dst.bytes = c->op_bytes;
2032 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
2033 (s16) c->src.val;
6aa8b732 2034 break;
a012e65a 2035 case 0xc3: /* movnti */
e4e03ded
LV		 2036 c->dst.bytes = c->op_bytes;
2037 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
2038 (u64) c->src.val;
a012e65a 2039 break;
6aa8b732 2040 case 0xc7: /* Grp9 (cmpxchg8b) */
e8d8d7fe 2041 rc = emulate_grp9(ctxt, ops, memop);
8cdbd2c9
LV		 2042 if (rc != 0)
2043 goto done;
018a98db 2044 c->dst.type = OP_NONE;
8cdbd2c9 2045 break;
6aa8b732
AK		 2046 }
2047 goto writeback;
2048
2049cannot_emulate:
e4e03ded 2050 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 2051 c->eip = saved_eip;
6aa8b732
AK		 2052 return -1;
2053}
Linux kernel - Deliverables
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