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KVM: x86 emulator: make register_address, address_mask static inlines
[deliverable/linux.git] / arch / x86 / kvm / x86_emulate.c
CommitLineData
6aa8b732
AK		 1/******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
d77c26fc 26#define DPRINTF(_f, _a ...) printf(_f , ## _a)
6aa8b732 27#else
edf88417 28#include <linux/kvm_host.h>
6aa8b732
AK		 29#define DPRINTF(x...) do {} while (0)
30#endif
6aa8b732 31#include <linux/module.h>
edf88417 32#include <asm/kvm_x86_emulate.h>
6aa8b732
AK		 33
34/*
35 * Opcode effective-address decode tables.
36 * Note that we only emulate instructions that have at least one memory
37 * operand (excluding implicit stack references). We assume that stack
38 * references and instruction fetches will never occur in special memory
39 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
40 * not be handled.
41 */
42
43/* Operand sizes: 8-bit operands or specified/overridden size. */
44#define ByteOp (1<<0) /* 8-bit operands. */
45/* Destination operand type. */
46#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
47#define DstReg (2<<1) /* Register operand. */
48#define DstMem (3<<1) /* Memory operand. */
49#define DstMask (3<<1)
50/* Source operand type. */
51#define SrcNone (0<<3) /* No source operand. */
52#define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */
53#define SrcReg (1<<3) /* Register operand. */
54#define SrcMem (2<<3) /* Memory operand. */
55#define SrcMem16 (3<<3) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<3) /* Memory operand (32-bit). */
57#define SrcImm (5<<3) /* Immediate operand. */
58#define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */
59#define SrcMask (7<<3)
60/* Generic ModRM decode. */
61#define ModRM (1<<6)
62/* Destination is only written; never read. */
63#define Mov (1<<7)
038e51de 64#define BitOp (1<<8)
c7e75a3d 65#define MemAbs (1<<9) /* Memory operand is absolute displacement */
b9fa9d6b 66#define String (1<<10) /* String instruction (rep capable) */
6e3d5dfb 67#define Stack (1<<11) /* Stack instruction (push/pop) */
e09d082c
AK		 68#define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
69#define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
70#define GroupMask 0xff /* Group number stored in bits 0:7 */
6aa8b732 71
43bb19cd 72enum {
1d6ad207 73 Group1_80, Group1_81, Group1_82, Group1_83,
d95058a1 74 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
43bb19cd
AK		 75};
76
c7e75a3d 77static u16 opcode_table[256] = {
6aa8b732
AK		 78 /* 0x00 - 0x07 */
79 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
80 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
81 0, 0, 0, 0,
82 /* 0x08 - 0x0F */
83 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
84 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
85 0, 0, 0, 0,
86 /* 0x10 - 0x17 */
87 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
88 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
89 0, 0, 0, 0,
90 /* 0x18 - 0x1F */
91 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
92 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
93 0, 0, 0, 0,
94 /* 0x20 - 0x27 */
95 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
96 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
19eb938e 97 SrcImmByte, SrcImm, 0, 0,
6aa8b732
AK		 98 /* 0x28 - 0x2F */
99 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
100 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
101 0, 0, 0, 0,
102 /* 0x30 - 0x37 */
103 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
104 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
105 0, 0, 0, 0,
106 /* 0x38 - 0x3F */
107 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
108 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
109 0, 0, 0, 0,
d77a2507 110 /* 0x40 - 0x47 */
33615aa9 111 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
d77a2507 112 /* 0x48 - 0x4F */
33615aa9 113 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
7f0aaee0 114 /* 0x50 - 0x57 */
6e3d5dfb
AK		 115 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
116 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
7f0aaee0 117 /* 0x58 - 0x5F */
6e3d5dfb
AK		 118 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
119 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
7d316911 120 /* 0x60 - 0x67 */
6aa8b732 121 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 122 0, 0, 0, 0,
123 /* 0x68 - 0x6F */
6e3d5dfb 124 0, 0, ImplicitOps | Mov | Stack, 0,
e70669ab
LV		 125 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
126 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4
NK		 127 /* 0x70 - 0x77 */
128 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
129 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
130 /* 0x78 - 0x7F */
131 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
132 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732 133 /* 0x80 - 0x87 */
1d6ad207
AK		 134 Group | Group1_80, Group | Group1_81,
135 Group | Group1_82, Group | Group1_83,
6aa8b732
AK		 136 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
137 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
138 /* 0x88 - 0x8F */
139 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
140 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
43bb19cd 141 0, ModRM | DstReg, 0, Group | Group1A,
6aa8b732 142 /* 0x90 - 0x9F */
6e3d5dfb
AK		 143 0, 0, 0, 0, 0, 0, 0, 0,
144 0, 0, 0, 0, ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
6aa8b732 145 /* 0xA0 - 0xA7 */
c7e75a3d
AK		 146 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
147 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
b9fa9d6b
AK		 148 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
149 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732 150 /* 0xA8 - 0xAF */
b9fa9d6b
AK		 151 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
152 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
153 ByteOp | ImplicitOps | String, ImplicitOps | String,
6aa8b732
AK		 154 /* 0xB0 - 0xBF */
155 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
156 /* 0xC0 - 0xC7 */
d9413cd7 157 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
6e3d5dfb 158 0, ImplicitOps | Stack, 0, 0,
d9413cd7 159 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732
AK		 160 /* 0xC8 - 0xCF */
161 0, 0, 0, 0, 0, 0, 0, 0,
162 /* 0xD0 - 0xD7 */
163 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
164 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
165 0, 0, 0, 0,
166 /* 0xD8 - 0xDF */
167 0, 0, 0, 0, 0, 0, 0, 0,
098c937b
NK		 168 /* 0xE0 - 0xE7 */
169 0, 0, 0, 0, 0, 0, 0, 0,
170 /* 0xE8 - 0xEF */
6e3d5dfb
AK		 171 ImplicitOps | Stack, SrcImm|ImplicitOps, 0, SrcImmByte|ImplicitOps,
172 0, 0, 0, 0,
6aa8b732
AK		 173 /* 0xF0 - 0xF7 */
174 0, 0, 0, 0,
7d858a19 175 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
6aa8b732 176 /* 0xF8 - 0xFF */
b284be57 177 ImplicitOps, 0, ImplicitOps, ImplicitOps,
fd60754e 178 0, 0, Group | Group4, Group | Group5,
6aa8b732
AK		 179};
180
038e51de 181static u16 twobyte_table[256] = {
6aa8b732 182 /* 0x00 - 0x0F */
d95058a1 183 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
651a3e29 184 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 185 /* 0x10 - 0x1F */
186 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
187 /* 0x20 - 0x2F */
188 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
189 0, 0, 0, 0, 0, 0, 0, 0,
190 /* 0x30 - 0x3F */
35f3f286 191 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 192 /* 0x40 - 0x47 */
193 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
194 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
195 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
196 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
197 /* 0x48 - 0x4F */
198 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
199 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
200 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
201 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
202 /* 0x50 - 0x5F */
203 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
204 /* 0x60 - 0x6F */
205 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
206 /* 0x70 - 0x7F */
207 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
208 /* 0x80 - 0x8F */
bbe9abbd
NK		 209 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
210 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
211 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
212 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 213 /* 0x90 - 0x9F */
214 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
215 /* 0xA0 - 0xA7 */
038e51de 216 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732 217 /* 0xA8 - 0xAF */
038e51de 218 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732
AK		 219 /* 0xB0 - 0xB7 */
220 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 221 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 222 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
223 DstReg | SrcMem16 | ModRM | Mov,
224 /* 0xB8 - 0xBF */
038e51de 225 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 226 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
227 DstReg | SrcMem16 | ModRM | Mov,
228 /* 0xC0 - 0xCF */
a012e65a
SY		 229 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
230 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 231 /* 0xD0 - 0xDF */
232 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
233 /* 0xE0 - 0xEF */
234 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
235 /* 0xF0 - 0xFF */
236 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
237};
238
e09d082c 239static u16 group_table[] = {
1d6ad207
AK		 240 [Group1_80*8] =
241 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
242 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
243 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
244 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
245 [Group1_81*8] =
246 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
247 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
248 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
249 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
250 [Group1_82*8] =
251 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
252 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
253 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
254 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
255 [Group1_83*8] =
256 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
257 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
258 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
259 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
43bb19cd
AK		 260 [Group1A*8] =
261 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
7d858a19
AK		 262 [Group3_Byte*8] =
263 ByteOp | SrcImm | DstMem | ModRM, 0,
264 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
265 0, 0, 0, 0,
266 [Group3*8] =
267 DstMem | SrcImm | ModRM | SrcImm, 0,
268 DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
269 0, 0, 0, 0,
fd60754e
AK		 270 [Group4*8] =
271 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
272 0, 0, 0, 0, 0, 0,
273 [Group5*8] =
274 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM, 0, 0,
275 SrcMem | ModRM, 0, SrcMem | ModRM | Stack, 0,
d95058a1
AK		 276 [Group7*8] =
277 0, 0, ModRM | SrcMem, ModRM | SrcMem,
278 SrcNone | ModRM | DstMem, 0, SrcMem | ModRM, SrcMem | ModRM | ByteOp,
e09d082c
AK		 279};
280
281static u16 group2_table[] = {
d95058a1
AK		 282 [Group7*8] =
283 SrcNone | ModRM, 0, 0, 0, SrcNone | ModRM | DstMem, 0, SrcMem | ModRM, 0,
e09d082c
AK		 284};
285
6aa8b732
AK		 286/* EFLAGS bit definitions. */
287#define EFLG_OF (1<<11)
288#define EFLG_DF (1<<10)
289#define EFLG_SF (1<<7)
290#define EFLG_ZF (1<<6)
291#define EFLG_AF (1<<4)
292#define EFLG_PF (1<<2)
293#define EFLG_CF (1<<0)
294
295/*
296 * Instruction emulation:
297 * Most instructions are emulated directly via a fragment of inline assembly
298 * code. This allows us to save/restore EFLAGS and thus very easily pick up
299 * any modified flags.
300 */
301
05b3e0c2 302#if defined(CONFIG_X86_64)
6aa8b732
AK		 303#define _LO32 "k" /* force 32-bit operand */
304#define _STK "%%rsp" /* stack pointer */
305#elif defined(__i386__)
306#define _LO32 "" /* force 32-bit operand */
307#define _STK "%%esp" /* stack pointer */
308#endif
309
310/*
311 * These EFLAGS bits are restored from saved value during emulation, and
312 * any changes are written back to the saved value after emulation.
313 */
314#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
315
316/* Before executing instruction: restore necessary bits in EFLAGS. */
e934c9c1
AK		 317#define _PRE_EFLAGS(_sav, _msk, _tmp) \
318 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
319 "movl %"_sav",%"_LO32 _tmp"; " \
320 "push %"_tmp"; " \
321 "push %"_tmp"; " \
322 "movl %"_msk",%"_LO32 _tmp"; " \
323 "andl %"_LO32 _tmp",("_STK"); " \
324 "pushf; " \
325 "notl %"_LO32 _tmp"; " \
326 "andl %"_LO32 _tmp",("_STK"); " \
327 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
328 "pop %"_tmp"; " \
329 "orl %"_LO32 _tmp",("_STK"); " \
330 "popf; " \
331 "pop %"_sav"; "
6aa8b732
AK		 332
333/* After executing instruction: write-back necessary bits in EFLAGS. */
334#define _POST_EFLAGS(_sav, _msk, _tmp) \
335 /* _sav |= EFLAGS & _msk; */ \
336 "pushf; " \
337 "pop %"_tmp"; " \
338 "andl %"_msk",%"_LO32 _tmp"; " \
339 "orl %"_LO32 _tmp",%"_sav"; "
340
341/* Raw emulation: instruction has two explicit operands. */
342#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
343 do { \
344 unsigned long _tmp; \
345 \
346 switch ((_dst).bytes) { \
347 case 2: \
348 __asm__ __volatile__ ( \
d77c26fc 349 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 350 _op"w %"_wx"3,%1; " \
d77c26fc 351 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 352 : "=m" (_eflags), "=m" ((_dst).val), \
353 "=&r" (_tmp) \
d77c26fc 354 : _wy ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 355 break; \
356 case 4: \
357 __asm__ __volatile__ ( \
d77c26fc 358 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 359 _op"l %"_lx"3,%1; " \
d77c26fc 360 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 361 : "=m" (_eflags), "=m" ((_dst).val), \
362 "=&r" (_tmp) \
d77c26fc 363 : _ly ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 364 break; \
365 case 8: \
366 __emulate_2op_8byte(_op, _src, _dst, \
367 _eflags, _qx, _qy); \
368 break; \
369 } \
370 } while (0)
371
372#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
373 do { \
374 unsigned long _tmp; \
d77c26fc 375 switch ((_dst).bytes) { \
6aa8b732
AK		 376 case 1: \
377 __asm__ __volatile__ ( \
d77c26fc 378 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 379 _op"b %"_bx"3,%1; " \
d77c26fc 380 _POST_EFLAGS("0", "4", "2") \
6aa8b732
AK		 381 : "=m" (_eflags), "=m" ((_dst).val), \
382 "=&r" (_tmp) \
d77c26fc 383 : _by ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 384 break; \
385 default: \
386 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
387 _wx, _wy, _lx, _ly, _qx, _qy); \
388 break; \
389 } \
390 } while (0)
391
392/* Source operand is byte-sized and may be restricted to just %cl. */
393#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
394 __emulate_2op(_op, _src, _dst, _eflags, \
395 "b", "c", "b", "c", "b", "c", "b", "c")
396
397/* Source operand is byte, word, long or quad sized. */
398#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
399 __emulate_2op(_op, _src, _dst, _eflags, \
400 "b", "q", "w", "r", _LO32, "r", "", "r")
401
402/* Source operand is word, long or quad sized. */
403#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
404 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
405 "w", "r", _LO32, "r", "", "r")
406
407/* Instruction has only one explicit operand (no source operand). */
408#define emulate_1op(_op, _dst, _eflags) \
409 do { \
410 unsigned long _tmp; \
411 \
d77c26fc 412 switch ((_dst).bytes) { \
6aa8b732
AK		 413 case 1: \
414 __asm__ __volatile__ ( \
d77c26fc 415 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 416 _op"b %1; " \
d77c26fc 417 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 418 : "=m" (_eflags), "=m" ((_dst).val), \
419 "=&r" (_tmp) \
d77c26fc 420 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 421 break; \
422 case 2: \
423 __asm__ __volatile__ ( \
d77c26fc 424 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 425 _op"w %1; " \
d77c26fc 426 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 427 : "=m" (_eflags), "=m" ((_dst).val), \
428 "=&r" (_tmp) \
d77c26fc 429 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 430 break; \
431 case 4: \
432 __asm__ __volatile__ ( \
d77c26fc 433 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 434 _op"l %1; " \
d77c26fc 435 _POST_EFLAGS("0", "3", "2") \
6aa8b732
AK		 436 : "=m" (_eflags), "=m" ((_dst).val), \
437 "=&r" (_tmp) \
d77c26fc 438 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 439 break; \
440 case 8: \
441 __emulate_1op_8byte(_op, _dst, _eflags); \
442 break; \
443 } \
444 } while (0)
445
446/* Emulate an instruction with quadword operands (x86/64 only). */
05b3e0c2 447#if defined(CONFIG_X86_64)
6aa8b732
AK		 448#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
449 do { \
450 __asm__ __volatile__ ( \
d77c26fc 451 _PRE_EFLAGS("0", "4", "2") \
6aa8b732 452 _op"q %"_qx"3,%1; " \
d77c26fc 453 _POST_EFLAGS("0", "4", "2") \
6aa8b732 454 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
d77c26fc 455 : _qy ((_src).val), "i" (EFLAGS_MASK)); \
6aa8b732
AK		 456 } while (0)
457
458#define __emulate_1op_8byte(_op, _dst, _eflags) \
459 do { \
460 __asm__ __volatile__ ( \
d77c26fc 461 _PRE_EFLAGS("0", "3", "2") \
6aa8b732 462 _op"q %1; " \
d77c26fc 463 _POST_EFLAGS("0", "3", "2") \
6aa8b732 464 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
d77c26fc 465 : "i" (EFLAGS_MASK)); \
6aa8b732
AK		 466 } while (0)
467
468#elif defined(__i386__)
469#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
470#define __emulate_1op_8byte(_op, _dst, _eflags)
471#endif /* __i386__ */
472
473/* Fetch next part of the instruction being emulated. */
474#define insn_fetch(_type, _size, _eip) \
475({ unsigned long _x; \
62266869 476 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
d77c26fc 477 if (rc != 0) \
6aa8b732
AK		 478 goto done; \
479 (_eip) += (_size); \
480 (_type)_x; \
481})
482
ddcb2885
HH		 483static inline unsigned long ad_mask(struct decode_cache *c)
484{
485 return (1UL << (c->ad_bytes << 3)) - 1;
486}
487
6aa8b732 488/* Access/update address held in a register, based on addressing mode. */
e4706772
HH		 489static inline unsigned long
490address_mask(struct decode_cache *c, unsigned long reg)
491{
492 if (c->ad_bytes == sizeof(unsigned long))
493 return reg;
494 else
495 return reg & ad_mask(c);
496}
497
498static inline unsigned long
499register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
500{
501 return base + address_mask(c, reg);
502}
503
6aa8b732
AK		 504#define register_address_increment(reg, inc) \
505 do { \
506 /* signed type ensures sign extension to long */ \
507 int _inc = (inc); \
e4e03ded 508 if (c->ad_bytes == sizeof(unsigned long)) \
6aa8b732
AK		 509 (reg) += _inc; \
510 else \
e4e03ded 511 (reg) = ((reg) & \
ddcb2885 512 ~ad_mask(c)) | \
e4e03ded 513 (((reg) + _inc) & \
ddcb2885 514 ad_mask(c)); \
6aa8b732
AK		 515 } while (0)
516
098c937b
NK		 517#define JMP_REL(rel) \
518 do { \
e4e03ded 519 register_address_increment(c->eip, rel); \
098c937b
NK		 520 } while (0)
521
62266869
AK		 522static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
523 struct x86_emulate_ops *ops,
524 unsigned long linear, u8 *dest)
525{
526 struct fetch_cache *fc = &ctxt->decode.fetch;
527 int rc;
528 int size;
529
530 if (linear < fc->start || linear >= fc->end) {
531 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
532 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
533 if (rc)
534 return rc;
535 fc->start = linear;
536 fc->end = linear + size;
537 }
538 *dest = fc->data[linear - fc->start];
539 return 0;
540}
541
542static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
543 struct x86_emulate_ops *ops,
544 unsigned long eip, void *dest, unsigned size)
545{
546 int rc = 0;
547
548 eip += ctxt->cs_base;
549 while (size--) {
550 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
551 if (rc)
552 return rc;
553 }
554 return 0;
555}
556
1e3c5cb0
RR		 557/*
558 * Given the 'reg' portion of a ModRM byte, and a register block, return a
559 * pointer into the block that addresses the relevant register.
560 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
561 */
562static void *decode_register(u8 modrm_reg, unsigned long *regs,
563 int highbyte_regs)
6aa8b732
AK		 564{
565 void *p;
566
567 p = &regs[modrm_reg];
568 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
569 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
570 return p;
571}
572
573static int read_descriptor(struct x86_emulate_ctxt *ctxt,
574 struct x86_emulate_ops *ops,
575 void *ptr,
576 u16 *size, unsigned long *address, int op_bytes)
577{
578 int rc;
579
580 if (op_bytes == 2)
581 op_bytes = 3;
582 *address = 0;
cebff02b
LV		 583 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
584 ctxt->vcpu);
6aa8b732
AK		 585 if (rc)
586 return rc;
cebff02b
LV		 587 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
588 ctxt->vcpu);
6aa8b732
AK		 589 return rc;
590}
591
bbe9abbd
NK		 592static int test_cc(unsigned int condition, unsigned int flags)
593{
594 int rc = 0;
595
596 switch ((condition & 15) >> 1) {
597 case 0: /* o */
598 rc |= (flags & EFLG_OF);
599 break;
600 case 1: /* b/c/nae */
601 rc |= (flags & EFLG_CF);
602 break;
603 case 2: /* z/e */
604 rc |= (flags & EFLG_ZF);
605 break;
606 case 3: /* be/na */
607 rc |= (flags & (EFLG_CF|EFLG_ZF));
608 break;
609 case 4: /* s */
610 rc |= (flags & EFLG_SF);
611 break;
612 case 5: /* p/pe */
613 rc |= (flags & EFLG_PF);
614 break;
615 case 7: /* le/ng */
616 rc |= (flags & EFLG_ZF);
617 /* fall through */
618 case 6: /* l/nge */
619 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
620 break;
621 }
622
623 /* Odd condition identifiers (lsb == 1) have inverted sense. */
624 return (!!rc ^ (condition & 1));
625}
626
3c118e24
AK		 627static void decode_register_operand(struct operand *op,
628 struct decode_cache *c,
3c118e24
AK		 629 int inhibit_bytereg)
630{
33615aa9 631 unsigned reg = c->modrm_reg;
9f1ef3f8 632 int highbyte_regs = c->rex_prefix == 0;
33615aa9
AK		 633
634 if (!(c->d & ModRM))
635 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
3c118e24
AK		 636 op->type = OP_REG;
637 if ((c->d & ByteOp) && !inhibit_bytereg) {
33615aa9 638 op->ptr = decode_register(reg, c->regs, highbyte_regs);
3c118e24
AK		 639 op->val = *(u8 *)op->ptr;
640 op->bytes = 1;
641 } else {
33615aa9 642 op->ptr = decode_register(reg, c->regs, 0);
3c118e24
AK		 643 op->bytes = c->op_bytes;
644 switch (op->bytes) {
645 case 2:
646 op->val = *(u16 *)op->ptr;
647 break;
648 case 4:
649 op->val = *(u32 *)op->ptr;
650 break;
651 case 8:
652 op->val = *(u64 *) op->ptr;
653 break;
654 }
655 }
656 op->orig_val = op->val;
657}
658
1c73ef66
AK		 659static int decode_modrm(struct x86_emulate_ctxt *ctxt,
660 struct x86_emulate_ops *ops)
661{
662 struct decode_cache *c = &ctxt->decode;
663 u8 sib;
664 int index_reg = 0, base_reg = 0, scale, rip_relative = 0;
665 int rc = 0;
666
667 if (c->rex_prefix) {
668 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
669 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
670 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
671 }
672
673 c->modrm = insn_fetch(u8, 1, c->eip);
674 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
675 c->modrm_reg |= (c->modrm & 0x38) >> 3;
676 c->modrm_rm |= (c->modrm & 0x07);
677 c->modrm_ea = 0;
678 c->use_modrm_ea = 1;
679
680 if (c->modrm_mod == 3) {
681 c->modrm_val = *(unsigned long *)
682 decode_register(c->modrm_rm, c->regs, c->d & ByteOp);
683 return rc;
684 }
685
686 if (c->ad_bytes == 2) {
687 unsigned bx = c->regs[VCPU_REGS_RBX];
688 unsigned bp = c->regs[VCPU_REGS_RBP];
689 unsigned si = c->regs[VCPU_REGS_RSI];
690 unsigned di = c->regs[VCPU_REGS_RDI];
691
692 /* 16-bit ModR/M decode. */
693 switch (c->modrm_mod) {
694 case 0:
695 if (c->modrm_rm == 6)
696 c->modrm_ea += insn_fetch(u16, 2, c->eip);
697 break;
698 case 1:
699 c->modrm_ea += insn_fetch(s8, 1, c->eip);
700 break;
701 case 2:
702 c->modrm_ea += insn_fetch(u16, 2, c->eip);
703 break;
704 }
705 switch (c->modrm_rm) {
706 case 0:
707 c->modrm_ea += bx + si;
708 break;
709 case 1:
710 c->modrm_ea += bx + di;
711 break;
712 case 2:
713 c->modrm_ea += bp + si;
714 break;
715 case 3:
716 c->modrm_ea += bp + di;
717 break;
718 case 4:
719 c->modrm_ea += si;
720 break;
721 case 5:
722 c->modrm_ea += di;
723 break;
724 case 6:
725 if (c->modrm_mod != 0)
726 c->modrm_ea += bp;
727 break;
728 case 7:
729 c->modrm_ea += bx;
730 break;
731 }
732 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
733 (c->modrm_rm == 6 && c->modrm_mod != 0))
734 if (!c->override_base)
735 c->override_base = &ctxt->ss_base;
736 c->modrm_ea = (u16)c->modrm_ea;
737 } else {
738 /* 32/64-bit ModR/M decode. */
739 switch (c->modrm_rm) {
740 case 4:
741 case 12:
742 sib = insn_fetch(u8, 1, c->eip);
743 index_reg |= (sib >> 3) & 7;
744 base_reg |= sib & 7;
745 scale = sib >> 6;
746
747 switch (base_reg) {
748 case 5:
749 if (c->modrm_mod != 0)
750 c->modrm_ea += c->regs[base_reg];
751 else
752 c->modrm_ea +=
753 insn_fetch(s32, 4, c->eip);
754 break;
755 default:
756 c->modrm_ea += c->regs[base_reg];
757 }
758 switch (index_reg) {
759 case 4:
760 break;
761 default:
762 c->modrm_ea += c->regs[index_reg] << scale;
763 }
764 break;
765 case 5:
766 if (c->modrm_mod != 0)
767 c->modrm_ea += c->regs[c->modrm_rm];
768 else if (ctxt->mode == X86EMUL_MODE_PROT64)
769 rip_relative = 1;
770 break;
771 default:
772 c->modrm_ea += c->regs[c->modrm_rm];
773 break;
774 }
775 switch (c->modrm_mod) {
776 case 0:
777 if (c->modrm_rm == 5)
778 c->modrm_ea += insn_fetch(s32, 4, c->eip);
779 break;
780 case 1:
781 c->modrm_ea += insn_fetch(s8, 1, c->eip);
782 break;
783 case 2:
784 c->modrm_ea += insn_fetch(s32, 4, c->eip);
785 break;
786 }
787 }
788 if (rip_relative) {
789 c->modrm_ea += c->eip;
790 switch (c->d & SrcMask) {
791 case SrcImmByte:
792 c->modrm_ea += 1;
793 break;
794 case SrcImm:
795 if (c->d & ByteOp)
796 c->modrm_ea += 1;
797 else
798 if (c->op_bytes == 8)
799 c->modrm_ea += 4;
800 else
801 c->modrm_ea += c->op_bytes;
802 }
803 }
804done:
805 return rc;
806}
807
808static int decode_abs(struct x86_emulate_ctxt *ctxt,
809 struct x86_emulate_ops *ops)
810{
811 struct decode_cache *c = &ctxt->decode;
812 int rc = 0;
813
814 switch (c->ad_bytes) {
815 case 2:
816 c->modrm_ea = insn_fetch(u16, 2, c->eip);
817 break;
818 case 4:
819 c->modrm_ea = insn_fetch(u32, 4, c->eip);
820 break;
821 case 8:
822 c->modrm_ea = insn_fetch(u64, 8, c->eip);
823 break;
824 }
825done:
826 return rc;
827}
828
6aa8b732 829int
8b4caf66 830x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 831{
e4e03ded 832 struct decode_cache *c = &ctxt->decode;
6aa8b732 833 int rc = 0;
6aa8b732 834 int mode = ctxt->mode;
e09d082c 835 int def_op_bytes, def_ad_bytes, group;
6aa8b732
AK		 836
837 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 838
e4e03ded 839 memset(c, 0, sizeof(struct decode_cache));
ad312c7c
ZX		 840 c->eip = ctxt->vcpu->arch.rip;
841 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
6aa8b732
AK		 842
843 switch (mode) {
844 case X86EMUL_MODE_REAL:
845 case X86EMUL_MODE_PROT16:
f21b8bf4 846 def_op_bytes = def_ad_bytes = 2;
6aa8b732
AK		 847 break;
848 case X86EMUL_MODE_PROT32:
f21b8bf4 849 def_op_bytes = def_ad_bytes = 4;
6aa8b732 850 break;
05b3e0c2 851#ifdef CONFIG_X86_64
6aa8b732 852 case X86EMUL_MODE_PROT64:
f21b8bf4
AK		 853 def_op_bytes = 4;
854 def_ad_bytes = 8;
6aa8b732
AK		 855 break;
856#endif
857 default:
858 return -1;
859 }
860
f21b8bf4
AK		 861 c->op_bytes = def_op_bytes;
862 c->ad_bytes = def_ad_bytes;
863
6aa8b732 864 /* Legacy prefixes. */
b4c6abfe 865 for (;;) {
e4e03ded 866 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 867 case 0x66: /* operand-size override */
f21b8bf4
AK		 868 /* switch between 2/4 bytes */
869 c->op_bytes = def_op_bytes ^ 6;
6aa8b732
AK		 870 break;
871 case 0x67: /* address-size override */
872 if (mode == X86EMUL_MODE_PROT64)
e4e03ded 873 /* switch between 4/8 bytes */
f21b8bf4 874 c->ad_bytes = def_ad_bytes ^ 12;
6aa8b732 875 else
e4e03ded 876 /* switch between 2/4 bytes */
f21b8bf4 877 c->ad_bytes = def_ad_bytes ^ 6;
6aa8b732
AK		 878 break;
879 case 0x2e: /* CS override */
e4e03ded 880 c->override_base = &ctxt->cs_base;
6aa8b732
AK		 881 break;
882 case 0x3e: /* DS override */
e4e03ded 883 c->override_base = &ctxt->ds_base;
6aa8b732
AK		 884 break;
885 case 0x26: /* ES override */
e4e03ded 886 c->override_base = &ctxt->es_base;
6aa8b732
AK		 887 break;
888 case 0x64: /* FS override */
e4e03ded 889 c->override_base = &ctxt->fs_base;
6aa8b732
AK		 890 break;
891 case 0x65: /* GS override */
e4e03ded 892 c->override_base = &ctxt->gs_base;
6aa8b732
AK		 893 break;
894 case 0x36: /* SS override */
e4e03ded 895 c->override_base = &ctxt->ss_base;
6aa8b732 896 break;
b4c6abfe
LV		 897 case 0x40 ... 0x4f: /* REX */
898 if (mode != X86EMUL_MODE_PROT64)
899 goto done_prefixes;
33615aa9 900 c->rex_prefix = c->b;
b4c6abfe 901 continue;
6aa8b732 902 case 0xf0: /* LOCK */
e4e03ded 903 c->lock_prefix = 1;
6aa8b732 904 break;
ae6200ba 905 case 0xf2: /* REPNE/REPNZ */
90e0a28f
GT		 906 c->rep_prefix = REPNE_PREFIX;
907 break;
6aa8b732 908 case 0xf3: /* REP/REPE/REPZ */
90e0a28f 909 c->rep_prefix = REPE_PREFIX;
6aa8b732 910 break;
6aa8b732
AK		 911 default:
912 goto done_prefixes;
913 }
b4c6abfe
LV		 914
915 /* Any legacy prefix after a REX prefix nullifies its effect. */
916
33615aa9 917 c->rex_prefix = 0;
6aa8b732
AK		 918 }
919
920done_prefixes:
921
922 /* REX prefix. */
1c73ef66 923 if (c->rex_prefix)
33615aa9 924 if (c->rex_prefix & 8)
e4e03ded 925 c->op_bytes = 8; /* REX.W */
6aa8b732
AK		 926
927 /* Opcode byte(s). */
e4e03ded
LV		 928 c->d = opcode_table[c->b];
929 if (c->d == 0) {
6aa8b732 930 /* Two-byte opcode? */
e4e03ded
LV		 931 if (c->b == 0x0f) {
932 c->twobyte = 1;
933 c->b = insn_fetch(u8, 1, c->eip);
934 c->d = twobyte_table[c->b];
6aa8b732 935 }
e09d082c 936 }
6aa8b732 937
e09d082c
AK		 938 if (c->d & Group) {
939 group = c->d & GroupMask;
940 c->modrm = insn_fetch(u8, 1, c->eip);
941 --c->eip;
942
943 group = (group << 3) + ((c->modrm >> 3) & 7);
944 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
945 c->d = group2_table[group];
946 else
947 c->d = group_table[group];
948 }
949
950 /* Unrecognised? */
951 if (c->d == 0) {
952 DPRINTF("Cannot emulate %02x\n", c->b);
953 return -1;
6aa8b732
AK		 954 }
955
6e3d5dfb
AK		 956 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
957 c->op_bytes = 8;
958
6aa8b732 959 /* ModRM and SIB bytes. */
1c73ef66
AK		 960 if (c->d & ModRM)
961 rc = decode_modrm(ctxt, ops);
962 else if (c->d & MemAbs)
963 rc = decode_abs(ctxt, ops);
964 if (rc)
965 goto done;
6aa8b732 966
c7e75a3d
AK		 967 if (!c->override_base)
968 c->override_base = &ctxt->ds_base;
969 if (mode == X86EMUL_MODE_PROT64 &&
970 c->override_base != &ctxt->fs_base &&
971 c->override_base != &ctxt->gs_base)
972 c->override_base = NULL;
973
974 if (c->override_base)
975 c->modrm_ea += *c->override_base;
976
977 if (c->ad_bytes != 8)
978 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 979 /*
980 * Decode and fetch the source operand: register, memory
981 * or immediate.
982 */
e4e03ded 983 switch (c->d & SrcMask) {
6aa8b732
AK		 984 case SrcNone:
985 break;
986 case SrcReg:
9f1ef3f8 987 decode_register_operand(&c->src, c, 0);
6aa8b732
AK		 988 break;
989 case SrcMem16:
e4e03ded 990 c->src.bytes = 2;
6aa8b732
AK		 991 goto srcmem_common;
992 case SrcMem32:
e4e03ded 993 c->src.bytes = 4;
6aa8b732
AK		 994 goto srcmem_common;
995 case SrcMem:
e4e03ded
LV		 996 c->src.bytes = (c->d & ByteOp) ? 1 :
997 c->op_bytes;
b85b9ee9 998 /* Don't fetch the address for invlpg: it could be unmapped. */
d77c26fc 999 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
b85b9ee9 1000 break;
d77c26fc 1001 srcmem_common:
4e62417b
AJ		 1002 /*
1003 * For instructions with a ModR/M byte, switch to register
1004 * access if Mod = 3.
1005 */
e4e03ded
LV		 1006 if ((c->d & ModRM) && c->modrm_mod == 3) {
1007 c->src.type = OP_REG;
4e62417b
AJ		 1008 break;
1009 }
e4e03ded 1010 c->src.type = OP_MEM;
6aa8b732
AK		 1011 break;
1012 case SrcImm:
e4e03ded
LV		 1013 c->src.type = OP_IMM;
1014 c->src.ptr = (unsigned long *)c->eip;
1015 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1016 if (c->src.bytes == 8)
1017 c->src.bytes = 4;
6aa8b732 1018 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 1019 switch (c->src.bytes) {
6aa8b732 1020 case 1:
e4e03ded 1021 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1022 break;
1023 case 2:
e4e03ded 1024 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1025 break;
1026 case 4:
e4e03ded 1027 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1028 break;
1029 }
1030 break;
1031 case SrcImmByte:
e4e03ded
LV		 1032 c->src.type = OP_IMM;
1033 c->src.ptr = (unsigned long *)c->eip;
1034 c->src.bytes = 1;
1035 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1036 break;
1037 }
1038
038e51de 1039 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 1040 switch (c->d & DstMask) {
038e51de
AK		 1041 case ImplicitOps:
1042 /* Special instructions do their own operand decoding. */
8b4caf66 1043 return 0;
038e51de 1044 case DstReg:
9f1ef3f8 1045 decode_register_operand(&c->dst, c,
3c118e24 1046 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
038e51de
AK		 1047 break;
1048 case DstMem:
e4e03ded
LV		 1049 if ((c->d & ModRM) && c->modrm_mod == 3) {
1050 c->dst.type = OP_REG;
4e62417b
AJ		 1051 break;
1052 }
8b4caf66
LV		 1053 c->dst.type = OP_MEM;
1054 break;
1055 }
1056
1057done:
1058 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1059}
1060
8cdbd2c9
LV		 1061static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1062{
1063 struct decode_cache *c = &ctxt->decode;
1064
1065 c->dst.type = OP_MEM;
1066 c->dst.bytes = c->op_bytes;
1067 c->dst.val = c->src.val;
1068 register_address_increment(c->regs[VCPU_REGS_RSP], -c->op_bytes);
e4706772 1069 c->dst.ptr = (void *) register_address(c, ctxt->ss_base,
8cdbd2c9
LV		 1070 c->regs[VCPU_REGS_RSP]);
1071}
1072
1073static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1074 struct x86_emulate_ops *ops)
1075{
1076 struct decode_cache *c = &ctxt->decode;
1077 int rc;
1078
e4706772 1079 rc = ops->read_std(register_address(c, ctxt->ss_base,
8cdbd2c9
LV		 1080 c->regs[VCPU_REGS_RSP]),
1081 &c->dst.val, c->dst.bytes, ctxt->vcpu);
1082 if (rc != 0)
1083 return rc;
1084
1085 register_address_increment(c->regs[VCPU_REGS_RSP], c->dst.bytes);
1086
1087 return 0;
1088}
1089
05f086f8 1090static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 1091{
05f086f8 1092 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1093 switch (c->modrm_reg) {
1094 case 0: /* rol */
05f086f8 1095 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1096 break;
1097 case 1: /* ror */
05f086f8 1098 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1099 break;
1100 case 2: /* rcl */
05f086f8 1101 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1102 break;
1103 case 3: /* rcr */
05f086f8 1104 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1105 break;
1106 case 4: /* sal/shl */
1107 case 6: /* sal/shl */
05f086f8 1108 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1109 break;
1110 case 5: /* shr */
05f086f8 1111 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1112 break;
1113 case 7: /* sar */
05f086f8 1114 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1115 break;
1116 }
1117}
1118
1119static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 1120 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1121{
1122 struct decode_cache *c = &ctxt->decode;
1123 int rc = 0;
1124
1125 switch (c->modrm_reg) {
1126 case 0 ... 1: /* test */
05f086f8 1127 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1128 break;
1129 case 2: /* not */
1130 c->dst.val = ~c->dst.val;
1131 break;
1132 case 3: /* neg */
05f086f8 1133 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1134 break;
1135 default:
1136 DPRINTF("Cannot emulate %02x\n", c->b);
1137 rc = X86EMUL_UNHANDLEABLE;
1138 break;
1139 }
8cdbd2c9
LV		 1140 return rc;
1141}
1142
1143static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1144 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1145{
1146 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 1147
1148 switch (c->modrm_reg) {
1149 case 0: /* inc */
05f086f8 1150 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1151 break;
1152 case 1: /* dec */
05f086f8 1153 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1154 break;
1155 case 4: /* jmp abs */
fd60754e 1156 c->eip = c->src.val;
8cdbd2c9
LV		 1157 break;
1158 case 6: /* push */
fd60754e 1159 emulate_push(ctxt);
8cdbd2c9 1160 break;
8cdbd2c9
LV		 1161 }
1162 return 0;
1163}
1164
1165static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1166 struct x86_emulate_ops *ops,
e8d8d7fe 1167 unsigned long memop)
8cdbd2c9
LV		 1168{
1169 struct decode_cache *c = &ctxt->decode;
1170 u64 old, new;
1171 int rc;
1172
e8d8d7fe 1173 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
8cdbd2c9
LV		 1174 if (rc != 0)
1175 return rc;
1176
1177 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1178 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1179
1180 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1181 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1182 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1183
1184 } else {
1185 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1186 (u32) c->regs[VCPU_REGS_RBX];
1187
e8d8d7fe 1188 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
8cdbd2c9
LV		 1189 if (rc != 0)
1190 return rc;
05f086f8 1191 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1192 }
1193 return 0;
1194}
1195
1196static inline int writeback(struct x86_emulate_ctxt *ctxt,
1197 struct x86_emulate_ops *ops)
1198{
1199 int rc;
1200 struct decode_cache *c = &ctxt->decode;
1201
1202 switch (c->dst.type) {
1203 case OP_REG:
1204 /* The 4-byte case *is* correct:
1205 * in 64-bit mode we zero-extend.
1206 */
1207 switch (c->dst.bytes) {
1208 case 1:
1209 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1210 break;
1211 case 2:
1212 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1213 break;
1214 case 4:
1215 *c->dst.ptr = (u32)c->dst.val;
1216 break; /* 64b: zero-ext */
1217 case 8:
1218 *c->dst.ptr = c->dst.val;
1219 break;
1220 }
1221 break;
1222 case OP_MEM:
1223 if (c->lock_prefix)
1224 rc = ops->cmpxchg_emulated(
1225 (unsigned long)c->dst.ptr,
1226 &c->dst.orig_val,
1227 &c->dst.val,
1228 c->dst.bytes,
1229 ctxt->vcpu);
1230 else
1231 rc = ops->write_emulated(
1232 (unsigned long)c->dst.ptr,
1233 &c->dst.val,
1234 c->dst.bytes,
1235 ctxt->vcpu);
1236 if (rc != 0)
1237 return rc;
a01af5ec
LV		 1238 break;
1239 case OP_NONE:
1240 /* no writeback */
1241 break;
8cdbd2c9
LV		 1242 default:
1243 break;
1244 }
1245 return 0;
1246}
1247
8b4caf66 1248int
1be3aa47 1249x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66 1250{
e8d8d7fe 1251 unsigned long memop = 0;
8b4caf66 1252 u64 msr_data;
3427318f 1253 unsigned long saved_eip = 0;
8b4caf66 1254 struct decode_cache *c = &ctxt->decode;
1be3aa47 1255 int rc = 0;
8b4caf66 1256
3427318f
LV		 1257 /* Shadow copy of register state. Committed on successful emulation.
1258 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1259 * modify them.
1260 */
1261
ad312c7c 1262 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
3427318f
LV		 1263 saved_eip = c->eip;
1264
c7e75a3d 1265 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
e8d8d7fe 1266 memop = c->modrm_ea;
8b4caf66 1267
b9fa9d6b
AK		 1268 if (c->rep_prefix && (c->d & String)) {
1269 /* All REP prefixes have the same first termination condition */
1270 if (c->regs[VCPU_REGS_RCX] == 0) {
ad312c7c 1271 ctxt->vcpu->arch.rip = c->eip;
b9fa9d6b
AK		 1272 goto done;
1273 }
1274 /* The second termination condition only applies for REPE
1275 * and REPNE. Test if the repeat string operation prefix is
1276 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1277 * corresponding termination condition according to:
1278 * - if REPE/REPZ and ZF = 0 then done
1279 * - if REPNE/REPNZ and ZF = 1 then done
1280 */
1281 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1282 (c->b == 0xae) || (c->b == 0xaf)) {
1283 if ((c->rep_prefix == REPE_PREFIX) &&
1284 ((ctxt->eflags & EFLG_ZF) == 0)) {
ad312c7c 1285 ctxt->vcpu->arch.rip = c->eip;
b9fa9d6b
AK		 1286 goto done;
1287 }
1288 if ((c->rep_prefix == REPNE_PREFIX) &&
1289 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
ad312c7c 1290 ctxt->vcpu->arch.rip = c->eip;
b9fa9d6b
AK		 1291 goto done;
1292 }
1293 }
1294 c->regs[VCPU_REGS_RCX]--;
ad312c7c 1295 c->eip = ctxt->vcpu->arch.rip;
b9fa9d6b
AK		 1296 }
1297
8b4caf66 1298 if (c->src.type == OP_MEM) {
e8d8d7fe 1299 c->src.ptr = (unsigned long *)memop;
8b4caf66 1300 c->src.val = 0;
d77c26fc
MD		 1301 rc = ops->read_emulated((unsigned long)c->src.ptr,
1302 &c->src.val,
1303 c->src.bytes,
1304 ctxt->vcpu);
1305 if (rc != 0)
8b4caf66
LV		 1306 goto done;
1307 c->src.orig_val = c->src.val;
1308 }
1309
1310 if ((c->d & DstMask) == ImplicitOps)
1311 goto special_insn;
1312
1313
1314 if (c->dst.type == OP_MEM) {
e8d8d7fe 1315 c->dst.ptr = (unsigned long *)memop;
8b4caf66
LV		 1316 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1317 c->dst.val = 0;
e4e03ded
LV		 1318 if (c->d & BitOp) {
1319 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1320
e4e03ded
LV		 1321 c->dst.ptr = (void *)c->dst.ptr +
1322 (c->src.val & mask) / 8;
038e51de 1323 }
e4e03ded
LV		 1324 if (!(c->d & Mov) &&
1325 /* optimisation - avoid slow emulated read */
1326 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1327 &c->dst.val,
1328 c->dst.bytes, ctxt->vcpu)) != 0))
038e51de 1329 goto done;
038e51de 1330 }
e4e03ded 1331 c->dst.orig_val = c->dst.val;
038e51de 1332
018a98db
AK		 1333special_insn:
1334
e4e03ded 1335 if (c->twobyte)
6aa8b732
AK		 1336 goto twobyte_insn;
1337
e4e03ded 1338 switch (c->b) {
6aa8b732
AK		 1339 case 0x00 ... 0x05:
1340 add: /* add */
05f086f8 1341 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1342 break;
1343 case 0x08 ... 0x0d:
1344 or: /* or */
05f086f8 1345 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1346 break;
1347 case 0x10 ... 0x15:
1348 adc: /* adc */
05f086f8 1349 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1350 break;
1351 case 0x18 ... 0x1d:
1352 sbb: /* sbb */
05f086f8 1353 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1354 break;
19eb938e 1355 case 0x20 ... 0x23:
6aa8b732 1356 and: /* and */
05f086f8 1357 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732 1358 break;
19eb938e 1359 case 0x24: /* and al imm8 */
e4e03ded
LV		 1360 c->dst.type = OP_REG;
1361 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1362 c->dst.val = *(u8 *)c->dst.ptr;
1363 c->dst.bytes = 1;
1364 c->dst.orig_val = c->dst.val;
19eb938e
NK		 1365 goto and;
1366 case 0x25: /* and ax imm16, or eax imm32 */
e4e03ded
LV		 1367 c->dst.type = OP_REG;
1368 c->dst.bytes = c->op_bytes;
1369 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1370 if (c->op_bytes == 2)
1371 c->dst.val = *(u16 *)c->dst.ptr;
19eb938e 1372 else
e4e03ded
LV		 1373 c->dst.val = *(u32 *)c->dst.ptr;
1374 c->dst.orig_val = c->dst.val;
19eb938e 1375 goto and;
6aa8b732
AK		 1376 case 0x28 ... 0x2d:
1377 sub: /* sub */
05f086f8 1378 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1379 break;
1380 case 0x30 ... 0x35:
1381 xor: /* xor */
05f086f8 1382 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1383 break;
1384 case 0x38 ... 0x3d:
1385 cmp: /* cmp */
05f086f8 1386 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732 1387 break;
33615aa9
AK		 1388 case 0x40 ... 0x47: /* inc r16/r32 */
1389 emulate_1op("inc", c->dst, ctxt->eflags);
1390 break;
1391 case 0x48 ... 0x4f: /* dec r16/r32 */
1392 emulate_1op("dec", c->dst, ctxt->eflags);
1393 break;
1394 case 0x50 ... 0x57: /* push reg */
1395 c->dst.type = OP_MEM;
1396 c->dst.bytes = c->op_bytes;
1397 c->dst.val = c->src.val;
1398 register_address_increment(c->regs[VCPU_REGS_RSP],
1399 -c->op_bytes);
1400 c->dst.ptr = (void *) register_address(
e4706772 1401 c, ctxt->ss_base, c->regs[VCPU_REGS_RSP]);
33615aa9
AK		 1402 break;
1403 case 0x58 ... 0x5f: /* pop reg */
1404 pop_instruction:
e4706772 1405 if ((rc = ops->read_std(register_address(c, ctxt->ss_base,
33615aa9
AK		 1406 c->regs[VCPU_REGS_RSP]), c->dst.ptr,
1407 c->op_bytes, ctxt->vcpu)) != 0)
1408 goto done;
1409
1410 register_address_increment(c->regs[VCPU_REGS_RSP],
1411 c->op_bytes);
1412 c->dst.type = OP_NONE; /* Disable writeback. */
1413 break;
6aa8b732 1414 case 0x63: /* movsxd */
8b4caf66 1415 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1416 goto cannot_emulate;
e4e03ded 1417 c->dst.val = (s32) c->src.val;
6aa8b732 1418 break;
018a98db
AK		 1419 case 0x6a: /* push imm8 */
1420 c->src.val = 0L;
1421 c->src.val = insn_fetch(s8, 1, c->eip);
1422 emulate_push(ctxt);
1423 break;
1424 case 0x6c: /* insb */
1425 case 0x6d: /* insw/insd */
1426 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1427 1,
1428 (c->d & ByteOp) ? 1 : c->op_bytes,
1429 c->rep_prefix ?
e4706772 1430 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1431 (ctxt->eflags & EFLG_DF),
e4706772 1432 register_address(c, ctxt->es_base,
018a98db
AK		 1433 c->regs[VCPU_REGS_RDI]),
1434 c->rep_prefix,
1435 c->regs[VCPU_REGS_RDX]) == 0) {
1436 c->eip = saved_eip;
1437 return -1;
1438 }
1439 return 0;
1440 case 0x6e: /* outsb */
1441 case 0x6f: /* outsw/outsd */
1442 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1443 0,
1444 (c->d & ByteOp) ? 1 : c->op_bytes,
1445 c->rep_prefix ?
e4706772 1446 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
018a98db 1447 (ctxt->eflags & EFLG_DF),
e4706772 1448 register_address(c, c->override_base ?
018a98db
AK		 1449 *c->override_base :
1450 ctxt->ds_base,
1451 c->regs[VCPU_REGS_RSI]),
1452 c->rep_prefix,
1453 c->regs[VCPU_REGS_RDX]) == 0) {
1454 c->eip = saved_eip;
1455 return -1;
1456 }
1457 return 0;
1458 case 0x70 ... 0x7f: /* jcc (short) */ {
1459 int rel = insn_fetch(s8, 1, c->eip);
1460
1461 if (test_cc(c->b, ctxt->eflags))
1462 JMP_REL(rel);
1463 break;
1464 }
6aa8b732 1465 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 1466 switch (c->modrm_reg) {
6aa8b732
AK		 1467 case 0:
1468 goto add;
1469 case 1:
1470 goto or;
1471 case 2:
1472 goto adc;
1473 case 3:
1474 goto sbb;
1475 case 4:
1476 goto and;
1477 case 5:
1478 goto sub;
1479 case 6:
1480 goto xor;
1481 case 7:
1482 goto cmp;
1483 }
1484 break;
1485 case 0x84 ... 0x85:
05f086f8 1486 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1487 break;
1488 case 0x86 ... 0x87: /* xchg */
1489 /* Write back the register source. */
e4e03ded 1490 switch (c->dst.bytes) {
6aa8b732 1491 case 1:
e4e03ded 1492 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 1493 break;
1494 case 2:
e4e03ded 1495 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 1496 break;
1497 case 4:
e4e03ded 1498 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 1499 break; /* 64b reg: zero-extend */
1500 case 8:
e4e03ded 1501 *c->src.ptr = c->dst.val;
6aa8b732
AK		 1502 break;
1503 }
1504 /*
1505 * Write back the memory destination with implicit LOCK
1506 * prefix.
1507 */
e4e03ded
LV		 1508 c->dst.val = c->src.val;
1509 c->lock_prefix = 1;
6aa8b732 1510 break;
6aa8b732 1511 case 0x88 ... 0x8b: /* mov */
7de75248 1512 goto mov;
7e0b54b1 1513 case 0x8d: /* lea r16/r32, m */
e4e03ded 1514 c->dst.val = c->modrm_val;
7e0b54b1 1515 break;
6aa8b732 1516 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 1517 rc = emulate_grp1a(ctxt, ops);
1518 if (rc != 0)
6aa8b732 1519 goto done;
6aa8b732 1520 break;
fd2a7608 1521 case 0x9c: /* pushf */
05f086f8 1522 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 1523 emulate_push(ctxt);
1524 break;
535eabcf 1525 case 0x9d: /* popf */
05f086f8 1526 c->dst.ptr = (unsigned long *) &ctxt->eflags;
535eabcf 1527 goto pop_instruction;
018a98db
AK		 1528 case 0xa0 ... 0xa1: /* mov */
1529 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1530 c->dst.val = c->src.val;
1531 break;
1532 case 0xa2 ... 0xa3: /* mov */
1533 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1534 break;
6aa8b732 1535 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 1536 c->dst.type = OP_MEM;
1537 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1538 c->dst.ptr = (unsigned long *)register_address(c,
e4e03ded
LV		 1539 ctxt->es_base,
1540 c->regs[VCPU_REGS_RDI]);
e4706772 1541 if ((rc = ops->read_emulated(register_address(c,
e4e03ded
LV		 1542 c->override_base ? *c->override_base :
1543 ctxt->ds_base,
1544 c->regs[VCPU_REGS_RSI]),
1545 &c->dst.val,
1546 c->dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1547 goto done;
e4e03ded 1548 register_address_increment(c->regs[VCPU_REGS_RSI],
05f086f8 1549 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded
LV		 1550 : c->dst.bytes);
1551 register_address_increment(c->regs[VCPU_REGS_RDI],
05f086f8 1552 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1553 : c->dst.bytes);
6aa8b732
AK		 1554 break;
1555 case 0xa6 ... 0xa7: /* cmps */
d7e5117a
GT		 1556 c->src.type = OP_NONE; /* Disable writeback. */
1557 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1558 c->src.ptr = (unsigned long *)register_address(c,
d7e5117a
GT		 1559 c->override_base ? *c->override_base :
1560 ctxt->ds_base,
1561 c->regs[VCPU_REGS_RSI]);
1562 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1563 &c->src.val,
1564 c->src.bytes,
1565 ctxt->vcpu)) != 0)
1566 goto done;
1567
1568 c->dst.type = OP_NONE; /* Disable writeback. */
1569 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1570 c->dst.ptr = (unsigned long *)register_address(c,
d7e5117a
GT		 1571 ctxt->es_base,
1572 c->regs[VCPU_REGS_RDI]);
1573 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1574 &c->dst.val,
1575 c->dst.bytes,
1576 ctxt->vcpu)) != 0)
1577 goto done;
1578
1579 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1580
1581 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1582
1583 register_address_increment(c->regs[VCPU_REGS_RSI],
1584 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1585 : c->src.bytes);
1586 register_address_increment(c->regs[VCPU_REGS_RDI],
1587 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1588 : c->dst.bytes);
1589
1590 break;
6aa8b732 1591 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 1592 c->dst.type = OP_MEM;
1593 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
e4706772 1594 c->dst.ptr = (unsigned long *)register_address(c,
a7e6c88a
SY		 1595 ctxt->es_base,
1596 c->regs[VCPU_REGS_RDI]);
e4e03ded
LV		 1597 c->dst.val = c->regs[VCPU_REGS_RAX];
1598 register_address_increment(c->regs[VCPU_REGS_RDI],
05f086f8 1599 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1600 : c->dst.bytes);
6aa8b732
AK		 1601 break;
1602 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 1603 c->dst.type = OP_REG;
1604 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1605 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
e4706772 1606 if ((rc = ops->read_emulated(register_address(c,
a7e6c88a
SY		 1607 c->override_base ? *c->override_base :
1608 ctxt->ds_base,
1609 c->regs[VCPU_REGS_RSI]),
1610 &c->dst.val,
1611 c->dst.bytes,
1612 ctxt->vcpu)) != 0)
6aa8b732 1613 goto done;
e4e03ded 1614 register_address_increment(c->regs[VCPU_REGS_RSI],
05f086f8 1615 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1616 : c->dst.bytes);
6aa8b732
AK		 1617 break;
1618 case 0xae ... 0xaf: /* scas */
1619 DPRINTF("Urk! I don't handle SCAS.\n");
1620 goto cannot_emulate;
018a98db
AK		 1621 case 0xc0 ... 0xc1:
1622 emulate_grp2(ctxt);
1623 break;
111de5d6
AK		 1624 case 0xc3: /* ret */
1625 c->dst.ptr = &c->eip;
1626 goto pop_instruction;
018a98db
AK		 1627 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1628 mov:
1629 c->dst.val = c->src.val;
1630 break;
1631 case 0xd0 ... 0xd1: /* Grp2 */
1632 c->src.val = 1;
1633 emulate_grp2(ctxt);
1634 break;
1635 case 0xd2 ... 0xd3: /* Grp2 */
1636 c->src.val = c->regs[VCPU_REGS_RCX];
1637 emulate_grp2(ctxt);
1638 break;
1a52e051
NK		 1639 case 0xe8: /* call (near) */ {
1640 long int rel;
e4e03ded 1641 switch (c->op_bytes) {
1a52e051 1642 case 2:
e4e03ded 1643 rel = insn_fetch(s16, 2, c->eip);
1a52e051
NK		 1644 break;
1645 case 4:
e4e03ded 1646 rel = insn_fetch(s32, 4, c->eip);
1a52e051 1647 break;
1a52e051
NK		 1648 default:
1649 DPRINTF("Call: Invalid op_bytes\n");
1650 goto cannot_emulate;
1651 }
e4e03ded 1652 c->src.val = (unsigned long) c->eip;
1a52e051 1653 JMP_REL(rel);
e4e03ded 1654 c->op_bytes = c->ad_bytes;
8cdbd2c9
LV		 1655 emulate_push(ctxt);
1656 break;
1a52e051
NK		 1657 }
1658 case 0xe9: /* jmp rel */
1659 case 0xeb: /* jmp rel short */
e4e03ded 1660 JMP_REL(c->src.val);
a01af5ec 1661 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051 1662 break;
111de5d6 1663 case 0xf4: /* hlt */
ad312c7c 1664 ctxt->vcpu->arch.halt_request = 1;
111de5d6
AK		 1665 goto done;
1666 case 0xf5: /* cmc */
1667 /* complement carry flag from eflags reg */
1668 ctxt->eflags ^= EFLG_CF;
1669 c->dst.type = OP_NONE; /* Disable writeback. */
1670 break;
018a98db
AK		 1671 case 0xf6 ... 0xf7: /* Grp3 */
1672 rc = emulate_grp3(ctxt, ops);
1673 if (rc != 0)
1674 goto done;
1675 break;
111de5d6
AK		 1676 case 0xf8: /* clc */
1677 ctxt->eflags &= ~EFLG_CF;
1678 c->dst.type = OP_NONE; /* Disable writeback. */
1679 break;
1680 case 0xfa: /* cli */
1681 ctxt->eflags &= ~X86_EFLAGS_IF;
1682 c->dst.type = OP_NONE; /* Disable writeback. */
1683 break;
1684 case 0xfb: /* sti */
1685 ctxt->eflags |= X86_EFLAGS_IF;
1686 c->dst.type = OP_NONE; /* Disable writeback. */
1687 break;
018a98db
AK		 1688 case 0xfe ... 0xff: /* Grp4/Grp5 */
1689 rc = emulate_grp45(ctxt, ops);
1690 if (rc != 0)
1691 goto done;
1692 break;
6aa8b732 1693 }
018a98db
AK		 1694
1695writeback:
1696 rc = writeback(ctxt, ops);
1697 if (rc != 0)
1698 goto done;
1699
1700 /* Commit shadow register state. */
ad312c7c
ZX		 1701 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
1702 ctxt->vcpu->arch.rip = c->eip;
018a98db
AK		 1703
1704done:
1705 if (rc == X86EMUL_UNHANDLEABLE) {
1706 c->eip = saved_eip;
1707 return -1;
1708 }
1709 return 0;
6aa8b732
AK		 1710
1711twobyte_insn:
e4e03ded 1712 switch (c->b) {
6aa8b732 1713 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 1714 switch (c->modrm_reg) {
6aa8b732
AK		 1715 u16 size;
1716 unsigned long address;
1717
aca7f966 1718 case 0: /* vmcall */
e4e03ded 1719 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 1720 goto cannot_emulate;
1721
7aa81cc0
AL		 1722 rc = kvm_fix_hypercall(ctxt->vcpu);
1723 if (rc)
1724 goto done;
1725
1726 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1727 break;
6aa8b732 1728 case 2: /* lgdt */
e4e03ded
LV		 1729 rc = read_descriptor(ctxt, ops, c->src.ptr,
1730 &size, &address, c->op_bytes);
6aa8b732
AK		 1731 if (rc)
1732 goto done;
1733 realmode_lgdt(ctxt->vcpu, size, address);
1734 break;
aca7f966 1735 case 3: /* lidt/vmmcall */
e4e03ded 1736 if (c->modrm_mod == 3 && c->modrm_rm == 1) {
7aa81cc0
AL		 1737 rc = kvm_fix_hypercall(ctxt->vcpu);
1738 if (rc)
1739 goto done;
1740 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1741 } else {
e4e03ded 1742 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 1743 &size, &address,
e4e03ded 1744 c->op_bytes);
aca7f966
AL		 1745 if (rc)
1746 goto done;
1747 realmode_lidt(ctxt->vcpu, size, address);
1748 }
6aa8b732
AK		 1749 break;
1750 case 4: /* smsw */
e4e03ded 1751 if (c->modrm_mod != 3)
6aa8b732 1752 goto cannot_emulate;
e4e03ded 1753 *(u16 *)&c->regs[c->modrm_rm]
6aa8b732
AK		 1754 = realmode_get_cr(ctxt->vcpu, 0);
1755 break;
1756 case 6: /* lmsw */
e4e03ded 1757 if (c->modrm_mod != 3)
6aa8b732 1758 goto cannot_emulate;
05f086f8
LV		 1759 realmode_lmsw(ctxt->vcpu, (u16)c->modrm_val,
1760 &ctxt->eflags);
6aa8b732
AK		 1761 break;
1762 case 7: /* invlpg*/
e8d8d7fe 1763 emulate_invlpg(ctxt->vcpu, memop);
6aa8b732
AK		 1764 break;
1765 default:
1766 goto cannot_emulate;
1767 }
a01af5ec
LV		 1768 /* Disable writeback. */
1769 c->dst.type = OP_NONE;
6aa8b732 1770 break;
018a98db
AK		 1771 case 0x06:
1772 emulate_clts(ctxt->vcpu);
1773 c->dst.type = OP_NONE;
1774 break;
1775 case 0x08: /* invd */
1776 case 0x09: /* wbinvd */
1777 case 0x0d: /* GrpP (prefetch) */
1778 case 0x18: /* Grp16 (prefetch/nop) */
1779 c->dst.type = OP_NONE;
1780 break;
1781 case 0x20: /* mov cr, reg */
1782 if (c->modrm_mod != 3)
1783 goto cannot_emulate;
1784 c->regs[c->modrm_rm] =
1785 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1786 c->dst.type = OP_NONE; /* no writeback */
1787 break;
6aa8b732 1788 case 0x21: /* mov from dr to reg */
e4e03ded 1789 if (c->modrm_mod != 3)
6aa8b732 1790 goto cannot_emulate;
8cdbd2c9 1791 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 1792 if (rc)
1793 goto cannot_emulate;
1794 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1795 break;
018a98db
AK		 1796 case 0x22: /* mov reg, cr */
1797 if (c->modrm_mod != 3)
1798 goto cannot_emulate;
1799 realmode_set_cr(ctxt->vcpu,
1800 c->modrm_reg, c->modrm_val, &ctxt->eflags);
1801 c->dst.type = OP_NONE;
1802 break;
6aa8b732 1803 case 0x23: /* mov from reg to dr */
e4e03ded 1804 if (c->modrm_mod != 3)
6aa8b732 1805 goto cannot_emulate;
e4e03ded
LV		 1806 rc = emulator_set_dr(ctxt, c->modrm_reg,
1807 c->regs[c->modrm_rm]);
a01af5ec
LV		 1808 if (rc)
1809 goto cannot_emulate;
1810 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1811 break;
018a98db
AK		 1812 case 0x30:
1813 /* wrmsr */
1814 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1815 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1816 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
1817 if (rc) {
c1a5d4f9 1818 kvm_inject_gp(ctxt->vcpu, 0);
ad312c7c 1819 c->eip = ctxt->vcpu->arch.rip;
018a98db
AK		 1820 }
1821 rc = X86EMUL_CONTINUE;
1822 c->dst.type = OP_NONE;
1823 break;
1824 case 0x32:
1825 /* rdmsr */
1826 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
1827 if (rc) {
c1a5d4f9 1828 kvm_inject_gp(ctxt->vcpu, 0);
ad312c7c 1829 c->eip = ctxt->vcpu->arch.rip;
018a98db
AK		 1830 } else {
1831 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
1832 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
1833 }
1834 rc = X86EMUL_CONTINUE;
1835 c->dst.type = OP_NONE;
1836 break;
6aa8b732 1837 case 0x40 ... 0x4f: /* cmov */
e4e03ded 1838 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 1839 if (!test_cc(c->b, ctxt->eflags))
1840 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1841 break;
018a98db
AK		 1842 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1843 long int rel;
1844
1845 switch (c->op_bytes) {
1846 case 2:
1847 rel = insn_fetch(s16, 2, c->eip);
1848 break;
1849 case 4:
1850 rel = insn_fetch(s32, 4, c->eip);
1851 break;
1852 case 8:
1853 rel = insn_fetch(s64, 8, c->eip);
1854 break;
1855 default:
1856 DPRINTF("jnz: Invalid op_bytes\n");
1857 goto cannot_emulate;
1858 }
1859 if (test_cc(c->b, ctxt->eflags))
1860 JMP_REL(rel);
1861 c->dst.type = OP_NONE;
1862 break;
1863 }
7de75248
NK		 1864 case 0xa3:
1865 bt: /* bt */
e4f8e039 1866 c->dst.type = OP_NONE;
e4e03ded
LV		 1867 /* only subword offset */
1868 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1869 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248
NK		 1870 break;
1871 case 0xab:
1872 bts: /* bts */
e4e03ded
LV		 1873 /* only subword offset */
1874 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1875 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 1876 break;
6aa8b732
AK		 1877 case 0xb0 ... 0xb1: /* cmpxchg */
1878 /*
1879 * Save real source value, then compare EAX against
1880 * destination.
1881 */
e4e03ded
LV		 1882 c->src.orig_val = c->src.val;
1883 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 1884 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1885 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 1886 /* Success: write back to memory. */
e4e03ded 1887 c->dst.val = c->src.orig_val;
6aa8b732
AK		 1888 } else {
1889 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 1890 c->dst.type = OP_REG;
1891 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 1892 }
1893 break;
6aa8b732
AK		 1894 case 0xb3:
1895 btr: /* btr */
e4e03ded
LV		 1896 /* only subword offset */
1897 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1898 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 1899 break;
6aa8b732 1900 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 1901 c->dst.bytes = c->op_bytes;
1902 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
1903 : (u16) c->src.val;
6aa8b732 1904 break;
6aa8b732 1905 case 0xba: /* Grp8 */
e4e03ded 1906 switch (c->modrm_reg & 3) {
6aa8b732
AK		 1907 case 0:
1908 goto bt;
1909 case 1:
1910 goto bts;
1911 case 2:
1912 goto btr;
1913 case 3:
1914 goto btc;
1915 }
1916 break;
7de75248
NK		 1917 case 0xbb:
1918 btc: /* btc */
e4e03ded
LV		 1919 /* only subword offset */
1920 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1921 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 1922 break;
6aa8b732 1923 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 1924 c->dst.bytes = c->op_bytes;
1925 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
1926 (s16) c->src.val;
6aa8b732 1927 break;
a012e65a 1928 case 0xc3: /* movnti */
e4e03ded
LV		 1929 c->dst.bytes = c->op_bytes;
1930 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
1931 (u64) c->src.val;
a012e65a 1932 break;
6aa8b732 1933 case 0xc7: /* Grp9 (cmpxchg8b) */
e8d8d7fe 1934 rc = emulate_grp9(ctxt, ops, memop);
8cdbd2c9
LV		 1935 if (rc != 0)
1936 goto done;
018a98db 1937 c->dst.type = OP_NONE;
8cdbd2c9 1938 break;
6aa8b732
AK		 1939 }
1940 goto writeback;
1941
1942cannot_emulate:
e4e03ded 1943 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 1944 c->eip = saved_eip;
6aa8b732
AK		 1945 return -1;
1946}
Linux kernel - Deliverables
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