x86, setup: correct include file in <asm/boot.h>
[deliverable/linux.git] / arch / x86 / lib / delay.c
CommitLineData
1da177e4
LT
1/*
2 * Precise Delay Loops for i386
3 *
4 * Copyright (C) 1993 Linus Torvalds
5 * Copyright (C) 1997 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
e01b70ef 6 * Copyright (C) 2008 Jiri Hladky <hladky _dot_ jiri _at_ gmail _dot_ com>
1da177e4
LT
7 *
8 * The __delay function must _NOT_ be inlined as its execution time
9 * depends wildly on alignment on many x86 processors. The additional
10 * jump magic is needed to get the timing stable on all the CPU's
11 * we have to worry about.
12 */
13
6f84fa2f 14#include <linux/module.h>
1da177e4 15#include <linux/sched.h>
941e492b 16#include <linux/timex.h>
35d5d08a 17#include <linux/preempt.h>
1da177e4 18#include <linux/delay.h>
941e492b 19#include <linux/init.h>
6f84fa2f 20
1da177e4
LT
21#include <asm/processor.h>
22#include <asm/delay.h>
23#include <asm/timer.h>
24
25#ifdef CONFIG_SMP
6f84fa2f 26# include <asm/smp.h>
1da177e4
LT
27#endif
28
6f84fa2f 29/* simple loop based delay: */
30static void delay_loop(unsigned long loops)
31{
f0fbf0ab 32 asm volatile(
e01b70ef
JH
33 " test %0,%0 \n"
34 " jz 3f \n"
35 " jmp 1f \n"
36
37 ".align 16 \n"
38 "1: jmp 2f \n"
39
40 ".align 16 \n"
ff1b15b6 41 "2: dec %0 \n"
e01b70ef 42 " jnz 2b \n"
ff1b15b6 43 "3: dec %0 \n"
e01b70ef
JH
44
45 : /* we don't need output */
46 :"a" (loops)
47 );
6f84fa2f 48}
49
50/* TSC based delay: */
51static void delay_tsc(unsigned long loops)
52{
53 unsigned long bclock, now;
5c1ea082 54 int cpu;
6f84fa2f 55
5c1ea082
SR
56 preempt_disable();
57 cpu = smp_processor_id();
6f84fa2f 58 rdtscl(bclock);
5c1ea082 59 for (;;) {
6f84fa2f 60 rdtscl(now);
5c1ea082
SR
61 if ((now - bclock) >= loops)
62 break;
63
64 /* Allow RT tasks to run */
65 preempt_enable();
66 rep_nop();
67 preempt_disable();
68
69 /*
70 * It is possible that we moved to another CPU, and
71 * since TSC's are per-cpu we need to calculate
72 * that. The delay must guarantee that we wait "at
73 * least" the amount of time. Being moved to another
74 * CPU could make the wait longer but we just need to
75 * make sure we waited long enough. Rebalance the
76 * counter for this CPU.
77 */
78 if (unlikely(cpu != smp_processor_id())) {
79 loops -= (now - bclock);
80 cpu = smp_processor_id();
81 rdtscl(bclock);
82 }
83 }
35d5d08a 84 preempt_enable();
6f84fa2f 85}
86
87/*
88 * Since we calibrate only once at boot, this
89 * function should be set once at boot and not changed
90 */
91static void (*delay_fn)(unsigned long) = delay_loop;
92
93void use_tsc_delay(void)
94{
95 delay_fn = delay_tsc;
96}
97
941e492b 98int __devinit read_current_timer(unsigned long *timer_val)
6f84fa2f 99{
100 if (delay_fn == delay_tsc) {
a76febe9 101 rdtscll(*timer_val);
6f84fa2f 102 return 0;
103 }
104 return -1;
105}
1da177e4
LT
106
107void __delay(unsigned long loops)
108{
6f84fa2f 109 delay_fn(loops);
1da177e4 110}
f0fbf0ab 111EXPORT_SYMBOL(__delay);
1da177e4
LT
112
113inline void __const_udelay(unsigned long xloops)
114{
115 int d0;
6f84fa2f 116
1da177e4 117 xloops *= 4;
f0fbf0ab 118 asm("mull %%edx"
1da177e4 119 :"=d" (xloops), "=&a" (d0)
6f84fa2f 120 :"1" (xloops), "0"
92cb7612 121 (cpu_data(raw_smp_processor_id()).loops_per_jiffy * (HZ/4)));
6f84fa2f 122
123 __delay(++xloops);
1da177e4 124}
f0fbf0ab 125EXPORT_SYMBOL(__const_udelay);
1da177e4
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126
127void __udelay(unsigned long usecs)
128{
6f84fa2f 129 __const_udelay(usecs * 0x000010c7); /* 2**32 / 1000000 (rounded up) */
1da177e4 130}
f0fbf0ab 131EXPORT_SYMBOL(__udelay);
1da177e4
LT
132
133void __ndelay(unsigned long nsecs)
134{
6f84fa2f 135 __const_udelay(nsecs * 0x00005); /* 2**32 / 1000000000 (rounded up) */
1da177e4 136}
129f6946 137EXPORT_SYMBOL(__ndelay);
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