[deliverable/linux.git] / arch / x86 / mach-voyager / setup.c

/*
 *	Machine specific setup for generic
 */

#include <linux/init.h>
#include <linux/interrupt.h>
#include <asm/arch_hooks.h>
#include <asm/voyager.h>
#include <asm/e820.h>
#include <asm/io.h>
#include <asm/setup.h>

void __init pre_intr_init_hook(void)
{
	init_ISA_irqs();
}

/*
 * IRQ2 is cascade interrupt to second interrupt controller
 */
static struct irqaction irq2 = {
	.handler = no_action,
	.mask = CPU_MASK_NONE,
	.name = "cascade",
};

void __init intr_init_hook(void)
{
#ifdef CONFIG_SMP
	voyager_smp_intr_init();
#endif

	setup_irq(2, &irq2);
}

void __init pre_setup_arch_hook(void)
{
	/* Voyagers run their CPUs from independent clocks, so disable
	 * the TSC code because we can't sync them */
	setup_clear_cpu_cap(X86_FEATURE_TSC);
}

void __init trap_init_hook(void)
{
}

static struct irqaction irq0 = {
	.handler = timer_interrupt,
	.flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_IRQPOLL,
	.mask = CPU_MASK_NONE,
	.name = "timer"
};

void __init time_init_hook(void)
{
	irq0.mask = cpumask_of_cpu(safe_smp_processor_id());
	setup_irq(0, &irq0);
}

/* Hook for machine specific memory setup. */

char *__init machine_specific_memory_setup(void)
{
	char *who;
	int new_nr;

	who = "NOT VOYAGER";

	if (voyager_level == 5) {
		__u32 addr, length;
		int i;

		who = "Voyager-SUS";

		e820.nr_map = 0;
		for (i = 0; voyager_memory_detect(i, &addr, &length); i++) {
			e820_add_region(addr, length, E820_RAM);
		}
		return who;
	} else if (voyager_level == 4) {
		__u32 tom;
		__u16 catbase = inb(VOYAGER_SSPB_RELOCATION_PORT) << 8;
		/* select the DINO config space */
		outb(VOYAGER_DINO, VOYAGER_CAT_CONFIG_PORT);
		/* Read DINO top of memory register */
		tom = ((inb(catbase + 0x4) & 0xf0) << 16)
		    + ((inb(catbase + 0x5) & 0x7f) << 24);

		if (inb(catbase) != VOYAGER_DINO) {
			printk(KERN_ERR
			       "Voyager: Failed to get DINO for L4, setting tom to EXT_MEM_K\n");
			tom = (boot_params.screen_info.ext_mem_k) << 10;
		}
		who = "Voyager-TOM";
		e820_add_region(0, 0x9f000, E820_RAM);
		/* map from 1M to top of memory */
		e820_add_region(1 * 1024 * 1024, tom - 1 * 1024 * 1024,
				  E820_RAM);
		/* FIXME: Should check the ASICs to see if I need to
		 * take out the 8M window.  Just do it at the moment
		 * */
		e820_add_region(8 * 1024 * 1024, 8 * 1024 * 1024,
				  E820_RESERVED);
		return who;
	}

	return default_machine_specific_memory_setup();
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Machine specific setup for generic
	3	*/
	4
1da177e4	5	#include <linux/init.h>
1da177e4	6	#include <linux/interrupt.h>
1da177e4	7	#include <asm/arch_hooks.h>
e75eac33 JF	8	#include <asm/voyager.h>
e75eac33 JF	9	#include <asm/e820.h>
d5fb3426	10	#include <asm/io.h>
e75eac33	11	#include <asm/setup.h>
1da177e4 LT	12
	13	void __init pre_intr_init_hook(void)
	14	{
	15	init_ISA_irqs();
	16	}
	17
	18	/*
	19	* IRQ2 is cascade interrupt to second interrupt controller
	20	*/
6a61f6a5 TG	21	static struct irqaction irq2 = {
	22	.handler = no_action,
	23	.mask = CPU_MASK_NONE,
	24	.name = "cascade",
	25	};
1da177e4 LT	26
	27	void __init intr_init_hook(void)
	28	{
	29	#ifdef CONFIG_SMP
73557af5	30	voyager_smp_intr_init();
1da177e4 LT	31	#endif
1da177e4 LT	32
d5fb3426	33	setup_irq(2, &irq2);
1da177e4 LT	34	}
	35
	36	void __init pre_setup_arch_hook(void)
	37	{
	38	/* Voyagers run their CPUs from independent clocks, so disable
	39	* the TSC code because we can't sync them */
404ee5b1	40	setup_clear_cpu_cap(X86_FEATURE_TSC);
1da177e4 LT	41	}
	42
	43	void __init trap_init_hook(void)
	44	{
	45	}
	46
a4ec1eff	47	static struct irqaction irq0 = {
9f483519	48	.handler = timer_interrupt,
b34942fe	49	.flags = IRQF_DISABLED \| IRQF_NOBALANCING \| IRQF_IRQPOLL,
9f483519 JB	50	.mask = CPU_MASK_NONE,
	51	.name = "timer"
	52	};
1da177e4 LT	53
	54	void __init time_init_hook(void)
	55	{
9f483519	56	irq0.mask = cpumask_of_cpu(safe_smp_processor_id());
1da177e4 LT	57	setup_irq(0, &irq0);
1da177e4 LT	58	}
e75eac33 JF	59
	60	/* Hook for machine specific memory setup. */
	61
a4ec1eff	62	char *__init machine_specific_memory_setup(void)
e75eac33 JF	63	{
e75eac33 JF	64	char *who;
6e9bcc79	65	int new_nr;
e75eac33 JF	66
	67	who = "NOT VOYAGER";
	68
a4ec1eff	69	if (voyager_level == 5) {
e75eac33 JF	70	__u32 addr, length;
	71	int i;
	72
	73	who = "Voyager-SUS";
	74
	75	e820.nr_map = 0;
a4ec1eff	76	for (i = 0; voyager_memory_detect(i, &addr, &length); i++) {
d0be6bde	77	e820_add_region(addr, length, E820_RAM);
e75eac33 JF	78	}
e75eac33 JF	79	return who;
a4ec1eff	80	} else if (voyager_level == 4) {
e75eac33	81	__u32 tom;
a4ec1eff	82	__u16 catbase = inb(VOYAGER_SSPB_RELOCATION_PORT) << 8;
e75eac33 JF	83	/* select the DINO config space */
	84	outb(VOYAGER_DINO, VOYAGER_CAT_CONFIG_PORT);
	85	/* Read DINO top of memory register */
	86	tom = ((inb(catbase + 0x4) & 0xf0) << 16)
a4ec1eff	87	+ ((inb(catbase + 0x5) & 0x7f) << 24);
e75eac33	88
a4ec1eff IM	89	if (inb(catbase) != VOYAGER_DINO) {
	90	printk(KERN_ERR
	91	"Voyager: Failed to get DINO for L4, setting tom to EXT_MEM_K\n");
	92	tom = (boot_params.screen_info.ext_mem_k) << 10;
e75eac33 JF	93	}
e75eac33 JF	94	who = "Voyager-TOM";
d0be6bde	95	e820_add_region(0, 0x9f000, E820_RAM);
e75eac33	96	/* map from 1M to top of memory */
d0be6bde	97	e820_add_region(1 * 1024 * 1024, tom - 1 * 1024 * 1024,
a4ec1eff	98	E820_RAM);
e75eac33 JF	99	/* FIXME: Should check the ASICs to see if I need to
	100	* take out the 8M window. Just do it at the moment
	101	* */
d0be6bde	102	e820_add_region(8 * 1024 * 1024, 8 * 1024 * 1024,
a4ec1eff	103	E820_RESERVED);
e75eac33 JF	104	return who;
	105	}
	106
95a71a45	107	return default_machine_specific_memory_setup();
e75eac33	108	}