Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Re-map IO memory to kernel address space so that we can access it. |
3 | * This is needed for high PCI addresses that aren't mapped in the | |
4 | * 640k-1MB IO memory area on PC's | |
5 | * | |
6 | * (C) Copyright 1995 1996 Linus Torvalds | |
7 | */ | |
8 | ||
e9332cac | 9 | #include <linux/bootmem.h> |
1da177e4 | 10 | #include <linux/init.h> |
a148ecfd | 11 | #include <linux/io.h> |
3cbd09e4 TG |
12 | #include <linux/slab.h> |
13 | #include <linux/vmalloc.h> | |
d61fc448 | 14 | #include <linux/mmiotrace.h> |
3cbd09e4 | 15 | |
1da177e4 | 16 | #include <asm/cacheflush.h> |
3cbd09e4 TG |
17 | #include <asm/e820.h> |
18 | #include <asm/fixmap.h> | |
1da177e4 | 19 | #include <asm/pgtable.h> |
3cbd09e4 | 20 | #include <asm/tlbflush.h> |
f6df72e7 | 21 | #include <asm/pgalloc.h> |
d7677d40 | 22 | #include <asm/pat.h> |
1da177e4 | 23 | |
78c86e5e | 24 | #include "physaddr.h" |
240d3a7c | 25 | |
e9332cac TG |
26 | /* |
27 | * Fix up the linear direct mapping of the kernel to avoid cache attribute | |
28 | * conflicts. | |
29 | */ | |
3a96ce8c | 30 | int ioremap_change_attr(unsigned long vaddr, unsigned long size, |
b14097bd | 31 | enum page_cache_mode pcm) |
e9332cac | 32 | { |
d806e5ee | 33 | unsigned long nrpages = size >> PAGE_SHIFT; |
93809be8 | 34 | int err; |
e9332cac | 35 | |
b14097bd JG |
36 | switch (pcm) { |
37 | case _PAGE_CACHE_MODE_UC: | |
d806e5ee | 38 | default: |
1219333d | 39 | err = _set_memory_uc(vaddr, nrpages); |
d806e5ee | 40 | break; |
b14097bd | 41 | case _PAGE_CACHE_MODE_WC: |
b310f381 | 42 | err = _set_memory_wc(vaddr, nrpages); |
43 | break; | |
623dffb2 TK |
44 | case _PAGE_CACHE_MODE_WT: |
45 | err = _set_memory_wt(vaddr, nrpages); | |
46 | break; | |
b14097bd | 47 | case _PAGE_CACHE_MODE_WB: |
1219333d | 48 | err = _set_memory_wb(vaddr, nrpages); |
d806e5ee TG |
49 | break; |
50 | } | |
e9332cac TG |
51 | |
52 | return err; | |
53 | } | |
54 | ||
c81c8a1e RD |
55 | static int __ioremap_check_ram(unsigned long start_pfn, unsigned long nr_pages, |
56 | void *arg) | |
57 | { | |
58 | unsigned long i; | |
59 | ||
60 | for (i = 0; i < nr_pages; ++i) | |
61 | if (pfn_valid(start_pfn + i) && | |
62 | !PageReserved(pfn_to_page(start_pfn + i))) | |
63 | return 1; | |
64 | ||
c81c8a1e RD |
65 | return 0; |
66 | } | |
67 | ||
1da177e4 LT |
68 | /* |
69 | * Remap an arbitrary physical address space into the kernel virtual | |
5d72b4fb TK |
70 | * address space. It transparently creates kernel huge I/O mapping when |
71 | * the physical address is aligned by a huge page size (1GB or 2MB) and | |
72 | * the requested size is at least the huge page size. | |
73 | * | |
74 | * NOTE: MTRRs can override PAT memory types with a 4KB granularity. | |
75 | * Therefore, the mapping code falls back to use a smaller page toward 4KB | |
76 | * when a mapping range is covered by non-WB type of MTRRs. | |
1da177e4 LT |
77 | * |
78 | * NOTE! We need to allow non-page-aligned mappings too: we will obviously | |
79 | * have to convert them into an offset in a page-aligned mapping, but the | |
80 | * caller shouldn't need to know that small detail. | |
81 | */ | |
23016969 | 82 | static void __iomem *__ioremap_caller(resource_size_t phys_addr, |
b14097bd | 83 | unsigned long size, enum page_cache_mode pcm, void *caller) |
1da177e4 | 84 | { |
ffa71f33 KK |
85 | unsigned long offset, vaddr; |
86 | resource_size_t pfn, last_pfn, last_addr; | |
87e547fe PP |
87 | const resource_size_t unaligned_phys_addr = phys_addr; |
88 | const unsigned long unaligned_size = size; | |
91eebf40 | 89 | struct vm_struct *area; |
b14097bd | 90 | enum page_cache_mode new_pcm; |
d806e5ee | 91 | pgprot_t prot; |
dee7cbb2 | 92 | int retval; |
d61fc448 | 93 | void __iomem *ret_addr; |
1da177e4 LT |
94 | |
95 | /* Don't allow wraparound or zero size */ | |
96 | last_addr = phys_addr + size - 1; | |
97 | if (!size || last_addr < phys_addr) | |
98 | return NULL; | |
99 | ||
e3100c82 | 100 | if (!phys_addr_valid(phys_addr)) { |
6997ab49 | 101 | printk(KERN_WARNING "ioremap: invalid physical address %llx\n", |
4c8337ac | 102 | (unsigned long long)phys_addr); |
e3100c82 TG |
103 | WARN_ON_ONCE(1); |
104 | return NULL; | |
105 | } | |
106 | ||
1da177e4 LT |
107 | /* |
108 | * Don't remap the low PCI/ISA area, it's always mapped.. | |
109 | */ | |
bcc643dc | 110 | if (is_ISA_range(phys_addr, last_addr)) |
4b40fcee | 111 | return (__force void __iomem *)phys_to_virt(phys_addr); |
1da177e4 LT |
112 | |
113 | /* | |
114 | * Don't allow anybody to remap normal RAM that we're using.. | |
115 | */ | |
9a58eebe TK |
116 | pfn = phys_addr >> PAGE_SHIFT; |
117 | last_pfn = last_addr >> PAGE_SHIFT; | |
118 | if (walk_system_ram_range(pfn, last_pfn - pfn + 1, NULL, | |
1c9cf9b2 | 119 | __ioremap_check_ram) == 1) { |
8a0a5da6 TG |
120 | WARN_ONCE(1, "ioremap on RAM at %pa - %pa\n", |
121 | &phys_addr, &last_addr); | |
9a58eebe | 122 | return NULL; |
906e36c5 | 123 | } |
9a58eebe | 124 | |
d7677d40 | 125 | /* |
126 | * Mappings have to be page-aligned | |
127 | */ | |
128 | offset = phys_addr & ~PAGE_MASK; | |
ffa71f33 | 129 | phys_addr &= PHYSICAL_PAGE_MASK; |
d7677d40 | 130 | size = PAGE_ALIGN(last_addr+1) - phys_addr; |
131 | ||
e213e877 | 132 | retval = reserve_memtype(phys_addr, (u64)phys_addr + size, |
e00c8cc9 | 133 | pcm, &new_pcm); |
dee7cbb2 | 134 | if (retval) { |
279e669b | 135 | printk(KERN_ERR "ioremap reserve_memtype failed %d\n", retval); |
dee7cbb2 VP |
136 | return NULL; |
137 | } | |
138 | ||
b14097bd JG |
139 | if (pcm != new_pcm) { |
140 | if (!is_new_memtype_allowed(phys_addr, size, pcm, new_pcm)) { | |
279e669b | 141 | printk(KERN_ERR |
b14097bd | 142 | "ioremap error for 0x%llx-0x%llx, requested 0x%x, got 0x%x\n", |
4c8337ac RD |
143 | (unsigned long long)phys_addr, |
144 | (unsigned long long)(phys_addr + size), | |
b14097bd | 145 | pcm, new_pcm); |
de2a47cf | 146 | goto err_free_memtype; |
d7677d40 | 147 | } |
b14097bd | 148 | pcm = new_pcm; |
d7677d40 | 149 | } |
150 | ||
b14097bd JG |
151 | prot = PAGE_KERNEL_IO; |
152 | switch (pcm) { | |
153 | case _PAGE_CACHE_MODE_UC: | |
d806e5ee | 154 | default: |
b14097bd JG |
155 | prot = __pgprot(pgprot_val(prot) | |
156 | cachemode2protval(_PAGE_CACHE_MODE_UC)); | |
d806e5ee | 157 | break; |
b14097bd JG |
158 | case _PAGE_CACHE_MODE_UC_MINUS: |
159 | prot = __pgprot(pgprot_val(prot) | | |
160 | cachemode2protval(_PAGE_CACHE_MODE_UC_MINUS)); | |
de33c442 | 161 | break; |
b14097bd JG |
162 | case _PAGE_CACHE_MODE_WC: |
163 | prot = __pgprot(pgprot_val(prot) | | |
164 | cachemode2protval(_PAGE_CACHE_MODE_WC)); | |
b310f381 | 165 | break; |
d838270e TK |
166 | case _PAGE_CACHE_MODE_WT: |
167 | prot = __pgprot(pgprot_val(prot) | | |
168 | cachemode2protval(_PAGE_CACHE_MODE_WT)); | |
169 | break; | |
b14097bd | 170 | case _PAGE_CACHE_MODE_WB: |
d806e5ee TG |
171 | break; |
172 | } | |
a148ecfd | 173 | |
1da177e4 LT |
174 | /* |
175 | * Ok, go for it.. | |
176 | */ | |
23016969 | 177 | area = get_vm_area_caller(size, VM_IOREMAP, caller); |
1da177e4 | 178 | if (!area) |
de2a47cf | 179 | goto err_free_memtype; |
1da177e4 | 180 | area->phys_addr = phys_addr; |
e66aadbe | 181 | vaddr = (unsigned long) area->addr; |
43a432b1 | 182 | |
b14097bd | 183 | if (kernel_map_sync_memtype(phys_addr, size, pcm)) |
de2a47cf | 184 | goto err_free_area; |
e9332cac | 185 | |
de2a47cf XF |
186 | if (ioremap_page_range(vaddr, vaddr + size, phys_addr, prot)) |
187 | goto err_free_area; | |
e9332cac | 188 | |
d61fc448 | 189 | ret_addr = (void __iomem *) (vaddr + offset); |
87e547fe | 190 | mmiotrace_ioremap(unaligned_phys_addr, unaligned_size, ret_addr); |
d61fc448 | 191 | |
c7a7b814 TG |
192 | /* |
193 | * Check if the request spans more than any BAR in the iomem resource | |
194 | * tree. | |
195 | */ | |
9abb0ecd LA |
196 | if (iomem_map_sanity_check(unaligned_phys_addr, unaligned_size)) |
197 | pr_warn("caller %pS mapping multiple BARs\n", caller); | |
c7a7b814 | 198 | |
d61fc448 | 199 | return ret_addr; |
de2a47cf XF |
200 | err_free_area: |
201 | free_vm_area(area); | |
202 | err_free_memtype: | |
203 | free_memtype(phys_addr, phys_addr + size); | |
204 | return NULL; | |
1da177e4 | 205 | } |
1da177e4 LT |
206 | |
207 | /** | |
208 | * ioremap_nocache - map bus memory into CPU space | |
9efc31b8 | 209 | * @phys_addr: bus address of the memory |
1da177e4 LT |
210 | * @size: size of the resource to map |
211 | * | |
212 | * ioremap_nocache performs a platform specific sequence of operations to | |
213 | * make bus memory CPU accessible via the readb/readw/readl/writeb/ | |
214 | * writew/writel functions and the other mmio helpers. The returned | |
215 | * address is not guaranteed to be usable directly as a virtual | |
91eebf40 | 216 | * address. |
1da177e4 LT |
217 | * |
218 | * This version of ioremap ensures that the memory is marked uncachable | |
219 | * on the CPU as well as honouring existing caching rules from things like | |
91eebf40 | 220 | * the PCI bus. Note that there are other caches and buffers on many |
1da177e4 LT |
221 | * busses. In particular driver authors should read up on PCI writes |
222 | * | |
223 | * It's useful if some control registers are in such an area and | |
224 | * write combining or read caching is not desirable: | |
91eebf40 | 225 | * |
1da177e4 LT |
226 | * Must be freed with iounmap. |
227 | */ | |
b9e76a00 | 228 | void __iomem *ioremap_nocache(resource_size_t phys_addr, unsigned long size) |
1da177e4 | 229 | { |
de33c442 SS |
230 | /* |
231 | * Ideally, this should be: | |
cb32edf6 | 232 | * pat_enabled() ? _PAGE_CACHE_MODE_UC : _PAGE_CACHE_MODE_UC_MINUS; |
de33c442 SS |
233 | * |
234 | * Till we fix all X drivers to use ioremap_wc(), we will use | |
e4b6be33 LR |
235 | * UC MINUS. Drivers that are certain they need or can already |
236 | * be converted over to strong UC can use ioremap_uc(). | |
de33c442 | 237 | */ |
b14097bd | 238 | enum page_cache_mode pcm = _PAGE_CACHE_MODE_UC_MINUS; |
de33c442 | 239 | |
b14097bd | 240 | return __ioremap_caller(phys_addr, size, pcm, |
23016969 | 241 | __builtin_return_address(0)); |
1da177e4 | 242 | } |
129f6946 | 243 | EXPORT_SYMBOL(ioremap_nocache); |
1da177e4 | 244 | |
e4b6be33 LR |
245 | /** |
246 | * ioremap_uc - map bus memory into CPU space as strongly uncachable | |
247 | * @phys_addr: bus address of the memory | |
248 | * @size: size of the resource to map | |
249 | * | |
250 | * ioremap_uc performs a platform specific sequence of operations to | |
251 | * make bus memory CPU accessible via the readb/readw/readl/writeb/ | |
252 | * writew/writel functions and the other mmio helpers. The returned | |
253 | * address is not guaranteed to be usable directly as a virtual | |
254 | * address. | |
255 | * | |
256 | * This version of ioremap ensures that the memory is marked with a strong | |
257 | * preference as completely uncachable on the CPU when possible. For non-PAT | |
258 | * systems this ends up setting page-attribute flags PCD=1, PWT=1. For PAT | |
259 | * systems this will set the PAT entry for the pages as strong UC. This call | |
260 | * will honor existing caching rules from things like the PCI bus. Note that | |
261 | * there are other caches and buffers on many busses. In particular driver | |
262 | * authors should read up on PCI writes. | |
263 | * | |
264 | * It's useful if some control registers are in such an area and | |
265 | * write combining or read caching is not desirable: | |
266 | * | |
267 | * Must be freed with iounmap. | |
268 | */ | |
269 | void __iomem *ioremap_uc(resource_size_t phys_addr, unsigned long size) | |
270 | { | |
271 | enum page_cache_mode pcm = _PAGE_CACHE_MODE_UC; | |
272 | ||
273 | return __ioremap_caller(phys_addr, size, pcm, | |
274 | __builtin_return_address(0)); | |
275 | } | |
276 | EXPORT_SYMBOL_GPL(ioremap_uc); | |
277 | ||
b310f381 | 278 | /** |
279 | * ioremap_wc - map memory into CPU space write combined | |
9efc31b8 | 280 | * @phys_addr: bus address of the memory |
b310f381 | 281 | * @size: size of the resource to map |
282 | * | |
283 | * This version of ioremap ensures that the memory is marked write combining. | |
284 | * Write combining allows faster writes to some hardware devices. | |
285 | * | |
286 | * Must be freed with iounmap. | |
287 | */ | |
d639bab8 | 288 | void __iomem *ioremap_wc(resource_size_t phys_addr, unsigned long size) |
b310f381 | 289 | { |
7202fdb1 | 290 | return __ioremap_caller(phys_addr, size, _PAGE_CACHE_MODE_WC, |
23016969 | 291 | __builtin_return_address(0)); |
b310f381 | 292 | } |
293 | EXPORT_SYMBOL(ioremap_wc); | |
294 | ||
d838270e TK |
295 | /** |
296 | * ioremap_wt - map memory into CPU space write through | |
297 | * @phys_addr: bus address of the memory | |
298 | * @size: size of the resource to map | |
299 | * | |
300 | * This version of ioremap ensures that the memory is marked write through. | |
301 | * Write through stores data into memory while keeping the cache up-to-date. | |
302 | * | |
303 | * Must be freed with iounmap. | |
304 | */ | |
305 | void __iomem *ioremap_wt(resource_size_t phys_addr, unsigned long size) | |
306 | { | |
307 | return __ioremap_caller(phys_addr, size, _PAGE_CACHE_MODE_WT, | |
308 | __builtin_return_address(0)); | |
309 | } | |
310 | EXPORT_SYMBOL(ioremap_wt); | |
311 | ||
b9e76a00 | 312 | void __iomem *ioremap_cache(resource_size_t phys_addr, unsigned long size) |
5f868152 | 313 | { |
b14097bd | 314 | return __ioremap_caller(phys_addr, size, _PAGE_CACHE_MODE_WB, |
23016969 | 315 | __builtin_return_address(0)); |
5f868152 TG |
316 | } |
317 | EXPORT_SYMBOL(ioremap_cache); | |
318 | ||
28b2ee20 RR |
319 | void __iomem *ioremap_prot(resource_size_t phys_addr, unsigned long size, |
320 | unsigned long prot_val) | |
321 | { | |
b14097bd JG |
322 | return __ioremap_caller(phys_addr, size, |
323 | pgprot2cachemode(__pgprot(prot_val)), | |
28b2ee20 RR |
324 | __builtin_return_address(0)); |
325 | } | |
326 | EXPORT_SYMBOL(ioremap_prot); | |
327 | ||
bf5421c3 AK |
328 | /** |
329 | * iounmap - Free a IO remapping | |
330 | * @addr: virtual address from ioremap_* | |
331 | * | |
332 | * Caller must ensure there is only one unmapping for the same pointer. | |
333 | */ | |
1da177e4 LT |
334 | void iounmap(volatile void __iomem *addr) |
335 | { | |
bf5421c3 | 336 | struct vm_struct *p, *o; |
c23a4e96 AM |
337 | |
338 | if ((void __force *)addr <= high_memory) | |
1da177e4 LT |
339 | return; |
340 | ||
341 | /* | |
342 | * __ioremap special-cases the PCI/ISA range by not instantiating a | |
343 | * vm_area and by simply returning an address into the kernel mapping | |
344 | * of ISA space. So handle that here. | |
345 | */ | |
6e92a5a6 TG |
346 | if ((void __force *)addr >= phys_to_virt(ISA_START_ADDRESS) && |
347 | (void __force *)addr < phys_to_virt(ISA_END_ADDRESS)) | |
1da177e4 LT |
348 | return; |
349 | ||
91eebf40 TG |
350 | addr = (volatile void __iomem *) |
351 | (PAGE_MASK & (unsigned long __force)addr); | |
bf5421c3 | 352 | |
d61fc448 PP |
353 | mmiotrace_iounmap(addr); |
354 | ||
bf5421c3 AK |
355 | /* Use the vm area unlocked, assuming the caller |
356 | ensures there isn't another iounmap for the same address | |
357 | in parallel. Reuse of the virtual address is prevented by | |
358 | leaving it in the global lists until we're done with it. | |
359 | cpa takes care of the direct mappings. */ | |
ef932473 | 360 | p = find_vm_area((void __force *)addr); |
bf5421c3 AK |
361 | |
362 | if (!p) { | |
91eebf40 | 363 | printk(KERN_ERR "iounmap: bad address %p\n", addr); |
c23a4e96 | 364 | dump_stack(); |
bf5421c3 | 365 | return; |
1da177e4 LT |
366 | } |
367 | ||
d7677d40 | 368 | free_memtype(p->phys_addr, p->phys_addr + get_vm_area_size(p)); |
369 | ||
bf5421c3 | 370 | /* Finally remove it */ |
6e92a5a6 | 371 | o = remove_vm_area((void __force *)addr); |
bf5421c3 | 372 | BUG_ON(p != o || o == NULL); |
91eebf40 | 373 | kfree(p); |
1da177e4 | 374 | } |
129f6946 | 375 | EXPORT_SYMBOL(iounmap); |
1da177e4 | 376 | |
1e6277de | 377 | int __init arch_ioremap_pud_supported(void) |
5d72b4fb TK |
378 | { |
379 | #ifdef CONFIG_X86_64 | |
b8291adc | 380 | return boot_cpu_has(X86_FEATURE_GBPAGES); |
5d72b4fb TK |
381 | #else |
382 | return 0; | |
383 | #endif | |
384 | } | |
385 | ||
1e6277de | 386 | int __init arch_ioremap_pmd_supported(void) |
5d72b4fb | 387 | { |
16bf9226 | 388 | return boot_cpu_has(X86_FEATURE_PSE); |
5d72b4fb TK |
389 | } |
390 | ||
e045fb2a | 391 | /* |
392 | * Convert a physical pointer to a virtual kernel pointer for /dev/mem | |
393 | * access | |
394 | */ | |
4707a341 | 395 | void *xlate_dev_mem_ptr(phys_addr_t phys) |
e045fb2a | 396 | { |
94d4b476 IM |
397 | unsigned long start = phys & PAGE_MASK; |
398 | unsigned long offset = phys & ~PAGE_MASK; | |
562bfca4 | 399 | void *vaddr; |
e045fb2a | 400 | |
401 | /* If page is RAM, we can use __va. Otherwise ioremap and unmap. */ | |
402 | if (page_is_ram(start >> PAGE_SHIFT)) | |
403 | return __va(phys); | |
404 | ||
562bfca4 | 405 | vaddr = ioremap_cache(start, PAGE_SIZE); |
94d4b476 IM |
406 | /* Only add the offset on success and return NULL if the ioremap() failed: */ |
407 | if (vaddr) | |
408 | vaddr += offset; | |
e045fb2a | 409 | |
562bfca4 | 410 | return vaddr; |
e045fb2a | 411 | } |
412 | ||
4707a341 | 413 | void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr) |
e045fb2a | 414 | { |
415 | if (page_is_ram(phys >> PAGE_SHIFT)) | |
416 | return; | |
417 | ||
418 | iounmap((void __iomem *)((unsigned long)addr & PAGE_MASK)); | |
e045fb2a | 419 | } |
420 | ||
45c7b28f | 421 | static pte_t bm_pte[PAGE_SIZE/sizeof(pte_t)] __page_aligned_bss; |
0947b2f3 | 422 | |
551889a6 | 423 | static inline pmd_t * __init early_ioremap_pmd(unsigned long addr) |
0947b2f3 | 424 | { |
37cc8d7f JF |
425 | /* Don't assume we're using swapper_pg_dir at this point */ |
426 | pgd_t *base = __va(read_cr3()); | |
427 | pgd_t *pgd = &base[pgd_index(addr)]; | |
551889a6 IC |
428 | pud_t *pud = pud_offset(pgd, addr); |
429 | pmd_t *pmd = pmd_offset(pud, addr); | |
430 | ||
431 | return pmd; | |
0947b2f3 HY |
432 | } |
433 | ||
551889a6 | 434 | static inline pte_t * __init early_ioremap_pte(unsigned long addr) |
0947b2f3 | 435 | { |
551889a6 | 436 | return &bm_pte[pte_index(addr)]; |
0947b2f3 HY |
437 | } |
438 | ||
fef5ba79 JF |
439 | bool __init is_early_ioremap_ptep(pte_t *ptep) |
440 | { | |
441 | return ptep >= &bm_pte[0] && ptep < &bm_pte[PAGE_SIZE/sizeof(pte_t)]; | |
442 | } | |
443 | ||
beacfaac | 444 | void __init early_ioremap_init(void) |
0947b2f3 | 445 | { |
551889a6 | 446 | pmd_t *pmd; |
0947b2f3 | 447 | |
73159fdc AL |
448 | #ifdef CONFIG_X86_64 |
449 | BUILD_BUG_ON((fix_to_virt(0) + PAGE_SIZE) & ((1 << PMD_SHIFT) - 1)); | |
450 | #else | |
451 | WARN_ON((fix_to_virt(0) + PAGE_SIZE) & ((1 << PMD_SHIFT) - 1)); | |
452 | #endif | |
453 | ||
5b7c73e0 | 454 | early_ioremap_setup(); |
8827247f | 455 | |
551889a6 | 456 | pmd = early_ioremap_pmd(fix_to_virt(FIX_BTMAP_BEGIN)); |
45c7b28f JF |
457 | memset(bm_pte, 0, sizeof(bm_pte)); |
458 | pmd_populate_kernel(&init_mm, pmd, bm_pte); | |
551889a6 | 459 | |
0e3a9549 | 460 | /* |
551889a6 | 461 | * The boot-ioremap range spans multiple pmds, for which |
0e3a9549 IM |
462 | * we are not prepared: |
463 | */ | |
499a5f1e JB |
464 | #define __FIXADDR_TOP (-PAGE_SIZE) |
465 | BUILD_BUG_ON((__fix_to_virt(FIX_BTMAP_BEGIN) >> PMD_SHIFT) | |
466 | != (__fix_to_virt(FIX_BTMAP_END) >> PMD_SHIFT)); | |
467 | #undef __FIXADDR_TOP | |
551889a6 | 468 | if (pmd != early_ioremap_pmd(fix_to_virt(FIX_BTMAP_END))) { |
0e3a9549 | 469 | WARN_ON(1); |
551889a6 IC |
470 | printk(KERN_WARNING "pmd %p != %p\n", |
471 | pmd, early_ioremap_pmd(fix_to_virt(FIX_BTMAP_END))); | |
91eebf40 | 472 | printk(KERN_WARNING "fix_to_virt(FIX_BTMAP_BEGIN): %08lx\n", |
551889a6 | 473 | fix_to_virt(FIX_BTMAP_BEGIN)); |
91eebf40 | 474 | printk(KERN_WARNING "fix_to_virt(FIX_BTMAP_END): %08lx\n", |
551889a6 | 475 | fix_to_virt(FIX_BTMAP_END)); |
91eebf40 TG |
476 | |
477 | printk(KERN_WARNING "FIX_BTMAP_END: %d\n", FIX_BTMAP_END); | |
478 | printk(KERN_WARNING "FIX_BTMAP_BEGIN: %d\n", | |
479 | FIX_BTMAP_BEGIN); | |
0e3a9549 | 480 | } |
0947b2f3 HY |
481 | } |
482 | ||
5b7c73e0 MS |
483 | void __init __early_set_fixmap(enum fixed_addresses idx, |
484 | phys_addr_t phys, pgprot_t flags) | |
0947b2f3 | 485 | { |
551889a6 IC |
486 | unsigned long addr = __fix_to_virt(idx); |
487 | pte_t *pte; | |
0947b2f3 HY |
488 | |
489 | if (idx >= __end_of_fixed_addresses) { | |
490 | BUG(); | |
491 | return; | |
492 | } | |
beacfaac | 493 | pte = early_ioremap_pte(addr); |
4583ed51 | 494 | |
0947b2f3 | 495 | if (pgprot_val(flags)) |
551889a6 | 496 | set_pte(pte, pfn_pte(phys >> PAGE_SHIFT, flags)); |
0947b2f3 | 497 | else |
4f9c11dd | 498 | pte_clear(&init_mm, addr, pte); |
0947b2f3 HY |
499 | __flush_tlb_one(addr); |
500 | } |