Commit | Line | Data |
---|---|---|
9f4c815c IM |
1 | /* |
2 | * Copyright 2002 Andi Kleen, SuSE Labs. | |
1da177e4 | 3 | * Thanks to Ben LaHaise for precious feedback. |
9f4c815c | 4 | */ |
1da177e4 | 5 | #include <linux/highmem.h> |
8192206d | 6 | #include <linux/bootmem.h> |
9f4c815c | 7 | #include <linux/sched.h> |
9f4c815c | 8 | #include <linux/mm.h> |
76ebd054 | 9 | #include <linux/interrupt.h> |
ee7ae7a1 TG |
10 | #include <linux/seq_file.h> |
11 | #include <linux/debugfs.h> | |
e59a1bb2 | 12 | #include <linux/pfn.h> |
8c4bfc6e | 13 | #include <linux/percpu.h> |
5a0e3ad6 | 14 | #include <linux/gfp.h> |
5bd5a452 | 15 | #include <linux/pci.h> |
d6472302 | 16 | #include <linux/vmalloc.h> |
9f4c815c | 17 | |
950f9d95 | 18 | #include <asm/e820.h> |
1da177e4 LT |
19 | #include <asm/processor.h> |
20 | #include <asm/tlbflush.h> | |
f8af095d | 21 | #include <asm/sections.h> |
93dbda7c | 22 | #include <asm/setup.h> |
9f4c815c IM |
23 | #include <asm/uaccess.h> |
24 | #include <asm/pgalloc.h> | |
c31c7d48 | 25 | #include <asm/proto.h> |
1219333d | 26 | #include <asm/pat.h> |
1da177e4 | 27 | |
9df84993 IM |
28 | /* |
29 | * The current flushing context - we pass it instead of 5 arguments: | |
30 | */ | |
72e458df | 31 | struct cpa_data { |
d75586ad | 32 | unsigned long *vaddr; |
0fd64c23 | 33 | pgd_t *pgd; |
72e458df TG |
34 | pgprot_t mask_set; |
35 | pgprot_t mask_clr; | |
65e074df | 36 | int numpages; |
d75586ad | 37 | int flags; |
c31c7d48 | 38 | unsigned long pfn; |
c9caa02c | 39 | unsigned force_split : 1; |
d75586ad | 40 | int curpage; |
9ae28475 | 41 | struct page **pages; |
72e458df TG |
42 | }; |
43 | ||
ad5ca55f SS |
44 | /* |
45 | * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings) | |
46 | * using cpa_lock. So that we don't allow any other cpu, with stale large tlb | |
47 | * entries change the page attribute in parallel to some other cpu | |
48 | * splitting a large page entry along with changing the attribute. | |
49 | */ | |
50 | static DEFINE_SPINLOCK(cpa_lock); | |
51 | ||
d75586ad SL |
52 | #define CPA_FLUSHTLB 1 |
53 | #define CPA_ARRAY 2 | |
9ae28475 | 54 | #define CPA_PAGES_ARRAY 4 |
d75586ad | 55 | |
65280e61 | 56 | #ifdef CONFIG_PROC_FS |
ce0c0e50 AK |
57 | static unsigned long direct_pages_count[PG_LEVEL_NUM]; |
58 | ||
65280e61 | 59 | void update_page_count(int level, unsigned long pages) |
ce0c0e50 | 60 | { |
ce0c0e50 | 61 | /* Protect against CPA */ |
a79e53d8 | 62 | spin_lock(&pgd_lock); |
ce0c0e50 | 63 | direct_pages_count[level] += pages; |
a79e53d8 | 64 | spin_unlock(&pgd_lock); |
65280e61 TG |
65 | } |
66 | ||
67 | static void split_page_count(int level) | |
68 | { | |
69 | direct_pages_count[level]--; | |
70 | direct_pages_count[level - 1] += PTRS_PER_PTE; | |
71 | } | |
72 | ||
e1759c21 | 73 | void arch_report_meminfo(struct seq_file *m) |
65280e61 | 74 | { |
b9c3bfc2 | 75 | seq_printf(m, "DirectMap4k: %8lu kB\n", |
a06de630 HD |
76 | direct_pages_count[PG_LEVEL_4K] << 2); |
77 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
b9c3bfc2 | 78 | seq_printf(m, "DirectMap2M: %8lu kB\n", |
a06de630 HD |
79 | direct_pages_count[PG_LEVEL_2M] << 11); |
80 | #else | |
b9c3bfc2 | 81 | seq_printf(m, "DirectMap4M: %8lu kB\n", |
a06de630 HD |
82 | direct_pages_count[PG_LEVEL_2M] << 12); |
83 | #endif | |
a06de630 | 84 | if (direct_gbpages) |
b9c3bfc2 | 85 | seq_printf(m, "DirectMap1G: %8lu kB\n", |
a06de630 | 86 | direct_pages_count[PG_LEVEL_1G] << 20); |
ce0c0e50 | 87 | } |
65280e61 TG |
88 | #else |
89 | static inline void split_page_count(int level) { } | |
90 | #endif | |
ce0c0e50 | 91 | |
c31c7d48 TG |
92 | #ifdef CONFIG_X86_64 |
93 | ||
94 | static inline unsigned long highmap_start_pfn(void) | |
95 | { | |
fc8d7826 | 96 | return __pa_symbol(_text) >> PAGE_SHIFT; |
c31c7d48 TG |
97 | } |
98 | ||
99 | static inline unsigned long highmap_end_pfn(void) | |
100 | { | |
fc8d7826 | 101 | return __pa_symbol(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT; |
c31c7d48 TG |
102 | } |
103 | ||
104 | #endif | |
105 | ||
92cb54a3 IM |
106 | #ifdef CONFIG_DEBUG_PAGEALLOC |
107 | # define debug_pagealloc 1 | |
108 | #else | |
109 | # define debug_pagealloc 0 | |
110 | #endif | |
111 | ||
ed724be6 AV |
112 | static inline int |
113 | within(unsigned long addr, unsigned long start, unsigned long end) | |
687c4825 | 114 | { |
ed724be6 AV |
115 | return addr >= start && addr < end; |
116 | } | |
117 | ||
d7c8f21a TG |
118 | /* |
119 | * Flushing functions | |
120 | */ | |
cd8ddf1a | 121 | |
cd8ddf1a TG |
122 | /** |
123 | * clflush_cache_range - flush a cache range with clflush | |
9efc31b8 | 124 | * @vaddr: virtual start address |
cd8ddf1a TG |
125 | * @size: number of bytes to flush |
126 | * | |
8b80fd8b RZ |
127 | * clflushopt is an unordered instruction which needs fencing with mfence or |
128 | * sfence to avoid ordering issues. | |
cd8ddf1a | 129 | */ |
4c61afcd | 130 | void clflush_cache_range(void *vaddr, unsigned int size) |
d7c8f21a | 131 | { |
6c434d61 RZ |
132 | unsigned long clflush_mask = boot_cpu_data.x86_clflush_size - 1; |
133 | void *vend = vaddr + size; | |
134 | void *p; | |
d7c8f21a | 135 | |
cd8ddf1a | 136 | mb(); |
4c61afcd | 137 | |
6c434d61 RZ |
138 | for (p = (void *)((unsigned long)vaddr & ~clflush_mask); |
139 | p < vend; p += boot_cpu_data.x86_clflush_size) | |
140 | clflushopt(p); | |
4c61afcd | 141 | |
cd8ddf1a | 142 | mb(); |
d7c8f21a | 143 | } |
e517a5e9 | 144 | EXPORT_SYMBOL_GPL(clflush_cache_range); |
d7c8f21a | 145 | |
af1e6844 | 146 | static void __cpa_flush_all(void *arg) |
d7c8f21a | 147 | { |
6bb8383b AK |
148 | unsigned long cache = (unsigned long)arg; |
149 | ||
d7c8f21a TG |
150 | /* |
151 | * Flush all to work around Errata in early athlons regarding | |
152 | * large page flushing. | |
153 | */ | |
154 | __flush_tlb_all(); | |
155 | ||
0b827537 | 156 | if (cache && boot_cpu_data.x86 >= 4) |
d7c8f21a TG |
157 | wbinvd(); |
158 | } | |
159 | ||
6bb8383b | 160 | static void cpa_flush_all(unsigned long cache) |
d7c8f21a TG |
161 | { |
162 | BUG_ON(irqs_disabled()); | |
163 | ||
15c8b6c1 | 164 | on_each_cpu(__cpa_flush_all, (void *) cache, 1); |
d7c8f21a TG |
165 | } |
166 | ||
57a6a46a TG |
167 | static void __cpa_flush_range(void *arg) |
168 | { | |
57a6a46a TG |
169 | /* |
170 | * We could optimize that further and do individual per page | |
171 | * tlb invalidates for a low number of pages. Caveat: we must | |
172 | * flush the high aliases on 64bit as well. | |
173 | */ | |
174 | __flush_tlb_all(); | |
57a6a46a TG |
175 | } |
176 | ||
6bb8383b | 177 | static void cpa_flush_range(unsigned long start, int numpages, int cache) |
57a6a46a | 178 | { |
4c61afcd IM |
179 | unsigned int i, level; |
180 | unsigned long addr; | |
181 | ||
57a6a46a | 182 | BUG_ON(irqs_disabled()); |
4c61afcd | 183 | WARN_ON(PAGE_ALIGN(start) != start); |
57a6a46a | 184 | |
15c8b6c1 | 185 | on_each_cpu(__cpa_flush_range, NULL, 1); |
57a6a46a | 186 | |
6bb8383b AK |
187 | if (!cache) |
188 | return; | |
189 | ||
3b233e52 TG |
190 | /* |
191 | * We only need to flush on one CPU, | |
192 | * clflush is a MESI-coherent instruction that | |
193 | * will cause all other CPUs to flush the same | |
194 | * cachelines: | |
195 | */ | |
4c61afcd IM |
196 | for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) { |
197 | pte_t *pte = lookup_address(addr, &level); | |
198 | ||
199 | /* | |
200 | * Only flush present addresses: | |
201 | */ | |
7bfb72e8 | 202 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) |
4c61afcd IM |
203 | clflush_cache_range((void *) addr, PAGE_SIZE); |
204 | } | |
57a6a46a TG |
205 | } |
206 | ||
9ae28475 | 207 | static void cpa_flush_array(unsigned long *start, int numpages, int cache, |
208 | int in_flags, struct page **pages) | |
d75586ad SL |
209 | { |
210 | unsigned int i, level; | |
2171787b | 211 | unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */ |
d75586ad SL |
212 | |
213 | BUG_ON(irqs_disabled()); | |
214 | ||
2171787b | 215 | on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1); |
d75586ad | 216 | |
2171787b | 217 | if (!cache || do_wbinvd) |
d75586ad SL |
218 | return; |
219 | ||
d75586ad SL |
220 | /* |
221 | * We only need to flush on one CPU, | |
222 | * clflush is a MESI-coherent instruction that | |
223 | * will cause all other CPUs to flush the same | |
224 | * cachelines: | |
225 | */ | |
9ae28475 | 226 | for (i = 0; i < numpages; i++) { |
227 | unsigned long addr; | |
228 | pte_t *pte; | |
229 | ||
230 | if (in_flags & CPA_PAGES_ARRAY) | |
231 | addr = (unsigned long)page_address(pages[i]); | |
232 | else | |
233 | addr = start[i]; | |
234 | ||
235 | pte = lookup_address(addr, &level); | |
d75586ad SL |
236 | |
237 | /* | |
238 | * Only flush present addresses: | |
239 | */ | |
240 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) | |
9ae28475 | 241 | clflush_cache_range((void *)addr, PAGE_SIZE); |
d75586ad SL |
242 | } |
243 | } | |
244 | ||
ed724be6 AV |
245 | /* |
246 | * Certain areas of memory on x86 require very specific protection flags, | |
247 | * for example the BIOS area or kernel text. Callers don't always get this | |
248 | * right (again, ioremap() on BIOS memory is not uncommon) so this function | |
249 | * checks and fixes these known static required protection bits. | |
250 | */ | |
c31c7d48 TG |
251 | static inline pgprot_t static_protections(pgprot_t prot, unsigned long address, |
252 | unsigned long pfn) | |
ed724be6 AV |
253 | { |
254 | pgprot_t forbidden = __pgprot(0); | |
255 | ||
687c4825 | 256 | /* |
ed724be6 AV |
257 | * The BIOS area between 640k and 1Mb needs to be executable for |
258 | * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support. | |
687c4825 | 259 | */ |
5bd5a452 MC |
260 | #ifdef CONFIG_PCI_BIOS |
261 | if (pcibios_enabled && within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT)) | |
ed724be6 | 262 | pgprot_val(forbidden) |= _PAGE_NX; |
5bd5a452 | 263 | #endif |
ed724be6 AV |
264 | |
265 | /* | |
266 | * The kernel text needs to be executable for obvious reasons | |
c31c7d48 TG |
267 | * Does not cover __inittext since that is gone later on. On |
268 | * 64bit we do not enforce !NX on the low mapping | |
ed724be6 AV |
269 | */ |
270 | if (within(address, (unsigned long)_text, (unsigned long)_etext)) | |
271 | pgprot_val(forbidden) |= _PAGE_NX; | |
cc0f21bb | 272 | |
cc0f21bb | 273 | /* |
c31c7d48 TG |
274 | * The .rodata section needs to be read-only. Using the pfn |
275 | * catches all aliases. | |
cc0f21bb | 276 | */ |
fc8d7826 AD |
277 | if (within(pfn, __pa_symbol(__start_rodata) >> PAGE_SHIFT, |
278 | __pa_symbol(__end_rodata) >> PAGE_SHIFT)) | |
cc0f21bb | 279 | pgprot_val(forbidden) |= _PAGE_RW; |
ed724be6 | 280 | |
55ca3cc1 | 281 | #if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA) |
74e08179 | 282 | /* |
502f6604 SS |
283 | * Once the kernel maps the text as RO (kernel_set_to_readonly is set), |
284 | * kernel text mappings for the large page aligned text, rodata sections | |
285 | * will be always read-only. For the kernel identity mappings covering | |
286 | * the holes caused by this alignment can be anything that user asks. | |
74e08179 SS |
287 | * |
288 | * This will preserve the large page mappings for kernel text/data | |
289 | * at no extra cost. | |
290 | */ | |
502f6604 SS |
291 | if (kernel_set_to_readonly && |
292 | within(address, (unsigned long)_text, | |
281ff33b SS |
293 | (unsigned long)__end_rodata_hpage_align)) { |
294 | unsigned int level; | |
295 | ||
296 | /* | |
297 | * Don't enforce the !RW mapping for the kernel text mapping, | |
298 | * if the current mapping is already using small page mapping. | |
299 | * No need to work hard to preserve large page mappings in this | |
300 | * case. | |
301 | * | |
302 | * This also fixes the Linux Xen paravirt guest boot failure | |
303 | * (because of unexpected read-only mappings for kernel identity | |
304 | * mappings). In this paravirt guest case, the kernel text | |
305 | * mapping and the kernel identity mapping share the same | |
306 | * page-table pages. Thus we can't really use different | |
307 | * protections for the kernel text and identity mappings. Also, | |
308 | * these shared mappings are made of small page mappings. | |
309 | * Thus this don't enforce !RW mapping for small page kernel | |
310 | * text mapping logic will help Linux Xen parvirt guest boot | |
0d2eb44f | 311 | * as well. |
281ff33b SS |
312 | */ |
313 | if (lookup_address(address, &level) && (level != PG_LEVEL_4K)) | |
314 | pgprot_val(forbidden) |= _PAGE_RW; | |
315 | } | |
74e08179 SS |
316 | #endif |
317 | ||
ed724be6 | 318 | prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden)); |
687c4825 IM |
319 | |
320 | return prot; | |
321 | } | |
322 | ||
426e34cc MF |
323 | /* |
324 | * Lookup the page table entry for a virtual address in a specific pgd. | |
325 | * Return a pointer to the entry and the level of the mapping. | |
326 | */ | |
327 | pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long address, | |
328 | unsigned int *level) | |
9f4c815c | 329 | { |
1da177e4 LT |
330 | pud_t *pud; |
331 | pmd_t *pmd; | |
9f4c815c | 332 | |
30551bb3 TG |
333 | *level = PG_LEVEL_NONE; |
334 | ||
1da177e4 LT |
335 | if (pgd_none(*pgd)) |
336 | return NULL; | |
9df84993 | 337 | |
1da177e4 LT |
338 | pud = pud_offset(pgd, address); |
339 | if (pud_none(*pud)) | |
340 | return NULL; | |
c2f71ee2 AK |
341 | |
342 | *level = PG_LEVEL_1G; | |
343 | if (pud_large(*pud) || !pud_present(*pud)) | |
344 | return (pte_t *)pud; | |
345 | ||
1da177e4 LT |
346 | pmd = pmd_offset(pud, address); |
347 | if (pmd_none(*pmd)) | |
348 | return NULL; | |
30551bb3 TG |
349 | |
350 | *level = PG_LEVEL_2M; | |
9a14aefc | 351 | if (pmd_large(*pmd) || !pmd_present(*pmd)) |
1da177e4 | 352 | return (pte_t *)pmd; |
1da177e4 | 353 | |
30551bb3 | 354 | *level = PG_LEVEL_4K; |
9df84993 | 355 | |
9f4c815c IM |
356 | return pte_offset_kernel(pmd, address); |
357 | } | |
0fd64c23 BP |
358 | |
359 | /* | |
360 | * Lookup the page table entry for a virtual address. Return a pointer | |
361 | * to the entry and the level of the mapping. | |
362 | * | |
363 | * Note: We return pud and pmd either when the entry is marked large | |
364 | * or when the present bit is not set. Otherwise we would return a | |
365 | * pointer to a nonexisting mapping. | |
366 | */ | |
367 | pte_t *lookup_address(unsigned long address, unsigned int *level) | |
368 | { | |
426e34cc | 369 | return lookup_address_in_pgd(pgd_offset_k(address), address, level); |
0fd64c23 | 370 | } |
75bb8835 | 371 | EXPORT_SYMBOL_GPL(lookup_address); |
9f4c815c | 372 | |
0fd64c23 BP |
373 | static pte_t *_lookup_address_cpa(struct cpa_data *cpa, unsigned long address, |
374 | unsigned int *level) | |
375 | { | |
376 | if (cpa->pgd) | |
426e34cc | 377 | return lookup_address_in_pgd(cpa->pgd + pgd_index(address), |
0fd64c23 BP |
378 | address, level); |
379 | ||
380 | return lookup_address(address, level); | |
381 | } | |
382 | ||
792230c3 JG |
383 | /* |
384 | * Lookup the PMD entry for a virtual address. Return a pointer to the entry | |
385 | * or NULL if not present. | |
386 | */ | |
387 | pmd_t *lookup_pmd_address(unsigned long address) | |
388 | { | |
389 | pgd_t *pgd; | |
390 | pud_t *pud; | |
391 | ||
392 | pgd = pgd_offset_k(address); | |
393 | if (pgd_none(*pgd)) | |
394 | return NULL; | |
395 | ||
396 | pud = pud_offset(pgd, address); | |
397 | if (pud_none(*pud) || pud_large(*pud) || !pud_present(*pud)) | |
398 | return NULL; | |
399 | ||
400 | return pmd_offset(pud, address); | |
401 | } | |
402 | ||
d7656534 DH |
403 | /* |
404 | * This is necessary because __pa() does not work on some | |
405 | * kinds of memory, like vmalloc() or the alloc_remap() | |
406 | * areas on 32-bit NUMA systems. The percpu areas can | |
407 | * end up in this kind of memory, for instance. | |
408 | * | |
409 | * This could be optimized, but it is only intended to be | |
410 | * used at inititalization time, and keeping it | |
411 | * unoptimized should increase the testing coverage for | |
412 | * the more obscure platforms. | |
413 | */ | |
414 | phys_addr_t slow_virt_to_phys(void *__virt_addr) | |
415 | { | |
416 | unsigned long virt_addr = (unsigned long)__virt_addr; | |
34437e67 | 417 | unsigned long phys_addr, offset; |
d7656534 | 418 | enum pg_level level; |
d7656534 DH |
419 | pte_t *pte; |
420 | ||
421 | pte = lookup_address(virt_addr, &level); | |
422 | BUG_ON(!pte); | |
34437e67 TK |
423 | |
424 | switch (level) { | |
425 | case PG_LEVEL_1G: | |
426 | phys_addr = pud_pfn(*(pud_t *)pte) << PAGE_SHIFT; | |
427 | offset = virt_addr & ~PUD_PAGE_MASK; | |
428 | break; | |
429 | case PG_LEVEL_2M: | |
430 | phys_addr = pmd_pfn(*(pmd_t *)pte) << PAGE_SHIFT; | |
431 | offset = virt_addr & ~PMD_PAGE_MASK; | |
432 | break; | |
433 | default: | |
434 | phys_addr = pte_pfn(*pte) << PAGE_SHIFT; | |
435 | offset = virt_addr & ~PAGE_MASK; | |
436 | } | |
437 | ||
438 | return (phys_addr_t)(phys_addr | offset); | |
d7656534 DH |
439 | } |
440 | EXPORT_SYMBOL_GPL(slow_virt_to_phys); | |
441 | ||
9df84993 IM |
442 | /* |
443 | * Set the new pmd in all the pgds we know about: | |
444 | */ | |
9a3dc780 | 445 | static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) |
9f4c815c | 446 | { |
9f4c815c IM |
447 | /* change init_mm */ |
448 | set_pte_atomic(kpte, pte); | |
44af6c41 | 449 | #ifdef CONFIG_X86_32 |
e4b71dcf | 450 | if (!SHARED_KERNEL_PMD) { |
44af6c41 IM |
451 | struct page *page; |
452 | ||
e3ed910d | 453 | list_for_each_entry(page, &pgd_list, lru) { |
44af6c41 IM |
454 | pgd_t *pgd; |
455 | pud_t *pud; | |
456 | pmd_t *pmd; | |
457 | ||
458 | pgd = (pgd_t *)page_address(page) + pgd_index(address); | |
459 | pud = pud_offset(pgd, address); | |
460 | pmd = pmd_offset(pud, address); | |
461 | set_pte_atomic((pte_t *)pmd, pte); | |
462 | } | |
1da177e4 | 463 | } |
44af6c41 | 464 | #endif |
1da177e4 LT |
465 | } |
466 | ||
9df84993 IM |
467 | static int |
468 | try_preserve_large_page(pte_t *kpte, unsigned long address, | |
469 | struct cpa_data *cpa) | |
65e074df | 470 | { |
3a19109e | 471 | unsigned long nextpage_addr, numpages, pmask, psize, addr, pfn, old_pfn; |
65e074df | 472 | pte_t new_pte, old_pte, *tmp; |
64edc8ed | 473 | pgprot_t old_prot, new_prot, req_prot; |
fac84939 | 474 | int i, do_split = 1; |
f3c4fbb6 | 475 | enum pg_level level; |
65e074df | 476 | |
c9caa02c AK |
477 | if (cpa->force_split) |
478 | return 1; | |
479 | ||
a79e53d8 | 480 | spin_lock(&pgd_lock); |
65e074df TG |
481 | /* |
482 | * Check for races, another CPU might have split this page | |
483 | * up already: | |
484 | */ | |
82f0712c | 485 | tmp = _lookup_address_cpa(cpa, address, &level); |
65e074df TG |
486 | if (tmp != kpte) |
487 | goto out_unlock; | |
488 | ||
489 | switch (level) { | |
490 | case PG_LEVEL_2M: | |
3a19109e TK |
491 | old_prot = pmd_pgprot(*(pmd_t *)kpte); |
492 | old_pfn = pmd_pfn(*(pmd_t *)kpte); | |
493 | break; | |
65e074df | 494 | case PG_LEVEL_1G: |
3a19109e TK |
495 | old_prot = pud_pgprot(*(pud_t *)kpte); |
496 | old_pfn = pud_pfn(*(pud_t *)kpte); | |
f3c4fbb6 | 497 | break; |
65e074df | 498 | default: |
beaff633 | 499 | do_split = -EINVAL; |
65e074df TG |
500 | goto out_unlock; |
501 | } | |
502 | ||
3a19109e TK |
503 | psize = page_level_size(level); |
504 | pmask = page_level_mask(level); | |
505 | ||
65e074df TG |
506 | /* |
507 | * Calculate the number of pages, which fit into this large | |
508 | * page starting at address: | |
509 | */ | |
510 | nextpage_addr = (address + psize) & pmask; | |
511 | numpages = (nextpage_addr - address) >> PAGE_SHIFT; | |
9b5cf48b RW |
512 | if (numpages < cpa->numpages) |
513 | cpa->numpages = numpages; | |
65e074df TG |
514 | |
515 | /* | |
516 | * We are safe now. Check whether the new pgprot is the same: | |
f5b2831d JG |
517 | * Convert protection attributes to 4k-format, as cpa->mask* are set |
518 | * up accordingly. | |
65e074df TG |
519 | */ |
520 | old_pte = *kpte; | |
55696b1f | 521 | req_prot = pgprot_large_2_4k(old_prot); |
65e074df | 522 | |
64edc8ed | 523 | pgprot_val(req_prot) &= ~pgprot_val(cpa->mask_clr); |
524 | pgprot_val(req_prot) |= pgprot_val(cpa->mask_set); | |
c31c7d48 | 525 | |
f5b2831d JG |
526 | /* |
527 | * req_prot is in format of 4k pages. It must be converted to large | |
528 | * page format: the caching mode includes the PAT bit located at | |
529 | * different bit positions in the two formats. | |
530 | */ | |
531 | req_prot = pgprot_4k_2_large(req_prot); | |
532 | ||
a8aed3e0 AA |
533 | /* |
534 | * Set the PSE and GLOBAL flags only if the PRESENT flag is | |
535 | * set otherwise pmd_present/pmd_huge will return true even on | |
536 | * a non present pmd. The canon_pgprot will clear _PAGE_GLOBAL | |
537 | * for the ancient hardware that doesn't support it. | |
538 | */ | |
f76cfa3c AA |
539 | if (pgprot_val(req_prot) & _PAGE_PRESENT) |
540 | pgprot_val(req_prot) |= _PAGE_PSE | _PAGE_GLOBAL; | |
a8aed3e0 | 541 | else |
f76cfa3c | 542 | pgprot_val(req_prot) &= ~(_PAGE_PSE | _PAGE_GLOBAL); |
a8aed3e0 | 543 | |
f76cfa3c | 544 | req_prot = canon_pgprot(req_prot); |
a8aed3e0 | 545 | |
c31c7d48 | 546 | /* |
3a19109e | 547 | * old_pfn points to the large page base pfn. So we need |
c31c7d48 TG |
548 | * to add the offset of the virtual address: |
549 | */ | |
3a19109e | 550 | pfn = old_pfn + ((address & (psize - 1)) >> PAGE_SHIFT); |
c31c7d48 TG |
551 | cpa->pfn = pfn; |
552 | ||
64edc8ed | 553 | new_prot = static_protections(req_prot, address, pfn); |
65e074df | 554 | |
fac84939 TG |
555 | /* |
556 | * We need to check the full range, whether | |
557 | * static_protection() requires a different pgprot for one of | |
558 | * the pages in the range we try to preserve: | |
559 | */ | |
64edc8ed | 560 | addr = address & pmask; |
3a19109e | 561 | pfn = old_pfn; |
64edc8ed | 562 | for (i = 0; i < (psize >> PAGE_SHIFT); i++, addr += PAGE_SIZE, pfn++) { |
563 | pgprot_t chk_prot = static_protections(req_prot, addr, pfn); | |
fac84939 TG |
564 | |
565 | if (pgprot_val(chk_prot) != pgprot_val(new_prot)) | |
566 | goto out_unlock; | |
567 | } | |
568 | ||
65e074df TG |
569 | /* |
570 | * If there are no changes, return. maxpages has been updated | |
571 | * above: | |
572 | */ | |
573 | if (pgprot_val(new_prot) == pgprot_val(old_prot)) { | |
beaff633 | 574 | do_split = 0; |
65e074df TG |
575 | goto out_unlock; |
576 | } | |
577 | ||
578 | /* | |
579 | * We need to change the attributes. Check, whether we can | |
580 | * change the large page in one go. We request a split, when | |
581 | * the address is not aligned and the number of pages is | |
582 | * smaller than the number of pages in the large page. Note | |
583 | * that we limited the number of possible pages already to | |
584 | * the number of pages in the large page. | |
585 | */ | |
64edc8ed | 586 | if (address == (address & pmask) && cpa->numpages == (psize >> PAGE_SHIFT)) { |
65e074df TG |
587 | /* |
588 | * The address is aligned and the number of pages | |
589 | * covers the full page. | |
590 | */ | |
3a19109e | 591 | new_pte = pfn_pte(old_pfn, new_prot); |
65e074df | 592 | __set_pmd_pte(kpte, address, new_pte); |
d75586ad | 593 | cpa->flags |= CPA_FLUSHTLB; |
beaff633 | 594 | do_split = 0; |
65e074df TG |
595 | } |
596 | ||
597 | out_unlock: | |
a79e53d8 | 598 | spin_unlock(&pgd_lock); |
9df84993 | 599 | |
beaff633 | 600 | return do_split; |
65e074df TG |
601 | } |
602 | ||
5952886b | 603 | static int |
82f0712c BP |
604 | __split_large_page(struct cpa_data *cpa, pte_t *kpte, unsigned long address, |
605 | struct page *base) | |
bb5c2dbd | 606 | { |
5952886b | 607 | pte_t *pbase = (pte_t *)page_address(base); |
d551aaa2 | 608 | unsigned long ref_pfn, pfn, pfninc = 1; |
9df84993 | 609 | unsigned int i, level; |
ae9aae9e | 610 | pte_t *tmp; |
9df84993 | 611 | pgprot_t ref_prot; |
bb5c2dbd | 612 | |
a79e53d8 | 613 | spin_lock(&pgd_lock); |
bb5c2dbd IM |
614 | /* |
615 | * Check for races, another CPU might have split this page | |
616 | * up for us already: | |
617 | */ | |
82f0712c | 618 | tmp = _lookup_address_cpa(cpa, address, &level); |
ae9aae9e WC |
619 | if (tmp != kpte) { |
620 | spin_unlock(&pgd_lock); | |
621 | return 1; | |
622 | } | |
bb5c2dbd | 623 | |
6944a9c8 | 624 | paravirt_alloc_pte(&init_mm, page_to_pfn(base)); |
f5b2831d | 625 | |
d551aaa2 TK |
626 | switch (level) { |
627 | case PG_LEVEL_2M: | |
628 | ref_prot = pmd_pgprot(*(pmd_t *)kpte); | |
629 | /* clear PSE and promote PAT bit to correct position */ | |
f5b2831d | 630 | ref_prot = pgprot_large_2_4k(ref_prot); |
d551aaa2 TK |
631 | ref_pfn = pmd_pfn(*(pmd_t *)kpte); |
632 | break; | |
bb5c2dbd | 633 | |
d551aaa2 TK |
634 | case PG_LEVEL_1G: |
635 | ref_prot = pud_pgprot(*(pud_t *)kpte); | |
636 | ref_pfn = pud_pfn(*(pud_t *)kpte); | |
f07333fd | 637 | pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT; |
d551aaa2 | 638 | |
a8aed3e0 | 639 | /* |
d551aaa2 | 640 | * Clear the PSE flags if the PRESENT flag is not set |
a8aed3e0 AA |
641 | * otherwise pmd_present/pmd_huge will return true |
642 | * even on a non present pmd. | |
643 | */ | |
d551aaa2 | 644 | if (!(pgprot_val(ref_prot) & _PAGE_PRESENT)) |
a8aed3e0 | 645 | pgprot_val(ref_prot) &= ~_PAGE_PSE; |
d551aaa2 TK |
646 | break; |
647 | ||
648 | default: | |
649 | spin_unlock(&pgd_lock); | |
650 | return 1; | |
f07333fd | 651 | } |
f07333fd | 652 | |
a8aed3e0 AA |
653 | /* |
654 | * Set the GLOBAL flags only if the PRESENT flag is set | |
655 | * otherwise pmd/pte_present will return true even on a non | |
656 | * present pmd/pte. The canon_pgprot will clear _PAGE_GLOBAL | |
657 | * for the ancient hardware that doesn't support it. | |
658 | */ | |
659 | if (pgprot_val(ref_prot) & _PAGE_PRESENT) | |
660 | pgprot_val(ref_prot) |= _PAGE_GLOBAL; | |
661 | else | |
662 | pgprot_val(ref_prot) &= ~_PAGE_GLOBAL; | |
663 | ||
63c1dcf4 TG |
664 | /* |
665 | * Get the target pfn from the original entry: | |
666 | */ | |
d551aaa2 | 667 | pfn = ref_pfn; |
f07333fd | 668 | for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc) |
a8aed3e0 | 669 | set_pte(&pbase[i], pfn_pte(pfn, canon_pgprot(ref_prot))); |
bb5c2dbd | 670 | |
2c66e24d SP |
671 | if (virt_addr_valid(address)) { |
672 | unsigned long pfn = PFN_DOWN(__pa(address)); | |
673 | ||
674 | if (pfn_range_is_mapped(pfn, pfn + 1)) | |
675 | split_page_count(level); | |
676 | } | |
f361a450 | 677 | |
bb5c2dbd | 678 | /* |
07a66d7c | 679 | * Install the new, split up pagetable. |
4c881ca1 | 680 | * |
07a66d7c IM |
681 | * We use the standard kernel pagetable protections for the new |
682 | * pagetable protections, the actual ptes set above control the | |
683 | * primary protection behavior: | |
bb5c2dbd | 684 | */ |
07a66d7c | 685 | __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); |
211b3d03 IM |
686 | |
687 | /* | |
688 | * Intel Atom errata AAH41 workaround. | |
689 | * | |
690 | * The real fix should be in hw or in a microcode update, but | |
691 | * we also probabilistically try to reduce the window of having | |
692 | * a large TLB mixed with 4K TLBs while instruction fetches are | |
693 | * going on. | |
694 | */ | |
695 | __flush_tlb_all(); | |
ae9aae9e | 696 | spin_unlock(&pgd_lock); |
211b3d03 | 697 | |
ae9aae9e WC |
698 | return 0; |
699 | } | |
bb5c2dbd | 700 | |
82f0712c BP |
701 | static int split_large_page(struct cpa_data *cpa, pte_t *kpte, |
702 | unsigned long address) | |
ae9aae9e | 703 | { |
ae9aae9e WC |
704 | struct page *base; |
705 | ||
706 | if (!debug_pagealloc) | |
707 | spin_unlock(&cpa_lock); | |
708 | base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0); | |
709 | if (!debug_pagealloc) | |
710 | spin_lock(&cpa_lock); | |
711 | if (!base) | |
712 | return -ENOMEM; | |
713 | ||
82f0712c | 714 | if (__split_large_page(cpa, kpte, address, base)) |
8311eb84 | 715 | __free_page(base); |
bb5c2dbd | 716 | |
bb5c2dbd IM |
717 | return 0; |
718 | } | |
719 | ||
52a628fb BP |
720 | static bool try_to_free_pte_page(pte_t *pte) |
721 | { | |
722 | int i; | |
723 | ||
724 | for (i = 0; i < PTRS_PER_PTE; i++) | |
725 | if (!pte_none(pte[i])) | |
726 | return false; | |
727 | ||
728 | free_page((unsigned long)pte); | |
729 | return true; | |
730 | } | |
731 | ||
732 | static bool try_to_free_pmd_page(pmd_t *pmd) | |
733 | { | |
734 | int i; | |
735 | ||
736 | for (i = 0; i < PTRS_PER_PMD; i++) | |
737 | if (!pmd_none(pmd[i])) | |
738 | return false; | |
739 | ||
740 | free_page((unsigned long)pmd); | |
741 | return true; | |
742 | } | |
743 | ||
42a54772 BP |
744 | static bool try_to_free_pud_page(pud_t *pud) |
745 | { | |
746 | int i; | |
747 | ||
748 | for (i = 0; i < PTRS_PER_PUD; i++) | |
749 | if (!pud_none(pud[i])) | |
750 | return false; | |
751 | ||
752 | free_page((unsigned long)pud); | |
753 | return true; | |
754 | } | |
755 | ||
52a628fb BP |
756 | static bool unmap_pte_range(pmd_t *pmd, unsigned long start, unsigned long end) |
757 | { | |
758 | pte_t *pte = pte_offset_kernel(pmd, start); | |
759 | ||
760 | while (start < end) { | |
761 | set_pte(pte, __pte(0)); | |
762 | ||
763 | start += PAGE_SIZE; | |
764 | pte++; | |
765 | } | |
766 | ||
767 | if (try_to_free_pte_page((pte_t *)pmd_page_vaddr(*pmd))) { | |
768 | pmd_clear(pmd); | |
769 | return true; | |
770 | } | |
771 | return false; | |
772 | } | |
773 | ||
774 | static void __unmap_pmd_range(pud_t *pud, pmd_t *pmd, | |
775 | unsigned long start, unsigned long end) | |
776 | { | |
777 | if (unmap_pte_range(pmd, start, end)) | |
778 | if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud))) | |
779 | pud_clear(pud); | |
780 | } | |
781 | ||
782 | static void unmap_pmd_range(pud_t *pud, unsigned long start, unsigned long end) | |
783 | { | |
784 | pmd_t *pmd = pmd_offset(pud, start); | |
785 | ||
786 | /* | |
787 | * Not on a 2MB page boundary? | |
788 | */ | |
789 | if (start & (PMD_SIZE - 1)) { | |
790 | unsigned long next_page = (start + PMD_SIZE) & PMD_MASK; | |
791 | unsigned long pre_end = min_t(unsigned long, end, next_page); | |
792 | ||
793 | __unmap_pmd_range(pud, pmd, start, pre_end); | |
794 | ||
795 | start = pre_end; | |
796 | pmd++; | |
797 | } | |
798 | ||
799 | /* | |
800 | * Try to unmap in 2M chunks. | |
801 | */ | |
802 | while (end - start >= PMD_SIZE) { | |
803 | if (pmd_large(*pmd)) | |
804 | pmd_clear(pmd); | |
805 | else | |
806 | __unmap_pmd_range(pud, pmd, start, start + PMD_SIZE); | |
807 | ||
808 | start += PMD_SIZE; | |
809 | pmd++; | |
810 | } | |
811 | ||
812 | /* | |
813 | * 4K leftovers? | |
814 | */ | |
815 | if (start < end) | |
816 | return __unmap_pmd_range(pud, pmd, start, end); | |
817 | ||
818 | /* | |
819 | * Try again to free the PMD page if haven't succeeded above. | |
820 | */ | |
821 | if (!pud_none(*pud)) | |
822 | if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud))) | |
823 | pud_clear(pud); | |
824 | } | |
0bb8aeee BP |
825 | |
826 | static void unmap_pud_range(pgd_t *pgd, unsigned long start, unsigned long end) | |
827 | { | |
828 | pud_t *pud = pud_offset(pgd, start); | |
829 | ||
830 | /* | |
831 | * Not on a GB page boundary? | |
832 | */ | |
833 | if (start & (PUD_SIZE - 1)) { | |
834 | unsigned long next_page = (start + PUD_SIZE) & PUD_MASK; | |
835 | unsigned long pre_end = min_t(unsigned long, end, next_page); | |
836 | ||
837 | unmap_pmd_range(pud, start, pre_end); | |
838 | ||
839 | start = pre_end; | |
840 | pud++; | |
841 | } | |
842 | ||
843 | /* | |
844 | * Try to unmap in 1G chunks? | |
845 | */ | |
846 | while (end - start >= PUD_SIZE) { | |
847 | ||
848 | if (pud_large(*pud)) | |
849 | pud_clear(pud); | |
850 | else | |
851 | unmap_pmd_range(pud, start, start + PUD_SIZE); | |
852 | ||
853 | start += PUD_SIZE; | |
854 | pud++; | |
855 | } | |
856 | ||
857 | /* | |
858 | * 2M leftovers? | |
859 | */ | |
860 | if (start < end) | |
861 | unmap_pmd_range(pud, start, end); | |
862 | ||
863 | /* | |
864 | * No need to try to free the PUD page because we'll free it in | |
865 | * populate_pgd's error path | |
866 | */ | |
867 | } | |
868 | ||
42a54772 BP |
869 | static void unmap_pgd_range(pgd_t *root, unsigned long addr, unsigned long end) |
870 | { | |
871 | pgd_t *pgd_entry = root + pgd_index(addr); | |
872 | ||
873 | unmap_pud_range(pgd_entry, addr, end); | |
874 | ||
875 | if (try_to_free_pud_page((pud_t *)pgd_page_vaddr(*pgd_entry))) | |
876 | pgd_clear(pgd_entry); | |
877 | } | |
878 | ||
f900a4b8 BP |
879 | static int alloc_pte_page(pmd_t *pmd) |
880 | { | |
881 | pte_t *pte = (pte_t *)get_zeroed_page(GFP_KERNEL | __GFP_NOTRACK); | |
882 | if (!pte) | |
883 | return -1; | |
884 | ||
885 | set_pmd(pmd, __pmd(__pa(pte) | _KERNPG_TABLE)); | |
886 | return 0; | |
887 | } | |
888 | ||
4b23538d BP |
889 | static int alloc_pmd_page(pud_t *pud) |
890 | { | |
891 | pmd_t *pmd = (pmd_t *)get_zeroed_page(GFP_KERNEL | __GFP_NOTRACK); | |
892 | if (!pmd) | |
893 | return -1; | |
894 | ||
895 | set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE)); | |
896 | return 0; | |
897 | } | |
898 | ||
c6b6f363 BP |
899 | static void populate_pte(struct cpa_data *cpa, |
900 | unsigned long start, unsigned long end, | |
901 | unsigned num_pages, pmd_t *pmd, pgprot_t pgprot) | |
902 | { | |
903 | pte_t *pte; | |
904 | ||
905 | pte = pte_offset_kernel(pmd, start); | |
906 | ||
907 | while (num_pages-- && start < end) { | |
908 | ||
909 | /* deal with the NX bit */ | |
910 | if (!(pgprot_val(pgprot) & _PAGE_NX)) | |
911 | cpa->pfn &= ~_PAGE_NX; | |
912 | ||
913 | set_pte(pte, pfn_pte(cpa->pfn >> PAGE_SHIFT, pgprot)); | |
914 | ||
915 | start += PAGE_SIZE; | |
916 | cpa->pfn += PAGE_SIZE; | |
917 | pte++; | |
918 | } | |
919 | } | |
f900a4b8 BP |
920 | |
921 | static int populate_pmd(struct cpa_data *cpa, | |
922 | unsigned long start, unsigned long end, | |
923 | unsigned num_pages, pud_t *pud, pgprot_t pgprot) | |
924 | { | |
925 | unsigned int cur_pages = 0; | |
926 | pmd_t *pmd; | |
f5b2831d | 927 | pgprot_t pmd_pgprot; |
f900a4b8 BP |
928 | |
929 | /* | |
930 | * Not on a 2M boundary? | |
931 | */ | |
932 | if (start & (PMD_SIZE - 1)) { | |
933 | unsigned long pre_end = start + (num_pages << PAGE_SHIFT); | |
934 | unsigned long next_page = (start + PMD_SIZE) & PMD_MASK; | |
935 | ||
936 | pre_end = min_t(unsigned long, pre_end, next_page); | |
937 | cur_pages = (pre_end - start) >> PAGE_SHIFT; | |
938 | cur_pages = min_t(unsigned int, num_pages, cur_pages); | |
939 | ||
940 | /* | |
941 | * Need a PTE page? | |
942 | */ | |
943 | pmd = pmd_offset(pud, start); | |
944 | if (pmd_none(*pmd)) | |
945 | if (alloc_pte_page(pmd)) | |
946 | return -1; | |
947 | ||
948 | populate_pte(cpa, start, pre_end, cur_pages, pmd, pgprot); | |
949 | ||
950 | start = pre_end; | |
951 | } | |
952 | ||
953 | /* | |
954 | * We mapped them all? | |
955 | */ | |
956 | if (num_pages == cur_pages) | |
957 | return cur_pages; | |
958 | ||
f5b2831d JG |
959 | pmd_pgprot = pgprot_4k_2_large(pgprot); |
960 | ||
f900a4b8 BP |
961 | while (end - start >= PMD_SIZE) { |
962 | ||
963 | /* | |
964 | * We cannot use a 1G page so allocate a PMD page if needed. | |
965 | */ | |
966 | if (pud_none(*pud)) | |
967 | if (alloc_pmd_page(pud)) | |
968 | return -1; | |
969 | ||
970 | pmd = pmd_offset(pud, start); | |
971 | ||
f5b2831d JG |
972 | set_pmd(pmd, __pmd(cpa->pfn | _PAGE_PSE | |
973 | massage_pgprot(pmd_pgprot))); | |
f900a4b8 BP |
974 | |
975 | start += PMD_SIZE; | |
976 | cpa->pfn += PMD_SIZE; | |
977 | cur_pages += PMD_SIZE >> PAGE_SHIFT; | |
978 | } | |
979 | ||
980 | /* | |
981 | * Map trailing 4K pages. | |
982 | */ | |
983 | if (start < end) { | |
984 | pmd = pmd_offset(pud, start); | |
985 | if (pmd_none(*pmd)) | |
986 | if (alloc_pte_page(pmd)) | |
987 | return -1; | |
988 | ||
989 | populate_pte(cpa, start, end, num_pages - cur_pages, | |
990 | pmd, pgprot); | |
991 | } | |
992 | return num_pages; | |
993 | } | |
4b23538d BP |
994 | |
995 | static int populate_pud(struct cpa_data *cpa, unsigned long start, pgd_t *pgd, | |
996 | pgprot_t pgprot) | |
997 | { | |
998 | pud_t *pud; | |
999 | unsigned long end; | |
1000 | int cur_pages = 0; | |
f5b2831d | 1001 | pgprot_t pud_pgprot; |
4b23538d BP |
1002 | |
1003 | end = start + (cpa->numpages << PAGE_SHIFT); | |
1004 | ||
1005 | /* | |
1006 | * Not on a Gb page boundary? => map everything up to it with | |
1007 | * smaller pages. | |
1008 | */ | |
1009 | if (start & (PUD_SIZE - 1)) { | |
1010 | unsigned long pre_end; | |
1011 | unsigned long next_page = (start + PUD_SIZE) & PUD_MASK; | |
1012 | ||
1013 | pre_end = min_t(unsigned long, end, next_page); | |
1014 | cur_pages = (pre_end - start) >> PAGE_SHIFT; | |
1015 | cur_pages = min_t(int, (int)cpa->numpages, cur_pages); | |
1016 | ||
1017 | pud = pud_offset(pgd, start); | |
1018 | ||
1019 | /* | |
1020 | * Need a PMD page? | |
1021 | */ | |
1022 | if (pud_none(*pud)) | |
1023 | if (alloc_pmd_page(pud)) | |
1024 | return -1; | |
1025 | ||
1026 | cur_pages = populate_pmd(cpa, start, pre_end, cur_pages, | |
1027 | pud, pgprot); | |
1028 | if (cur_pages < 0) | |
1029 | return cur_pages; | |
1030 | ||
1031 | start = pre_end; | |
1032 | } | |
1033 | ||
1034 | /* We mapped them all? */ | |
1035 | if (cpa->numpages == cur_pages) | |
1036 | return cur_pages; | |
1037 | ||
1038 | pud = pud_offset(pgd, start); | |
f5b2831d | 1039 | pud_pgprot = pgprot_4k_2_large(pgprot); |
4b23538d BP |
1040 | |
1041 | /* | |
1042 | * Map everything starting from the Gb boundary, possibly with 1G pages | |
1043 | */ | |
1044 | while (end - start >= PUD_SIZE) { | |
f5b2831d JG |
1045 | set_pud(pud, __pud(cpa->pfn | _PAGE_PSE | |
1046 | massage_pgprot(pud_pgprot))); | |
4b23538d BP |
1047 | |
1048 | start += PUD_SIZE; | |
1049 | cpa->pfn += PUD_SIZE; | |
1050 | cur_pages += PUD_SIZE >> PAGE_SHIFT; | |
1051 | pud++; | |
1052 | } | |
1053 | ||
1054 | /* Map trailing leftover */ | |
1055 | if (start < end) { | |
1056 | int tmp; | |
1057 | ||
1058 | pud = pud_offset(pgd, start); | |
1059 | if (pud_none(*pud)) | |
1060 | if (alloc_pmd_page(pud)) | |
1061 | return -1; | |
1062 | ||
1063 | tmp = populate_pmd(cpa, start, end, cpa->numpages - cur_pages, | |
1064 | pud, pgprot); | |
1065 | if (tmp < 0) | |
1066 | return cur_pages; | |
1067 | ||
1068 | cur_pages += tmp; | |
1069 | } | |
1070 | return cur_pages; | |
1071 | } | |
f3f72966 BP |
1072 | |
1073 | /* | |
1074 | * Restrictions for kernel page table do not necessarily apply when mapping in | |
1075 | * an alternate PGD. | |
1076 | */ | |
1077 | static int populate_pgd(struct cpa_data *cpa, unsigned long addr) | |
1078 | { | |
1079 | pgprot_t pgprot = __pgprot(_KERNPG_TABLE); | |
f3f72966 | 1080 | pud_t *pud = NULL; /* shut up gcc */ |
42a54772 | 1081 | pgd_t *pgd_entry; |
f3f72966 BP |
1082 | int ret; |
1083 | ||
1084 | pgd_entry = cpa->pgd + pgd_index(addr); | |
1085 | ||
1086 | /* | |
1087 | * Allocate a PUD page and hand it down for mapping. | |
1088 | */ | |
1089 | if (pgd_none(*pgd_entry)) { | |
1090 | pud = (pud_t *)get_zeroed_page(GFP_KERNEL | __GFP_NOTRACK); | |
1091 | if (!pud) | |
1092 | return -1; | |
1093 | ||
1094 | set_pgd(pgd_entry, __pgd(__pa(pud) | _KERNPG_TABLE)); | |
f3f72966 BP |
1095 | } |
1096 | ||
1097 | pgprot_val(pgprot) &= ~pgprot_val(cpa->mask_clr); | |
1098 | pgprot_val(pgprot) |= pgprot_val(cpa->mask_set); | |
1099 | ||
1100 | ret = populate_pud(cpa, addr, pgd_entry, pgprot); | |
0bb8aeee | 1101 | if (ret < 0) { |
42a54772 | 1102 | unmap_pgd_range(cpa->pgd, addr, |
0bb8aeee | 1103 | addr + (cpa->numpages << PAGE_SHIFT)); |
f3f72966 | 1104 | return ret; |
0bb8aeee | 1105 | } |
42a54772 | 1106 | |
f3f72966 BP |
1107 | cpa->numpages = ret; |
1108 | return 0; | |
1109 | } | |
1110 | ||
a1e46212 SS |
1111 | static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr, |
1112 | int primary) | |
1113 | { | |
82f0712c BP |
1114 | if (cpa->pgd) |
1115 | return populate_pgd(cpa, vaddr); | |
1116 | ||
a1e46212 SS |
1117 | /* |
1118 | * Ignore all non primary paths. | |
1119 | */ | |
1120 | if (!primary) | |
1121 | return 0; | |
1122 | ||
1123 | /* | |
1124 | * Ignore the NULL PTE for kernel identity mapping, as it is expected | |
1125 | * to have holes. | |
1126 | * Also set numpages to '1' indicating that we processed cpa req for | |
1127 | * one virtual address page and its pfn. TBD: numpages can be set based | |
1128 | * on the initial value and the level returned by lookup_address(). | |
1129 | */ | |
1130 | if (within(vaddr, PAGE_OFFSET, | |
1131 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) { | |
1132 | cpa->numpages = 1; | |
1133 | cpa->pfn = __pa(vaddr) >> PAGE_SHIFT; | |
1134 | return 0; | |
1135 | } else { | |
1136 | WARN(1, KERN_WARNING "CPA: called for zero pte. " | |
1137 | "vaddr = %lx cpa->vaddr = %lx\n", vaddr, | |
1138 | *cpa->vaddr); | |
1139 | ||
1140 | return -EFAULT; | |
1141 | } | |
1142 | } | |
1143 | ||
c31c7d48 | 1144 | static int __change_page_attr(struct cpa_data *cpa, int primary) |
9f4c815c | 1145 | { |
d75586ad | 1146 | unsigned long address; |
da7bfc50 HH |
1147 | int do_split, err; |
1148 | unsigned int level; | |
c31c7d48 | 1149 | pte_t *kpte, old_pte; |
1da177e4 | 1150 | |
8523acfe TH |
1151 | if (cpa->flags & CPA_PAGES_ARRAY) { |
1152 | struct page *page = cpa->pages[cpa->curpage]; | |
1153 | if (unlikely(PageHighMem(page))) | |
1154 | return 0; | |
1155 | address = (unsigned long)page_address(page); | |
1156 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
1157 | address = cpa->vaddr[cpa->curpage]; |
1158 | else | |
1159 | address = *cpa->vaddr; | |
97f99fed | 1160 | repeat: |
82f0712c | 1161 | kpte = _lookup_address_cpa(cpa, address, &level); |
1da177e4 | 1162 | if (!kpte) |
a1e46212 | 1163 | return __cpa_process_fault(cpa, address, primary); |
c31c7d48 TG |
1164 | |
1165 | old_pte = *kpte; | |
a1e46212 SS |
1166 | if (!pte_val(old_pte)) |
1167 | return __cpa_process_fault(cpa, address, primary); | |
9f4c815c | 1168 | |
30551bb3 | 1169 | if (level == PG_LEVEL_4K) { |
c31c7d48 | 1170 | pte_t new_pte; |
626c2c9d | 1171 | pgprot_t new_prot = pte_pgprot(old_pte); |
c31c7d48 | 1172 | unsigned long pfn = pte_pfn(old_pte); |
86f03989 | 1173 | |
72e458df TG |
1174 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); |
1175 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
86f03989 | 1176 | |
c31c7d48 | 1177 | new_prot = static_protections(new_prot, address, pfn); |
86f03989 | 1178 | |
a8aed3e0 AA |
1179 | /* |
1180 | * Set the GLOBAL flags only if the PRESENT flag is | |
1181 | * set otherwise pte_present will return true even on | |
1182 | * a non present pte. The canon_pgprot will clear | |
1183 | * _PAGE_GLOBAL for the ancient hardware that doesn't | |
1184 | * support it. | |
1185 | */ | |
1186 | if (pgprot_val(new_prot) & _PAGE_PRESENT) | |
1187 | pgprot_val(new_prot) |= _PAGE_GLOBAL; | |
1188 | else | |
1189 | pgprot_val(new_prot) &= ~_PAGE_GLOBAL; | |
1190 | ||
626c2c9d AV |
1191 | /* |
1192 | * We need to keep the pfn from the existing PTE, | |
1193 | * after all we're only going to change it's attributes | |
1194 | * not the memory it points to | |
1195 | */ | |
c31c7d48 TG |
1196 | new_pte = pfn_pte(pfn, canon_pgprot(new_prot)); |
1197 | cpa->pfn = pfn; | |
f4ae5da0 TG |
1198 | /* |
1199 | * Do we really change anything ? | |
1200 | */ | |
1201 | if (pte_val(old_pte) != pte_val(new_pte)) { | |
1202 | set_pte_atomic(kpte, new_pte); | |
d75586ad | 1203 | cpa->flags |= CPA_FLUSHTLB; |
f4ae5da0 | 1204 | } |
9b5cf48b | 1205 | cpa->numpages = 1; |
65e074df | 1206 | return 0; |
1da177e4 | 1207 | } |
65e074df TG |
1208 | |
1209 | /* | |
1210 | * Check, whether we can keep the large page intact | |
1211 | * and just change the pte: | |
1212 | */ | |
beaff633 | 1213 | do_split = try_preserve_large_page(kpte, address, cpa); |
65e074df TG |
1214 | /* |
1215 | * When the range fits into the existing large page, | |
9b5cf48b | 1216 | * return. cp->numpages and cpa->tlbflush have been updated in |
65e074df TG |
1217 | * try_large_page: |
1218 | */ | |
87f7f8fe IM |
1219 | if (do_split <= 0) |
1220 | return do_split; | |
65e074df TG |
1221 | |
1222 | /* | |
1223 | * We have to split the large page: | |
1224 | */ | |
82f0712c | 1225 | err = split_large_page(cpa, kpte, address); |
87f7f8fe | 1226 | if (!err) { |
ad5ca55f SS |
1227 | /* |
1228 | * Do a global flush tlb after splitting the large page | |
1229 | * and before we do the actual change page attribute in the PTE. | |
1230 | * | |
1231 | * With out this, we violate the TLB application note, that says | |
1232 | * "The TLBs may contain both ordinary and large-page | |
1233 | * translations for a 4-KByte range of linear addresses. This | |
1234 | * may occur if software modifies the paging structures so that | |
1235 | * the page size used for the address range changes. If the two | |
1236 | * translations differ with respect to page frame or attributes | |
1237 | * (e.g., permissions), processor behavior is undefined and may | |
1238 | * be implementation-specific." | |
1239 | * | |
1240 | * We do this global tlb flush inside the cpa_lock, so that we | |
1241 | * don't allow any other cpu, with stale tlb entries change the | |
1242 | * page attribute in parallel, that also falls into the | |
1243 | * just split large page entry. | |
1244 | */ | |
1245 | flush_tlb_all(); | |
87f7f8fe IM |
1246 | goto repeat; |
1247 | } | |
beaff633 | 1248 | |
87f7f8fe | 1249 | return err; |
9f4c815c | 1250 | } |
1da177e4 | 1251 | |
c31c7d48 TG |
1252 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias); |
1253 | ||
1254 | static int cpa_process_alias(struct cpa_data *cpa) | |
1da177e4 | 1255 | { |
c31c7d48 | 1256 | struct cpa_data alias_cpa; |
992f4c1c | 1257 | unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT); |
e933a73f | 1258 | unsigned long vaddr; |
992f4c1c | 1259 | int ret; |
44af6c41 | 1260 | |
8eb5779f | 1261 | if (!pfn_range_is_mapped(cpa->pfn, cpa->pfn + 1)) |
c31c7d48 | 1262 | return 0; |
626c2c9d | 1263 | |
f34b439f TG |
1264 | /* |
1265 | * No need to redo, when the primary call touched the direct | |
1266 | * mapping already: | |
1267 | */ | |
8523acfe TH |
1268 | if (cpa->flags & CPA_PAGES_ARRAY) { |
1269 | struct page *page = cpa->pages[cpa->curpage]; | |
1270 | if (unlikely(PageHighMem(page))) | |
1271 | return 0; | |
1272 | vaddr = (unsigned long)page_address(page); | |
1273 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
1274 | vaddr = cpa->vaddr[cpa->curpage]; |
1275 | else | |
1276 | vaddr = *cpa->vaddr; | |
1277 | ||
1278 | if (!(within(vaddr, PAGE_OFFSET, | |
a1e46212 | 1279 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) { |
44af6c41 | 1280 | |
f34b439f | 1281 | alias_cpa = *cpa; |
992f4c1c | 1282 | alias_cpa.vaddr = &laddr; |
9ae28475 | 1283 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); |
d75586ad | 1284 | |
f34b439f | 1285 | ret = __change_page_attr_set_clr(&alias_cpa, 0); |
992f4c1c TH |
1286 | if (ret) |
1287 | return ret; | |
f34b439f | 1288 | } |
44af6c41 | 1289 | |
44af6c41 | 1290 | #ifdef CONFIG_X86_64 |
488fd995 | 1291 | /* |
992f4c1c TH |
1292 | * If the primary call didn't touch the high mapping already |
1293 | * and the physical address is inside the kernel map, we need | |
0879750f | 1294 | * to touch the high mapped kernel as well: |
488fd995 | 1295 | */ |
992f4c1c TH |
1296 | if (!within(vaddr, (unsigned long)_text, _brk_end) && |
1297 | within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) { | |
1298 | unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) + | |
1299 | __START_KERNEL_map - phys_base; | |
1300 | alias_cpa = *cpa; | |
1301 | alias_cpa.vaddr = &temp_cpa_vaddr; | |
1302 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); | |
c31c7d48 | 1303 | |
992f4c1c TH |
1304 | /* |
1305 | * The high mapping range is imprecise, so ignore the | |
1306 | * return value. | |
1307 | */ | |
1308 | __change_page_attr_set_clr(&alias_cpa, 0); | |
1309 | } | |
488fd995 | 1310 | #endif |
992f4c1c TH |
1311 | |
1312 | return 0; | |
1da177e4 LT |
1313 | } |
1314 | ||
c31c7d48 | 1315 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias) |
ff31452b | 1316 | { |
65e074df | 1317 | int ret, numpages = cpa->numpages; |
ff31452b | 1318 | |
65e074df TG |
1319 | while (numpages) { |
1320 | /* | |
1321 | * Store the remaining nr of pages for the large page | |
1322 | * preservation check. | |
1323 | */ | |
9b5cf48b | 1324 | cpa->numpages = numpages; |
d75586ad | 1325 | /* for array changes, we can't use large page */ |
9ae28475 | 1326 | if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
d75586ad | 1327 | cpa->numpages = 1; |
c31c7d48 | 1328 | |
ad5ca55f SS |
1329 | if (!debug_pagealloc) |
1330 | spin_lock(&cpa_lock); | |
c31c7d48 | 1331 | ret = __change_page_attr(cpa, checkalias); |
ad5ca55f SS |
1332 | if (!debug_pagealloc) |
1333 | spin_unlock(&cpa_lock); | |
ff31452b TG |
1334 | if (ret) |
1335 | return ret; | |
ff31452b | 1336 | |
c31c7d48 TG |
1337 | if (checkalias) { |
1338 | ret = cpa_process_alias(cpa); | |
1339 | if (ret) | |
1340 | return ret; | |
1341 | } | |
1342 | ||
65e074df TG |
1343 | /* |
1344 | * Adjust the number of pages with the result of the | |
1345 | * CPA operation. Either a large page has been | |
1346 | * preserved or a single page update happened. | |
1347 | */ | |
9b5cf48b RW |
1348 | BUG_ON(cpa->numpages > numpages); |
1349 | numpages -= cpa->numpages; | |
9ae28475 | 1350 | if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) |
d75586ad SL |
1351 | cpa->curpage++; |
1352 | else | |
1353 | *cpa->vaddr += cpa->numpages * PAGE_SIZE; | |
1354 | ||
65e074df | 1355 | } |
ff31452b TG |
1356 | return 0; |
1357 | } | |
1358 | ||
d75586ad | 1359 | static int change_page_attr_set_clr(unsigned long *addr, int numpages, |
c9caa02c | 1360 | pgprot_t mask_set, pgprot_t mask_clr, |
9ae28475 | 1361 | int force_split, int in_flag, |
1362 | struct page **pages) | |
ff31452b | 1363 | { |
72e458df | 1364 | struct cpa_data cpa; |
cacf8906 | 1365 | int ret, cache, checkalias; |
fa526d0d | 1366 | unsigned long baddr = 0; |
331e4065 | 1367 | |
82f0712c BP |
1368 | memset(&cpa, 0, sizeof(cpa)); |
1369 | ||
331e4065 TG |
1370 | /* |
1371 | * Check, if we are requested to change a not supported | |
1372 | * feature: | |
1373 | */ | |
1374 | mask_set = canon_pgprot(mask_set); | |
1375 | mask_clr = canon_pgprot(mask_clr); | |
c9caa02c | 1376 | if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split) |
331e4065 TG |
1377 | return 0; |
1378 | ||
69b1415e | 1379 | /* Ensure we are PAGE_SIZE aligned */ |
9ae28475 | 1380 | if (in_flag & CPA_ARRAY) { |
d75586ad SL |
1381 | int i; |
1382 | for (i = 0; i < numpages; i++) { | |
1383 | if (addr[i] & ~PAGE_MASK) { | |
1384 | addr[i] &= PAGE_MASK; | |
1385 | WARN_ON_ONCE(1); | |
1386 | } | |
1387 | } | |
9ae28475 | 1388 | } else if (!(in_flag & CPA_PAGES_ARRAY)) { |
1389 | /* | |
1390 | * in_flag of CPA_PAGES_ARRAY implies it is aligned. | |
1391 | * No need to cehck in that case | |
1392 | */ | |
1393 | if (*addr & ~PAGE_MASK) { | |
1394 | *addr &= PAGE_MASK; | |
1395 | /* | |
1396 | * People should not be passing in unaligned addresses: | |
1397 | */ | |
1398 | WARN_ON_ONCE(1); | |
1399 | } | |
fa526d0d JS |
1400 | /* |
1401 | * Save address for cache flush. *addr is modified in the call | |
1402 | * to __change_page_attr_set_clr() below. | |
1403 | */ | |
1404 | baddr = *addr; | |
69b1415e TG |
1405 | } |
1406 | ||
5843d9a4 NP |
1407 | /* Must avoid aliasing mappings in the highmem code */ |
1408 | kmap_flush_unused(); | |
1409 | ||
db64fe02 NP |
1410 | vm_unmap_aliases(); |
1411 | ||
72e458df | 1412 | cpa.vaddr = addr; |
9ae28475 | 1413 | cpa.pages = pages; |
72e458df TG |
1414 | cpa.numpages = numpages; |
1415 | cpa.mask_set = mask_set; | |
1416 | cpa.mask_clr = mask_clr; | |
d75586ad SL |
1417 | cpa.flags = 0; |
1418 | cpa.curpage = 0; | |
c9caa02c | 1419 | cpa.force_split = force_split; |
72e458df | 1420 | |
9ae28475 | 1421 | if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
1422 | cpa.flags |= in_flag; | |
d75586ad | 1423 | |
af96e443 TG |
1424 | /* No alias checking for _NX bit modifications */ |
1425 | checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX; | |
1426 | ||
1427 | ret = __change_page_attr_set_clr(&cpa, checkalias); | |
ff31452b | 1428 | |
f4ae5da0 TG |
1429 | /* |
1430 | * Check whether we really changed something: | |
1431 | */ | |
d75586ad | 1432 | if (!(cpa.flags & CPA_FLUSHTLB)) |
1ac2f7d5 | 1433 | goto out; |
cacf8906 | 1434 | |
6bb8383b AK |
1435 | /* |
1436 | * No need to flush, when we did not set any of the caching | |
1437 | * attributes: | |
1438 | */ | |
c06814d8 | 1439 | cache = !!pgprot2cachemode(mask_set); |
6bb8383b | 1440 | |
57a6a46a | 1441 | /* |
b82ad3d3 BP |
1442 | * On success we use CLFLUSH, when the CPU supports it to |
1443 | * avoid the WBINVD. If the CPU does not support it and in the | |
f026cfa8 | 1444 | * error case we fall back to cpa_flush_all (which uses |
b82ad3d3 | 1445 | * WBINVD): |
57a6a46a | 1446 | */ |
f026cfa8 | 1447 | if (!ret && cpu_has_clflush) { |
9ae28475 | 1448 | if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) { |
1449 | cpa_flush_array(addr, numpages, cache, | |
1450 | cpa.flags, pages); | |
1451 | } else | |
fa526d0d | 1452 | cpa_flush_range(baddr, numpages, cache); |
d75586ad | 1453 | } else |
6bb8383b | 1454 | cpa_flush_all(cache); |
cacf8906 | 1455 | |
76ebd054 | 1456 | out: |
ff31452b TG |
1457 | return ret; |
1458 | } | |
1459 | ||
d75586ad SL |
1460 | static inline int change_page_attr_set(unsigned long *addr, int numpages, |
1461 | pgprot_t mask, int array) | |
75cbade8 | 1462 | { |
d75586ad | 1463 | return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0, |
9ae28475 | 1464 | (array ? CPA_ARRAY : 0), NULL); |
75cbade8 AV |
1465 | } |
1466 | ||
d75586ad SL |
1467 | static inline int change_page_attr_clear(unsigned long *addr, int numpages, |
1468 | pgprot_t mask, int array) | |
72932c7a | 1469 | { |
d75586ad | 1470 | return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0, |
9ae28475 | 1471 | (array ? CPA_ARRAY : 0), NULL); |
72932c7a TG |
1472 | } |
1473 | ||
0f350755 | 1474 | static inline int cpa_set_pages_array(struct page **pages, int numpages, |
1475 | pgprot_t mask) | |
1476 | { | |
1477 | return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0, | |
1478 | CPA_PAGES_ARRAY, pages); | |
1479 | } | |
1480 | ||
1481 | static inline int cpa_clear_pages_array(struct page **pages, int numpages, | |
1482 | pgprot_t mask) | |
1483 | { | |
1484 | return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0, | |
1485 | CPA_PAGES_ARRAY, pages); | |
1486 | } | |
1487 | ||
1219333d | 1488 | int _set_memory_uc(unsigned long addr, int numpages) |
72932c7a | 1489 | { |
de33c442 SS |
1490 | /* |
1491 | * for now UC MINUS. see comments in ioremap_nocache() | |
e4b6be33 LR |
1492 | * If you really need strong UC use ioremap_uc(), but note |
1493 | * that you cannot override IO areas with set_memory_*() as | |
1494 | * these helpers cannot work with IO memory. | |
de33c442 | 1495 | */ |
d75586ad | 1496 | return change_page_attr_set(&addr, numpages, |
c06814d8 JG |
1497 | cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS), |
1498 | 0); | |
75cbade8 | 1499 | } |
1219333d | 1500 | |
1501 | int set_memory_uc(unsigned long addr, int numpages) | |
1502 | { | |
9fa3ab39 | 1503 | int ret; |
1504 | ||
de33c442 SS |
1505 | /* |
1506 | * for now UC MINUS. see comments in ioremap_nocache() | |
1507 | */ | |
9fa3ab39 | 1508 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
e00c8cc9 | 1509 | _PAGE_CACHE_MODE_UC_MINUS, NULL); |
9fa3ab39 | 1510 | if (ret) |
1511 | goto out_err; | |
1512 | ||
1513 | ret = _set_memory_uc(addr, numpages); | |
1514 | if (ret) | |
1515 | goto out_free; | |
1516 | ||
1517 | return 0; | |
1219333d | 1518 | |
9fa3ab39 | 1519 | out_free: |
1520 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
1521 | out_err: | |
1522 | return ret; | |
1219333d | 1523 | } |
75cbade8 AV |
1524 | EXPORT_SYMBOL(set_memory_uc); |
1525 | ||
2d070eff | 1526 | static int _set_memory_array(unsigned long *addr, int addrinarray, |
c06814d8 | 1527 | enum page_cache_mode new_type) |
d75586ad | 1528 | { |
623dffb2 | 1529 | enum page_cache_mode set_type; |
9fa3ab39 | 1530 | int i, j; |
1531 | int ret; | |
1532 | ||
d75586ad | 1533 | for (i = 0; i < addrinarray; i++) { |
9fa3ab39 | 1534 | ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE, |
4f646254 | 1535 | new_type, NULL); |
9fa3ab39 | 1536 | if (ret) |
1537 | goto out_free; | |
d75586ad SL |
1538 | } |
1539 | ||
623dffb2 TK |
1540 | /* If WC, set to UC- first and then WC */ |
1541 | set_type = (new_type == _PAGE_CACHE_MODE_WC) ? | |
1542 | _PAGE_CACHE_MODE_UC_MINUS : new_type; | |
1543 | ||
9fa3ab39 | 1544 | ret = change_page_attr_set(addr, addrinarray, |
623dffb2 | 1545 | cachemode2pgprot(set_type), 1); |
4f646254 | 1546 | |
c06814d8 | 1547 | if (!ret && new_type == _PAGE_CACHE_MODE_WC) |
4f646254 | 1548 | ret = change_page_attr_set_clr(addr, addrinarray, |
c06814d8 JG |
1549 | cachemode2pgprot( |
1550 | _PAGE_CACHE_MODE_WC), | |
4f646254 PN |
1551 | __pgprot(_PAGE_CACHE_MASK), |
1552 | 0, CPA_ARRAY, NULL); | |
9fa3ab39 | 1553 | if (ret) |
1554 | goto out_free; | |
1555 | ||
1556 | return 0; | |
1557 | ||
1558 | out_free: | |
1559 | for (j = 0; j < i; j++) | |
1560 | free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE); | |
1561 | ||
1562 | return ret; | |
d75586ad | 1563 | } |
4f646254 PN |
1564 | |
1565 | int set_memory_array_uc(unsigned long *addr, int addrinarray) | |
1566 | { | |
c06814d8 | 1567 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_UC_MINUS); |
4f646254 | 1568 | } |
d75586ad SL |
1569 | EXPORT_SYMBOL(set_memory_array_uc); |
1570 | ||
4f646254 PN |
1571 | int set_memory_array_wc(unsigned long *addr, int addrinarray) |
1572 | { | |
c06814d8 | 1573 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_WC); |
4f646254 PN |
1574 | } |
1575 | EXPORT_SYMBOL(set_memory_array_wc); | |
1576 | ||
623dffb2 TK |
1577 | int set_memory_array_wt(unsigned long *addr, int addrinarray) |
1578 | { | |
1579 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_MODE_WT); | |
1580 | } | |
1581 | EXPORT_SYMBOL_GPL(set_memory_array_wt); | |
1582 | ||
ef354af4 | 1583 | int _set_memory_wc(unsigned long addr, int numpages) |
1584 | { | |
3869c4aa | 1585 | int ret; |
bdc6340f PV |
1586 | unsigned long addr_copy = addr; |
1587 | ||
3869c4aa | 1588 | ret = change_page_attr_set(&addr, numpages, |
c06814d8 JG |
1589 | cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS), |
1590 | 0); | |
3869c4aa | 1591 | if (!ret) { |
bdc6340f | 1592 | ret = change_page_attr_set_clr(&addr_copy, numpages, |
c06814d8 JG |
1593 | cachemode2pgprot( |
1594 | _PAGE_CACHE_MODE_WC), | |
bdc6340f PV |
1595 | __pgprot(_PAGE_CACHE_MASK), |
1596 | 0, 0, NULL); | |
3869c4aa | 1597 | } |
1598 | return ret; | |
ef354af4 | 1599 | } |
1600 | ||
1601 | int set_memory_wc(unsigned long addr, int numpages) | |
1602 | { | |
9fa3ab39 | 1603 | int ret; |
1604 | ||
9fa3ab39 | 1605 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
e00c8cc9 | 1606 | _PAGE_CACHE_MODE_WC, NULL); |
9fa3ab39 | 1607 | if (ret) |
623dffb2 | 1608 | return ret; |
ef354af4 | 1609 | |
9fa3ab39 | 1610 | ret = _set_memory_wc(addr, numpages); |
1611 | if (ret) | |
623dffb2 | 1612 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
9fa3ab39 | 1613 | |
9fa3ab39 | 1614 | return ret; |
ef354af4 | 1615 | } |
1616 | EXPORT_SYMBOL(set_memory_wc); | |
1617 | ||
623dffb2 TK |
1618 | int _set_memory_wt(unsigned long addr, int numpages) |
1619 | { | |
1620 | return change_page_attr_set(&addr, numpages, | |
1621 | cachemode2pgprot(_PAGE_CACHE_MODE_WT), 0); | |
1622 | } | |
1623 | ||
1624 | int set_memory_wt(unsigned long addr, int numpages) | |
1625 | { | |
1626 | int ret; | |
1627 | ||
1628 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, | |
1629 | _PAGE_CACHE_MODE_WT, NULL); | |
1630 | if (ret) | |
1631 | return ret; | |
1632 | ||
1633 | ret = _set_memory_wt(addr, numpages); | |
1634 | if (ret) | |
1635 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
1636 | ||
1637 | return ret; | |
1638 | } | |
1639 | EXPORT_SYMBOL_GPL(set_memory_wt); | |
1640 | ||
1219333d | 1641 | int _set_memory_wb(unsigned long addr, int numpages) |
75cbade8 | 1642 | { |
c06814d8 | 1643 | /* WB cache mode is hard wired to all cache attribute bits being 0 */ |
d75586ad SL |
1644 | return change_page_attr_clear(&addr, numpages, |
1645 | __pgprot(_PAGE_CACHE_MASK), 0); | |
75cbade8 | 1646 | } |
1219333d | 1647 | |
1648 | int set_memory_wb(unsigned long addr, int numpages) | |
1649 | { | |
9fa3ab39 | 1650 | int ret; |
1651 | ||
1652 | ret = _set_memory_wb(addr, numpages); | |
1653 | if (ret) | |
1654 | return ret; | |
1655 | ||
c15238df | 1656 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
9fa3ab39 | 1657 | return 0; |
1219333d | 1658 | } |
75cbade8 AV |
1659 | EXPORT_SYMBOL(set_memory_wb); |
1660 | ||
d75586ad SL |
1661 | int set_memory_array_wb(unsigned long *addr, int addrinarray) |
1662 | { | |
1663 | int i; | |
a5593e0b | 1664 | int ret; |
1665 | ||
c06814d8 | 1666 | /* WB cache mode is hard wired to all cache attribute bits being 0 */ |
a5593e0b | 1667 | ret = change_page_attr_clear(addr, addrinarray, |
1668 | __pgprot(_PAGE_CACHE_MASK), 1); | |
9fa3ab39 | 1669 | if (ret) |
1670 | return ret; | |
d75586ad | 1671 | |
9fa3ab39 | 1672 | for (i = 0; i < addrinarray; i++) |
1673 | free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE); | |
c5e147cf | 1674 | |
9fa3ab39 | 1675 | return 0; |
d75586ad SL |
1676 | } |
1677 | EXPORT_SYMBOL(set_memory_array_wb); | |
1678 | ||
75cbade8 AV |
1679 | int set_memory_x(unsigned long addr, int numpages) |
1680 | { | |
583140af PA |
1681 | if (!(__supported_pte_mask & _PAGE_NX)) |
1682 | return 0; | |
1683 | ||
d75586ad | 1684 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1685 | } |
1686 | EXPORT_SYMBOL(set_memory_x); | |
1687 | ||
1688 | int set_memory_nx(unsigned long addr, int numpages) | |
1689 | { | |
583140af PA |
1690 | if (!(__supported_pte_mask & _PAGE_NX)) |
1691 | return 0; | |
1692 | ||
d75586ad | 1693 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1694 | } |
1695 | EXPORT_SYMBOL(set_memory_nx); | |
1696 | ||
1697 | int set_memory_ro(unsigned long addr, int numpages) | |
1698 | { | |
d75586ad | 1699 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1700 | } |
75cbade8 AV |
1701 | |
1702 | int set_memory_rw(unsigned long addr, int numpages) | |
1703 | { | |
d75586ad | 1704 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1705 | } |
f62d0f00 IM |
1706 | |
1707 | int set_memory_np(unsigned long addr, int numpages) | |
1708 | { | |
d75586ad | 1709 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0); |
f62d0f00 | 1710 | } |
75cbade8 | 1711 | |
c9caa02c AK |
1712 | int set_memory_4k(unsigned long addr, int numpages) |
1713 | { | |
d75586ad | 1714 | return change_page_attr_set_clr(&addr, numpages, __pgprot(0), |
9ae28475 | 1715 | __pgprot(0), 1, 0, NULL); |
c9caa02c AK |
1716 | } |
1717 | ||
75cbade8 AV |
1718 | int set_pages_uc(struct page *page, int numpages) |
1719 | { | |
1720 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1721 | |
d7c8f21a | 1722 | return set_memory_uc(addr, numpages); |
75cbade8 AV |
1723 | } |
1724 | EXPORT_SYMBOL(set_pages_uc); | |
1725 | ||
4f646254 | 1726 | static int _set_pages_array(struct page **pages, int addrinarray, |
c06814d8 | 1727 | enum page_cache_mode new_type) |
0f350755 | 1728 | { |
1729 | unsigned long start; | |
1730 | unsigned long end; | |
623dffb2 | 1731 | enum page_cache_mode set_type; |
0f350755 | 1732 | int i; |
1733 | int free_idx; | |
4f646254 | 1734 | int ret; |
0f350755 | 1735 | |
1736 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1737 | if (PageHighMem(pages[i])) |
1738 | continue; | |
1739 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1740 | end = start + PAGE_SIZE; |
4f646254 | 1741 | if (reserve_memtype(start, end, new_type, NULL)) |
0f350755 | 1742 | goto err_out; |
1743 | } | |
1744 | ||
623dffb2 TK |
1745 | /* If WC, set to UC- first and then WC */ |
1746 | set_type = (new_type == _PAGE_CACHE_MODE_WC) ? | |
1747 | _PAGE_CACHE_MODE_UC_MINUS : new_type; | |
1748 | ||
4f646254 | 1749 | ret = cpa_set_pages_array(pages, addrinarray, |
623dffb2 | 1750 | cachemode2pgprot(set_type)); |
c06814d8 | 1751 | if (!ret && new_type == _PAGE_CACHE_MODE_WC) |
4f646254 | 1752 | ret = change_page_attr_set_clr(NULL, addrinarray, |
c06814d8 JG |
1753 | cachemode2pgprot( |
1754 | _PAGE_CACHE_MODE_WC), | |
4f646254 PN |
1755 | __pgprot(_PAGE_CACHE_MASK), |
1756 | 0, CPA_PAGES_ARRAY, pages); | |
1757 | if (ret) | |
1758 | goto err_out; | |
1759 | return 0; /* Success */ | |
0f350755 | 1760 | err_out: |
1761 | free_idx = i; | |
1762 | for (i = 0; i < free_idx; i++) { | |
8523acfe TH |
1763 | if (PageHighMem(pages[i])) |
1764 | continue; | |
1765 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1766 | end = start + PAGE_SIZE; |
1767 | free_memtype(start, end); | |
1768 | } | |
1769 | return -EINVAL; | |
1770 | } | |
4f646254 PN |
1771 | |
1772 | int set_pages_array_uc(struct page **pages, int addrinarray) | |
1773 | { | |
c06814d8 | 1774 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_UC_MINUS); |
4f646254 | 1775 | } |
0f350755 | 1776 | EXPORT_SYMBOL(set_pages_array_uc); |
1777 | ||
4f646254 PN |
1778 | int set_pages_array_wc(struct page **pages, int addrinarray) |
1779 | { | |
c06814d8 | 1780 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_WC); |
4f646254 PN |
1781 | } |
1782 | EXPORT_SYMBOL(set_pages_array_wc); | |
1783 | ||
623dffb2 TK |
1784 | int set_pages_array_wt(struct page **pages, int addrinarray) |
1785 | { | |
1786 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_MODE_WT); | |
1787 | } | |
1788 | EXPORT_SYMBOL_GPL(set_pages_array_wt); | |
1789 | ||
75cbade8 AV |
1790 | int set_pages_wb(struct page *page, int numpages) |
1791 | { | |
1792 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1793 | |
d7c8f21a | 1794 | return set_memory_wb(addr, numpages); |
75cbade8 AV |
1795 | } |
1796 | EXPORT_SYMBOL(set_pages_wb); | |
1797 | ||
0f350755 | 1798 | int set_pages_array_wb(struct page **pages, int addrinarray) |
1799 | { | |
1800 | int retval; | |
1801 | unsigned long start; | |
1802 | unsigned long end; | |
1803 | int i; | |
1804 | ||
c06814d8 | 1805 | /* WB cache mode is hard wired to all cache attribute bits being 0 */ |
0f350755 | 1806 | retval = cpa_clear_pages_array(pages, addrinarray, |
1807 | __pgprot(_PAGE_CACHE_MASK)); | |
9fa3ab39 | 1808 | if (retval) |
1809 | return retval; | |
0f350755 | 1810 | |
1811 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1812 | if (PageHighMem(pages[i])) |
1813 | continue; | |
1814 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1815 | end = start + PAGE_SIZE; |
1816 | free_memtype(start, end); | |
1817 | } | |
1818 | ||
9fa3ab39 | 1819 | return 0; |
0f350755 | 1820 | } |
1821 | EXPORT_SYMBOL(set_pages_array_wb); | |
1822 | ||
75cbade8 AV |
1823 | int set_pages_x(struct page *page, int numpages) |
1824 | { | |
1825 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1826 | |
d7c8f21a | 1827 | return set_memory_x(addr, numpages); |
75cbade8 AV |
1828 | } |
1829 | EXPORT_SYMBOL(set_pages_x); | |
1830 | ||
1831 | int set_pages_nx(struct page *page, int numpages) | |
1832 | { | |
1833 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1834 | |
d7c8f21a | 1835 | return set_memory_nx(addr, numpages); |
75cbade8 AV |
1836 | } |
1837 | EXPORT_SYMBOL(set_pages_nx); | |
1838 | ||
1839 | int set_pages_ro(struct page *page, int numpages) | |
1840 | { | |
1841 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1842 | |
d7c8f21a | 1843 | return set_memory_ro(addr, numpages); |
75cbade8 | 1844 | } |
75cbade8 AV |
1845 | |
1846 | int set_pages_rw(struct page *page, int numpages) | |
1847 | { | |
1848 | unsigned long addr = (unsigned long)page_address(page); | |
e81d5dc4 | 1849 | |
d7c8f21a | 1850 | return set_memory_rw(addr, numpages); |
78c94aba IM |
1851 | } |
1852 | ||
1da177e4 | 1853 | #ifdef CONFIG_DEBUG_PAGEALLOC |
f62d0f00 IM |
1854 | |
1855 | static int __set_pages_p(struct page *page, int numpages) | |
1856 | { | |
d75586ad SL |
1857 | unsigned long tempaddr = (unsigned long) page_address(page); |
1858 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
82f0712c | 1859 | .pgd = NULL, |
72e458df TG |
1860 | .numpages = numpages, |
1861 | .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW), | |
d75586ad SL |
1862 | .mask_clr = __pgprot(0), |
1863 | .flags = 0}; | |
72932c7a | 1864 | |
55121b43 SS |
1865 | /* |
1866 | * No alias checking needed for setting present flag. otherwise, | |
1867 | * we may need to break large pages for 64-bit kernel text | |
1868 | * mappings (this adds to complexity if we want to do this from | |
1869 | * atomic context especially). Let's keep it simple! | |
1870 | */ | |
1871 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1872 | } |
1873 | ||
1874 | static int __set_pages_np(struct page *page, int numpages) | |
1875 | { | |
d75586ad SL |
1876 | unsigned long tempaddr = (unsigned long) page_address(page); |
1877 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
82f0712c | 1878 | .pgd = NULL, |
72e458df TG |
1879 | .numpages = numpages, |
1880 | .mask_set = __pgprot(0), | |
d75586ad SL |
1881 | .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW), |
1882 | .flags = 0}; | |
72932c7a | 1883 | |
55121b43 SS |
1884 | /* |
1885 | * No alias checking needed for setting not present flag. otherwise, | |
1886 | * we may need to break large pages for 64-bit kernel text | |
1887 | * mappings (this adds to complexity if we want to do this from | |
1888 | * atomic context especially). Let's keep it simple! | |
1889 | */ | |
1890 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1891 | } |
1892 | ||
031bc574 | 1893 | void __kernel_map_pages(struct page *page, int numpages, int enable) |
1da177e4 LT |
1894 | { |
1895 | if (PageHighMem(page)) | |
1896 | return; | |
9f4c815c | 1897 | if (!enable) { |
f9b8404c IM |
1898 | debug_check_no_locks_freed(page_address(page), |
1899 | numpages * PAGE_SIZE); | |
9f4c815c | 1900 | } |
de5097c2 | 1901 | |
9f4c815c | 1902 | /* |
f8d8406b | 1903 | * The return value is ignored as the calls cannot fail. |
55121b43 SS |
1904 | * Large pages for identity mappings are not used at boot time |
1905 | * and hence no memory allocations during large page split. | |
1da177e4 | 1906 | */ |
f62d0f00 IM |
1907 | if (enable) |
1908 | __set_pages_p(page, numpages); | |
1909 | else | |
1910 | __set_pages_np(page, numpages); | |
9f4c815c IM |
1911 | |
1912 | /* | |
e4b71dcf IM |
1913 | * We should perform an IPI and flush all tlbs, |
1914 | * but that can deadlock->flush only current cpu: | |
1da177e4 LT |
1915 | */ |
1916 | __flush_tlb_all(); | |
26564600 BO |
1917 | |
1918 | arch_flush_lazy_mmu_mode(); | |
ee7ae7a1 TG |
1919 | } |
1920 | ||
8a235efa RW |
1921 | #ifdef CONFIG_HIBERNATION |
1922 | ||
1923 | bool kernel_page_present(struct page *page) | |
1924 | { | |
1925 | unsigned int level; | |
1926 | pte_t *pte; | |
1927 | ||
1928 | if (PageHighMem(page)) | |
1929 | return false; | |
1930 | ||
1931 | pte = lookup_address((unsigned long)page_address(page), &level); | |
1932 | return (pte_val(*pte) & _PAGE_PRESENT); | |
1933 | } | |
1934 | ||
1935 | #endif /* CONFIG_HIBERNATION */ | |
1936 | ||
1937 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
d1028a15 | 1938 | |
82f0712c BP |
1939 | int kernel_map_pages_in_pgd(pgd_t *pgd, u64 pfn, unsigned long address, |
1940 | unsigned numpages, unsigned long page_flags) | |
1941 | { | |
1942 | int retval = -EINVAL; | |
1943 | ||
1944 | struct cpa_data cpa = { | |
1945 | .vaddr = &address, | |
1946 | .pfn = pfn, | |
1947 | .pgd = pgd, | |
1948 | .numpages = numpages, | |
1949 | .mask_set = __pgprot(0), | |
1950 | .mask_clr = __pgprot(0), | |
1951 | .flags = 0, | |
1952 | }; | |
1953 | ||
1954 | if (!(__supported_pte_mask & _PAGE_NX)) | |
1955 | goto out; | |
1956 | ||
1957 | if (!(page_flags & _PAGE_NX)) | |
1958 | cpa.mask_clr = __pgprot(_PAGE_NX); | |
1959 | ||
1960 | cpa.mask_set = __pgprot(_PAGE_PRESENT | page_flags); | |
1961 | ||
1962 | retval = __change_page_attr_set_clr(&cpa, 0); | |
1963 | __flush_tlb_all(); | |
1964 | ||
1965 | out: | |
1966 | return retval; | |
1967 | } | |
1968 | ||
42a54772 BP |
1969 | void kernel_unmap_pages_in_pgd(pgd_t *root, unsigned long address, |
1970 | unsigned numpages) | |
1971 | { | |
1972 | unmap_pgd_range(root, address, address + (numpages << PAGE_SHIFT)); | |
1973 | } | |
1974 | ||
d1028a15 AV |
1975 | /* |
1976 | * The testcases use internal knowledge of the implementation that shouldn't | |
1977 | * be exposed to the rest of the kernel. Include these directly here. | |
1978 | */ | |
1979 | #ifdef CONFIG_CPA_DEBUG | |
1980 | #include "pageattr-test.c" | |
1981 | #endif |