Commit | Line | Data |
---|---|---|
9f4c815c IM |
1 | /* |
2 | * Copyright 2002 Andi Kleen, SuSE Labs. | |
1da177e4 | 3 | * Thanks to Ben LaHaise for precious feedback. |
9f4c815c | 4 | */ |
1da177e4 | 5 | #include <linux/highmem.h> |
8192206d | 6 | #include <linux/bootmem.h> |
1da177e4 | 7 | #include <linux/module.h> |
9f4c815c | 8 | #include <linux/sched.h> |
9f4c815c | 9 | #include <linux/mm.h> |
76ebd054 | 10 | #include <linux/interrupt.h> |
ee7ae7a1 TG |
11 | #include <linux/seq_file.h> |
12 | #include <linux/debugfs.h> | |
e59a1bb2 | 13 | #include <linux/pfn.h> |
8c4bfc6e | 14 | #include <linux/percpu.h> |
5a0e3ad6 | 15 | #include <linux/gfp.h> |
5bd5a452 | 16 | #include <linux/pci.h> |
9f4c815c | 17 | |
950f9d95 | 18 | #include <asm/e820.h> |
1da177e4 LT |
19 | #include <asm/processor.h> |
20 | #include <asm/tlbflush.h> | |
f8af095d | 21 | #include <asm/sections.h> |
93dbda7c | 22 | #include <asm/setup.h> |
9f4c815c IM |
23 | #include <asm/uaccess.h> |
24 | #include <asm/pgalloc.h> | |
c31c7d48 | 25 | #include <asm/proto.h> |
1219333d | 26 | #include <asm/pat.h> |
1da177e4 | 27 | |
9df84993 IM |
28 | /* |
29 | * The current flushing context - we pass it instead of 5 arguments: | |
30 | */ | |
72e458df | 31 | struct cpa_data { |
d75586ad | 32 | unsigned long *vaddr; |
72e458df TG |
33 | pgprot_t mask_set; |
34 | pgprot_t mask_clr; | |
65e074df | 35 | int numpages; |
d75586ad | 36 | int flags; |
c31c7d48 | 37 | unsigned long pfn; |
c9caa02c | 38 | unsigned force_split : 1; |
d75586ad | 39 | int curpage; |
9ae28475 | 40 | struct page **pages; |
72e458df TG |
41 | }; |
42 | ||
ad5ca55f SS |
43 | /* |
44 | * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings) | |
45 | * using cpa_lock. So that we don't allow any other cpu, with stale large tlb | |
46 | * entries change the page attribute in parallel to some other cpu | |
47 | * splitting a large page entry along with changing the attribute. | |
48 | */ | |
49 | static DEFINE_SPINLOCK(cpa_lock); | |
50 | ||
d75586ad SL |
51 | #define CPA_FLUSHTLB 1 |
52 | #define CPA_ARRAY 2 | |
9ae28475 | 53 | #define CPA_PAGES_ARRAY 4 |
d75586ad | 54 | |
65280e61 | 55 | #ifdef CONFIG_PROC_FS |
ce0c0e50 AK |
56 | static unsigned long direct_pages_count[PG_LEVEL_NUM]; |
57 | ||
65280e61 | 58 | void update_page_count(int level, unsigned long pages) |
ce0c0e50 | 59 | { |
ce0c0e50 | 60 | /* Protect against CPA */ |
a79e53d8 | 61 | spin_lock(&pgd_lock); |
ce0c0e50 | 62 | direct_pages_count[level] += pages; |
a79e53d8 | 63 | spin_unlock(&pgd_lock); |
65280e61 TG |
64 | } |
65 | ||
66 | static void split_page_count(int level) | |
67 | { | |
68 | direct_pages_count[level]--; | |
69 | direct_pages_count[level - 1] += PTRS_PER_PTE; | |
70 | } | |
71 | ||
e1759c21 | 72 | void arch_report_meminfo(struct seq_file *m) |
65280e61 | 73 | { |
b9c3bfc2 | 74 | seq_printf(m, "DirectMap4k: %8lu kB\n", |
a06de630 HD |
75 | direct_pages_count[PG_LEVEL_4K] << 2); |
76 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
b9c3bfc2 | 77 | seq_printf(m, "DirectMap2M: %8lu kB\n", |
a06de630 HD |
78 | direct_pages_count[PG_LEVEL_2M] << 11); |
79 | #else | |
b9c3bfc2 | 80 | seq_printf(m, "DirectMap4M: %8lu kB\n", |
a06de630 HD |
81 | direct_pages_count[PG_LEVEL_2M] << 12); |
82 | #endif | |
65280e61 | 83 | #ifdef CONFIG_X86_64 |
a06de630 | 84 | if (direct_gbpages) |
b9c3bfc2 | 85 | seq_printf(m, "DirectMap1G: %8lu kB\n", |
a06de630 | 86 | direct_pages_count[PG_LEVEL_1G] << 20); |
ce0c0e50 AK |
87 | #endif |
88 | } | |
65280e61 TG |
89 | #else |
90 | static inline void split_page_count(int level) { } | |
91 | #endif | |
ce0c0e50 | 92 | |
c31c7d48 TG |
93 | #ifdef CONFIG_X86_64 |
94 | ||
95 | static inline unsigned long highmap_start_pfn(void) | |
96 | { | |
fc8d7826 | 97 | return __pa_symbol(_text) >> PAGE_SHIFT; |
c31c7d48 TG |
98 | } |
99 | ||
100 | static inline unsigned long highmap_end_pfn(void) | |
101 | { | |
fc8d7826 | 102 | return __pa_symbol(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT; |
c31c7d48 TG |
103 | } |
104 | ||
105 | #endif | |
106 | ||
92cb54a3 IM |
107 | #ifdef CONFIG_DEBUG_PAGEALLOC |
108 | # define debug_pagealloc 1 | |
109 | #else | |
110 | # define debug_pagealloc 0 | |
111 | #endif | |
112 | ||
ed724be6 AV |
113 | static inline int |
114 | within(unsigned long addr, unsigned long start, unsigned long end) | |
687c4825 | 115 | { |
ed724be6 AV |
116 | return addr >= start && addr < end; |
117 | } | |
118 | ||
d7c8f21a TG |
119 | /* |
120 | * Flushing functions | |
121 | */ | |
cd8ddf1a | 122 | |
cd8ddf1a TG |
123 | /** |
124 | * clflush_cache_range - flush a cache range with clflush | |
9efc31b8 | 125 | * @vaddr: virtual start address |
cd8ddf1a TG |
126 | * @size: number of bytes to flush |
127 | * | |
128 | * clflush is an unordered instruction which needs fencing with mfence | |
129 | * to avoid ordering issues. | |
130 | */ | |
4c61afcd | 131 | void clflush_cache_range(void *vaddr, unsigned int size) |
d7c8f21a | 132 | { |
4c61afcd | 133 | void *vend = vaddr + size - 1; |
d7c8f21a | 134 | |
cd8ddf1a | 135 | mb(); |
4c61afcd IM |
136 | |
137 | for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size) | |
138 | clflush(vaddr); | |
139 | /* | |
140 | * Flush any possible final partial cacheline: | |
141 | */ | |
142 | clflush(vend); | |
143 | ||
cd8ddf1a | 144 | mb(); |
d7c8f21a | 145 | } |
e517a5e9 | 146 | EXPORT_SYMBOL_GPL(clflush_cache_range); |
d7c8f21a | 147 | |
af1e6844 | 148 | static void __cpa_flush_all(void *arg) |
d7c8f21a | 149 | { |
6bb8383b AK |
150 | unsigned long cache = (unsigned long)arg; |
151 | ||
d7c8f21a TG |
152 | /* |
153 | * Flush all to work around Errata in early athlons regarding | |
154 | * large page flushing. | |
155 | */ | |
156 | __flush_tlb_all(); | |
157 | ||
0b827537 | 158 | if (cache && boot_cpu_data.x86 >= 4) |
d7c8f21a TG |
159 | wbinvd(); |
160 | } | |
161 | ||
6bb8383b | 162 | static void cpa_flush_all(unsigned long cache) |
d7c8f21a TG |
163 | { |
164 | BUG_ON(irqs_disabled()); | |
165 | ||
15c8b6c1 | 166 | on_each_cpu(__cpa_flush_all, (void *) cache, 1); |
d7c8f21a TG |
167 | } |
168 | ||
57a6a46a TG |
169 | static void __cpa_flush_range(void *arg) |
170 | { | |
57a6a46a TG |
171 | /* |
172 | * We could optimize that further and do individual per page | |
173 | * tlb invalidates for a low number of pages. Caveat: we must | |
174 | * flush the high aliases on 64bit as well. | |
175 | */ | |
176 | __flush_tlb_all(); | |
57a6a46a TG |
177 | } |
178 | ||
6bb8383b | 179 | static void cpa_flush_range(unsigned long start, int numpages, int cache) |
57a6a46a | 180 | { |
4c61afcd IM |
181 | unsigned int i, level; |
182 | unsigned long addr; | |
183 | ||
57a6a46a | 184 | BUG_ON(irqs_disabled()); |
4c61afcd | 185 | WARN_ON(PAGE_ALIGN(start) != start); |
57a6a46a | 186 | |
15c8b6c1 | 187 | on_each_cpu(__cpa_flush_range, NULL, 1); |
57a6a46a | 188 | |
6bb8383b AK |
189 | if (!cache) |
190 | return; | |
191 | ||
3b233e52 TG |
192 | /* |
193 | * We only need to flush on one CPU, | |
194 | * clflush is a MESI-coherent instruction that | |
195 | * will cause all other CPUs to flush the same | |
196 | * cachelines: | |
197 | */ | |
4c61afcd IM |
198 | for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) { |
199 | pte_t *pte = lookup_address(addr, &level); | |
200 | ||
201 | /* | |
202 | * Only flush present addresses: | |
203 | */ | |
7bfb72e8 | 204 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) |
4c61afcd IM |
205 | clflush_cache_range((void *) addr, PAGE_SIZE); |
206 | } | |
57a6a46a TG |
207 | } |
208 | ||
9ae28475 | 209 | static void cpa_flush_array(unsigned long *start, int numpages, int cache, |
210 | int in_flags, struct page **pages) | |
d75586ad SL |
211 | { |
212 | unsigned int i, level; | |
2171787b | 213 | unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */ |
d75586ad SL |
214 | |
215 | BUG_ON(irqs_disabled()); | |
216 | ||
2171787b | 217 | on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1); |
d75586ad | 218 | |
2171787b | 219 | if (!cache || do_wbinvd) |
d75586ad SL |
220 | return; |
221 | ||
d75586ad SL |
222 | /* |
223 | * We only need to flush on one CPU, | |
224 | * clflush is a MESI-coherent instruction that | |
225 | * will cause all other CPUs to flush the same | |
226 | * cachelines: | |
227 | */ | |
9ae28475 | 228 | for (i = 0; i < numpages; i++) { |
229 | unsigned long addr; | |
230 | pte_t *pte; | |
231 | ||
232 | if (in_flags & CPA_PAGES_ARRAY) | |
233 | addr = (unsigned long)page_address(pages[i]); | |
234 | else | |
235 | addr = start[i]; | |
236 | ||
237 | pte = lookup_address(addr, &level); | |
d75586ad SL |
238 | |
239 | /* | |
240 | * Only flush present addresses: | |
241 | */ | |
242 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) | |
9ae28475 | 243 | clflush_cache_range((void *)addr, PAGE_SIZE); |
d75586ad SL |
244 | } |
245 | } | |
246 | ||
ed724be6 AV |
247 | /* |
248 | * Certain areas of memory on x86 require very specific protection flags, | |
249 | * for example the BIOS area or kernel text. Callers don't always get this | |
250 | * right (again, ioremap() on BIOS memory is not uncommon) so this function | |
251 | * checks and fixes these known static required protection bits. | |
252 | */ | |
c31c7d48 TG |
253 | static inline pgprot_t static_protections(pgprot_t prot, unsigned long address, |
254 | unsigned long pfn) | |
ed724be6 AV |
255 | { |
256 | pgprot_t forbidden = __pgprot(0); | |
257 | ||
687c4825 | 258 | /* |
ed724be6 AV |
259 | * The BIOS area between 640k and 1Mb needs to be executable for |
260 | * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support. | |
687c4825 | 261 | */ |
5bd5a452 MC |
262 | #ifdef CONFIG_PCI_BIOS |
263 | if (pcibios_enabled && within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT)) | |
ed724be6 | 264 | pgprot_val(forbidden) |= _PAGE_NX; |
5bd5a452 | 265 | #endif |
ed724be6 AV |
266 | |
267 | /* | |
268 | * The kernel text needs to be executable for obvious reasons | |
c31c7d48 TG |
269 | * Does not cover __inittext since that is gone later on. On |
270 | * 64bit we do not enforce !NX on the low mapping | |
ed724be6 AV |
271 | */ |
272 | if (within(address, (unsigned long)_text, (unsigned long)_etext)) | |
273 | pgprot_val(forbidden) |= _PAGE_NX; | |
cc0f21bb | 274 | |
cc0f21bb | 275 | /* |
c31c7d48 TG |
276 | * The .rodata section needs to be read-only. Using the pfn |
277 | * catches all aliases. | |
cc0f21bb | 278 | */ |
fc8d7826 AD |
279 | if (within(pfn, __pa_symbol(__start_rodata) >> PAGE_SHIFT, |
280 | __pa_symbol(__end_rodata) >> PAGE_SHIFT)) | |
cc0f21bb | 281 | pgprot_val(forbidden) |= _PAGE_RW; |
ed724be6 | 282 | |
55ca3cc1 | 283 | #if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA) |
74e08179 | 284 | /* |
502f6604 SS |
285 | * Once the kernel maps the text as RO (kernel_set_to_readonly is set), |
286 | * kernel text mappings for the large page aligned text, rodata sections | |
287 | * will be always read-only. For the kernel identity mappings covering | |
288 | * the holes caused by this alignment can be anything that user asks. | |
74e08179 SS |
289 | * |
290 | * This will preserve the large page mappings for kernel text/data | |
291 | * at no extra cost. | |
292 | */ | |
502f6604 SS |
293 | if (kernel_set_to_readonly && |
294 | within(address, (unsigned long)_text, | |
281ff33b SS |
295 | (unsigned long)__end_rodata_hpage_align)) { |
296 | unsigned int level; | |
297 | ||
298 | /* | |
299 | * Don't enforce the !RW mapping for the kernel text mapping, | |
300 | * if the current mapping is already using small page mapping. | |
301 | * No need to work hard to preserve large page mappings in this | |
302 | * case. | |
303 | * | |
304 | * This also fixes the Linux Xen paravirt guest boot failure | |
305 | * (because of unexpected read-only mappings for kernel identity | |
306 | * mappings). In this paravirt guest case, the kernel text | |
307 | * mapping and the kernel identity mapping share the same | |
308 | * page-table pages. Thus we can't really use different | |
309 | * protections for the kernel text and identity mappings. Also, | |
310 | * these shared mappings are made of small page mappings. | |
311 | * Thus this don't enforce !RW mapping for small page kernel | |
312 | * text mapping logic will help Linux Xen parvirt guest boot | |
0d2eb44f | 313 | * as well. |
281ff33b SS |
314 | */ |
315 | if (lookup_address(address, &level) && (level != PG_LEVEL_4K)) | |
316 | pgprot_val(forbidden) |= _PAGE_RW; | |
317 | } | |
74e08179 SS |
318 | #endif |
319 | ||
ed724be6 | 320 | prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden)); |
687c4825 IM |
321 | |
322 | return prot; | |
323 | } | |
324 | ||
9a14aefc TG |
325 | /* |
326 | * Lookup the page table entry for a virtual address. Return a pointer | |
327 | * to the entry and the level of the mapping. | |
328 | * | |
329 | * Note: We return pud and pmd either when the entry is marked large | |
330 | * or when the present bit is not set. Otherwise we would return a | |
331 | * pointer to a nonexisting mapping. | |
332 | */ | |
da7bfc50 | 333 | pte_t *lookup_address(unsigned long address, unsigned int *level) |
9f4c815c | 334 | { |
1da177e4 LT |
335 | pgd_t *pgd = pgd_offset_k(address); |
336 | pud_t *pud; | |
337 | pmd_t *pmd; | |
9f4c815c | 338 | |
30551bb3 TG |
339 | *level = PG_LEVEL_NONE; |
340 | ||
1da177e4 LT |
341 | if (pgd_none(*pgd)) |
342 | return NULL; | |
9df84993 | 343 | |
1da177e4 LT |
344 | pud = pud_offset(pgd, address); |
345 | if (pud_none(*pud)) | |
346 | return NULL; | |
c2f71ee2 AK |
347 | |
348 | *level = PG_LEVEL_1G; | |
349 | if (pud_large(*pud) || !pud_present(*pud)) | |
350 | return (pte_t *)pud; | |
351 | ||
1da177e4 LT |
352 | pmd = pmd_offset(pud, address); |
353 | if (pmd_none(*pmd)) | |
354 | return NULL; | |
30551bb3 TG |
355 | |
356 | *level = PG_LEVEL_2M; | |
9a14aefc | 357 | if (pmd_large(*pmd) || !pmd_present(*pmd)) |
1da177e4 | 358 | return (pte_t *)pmd; |
1da177e4 | 359 | |
30551bb3 | 360 | *level = PG_LEVEL_4K; |
9df84993 | 361 | |
9f4c815c IM |
362 | return pte_offset_kernel(pmd, address); |
363 | } | |
75bb8835 | 364 | EXPORT_SYMBOL_GPL(lookup_address); |
9f4c815c | 365 | |
d7656534 DH |
366 | /* |
367 | * This is necessary because __pa() does not work on some | |
368 | * kinds of memory, like vmalloc() or the alloc_remap() | |
369 | * areas on 32-bit NUMA systems. The percpu areas can | |
370 | * end up in this kind of memory, for instance. | |
371 | * | |
372 | * This could be optimized, but it is only intended to be | |
373 | * used at inititalization time, and keeping it | |
374 | * unoptimized should increase the testing coverage for | |
375 | * the more obscure platforms. | |
376 | */ | |
377 | phys_addr_t slow_virt_to_phys(void *__virt_addr) | |
378 | { | |
379 | unsigned long virt_addr = (unsigned long)__virt_addr; | |
380 | phys_addr_t phys_addr; | |
381 | unsigned long offset; | |
382 | enum pg_level level; | |
383 | unsigned long psize; | |
384 | unsigned long pmask; | |
385 | pte_t *pte; | |
386 | ||
387 | pte = lookup_address(virt_addr, &level); | |
388 | BUG_ON(!pte); | |
389 | psize = page_level_size(level); | |
390 | pmask = page_level_mask(level); | |
391 | offset = virt_addr & ~pmask; | |
392 | phys_addr = pte_pfn(*pte) << PAGE_SHIFT; | |
393 | return (phys_addr | offset); | |
394 | } | |
395 | EXPORT_SYMBOL_GPL(slow_virt_to_phys); | |
396 | ||
9df84993 IM |
397 | /* |
398 | * Set the new pmd in all the pgds we know about: | |
399 | */ | |
9a3dc780 | 400 | static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) |
9f4c815c | 401 | { |
9f4c815c IM |
402 | /* change init_mm */ |
403 | set_pte_atomic(kpte, pte); | |
44af6c41 | 404 | #ifdef CONFIG_X86_32 |
e4b71dcf | 405 | if (!SHARED_KERNEL_PMD) { |
44af6c41 IM |
406 | struct page *page; |
407 | ||
e3ed910d | 408 | list_for_each_entry(page, &pgd_list, lru) { |
44af6c41 IM |
409 | pgd_t *pgd; |
410 | pud_t *pud; | |
411 | pmd_t *pmd; | |
412 | ||
413 | pgd = (pgd_t *)page_address(page) + pgd_index(address); | |
414 | pud = pud_offset(pgd, address); | |
415 | pmd = pmd_offset(pud, address); | |
416 | set_pte_atomic((pte_t *)pmd, pte); | |
417 | } | |
1da177e4 | 418 | } |
44af6c41 | 419 | #endif |
1da177e4 LT |
420 | } |
421 | ||
9df84993 IM |
422 | static int |
423 | try_preserve_large_page(pte_t *kpte, unsigned long address, | |
424 | struct cpa_data *cpa) | |
65e074df | 425 | { |
a79e53d8 | 426 | unsigned long nextpage_addr, numpages, pmask, psize, addr, pfn; |
65e074df | 427 | pte_t new_pte, old_pte, *tmp; |
64edc8ed | 428 | pgprot_t old_prot, new_prot, req_prot; |
fac84939 | 429 | int i, do_split = 1; |
f3c4fbb6 | 430 | enum pg_level level; |
65e074df | 431 | |
c9caa02c AK |
432 | if (cpa->force_split) |
433 | return 1; | |
434 | ||
a79e53d8 | 435 | spin_lock(&pgd_lock); |
65e074df TG |
436 | /* |
437 | * Check for races, another CPU might have split this page | |
438 | * up already: | |
439 | */ | |
440 | tmp = lookup_address(address, &level); | |
441 | if (tmp != kpte) | |
442 | goto out_unlock; | |
443 | ||
444 | switch (level) { | |
445 | case PG_LEVEL_2M: | |
f07333fd | 446 | #ifdef CONFIG_X86_64 |
65e074df | 447 | case PG_LEVEL_1G: |
f07333fd | 448 | #endif |
f3c4fbb6 DH |
449 | psize = page_level_size(level); |
450 | pmask = page_level_mask(level); | |
451 | break; | |
65e074df | 452 | default: |
beaff633 | 453 | do_split = -EINVAL; |
65e074df TG |
454 | goto out_unlock; |
455 | } | |
456 | ||
457 | /* | |
458 | * Calculate the number of pages, which fit into this large | |
459 | * page starting at address: | |
460 | */ | |
461 | nextpage_addr = (address + psize) & pmask; | |
462 | numpages = (nextpage_addr - address) >> PAGE_SHIFT; | |
9b5cf48b RW |
463 | if (numpages < cpa->numpages) |
464 | cpa->numpages = numpages; | |
65e074df TG |
465 | |
466 | /* | |
467 | * We are safe now. Check whether the new pgprot is the same: | |
468 | */ | |
469 | old_pte = *kpte; | |
f76cfa3c | 470 | old_prot = req_prot = pte_pgprot(old_pte); |
65e074df | 471 | |
64edc8ed | 472 | pgprot_val(req_prot) &= ~pgprot_val(cpa->mask_clr); |
473 | pgprot_val(req_prot) |= pgprot_val(cpa->mask_set); | |
c31c7d48 | 474 | |
a8aed3e0 AA |
475 | /* |
476 | * Set the PSE and GLOBAL flags only if the PRESENT flag is | |
477 | * set otherwise pmd_present/pmd_huge will return true even on | |
478 | * a non present pmd. The canon_pgprot will clear _PAGE_GLOBAL | |
479 | * for the ancient hardware that doesn't support it. | |
480 | */ | |
f76cfa3c AA |
481 | if (pgprot_val(req_prot) & _PAGE_PRESENT) |
482 | pgprot_val(req_prot) |= _PAGE_PSE | _PAGE_GLOBAL; | |
a8aed3e0 | 483 | else |
f76cfa3c | 484 | pgprot_val(req_prot) &= ~(_PAGE_PSE | _PAGE_GLOBAL); |
a8aed3e0 | 485 | |
f76cfa3c | 486 | req_prot = canon_pgprot(req_prot); |
a8aed3e0 | 487 | |
c31c7d48 TG |
488 | /* |
489 | * old_pte points to the large page base address. So we need | |
490 | * to add the offset of the virtual address: | |
491 | */ | |
492 | pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT); | |
493 | cpa->pfn = pfn; | |
494 | ||
64edc8ed | 495 | new_prot = static_protections(req_prot, address, pfn); |
65e074df | 496 | |
fac84939 TG |
497 | /* |
498 | * We need to check the full range, whether | |
499 | * static_protection() requires a different pgprot for one of | |
500 | * the pages in the range we try to preserve: | |
501 | */ | |
64edc8ed | 502 | addr = address & pmask; |
503 | pfn = pte_pfn(old_pte); | |
504 | for (i = 0; i < (psize >> PAGE_SHIFT); i++, addr += PAGE_SIZE, pfn++) { | |
505 | pgprot_t chk_prot = static_protections(req_prot, addr, pfn); | |
fac84939 TG |
506 | |
507 | if (pgprot_val(chk_prot) != pgprot_val(new_prot)) | |
508 | goto out_unlock; | |
509 | } | |
510 | ||
65e074df TG |
511 | /* |
512 | * If there are no changes, return. maxpages has been updated | |
513 | * above: | |
514 | */ | |
515 | if (pgprot_val(new_prot) == pgprot_val(old_prot)) { | |
beaff633 | 516 | do_split = 0; |
65e074df TG |
517 | goto out_unlock; |
518 | } | |
519 | ||
520 | /* | |
521 | * We need to change the attributes. Check, whether we can | |
522 | * change the large page in one go. We request a split, when | |
523 | * the address is not aligned and the number of pages is | |
524 | * smaller than the number of pages in the large page. Note | |
525 | * that we limited the number of possible pages already to | |
526 | * the number of pages in the large page. | |
527 | */ | |
64edc8ed | 528 | if (address == (address & pmask) && cpa->numpages == (psize >> PAGE_SHIFT)) { |
65e074df TG |
529 | /* |
530 | * The address is aligned and the number of pages | |
531 | * covers the full page. | |
532 | */ | |
a8aed3e0 | 533 | new_pte = pfn_pte(pte_pfn(old_pte), new_prot); |
65e074df | 534 | __set_pmd_pte(kpte, address, new_pte); |
d75586ad | 535 | cpa->flags |= CPA_FLUSHTLB; |
beaff633 | 536 | do_split = 0; |
65e074df TG |
537 | } |
538 | ||
539 | out_unlock: | |
a79e53d8 | 540 | spin_unlock(&pgd_lock); |
9df84993 | 541 | |
beaff633 | 542 | return do_split; |
65e074df TG |
543 | } |
544 | ||
ae9aae9e | 545 | int __split_large_page(pte_t *kpte, unsigned long address, pte_t *pbase) |
bb5c2dbd | 546 | { |
a79e53d8 | 547 | unsigned long pfn, pfninc = 1; |
9df84993 | 548 | unsigned int i, level; |
ae9aae9e | 549 | pte_t *tmp; |
9df84993 | 550 | pgprot_t ref_prot; |
ae9aae9e | 551 | struct page *base = virt_to_page(pbase); |
bb5c2dbd | 552 | |
a79e53d8 | 553 | spin_lock(&pgd_lock); |
bb5c2dbd IM |
554 | /* |
555 | * Check for races, another CPU might have split this page | |
556 | * up for us already: | |
557 | */ | |
558 | tmp = lookup_address(address, &level); | |
ae9aae9e WC |
559 | if (tmp != kpte) { |
560 | spin_unlock(&pgd_lock); | |
561 | return 1; | |
562 | } | |
bb5c2dbd | 563 | |
6944a9c8 | 564 | paravirt_alloc_pte(&init_mm, page_to_pfn(base)); |
07cf89c0 | 565 | ref_prot = pte_pgprot(pte_clrhuge(*kpte)); |
7a5714e0 IM |
566 | /* |
567 | * If we ever want to utilize the PAT bit, we need to | |
568 | * update this function to make sure it's converted from | |
569 | * bit 12 to bit 7 when we cross from the 2MB level to | |
570 | * the 4K level: | |
571 | */ | |
572 | WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE); | |
bb5c2dbd | 573 | |
f07333fd AK |
574 | #ifdef CONFIG_X86_64 |
575 | if (level == PG_LEVEL_1G) { | |
576 | pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT; | |
a8aed3e0 AA |
577 | /* |
578 | * Set the PSE flags only if the PRESENT flag is set | |
579 | * otherwise pmd_present/pmd_huge will return true | |
580 | * even on a non present pmd. | |
581 | */ | |
582 | if (pgprot_val(ref_prot) & _PAGE_PRESENT) | |
583 | pgprot_val(ref_prot) |= _PAGE_PSE; | |
584 | else | |
585 | pgprot_val(ref_prot) &= ~_PAGE_PSE; | |
f07333fd AK |
586 | } |
587 | #endif | |
588 | ||
a8aed3e0 AA |
589 | /* |
590 | * Set the GLOBAL flags only if the PRESENT flag is set | |
591 | * otherwise pmd/pte_present will return true even on a non | |
592 | * present pmd/pte. The canon_pgprot will clear _PAGE_GLOBAL | |
593 | * for the ancient hardware that doesn't support it. | |
594 | */ | |
595 | if (pgprot_val(ref_prot) & _PAGE_PRESENT) | |
596 | pgprot_val(ref_prot) |= _PAGE_GLOBAL; | |
597 | else | |
598 | pgprot_val(ref_prot) &= ~_PAGE_GLOBAL; | |
599 | ||
63c1dcf4 TG |
600 | /* |
601 | * Get the target pfn from the original entry: | |
602 | */ | |
603 | pfn = pte_pfn(*kpte); | |
f07333fd | 604 | for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc) |
a8aed3e0 | 605 | set_pte(&pbase[i], pfn_pte(pfn, canon_pgprot(ref_prot))); |
bb5c2dbd | 606 | |
8eb5779f YL |
607 | if (pfn_range_is_mapped(PFN_DOWN(__pa(address)), |
608 | PFN_DOWN(__pa(address)) + 1)) | |
f361a450 YL |
609 | split_page_count(level); |
610 | ||
bb5c2dbd | 611 | /* |
07a66d7c | 612 | * Install the new, split up pagetable. |
4c881ca1 | 613 | * |
07a66d7c IM |
614 | * We use the standard kernel pagetable protections for the new |
615 | * pagetable protections, the actual ptes set above control the | |
616 | * primary protection behavior: | |
bb5c2dbd | 617 | */ |
07a66d7c | 618 | __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); |
211b3d03 IM |
619 | |
620 | /* | |
621 | * Intel Atom errata AAH41 workaround. | |
622 | * | |
623 | * The real fix should be in hw or in a microcode update, but | |
624 | * we also probabilistically try to reduce the window of having | |
625 | * a large TLB mixed with 4K TLBs while instruction fetches are | |
626 | * going on. | |
627 | */ | |
628 | __flush_tlb_all(); | |
ae9aae9e | 629 | spin_unlock(&pgd_lock); |
211b3d03 | 630 | |
ae9aae9e WC |
631 | return 0; |
632 | } | |
bb5c2dbd | 633 | |
ae9aae9e WC |
634 | static int split_large_page(pte_t *kpte, unsigned long address) |
635 | { | |
636 | pte_t *pbase; | |
637 | struct page *base; | |
638 | ||
639 | if (!debug_pagealloc) | |
640 | spin_unlock(&cpa_lock); | |
641 | base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0); | |
642 | if (!debug_pagealloc) | |
643 | spin_lock(&cpa_lock); | |
644 | if (!base) | |
645 | return -ENOMEM; | |
646 | ||
647 | pbase = (pte_t *)page_address(base); | |
648 | if (__split_large_page(kpte, address, pbase)) | |
8311eb84 | 649 | __free_page(base); |
bb5c2dbd | 650 | |
bb5c2dbd IM |
651 | return 0; |
652 | } | |
653 | ||
a1e46212 SS |
654 | static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr, |
655 | int primary) | |
656 | { | |
657 | /* | |
658 | * Ignore all non primary paths. | |
659 | */ | |
660 | if (!primary) | |
661 | return 0; | |
662 | ||
663 | /* | |
664 | * Ignore the NULL PTE for kernel identity mapping, as it is expected | |
665 | * to have holes. | |
666 | * Also set numpages to '1' indicating that we processed cpa req for | |
667 | * one virtual address page and its pfn. TBD: numpages can be set based | |
668 | * on the initial value and the level returned by lookup_address(). | |
669 | */ | |
670 | if (within(vaddr, PAGE_OFFSET, | |
671 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) { | |
672 | cpa->numpages = 1; | |
673 | cpa->pfn = __pa(vaddr) >> PAGE_SHIFT; | |
674 | return 0; | |
675 | } else { | |
676 | WARN(1, KERN_WARNING "CPA: called for zero pte. " | |
677 | "vaddr = %lx cpa->vaddr = %lx\n", vaddr, | |
678 | *cpa->vaddr); | |
679 | ||
680 | return -EFAULT; | |
681 | } | |
682 | } | |
683 | ||
c31c7d48 | 684 | static int __change_page_attr(struct cpa_data *cpa, int primary) |
9f4c815c | 685 | { |
d75586ad | 686 | unsigned long address; |
da7bfc50 HH |
687 | int do_split, err; |
688 | unsigned int level; | |
c31c7d48 | 689 | pte_t *kpte, old_pte; |
1da177e4 | 690 | |
8523acfe TH |
691 | if (cpa->flags & CPA_PAGES_ARRAY) { |
692 | struct page *page = cpa->pages[cpa->curpage]; | |
693 | if (unlikely(PageHighMem(page))) | |
694 | return 0; | |
695 | address = (unsigned long)page_address(page); | |
696 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
697 | address = cpa->vaddr[cpa->curpage]; |
698 | else | |
699 | address = *cpa->vaddr; | |
97f99fed | 700 | repeat: |
f0646e43 | 701 | kpte = lookup_address(address, &level); |
1da177e4 | 702 | if (!kpte) |
a1e46212 | 703 | return __cpa_process_fault(cpa, address, primary); |
c31c7d48 TG |
704 | |
705 | old_pte = *kpte; | |
a1e46212 SS |
706 | if (!pte_val(old_pte)) |
707 | return __cpa_process_fault(cpa, address, primary); | |
9f4c815c | 708 | |
30551bb3 | 709 | if (level == PG_LEVEL_4K) { |
c31c7d48 | 710 | pte_t new_pte; |
626c2c9d | 711 | pgprot_t new_prot = pte_pgprot(old_pte); |
c31c7d48 | 712 | unsigned long pfn = pte_pfn(old_pte); |
86f03989 | 713 | |
72e458df TG |
714 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); |
715 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
86f03989 | 716 | |
c31c7d48 | 717 | new_prot = static_protections(new_prot, address, pfn); |
86f03989 | 718 | |
a8aed3e0 AA |
719 | /* |
720 | * Set the GLOBAL flags only if the PRESENT flag is | |
721 | * set otherwise pte_present will return true even on | |
722 | * a non present pte. The canon_pgprot will clear | |
723 | * _PAGE_GLOBAL for the ancient hardware that doesn't | |
724 | * support it. | |
725 | */ | |
726 | if (pgprot_val(new_prot) & _PAGE_PRESENT) | |
727 | pgprot_val(new_prot) |= _PAGE_GLOBAL; | |
728 | else | |
729 | pgprot_val(new_prot) &= ~_PAGE_GLOBAL; | |
730 | ||
626c2c9d AV |
731 | /* |
732 | * We need to keep the pfn from the existing PTE, | |
733 | * after all we're only going to change it's attributes | |
734 | * not the memory it points to | |
735 | */ | |
c31c7d48 TG |
736 | new_pte = pfn_pte(pfn, canon_pgprot(new_prot)); |
737 | cpa->pfn = pfn; | |
f4ae5da0 TG |
738 | /* |
739 | * Do we really change anything ? | |
740 | */ | |
741 | if (pte_val(old_pte) != pte_val(new_pte)) { | |
742 | set_pte_atomic(kpte, new_pte); | |
d75586ad | 743 | cpa->flags |= CPA_FLUSHTLB; |
f4ae5da0 | 744 | } |
9b5cf48b | 745 | cpa->numpages = 1; |
65e074df | 746 | return 0; |
1da177e4 | 747 | } |
65e074df TG |
748 | |
749 | /* | |
750 | * Check, whether we can keep the large page intact | |
751 | * and just change the pte: | |
752 | */ | |
beaff633 | 753 | do_split = try_preserve_large_page(kpte, address, cpa); |
65e074df TG |
754 | /* |
755 | * When the range fits into the existing large page, | |
9b5cf48b | 756 | * return. cp->numpages and cpa->tlbflush have been updated in |
65e074df TG |
757 | * try_large_page: |
758 | */ | |
87f7f8fe IM |
759 | if (do_split <= 0) |
760 | return do_split; | |
65e074df TG |
761 | |
762 | /* | |
763 | * We have to split the large page: | |
764 | */ | |
87f7f8fe IM |
765 | err = split_large_page(kpte, address); |
766 | if (!err) { | |
ad5ca55f SS |
767 | /* |
768 | * Do a global flush tlb after splitting the large page | |
769 | * and before we do the actual change page attribute in the PTE. | |
770 | * | |
771 | * With out this, we violate the TLB application note, that says | |
772 | * "The TLBs may contain both ordinary and large-page | |
773 | * translations for a 4-KByte range of linear addresses. This | |
774 | * may occur if software modifies the paging structures so that | |
775 | * the page size used for the address range changes. If the two | |
776 | * translations differ with respect to page frame or attributes | |
777 | * (e.g., permissions), processor behavior is undefined and may | |
778 | * be implementation-specific." | |
779 | * | |
780 | * We do this global tlb flush inside the cpa_lock, so that we | |
781 | * don't allow any other cpu, with stale tlb entries change the | |
782 | * page attribute in parallel, that also falls into the | |
783 | * just split large page entry. | |
784 | */ | |
785 | flush_tlb_all(); | |
87f7f8fe IM |
786 | goto repeat; |
787 | } | |
beaff633 | 788 | |
87f7f8fe | 789 | return err; |
9f4c815c | 790 | } |
1da177e4 | 791 | |
c31c7d48 TG |
792 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias); |
793 | ||
794 | static int cpa_process_alias(struct cpa_data *cpa) | |
1da177e4 | 795 | { |
c31c7d48 | 796 | struct cpa_data alias_cpa; |
992f4c1c | 797 | unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT); |
e933a73f | 798 | unsigned long vaddr; |
992f4c1c | 799 | int ret; |
44af6c41 | 800 | |
8eb5779f | 801 | if (!pfn_range_is_mapped(cpa->pfn, cpa->pfn + 1)) |
c31c7d48 | 802 | return 0; |
626c2c9d | 803 | |
f34b439f TG |
804 | /* |
805 | * No need to redo, when the primary call touched the direct | |
806 | * mapping already: | |
807 | */ | |
8523acfe TH |
808 | if (cpa->flags & CPA_PAGES_ARRAY) { |
809 | struct page *page = cpa->pages[cpa->curpage]; | |
810 | if (unlikely(PageHighMem(page))) | |
811 | return 0; | |
812 | vaddr = (unsigned long)page_address(page); | |
813 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
814 | vaddr = cpa->vaddr[cpa->curpage]; |
815 | else | |
816 | vaddr = *cpa->vaddr; | |
817 | ||
818 | if (!(within(vaddr, PAGE_OFFSET, | |
a1e46212 | 819 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) { |
44af6c41 | 820 | |
f34b439f | 821 | alias_cpa = *cpa; |
992f4c1c | 822 | alias_cpa.vaddr = &laddr; |
9ae28475 | 823 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); |
d75586ad | 824 | |
f34b439f | 825 | ret = __change_page_attr_set_clr(&alias_cpa, 0); |
992f4c1c TH |
826 | if (ret) |
827 | return ret; | |
f34b439f | 828 | } |
44af6c41 | 829 | |
44af6c41 | 830 | #ifdef CONFIG_X86_64 |
488fd995 | 831 | /* |
992f4c1c TH |
832 | * If the primary call didn't touch the high mapping already |
833 | * and the physical address is inside the kernel map, we need | |
0879750f | 834 | * to touch the high mapped kernel as well: |
488fd995 | 835 | */ |
992f4c1c TH |
836 | if (!within(vaddr, (unsigned long)_text, _brk_end) && |
837 | within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) { | |
838 | unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) + | |
839 | __START_KERNEL_map - phys_base; | |
840 | alias_cpa = *cpa; | |
841 | alias_cpa.vaddr = &temp_cpa_vaddr; | |
842 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); | |
c31c7d48 | 843 | |
992f4c1c TH |
844 | /* |
845 | * The high mapping range is imprecise, so ignore the | |
846 | * return value. | |
847 | */ | |
848 | __change_page_attr_set_clr(&alias_cpa, 0); | |
849 | } | |
488fd995 | 850 | #endif |
992f4c1c TH |
851 | |
852 | return 0; | |
1da177e4 LT |
853 | } |
854 | ||
c31c7d48 | 855 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias) |
ff31452b | 856 | { |
65e074df | 857 | int ret, numpages = cpa->numpages; |
ff31452b | 858 | |
65e074df TG |
859 | while (numpages) { |
860 | /* | |
861 | * Store the remaining nr of pages for the large page | |
862 | * preservation check. | |
863 | */ | |
9b5cf48b | 864 | cpa->numpages = numpages; |
d75586ad | 865 | /* for array changes, we can't use large page */ |
9ae28475 | 866 | if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
d75586ad | 867 | cpa->numpages = 1; |
c31c7d48 | 868 | |
ad5ca55f SS |
869 | if (!debug_pagealloc) |
870 | spin_lock(&cpa_lock); | |
c31c7d48 | 871 | ret = __change_page_attr(cpa, checkalias); |
ad5ca55f SS |
872 | if (!debug_pagealloc) |
873 | spin_unlock(&cpa_lock); | |
ff31452b TG |
874 | if (ret) |
875 | return ret; | |
ff31452b | 876 | |
c31c7d48 TG |
877 | if (checkalias) { |
878 | ret = cpa_process_alias(cpa); | |
879 | if (ret) | |
880 | return ret; | |
881 | } | |
882 | ||
65e074df TG |
883 | /* |
884 | * Adjust the number of pages with the result of the | |
885 | * CPA operation. Either a large page has been | |
886 | * preserved or a single page update happened. | |
887 | */ | |
9b5cf48b RW |
888 | BUG_ON(cpa->numpages > numpages); |
889 | numpages -= cpa->numpages; | |
9ae28475 | 890 | if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) |
d75586ad SL |
891 | cpa->curpage++; |
892 | else | |
893 | *cpa->vaddr += cpa->numpages * PAGE_SIZE; | |
894 | ||
65e074df | 895 | } |
ff31452b TG |
896 | return 0; |
897 | } | |
898 | ||
6bb8383b AK |
899 | static inline int cache_attr(pgprot_t attr) |
900 | { | |
901 | return pgprot_val(attr) & | |
902 | (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD); | |
903 | } | |
904 | ||
d75586ad | 905 | static int change_page_attr_set_clr(unsigned long *addr, int numpages, |
c9caa02c | 906 | pgprot_t mask_set, pgprot_t mask_clr, |
9ae28475 | 907 | int force_split, int in_flag, |
908 | struct page **pages) | |
ff31452b | 909 | { |
72e458df | 910 | struct cpa_data cpa; |
cacf8906 | 911 | int ret, cache, checkalias; |
fa526d0d | 912 | unsigned long baddr = 0; |
331e4065 TG |
913 | |
914 | /* | |
915 | * Check, if we are requested to change a not supported | |
916 | * feature: | |
917 | */ | |
918 | mask_set = canon_pgprot(mask_set); | |
919 | mask_clr = canon_pgprot(mask_clr); | |
c9caa02c | 920 | if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split) |
331e4065 TG |
921 | return 0; |
922 | ||
69b1415e | 923 | /* Ensure we are PAGE_SIZE aligned */ |
9ae28475 | 924 | if (in_flag & CPA_ARRAY) { |
d75586ad SL |
925 | int i; |
926 | for (i = 0; i < numpages; i++) { | |
927 | if (addr[i] & ~PAGE_MASK) { | |
928 | addr[i] &= PAGE_MASK; | |
929 | WARN_ON_ONCE(1); | |
930 | } | |
931 | } | |
9ae28475 | 932 | } else if (!(in_flag & CPA_PAGES_ARRAY)) { |
933 | /* | |
934 | * in_flag of CPA_PAGES_ARRAY implies it is aligned. | |
935 | * No need to cehck in that case | |
936 | */ | |
937 | if (*addr & ~PAGE_MASK) { | |
938 | *addr &= PAGE_MASK; | |
939 | /* | |
940 | * People should not be passing in unaligned addresses: | |
941 | */ | |
942 | WARN_ON_ONCE(1); | |
943 | } | |
fa526d0d JS |
944 | /* |
945 | * Save address for cache flush. *addr is modified in the call | |
946 | * to __change_page_attr_set_clr() below. | |
947 | */ | |
948 | baddr = *addr; | |
69b1415e TG |
949 | } |
950 | ||
5843d9a4 NP |
951 | /* Must avoid aliasing mappings in the highmem code */ |
952 | kmap_flush_unused(); | |
953 | ||
db64fe02 NP |
954 | vm_unmap_aliases(); |
955 | ||
72e458df | 956 | cpa.vaddr = addr; |
9ae28475 | 957 | cpa.pages = pages; |
72e458df TG |
958 | cpa.numpages = numpages; |
959 | cpa.mask_set = mask_set; | |
960 | cpa.mask_clr = mask_clr; | |
d75586ad SL |
961 | cpa.flags = 0; |
962 | cpa.curpage = 0; | |
c9caa02c | 963 | cpa.force_split = force_split; |
72e458df | 964 | |
9ae28475 | 965 | if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
966 | cpa.flags |= in_flag; | |
d75586ad | 967 | |
af96e443 TG |
968 | /* No alias checking for _NX bit modifications */ |
969 | checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX; | |
970 | ||
971 | ret = __change_page_attr_set_clr(&cpa, checkalias); | |
ff31452b | 972 | |
f4ae5da0 TG |
973 | /* |
974 | * Check whether we really changed something: | |
975 | */ | |
d75586ad | 976 | if (!(cpa.flags & CPA_FLUSHTLB)) |
1ac2f7d5 | 977 | goto out; |
cacf8906 | 978 | |
6bb8383b AK |
979 | /* |
980 | * No need to flush, when we did not set any of the caching | |
981 | * attributes: | |
982 | */ | |
983 | cache = cache_attr(mask_set); | |
984 | ||
57a6a46a TG |
985 | /* |
986 | * On success we use clflush, when the CPU supports it to | |
f026cfa8 PA |
987 | * avoid the wbindv. If the CPU does not support it and in the |
988 | * error case we fall back to cpa_flush_all (which uses | |
989 | * wbindv): | |
57a6a46a | 990 | */ |
f026cfa8 | 991 | if (!ret && cpu_has_clflush) { |
9ae28475 | 992 | if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) { |
993 | cpa_flush_array(addr, numpages, cache, | |
994 | cpa.flags, pages); | |
995 | } else | |
fa526d0d | 996 | cpa_flush_range(baddr, numpages, cache); |
d75586ad | 997 | } else |
6bb8383b | 998 | cpa_flush_all(cache); |
cacf8906 | 999 | |
76ebd054 | 1000 | out: |
ff31452b TG |
1001 | return ret; |
1002 | } | |
1003 | ||
d75586ad SL |
1004 | static inline int change_page_attr_set(unsigned long *addr, int numpages, |
1005 | pgprot_t mask, int array) | |
75cbade8 | 1006 | { |
d75586ad | 1007 | return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0, |
9ae28475 | 1008 | (array ? CPA_ARRAY : 0), NULL); |
75cbade8 AV |
1009 | } |
1010 | ||
d75586ad SL |
1011 | static inline int change_page_attr_clear(unsigned long *addr, int numpages, |
1012 | pgprot_t mask, int array) | |
72932c7a | 1013 | { |
d75586ad | 1014 | return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0, |
9ae28475 | 1015 | (array ? CPA_ARRAY : 0), NULL); |
72932c7a TG |
1016 | } |
1017 | ||
0f350755 | 1018 | static inline int cpa_set_pages_array(struct page **pages, int numpages, |
1019 | pgprot_t mask) | |
1020 | { | |
1021 | return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0, | |
1022 | CPA_PAGES_ARRAY, pages); | |
1023 | } | |
1024 | ||
1025 | static inline int cpa_clear_pages_array(struct page **pages, int numpages, | |
1026 | pgprot_t mask) | |
1027 | { | |
1028 | return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0, | |
1029 | CPA_PAGES_ARRAY, pages); | |
1030 | } | |
1031 | ||
1219333d | 1032 | int _set_memory_uc(unsigned long addr, int numpages) |
72932c7a | 1033 | { |
de33c442 SS |
1034 | /* |
1035 | * for now UC MINUS. see comments in ioremap_nocache() | |
1036 | */ | |
d75586ad SL |
1037 | return change_page_attr_set(&addr, numpages, |
1038 | __pgprot(_PAGE_CACHE_UC_MINUS), 0); | |
75cbade8 | 1039 | } |
1219333d | 1040 | |
1041 | int set_memory_uc(unsigned long addr, int numpages) | |
1042 | { | |
9fa3ab39 | 1043 | int ret; |
1044 | ||
de33c442 SS |
1045 | /* |
1046 | * for now UC MINUS. see comments in ioremap_nocache() | |
1047 | */ | |
9fa3ab39 | 1048 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
1049 | _PAGE_CACHE_UC_MINUS, NULL); | |
1050 | if (ret) | |
1051 | goto out_err; | |
1052 | ||
1053 | ret = _set_memory_uc(addr, numpages); | |
1054 | if (ret) | |
1055 | goto out_free; | |
1056 | ||
1057 | return 0; | |
1219333d | 1058 | |
9fa3ab39 | 1059 | out_free: |
1060 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
1061 | out_err: | |
1062 | return ret; | |
1219333d | 1063 | } |
75cbade8 AV |
1064 | EXPORT_SYMBOL(set_memory_uc); |
1065 | ||
2d070eff | 1066 | static int _set_memory_array(unsigned long *addr, int addrinarray, |
4f646254 | 1067 | unsigned long new_type) |
d75586ad | 1068 | { |
9fa3ab39 | 1069 | int i, j; |
1070 | int ret; | |
1071 | ||
d75586ad SL |
1072 | /* |
1073 | * for now UC MINUS. see comments in ioremap_nocache() | |
1074 | */ | |
1075 | for (i = 0; i < addrinarray; i++) { | |
9fa3ab39 | 1076 | ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE, |
4f646254 | 1077 | new_type, NULL); |
9fa3ab39 | 1078 | if (ret) |
1079 | goto out_free; | |
d75586ad SL |
1080 | } |
1081 | ||
9fa3ab39 | 1082 | ret = change_page_attr_set(addr, addrinarray, |
d75586ad | 1083 | __pgprot(_PAGE_CACHE_UC_MINUS), 1); |
4f646254 PN |
1084 | |
1085 | if (!ret && new_type == _PAGE_CACHE_WC) | |
1086 | ret = change_page_attr_set_clr(addr, addrinarray, | |
1087 | __pgprot(_PAGE_CACHE_WC), | |
1088 | __pgprot(_PAGE_CACHE_MASK), | |
1089 | 0, CPA_ARRAY, NULL); | |
9fa3ab39 | 1090 | if (ret) |
1091 | goto out_free; | |
1092 | ||
1093 | return 0; | |
1094 | ||
1095 | out_free: | |
1096 | for (j = 0; j < i; j++) | |
1097 | free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE); | |
1098 | ||
1099 | return ret; | |
d75586ad | 1100 | } |
4f646254 PN |
1101 | |
1102 | int set_memory_array_uc(unsigned long *addr, int addrinarray) | |
1103 | { | |
1104 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_UC_MINUS); | |
1105 | } | |
d75586ad SL |
1106 | EXPORT_SYMBOL(set_memory_array_uc); |
1107 | ||
4f646254 PN |
1108 | int set_memory_array_wc(unsigned long *addr, int addrinarray) |
1109 | { | |
1110 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_WC); | |
1111 | } | |
1112 | EXPORT_SYMBOL(set_memory_array_wc); | |
1113 | ||
ef354af4 | 1114 | int _set_memory_wc(unsigned long addr, int numpages) |
1115 | { | |
3869c4aa | 1116 | int ret; |
bdc6340f PV |
1117 | unsigned long addr_copy = addr; |
1118 | ||
3869c4aa | 1119 | ret = change_page_attr_set(&addr, numpages, |
1120 | __pgprot(_PAGE_CACHE_UC_MINUS), 0); | |
3869c4aa | 1121 | if (!ret) { |
bdc6340f PV |
1122 | ret = change_page_attr_set_clr(&addr_copy, numpages, |
1123 | __pgprot(_PAGE_CACHE_WC), | |
1124 | __pgprot(_PAGE_CACHE_MASK), | |
1125 | 0, 0, NULL); | |
3869c4aa | 1126 | } |
1127 | return ret; | |
ef354af4 | 1128 | } |
1129 | ||
1130 | int set_memory_wc(unsigned long addr, int numpages) | |
1131 | { | |
9fa3ab39 | 1132 | int ret; |
1133 | ||
499f8f84 | 1134 | if (!pat_enabled) |
ef354af4 | 1135 | return set_memory_uc(addr, numpages); |
1136 | ||
9fa3ab39 | 1137 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
1138 | _PAGE_CACHE_WC, NULL); | |
1139 | if (ret) | |
1140 | goto out_err; | |
ef354af4 | 1141 | |
9fa3ab39 | 1142 | ret = _set_memory_wc(addr, numpages); |
1143 | if (ret) | |
1144 | goto out_free; | |
1145 | ||
1146 | return 0; | |
1147 | ||
1148 | out_free: | |
1149 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
1150 | out_err: | |
1151 | return ret; | |
ef354af4 | 1152 | } |
1153 | EXPORT_SYMBOL(set_memory_wc); | |
1154 | ||
1219333d | 1155 | int _set_memory_wb(unsigned long addr, int numpages) |
75cbade8 | 1156 | { |
d75586ad SL |
1157 | return change_page_attr_clear(&addr, numpages, |
1158 | __pgprot(_PAGE_CACHE_MASK), 0); | |
75cbade8 | 1159 | } |
1219333d | 1160 | |
1161 | int set_memory_wb(unsigned long addr, int numpages) | |
1162 | { | |
9fa3ab39 | 1163 | int ret; |
1164 | ||
1165 | ret = _set_memory_wb(addr, numpages); | |
1166 | if (ret) | |
1167 | return ret; | |
1168 | ||
c15238df | 1169 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
9fa3ab39 | 1170 | return 0; |
1219333d | 1171 | } |
75cbade8 AV |
1172 | EXPORT_SYMBOL(set_memory_wb); |
1173 | ||
d75586ad SL |
1174 | int set_memory_array_wb(unsigned long *addr, int addrinarray) |
1175 | { | |
1176 | int i; | |
a5593e0b | 1177 | int ret; |
1178 | ||
1179 | ret = change_page_attr_clear(addr, addrinarray, | |
1180 | __pgprot(_PAGE_CACHE_MASK), 1); | |
9fa3ab39 | 1181 | if (ret) |
1182 | return ret; | |
d75586ad | 1183 | |
9fa3ab39 | 1184 | for (i = 0; i < addrinarray; i++) |
1185 | free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE); | |
c5e147cf | 1186 | |
9fa3ab39 | 1187 | return 0; |
d75586ad SL |
1188 | } |
1189 | EXPORT_SYMBOL(set_memory_array_wb); | |
1190 | ||
75cbade8 AV |
1191 | int set_memory_x(unsigned long addr, int numpages) |
1192 | { | |
583140af PA |
1193 | if (!(__supported_pte_mask & _PAGE_NX)) |
1194 | return 0; | |
1195 | ||
d75586ad | 1196 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1197 | } |
1198 | EXPORT_SYMBOL(set_memory_x); | |
1199 | ||
1200 | int set_memory_nx(unsigned long addr, int numpages) | |
1201 | { | |
583140af PA |
1202 | if (!(__supported_pte_mask & _PAGE_NX)) |
1203 | return 0; | |
1204 | ||
d75586ad | 1205 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1206 | } |
1207 | EXPORT_SYMBOL(set_memory_nx); | |
1208 | ||
1209 | int set_memory_ro(unsigned long addr, int numpages) | |
1210 | { | |
d75586ad | 1211 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1212 | } |
a03352d2 | 1213 | EXPORT_SYMBOL_GPL(set_memory_ro); |
75cbade8 AV |
1214 | |
1215 | int set_memory_rw(unsigned long addr, int numpages) | |
1216 | { | |
d75586ad | 1217 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1218 | } |
a03352d2 | 1219 | EXPORT_SYMBOL_GPL(set_memory_rw); |
f62d0f00 IM |
1220 | |
1221 | int set_memory_np(unsigned long addr, int numpages) | |
1222 | { | |
d75586ad | 1223 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0); |
f62d0f00 | 1224 | } |
75cbade8 | 1225 | |
c9caa02c AK |
1226 | int set_memory_4k(unsigned long addr, int numpages) |
1227 | { | |
d75586ad | 1228 | return change_page_attr_set_clr(&addr, numpages, __pgprot(0), |
9ae28475 | 1229 | __pgprot(0), 1, 0, NULL); |
c9caa02c AK |
1230 | } |
1231 | ||
75cbade8 AV |
1232 | int set_pages_uc(struct page *page, int numpages) |
1233 | { | |
1234 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1235 | |
d7c8f21a | 1236 | return set_memory_uc(addr, numpages); |
75cbade8 AV |
1237 | } |
1238 | EXPORT_SYMBOL(set_pages_uc); | |
1239 | ||
4f646254 PN |
1240 | static int _set_pages_array(struct page **pages, int addrinarray, |
1241 | unsigned long new_type) | |
0f350755 | 1242 | { |
1243 | unsigned long start; | |
1244 | unsigned long end; | |
1245 | int i; | |
1246 | int free_idx; | |
4f646254 | 1247 | int ret; |
0f350755 | 1248 | |
1249 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1250 | if (PageHighMem(pages[i])) |
1251 | continue; | |
1252 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1253 | end = start + PAGE_SIZE; |
4f646254 | 1254 | if (reserve_memtype(start, end, new_type, NULL)) |
0f350755 | 1255 | goto err_out; |
1256 | } | |
1257 | ||
4f646254 PN |
1258 | ret = cpa_set_pages_array(pages, addrinarray, |
1259 | __pgprot(_PAGE_CACHE_UC_MINUS)); | |
1260 | if (!ret && new_type == _PAGE_CACHE_WC) | |
1261 | ret = change_page_attr_set_clr(NULL, addrinarray, | |
1262 | __pgprot(_PAGE_CACHE_WC), | |
1263 | __pgprot(_PAGE_CACHE_MASK), | |
1264 | 0, CPA_PAGES_ARRAY, pages); | |
1265 | if (ret) | |
1266 | goto err_out; | |
1267 | return 0; /* Success */ | |
0f350755 | 1268 | err_out: |
1269 | free_idx = i; | |
1270 | for (i = 0; i < free_idx; i++) { | |
8523acfe TH |
1271 | if (PageHighMem(pages[i])) |
1272 | continue; | |
1273 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1274 | end = start + PAGE_SIZE; |
1275 | free_memtype(start, end); | |
1276 | } | |
1277 | return -EINVAL; | |
1278 | } | |
4f646254 PN |
1279 | |
1280 | int set_pages_array_uc(struct page **pages, int addrinarray) | |
1281 | { | |
1282 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_UC_MINUS); | |
1283 | } | |
0f350755 | 1284 | EXPORT_SYMBOL(set_pages_array_uc); |
1285 | ||
4f646254 PN |
1286 | int set_pages_array_wc(struct page **pages, int addrinarray) |
1287 | { | |
1288 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_WC); | |
1289 | } | |
1290 | EXPORT_SYMBOL(set_pages_array_wc); | |
1291 | ||
75cbade8 AV |
1292 | int set_pages_wb(struct page *page, int numpages) |
1293 | { | |
1294 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1295 | |
d7c8f21a | 1296 | return set_memory_wb(addr, numpages); |
75cbade8 AV |
1297 | } |
1298 | EXPORT_SYMBOL(set_pages_wb); | |
1299 | ||
0f350755 | 1300 | int set_pages_array_wb(struct page **pages, int addrinarray) |
1301 | { | |
1302 | int retval; | |
1303 | unsigned long start; | |
1304 | unsigned long end; | |
1305 | int i; | |
1306 | ||
1307 | retval = cpa_clear_pages_array(pages, addrinarray, | |
1308 | __pgprot(_PAGE_CACHE_MASK)); | |
9fa3ab39 | 1309 | if (retval) |
1310 | return retval; | |
0f350755 | 1311 | |
1312 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1313 | if (PageHighMem(pages[i])) |
1314 | continue; | |
1315 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1316 | end = start + PAGE_SIZE; |
1317 | free_memtype(start, end); | |
1318 | } | |
1319 | ||
9fa3ab39 | 1320 | return 0; |
0f350755 | 1321 | } |
1322 | EXPORT_SYMBOL(set_pages_array_wb); | |
1323 | ||
75cbade8 AV |
1324 | int set_pages_x(struct page *page, int numpages) |
1325 | { | |
1326 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1327 | |
d7c8f21a | 1328 | return set_memory_x(addr, numpages); |
75cbade8 AV |
1329 | } |
1330 | EXPORT_SYMBOL(set_pages_x); | |
1331 | ||
1332 | int set_pages_nx(struct page *page, int numpages) | |
1333 | { | |
1334 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1335 | |
d7c8f21a | 1336 | return set_memory_nx(addr, numpages); |
75cbade8 AV |
1337 | } |
1338 | EXPORT_SYMBOL(set_pages_nx); | |
1339 | ||
1340 | int set_pages_ro(struct page *page, int numpages) | |
1341 | { | |
1342 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1343 | |
d7c8f21a | 1344 | return set_memory_ro(addr, numpages); |
75cbade8 | 1345 | } |
75cbade8 AV |
1346 | |
1347 | int set_pages_rw(struct page *page, int numpages) | |
1348 | { | |
1349 | unsigned long addr = (unsigned long)page_address(page); | |
e81d5dc4 | 1350 | |
d7c8f21a | 1351 | return set_memory_rw(addr, numpages); |
78c94aba IM |
1352 | } |
1353 | ||
1da177e4 | 1354 | #ifdef CONFIG_DEBUG_PAGEALLOC |
f62d0f00 IM |
1355 | |
1356 | static int __set_pages_p(struct page *page, int numpages) | |
1357 | { | |
d75586ad SL |
1358 | unsigned long tempaddr = (unsigned long) page_address(page); |
1359 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
72e458df TG |
1360 | .numpages = numpages, |
1361 | .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW), | |
d75586ad SL |
1362 | .mask_clr = __pgprot(0), |
1363 | .flags = 0}; | |
72932c7a | 1364 | |
55121b43 SS |
1365 | /* |
1366 | * No alias checking needed for setting present flag. otherwise, | |
1367 | * we may need to break large pages for 64-bit kernel text | |
1368 | * mappings (this adds to complexity if we want to do this from | |
1369 | * atomic context especially). Let's keep it simple! | |
1370 | */ | |
1371 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1372 | } |
1373 | ||
1374 | static int __set_pages_np(struct page *page, int numpages) | |
1375 | { | |
d75586ad SL |
1376 | unsigned long tempaddr = (unsigned long) page_address(page); |
1377 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
72e458df TG |
1378 | .numpages = numpages, |
1379 | .mask_set = __pgprot(0), | |
d75586ad SL |
1380 | .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW), |
1381 | .flags = 0}; | |
72932c7a | 1382 | |
55121b43 SS |
1383 | /* |
1384 | * No alias checking needed for setting not present flag. otherwise, | |
1385 | * we may need to break large pages for 64-bit kernel text | |
1386 | * mappings (this adds to complexity if we want to do this from | |
1387 | * atomic context especially). Let's keep it simple! | |
1388 | */ | |
1389 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1390 | } |
1391 | ||
1da177e4 LT |
1392 | void kernel_map_pages(struct page *page, int numpages, int enable) |
1393 | { | |
1394 | if (PageHighMem(page)) | |
1395 | return; | |
9f4c815c | 1396 | if (!enable) { |
f9b8404c IM |
1397 | debug_check_no_locks_freed(page_address(page), |
1398 | numpages * PAGE_SIZE); | |
9f4c815c | 1399 | } |
de5097c2 | 1400 | |
9f4c815c | 1401 | /* |
f8d8406b | 1402 | * The return value is ignored as the calls cannot fail. |
55121b43 SS |
1403 | * Large pages for identity mappings are not used at boot time |
1404 | * and hence no memory allocations during large page split. | |
1da177e4 | 1405 | */ |
f62d0f00 IM |
1406 | if (enable) |
1407 | __set_pages_p(page, numpages); | |
1408 | else | |
1409 | __set_pages_np(page, numpages); | |
9f4c815c IM |
1410 | |
1411 | /* | |
e4b71dcf IM |
1412 | * We should perform an IPI and flush all tlbs, |
1413 | * but that can deadlock->flush only current cpu: | |
1da177e4 LT |
1414 | */ |
1415 | __flush_tlb_all(); | |
26564600 BO |
1416 | |
1417 | arch_flush_lazy_mmu_mode(); | |
ee7ae7a1 TG |
1418 | } |
1419 | ||
8a235efa RW |
1420 | #ifdef CONFIG_HIBERNATION |
1421 | ||
1422 | bool kernel_page_present(struct page *page) | |
1423 | { | |
1424 | unsigned int level; | |
1425 | pte_t *pte; | |
1426 | ||
1427 | if (PageHighMem(page)) | |
1428 | return false; | |
1429 | ||
1430 | pte = lookup_address((unsigned long)page_address(page), &level); | |
1431 | return (pte_val(*pte) & _PAGE_PRESENT); | |
1432 | } | |
1433 | ||
1434 | #endif /* CONFIG_HIBERNATION */ | |
1435 | ||
1436 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
d1028a15 AV |
1437 | |
1438 | /* | |
1439 | * The testcases use internal knowledge of the implementation that shouldn't | |
1440 | * be exposed to the rest of the kernel. Include these directly here. | |
1441 | */ | |
1442 | #ifdef CONFIG_CPA_DEBUG | |
1443 | #include "pageattr-test.c" | |
1444 | #endif |