[deliverable/linux.git] / arch / x86 / mm / pageattr.c

/*
 * Copyright 2002 Andi Kleen, SuSE Labs.
 * Thanks to Ben LaHaise for precious feedback.
 */
#include <linux/highmem.h>
#include <linux/bootmem.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/mm.h>

#include <asm/e820.h>
#include <asm/processor.h>
#include <asm/tlbflush.h>
#include <asm/sections.h>
#include <asm/uaccess.h>
#include <asm/pgalloc.h>

static inline int
within(unsigned long addr, unsigned long start, unsigned long end)
{
	return addr >= start && addr < end;
}

/*
 * Flushing functions
 */


/**
 * clflush_cache_range - flush a cache range with clflush
 * @addr:	virtual start address
 * @size:	number of bytes to flush
 *
 * clflush is an unordered instruction which needs fencing with mfence
 * to avoid ordering issues.
 */
void clflush_cache_range(void *addr, int size)
{
	int i;

	mb();
	for (i = 0; i < size; i += boot_cpu_data.x86_clflush_size)
		clflush(addr+i);
	mb();
}

static void __cpa_flush_all(void *arg)
{
	/*
	 * Flush all to work around Errata in early athlons regarding
	 * large page flushing.
	 */
	__flush_tlb_all();

	if (boot_cpu_data.x86_model >= 4)
		wbinvd();
}

static void cpa_flush_all(void)
{
	BUG_ON(irqs_disabled());

	on_each_cpu(__cpa_flush_all, NULL, 1, 1);
}

static void __cpa_flush_range(void *arg)
{
	/*
	 * We could optimize that further and do individual per page
	 * tlb invalidates for a low number of pages. Caveat: we must
	 * flush the high aliases on 64bit as well.
	 */
	__flush_tlb_all();
}

static void cpa_flush_range(unsigned long addr, int numpages)
{
	BUG_ON(irqs_disabled());

	on_each_cpu(__cpa_flush_range, NULL, 1, 1);

	/*
	 * We only need to flush on one CPU,
	 * clflush is a MESI-coherent instruction that
	 * will cause all other CPUs to flush the same
	 * cachelines:
	 */
	clflush_cache_range((void *) addr, numpages * PAGE_SIZE);
}

/*
 * Certain areas of memory on x86 require very specific protection flags,
 * for example the BIOS area or kernel text. Callers don't always get this
 * right (again, ioremap() on BIOS memory is not uncommon) so this function
 * checks and fixes these known static required protection bits.
 */
static inline pgprot_t static_protections(pgprot_t prot, unsigned long address)
{
	pgprot_t forbidden = __pgprot(0);

	/*
	 * The BIOS area between 640k and 1Mb needs to be executable for
	 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
	 */
	if (within(__pa(address), BIOS_BEGIN, BIOS_END))
		pgprot_val(forbidden) |= _PAGE_NX;

	/*
	 * The kernel text needs to be executable for obvious reasons
	 * Does not cover __inittext since that is gone later on
	 */
	if (within(address, (unsigned long)_text, (unsigned long)_etext))
		pgprot_val(forbidden) |= _PAGE_NX;

#ifdef CONFIG_DEBUG_RODATA
	/* The .rodata section needs to be read-only */
	if (within(address, (unsigned long)__start_rodata,
				(unsigned long)__end_rodata))
		pgprot_val(forbidden) |= _PAGE_RW;
#endif

	prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));

	return prot;
}

pte_t *lookup_address(unsigned long address, int *level)
{
	pgd_t *pgd = pgd_offset_k(address);
	pud_t *pud;
	pmd_t *pmd;

	*level = PG_LEVEL_NONE;

	if (pgd_none(*pgd))
		return NULL;
	pud = pud_offset(pgd, address);
	if (pud_none(*pud))
		return NULL;
	pmd = pmd_offset(pud, address);
	if (pmd_none(*pmd))
		return NULL;

	*level = PG_LEVEL_2M;
	if (pmd_large(*pmd))
		return (pte_t *)pmd;

	*level = PG_LEVEL_4K;
	return pte_offset_kernel(pmd, address);
}

static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
{
	/* change init_mm */
	set_pte_atomic(kpte, pte);
#ifdef CONFIG_X86_32
	if (!SHARED_KERNEL_PMD) {
		struct page *page;

		for (page = pgd_list; page; page = (struct page *)page->index) {
			pgd_t *pgd;
			pud_t *pud;
			pmd_t *pmd;

			pgd = (pgd_t *)page_address(page) + pgd_index(address);
			pud = pud_offset(pgd, address);
			pmd = pmd_offset(pud, address);
			set_pte_atomic((pte_t *)pmd, pte);
		}
	}
#endif
}

static int split_large_page(pte_t *kpte, unsigned long address)
{
	pgprot_t ref_prot = pte_pgprot(pte_clrhuge(*kpte));
	gfp_t gfp_flags = GFP_KERNEL;
	unsigned long flags;
	unsigned long addr;
	pte_t *pbase, *tmp;
	struct page *base;
	int i, level;

#ifdef CONFIG_DEBUG_PAGEALLOC
	gfp_flags = GFP_ATOMIC;
#endif
	base = alloc_pages(gfp_flags, 0);
	if (!base)
		return -ENOMEM;

	spin_lock_irqsave(&pgd_lock, flags);
	/*
	 * Check for races, another CPU might have split this page
	 * up for us already:
	 */
	tmp = lookup_address(address, &level);
	if (tmp != kpte) {
		WARN_ON_ONCE(1);
		goto out_unlock;
	}

	address = __pa(address);
	addr = address & LARGE_PAGE_MASK;
	pbase = (pte_t *)page_address(base);
#ifdef CONFIG_X86_32
	paravirt_alloc_pt(&init_mm, page_to_pfn(base));
#endif

	for (i = 0; i < PTRS_PER_PTE; i++, addr += PAGE_SIZE)
		set_pte(&pbase[i], pfn_pte(addr >> PAGE_SHIFT, ref_prot));

	/*
	 * Install the new, split up pagetable. Important detail here:
	 *
	 * On Intel the NX bit of all levels must be cleared to make a
	 * page executable. See section 4.13.2 of Intel 64 and IA-32
	 * Architectures Software Developer's Manual).
	 */
	ref_prot = pte_pgprot(pte_mkexec(pte_clrhuge(*kpte)));
	__set_pmd_pte(kpte, address, mk_pte(base, ref_prot));
	base = NULL;

out_unlock:
	spin_unlock_irqrestore(&pgd_lock, flags);

	if (base)
		__free_pages(base, 0);

	return 0;
}

static int
__change_page_attr(unsigned long address, unsigned long pfn, pgprot_t prot)
{
	struct page *kpte_page;
	int level, err = 0;
	pte_t *kpte;

#ifdef CONFIG_X86_32
	BUG_ON(pfn > max_low_pfn);
#endif

repeat:
	kpte = lookup_address(address, &level);
	if (!kpte)
		return -EINVAL;

	kpte_page = virt_to_page(kpte);
	BUG_ON(PageLRU(kpte_page));
	BUG_ON(PageCompound(kpte_page));

	prot = static_protections(prot, address);

	if (level == PG_LEVEL_4K) {
		WARN_ON_ONCE(pgprot_val(prot) & _PAGE_PSE);
		set_pte_atomic(kpte, pfn_pte(pfn, canon_pgprot(prot)));
	} else {
		/* Clear the PSE bit for the 4k level pages ! */
		pgprot_val(prot) = pgprot_val(prot) & ~_PAGE_PSE;

		err = split_large_page(kpte, address);
		if (!err)
			goto repeat;
	}
	return err;
}

/**
 * change_page_attr_addr - Change page table attributes in linear mapping
 * @address: Virtual address in linear mapping.
 * @prot:    New page table attribute (PAGE_*)
 *
 * Change page attributes of a page in the direct mapping. This is a variant
 * of change_page_attr() that also works on memory holes that do not have
 * mem_map entry (pfn_valid() is false).
 *
 * See change_page_attr() documentation for more details.
 *
 * Modules and drivers should use the set_memory_* APIs instead.
 */

static int change_page_attr_addr(unsigned long address, pgprot_t prot)
{
	int err = 0, kernel_map = 0;
	unsigned long pfn = __pa(address) >> PAGE_SHIFT;

#ifdef CONFIG_X86_64
	if (address >= __START_KERNEL_map &&
			address < __START_KERNEL_map + KERNEL_TEXT_SIZE) {

		address = (unsigned long)__va(__pa(address));
		kernel_map = 1;
	}
#endif

	if (!kernel_map || pte_present(pfn_pte(0, prot))) {
		err = __change_page_attr(address, pfn, prot);
		if (err)
			return err;
	}

#ifdef CONFIG_X86_64
	/*
	 * Handle kernel mapping too which aliases part of
	 * lowmem:
	 */
	if (__pa(address) < KERNEL_TEXT_SIZE) {
		unsigned long addr2;
		pgprot_t prot2;

		addr2 = __START_KERNEL_map + __pa(address);
		/* Make sure the kernel mappings stay executable */
		prot2 = pte_pgprot(pte_mkexec(pfn_pte(0, prot)));
		err = __change_page_attr(addr2, pfn, prot2);
	}
#endif

	return err;
}

static int __change_page_attr_set_clr(unsigned long addr, int numpages,
				      pgprot_t mask_set, pgprot_t mask_clr)
{
	pgprot_t new_prot;
	int level;
	pte_t *pte;
	int i, ret;

	for (i = 0; i < numpages ; i++) {

		pte = lookup_address(addr, &level);
		if (!pte)
			return -EINVAL;

		new_prot = pte_pgprot(*pte);

		pgprot_val(new_prot) &= ~pgprot_val(mask_clr);
		pgprot_val(new_prot) |= pgprot_val(mask_set);

		ret = change_page_attr_addr(addr, new_prot);
		if (ret)
			return ret;
		addr += PAGE_SIZE;
	}

	return 0;
}

static int change_page_attr_set_clr(unsigned long addr, int numpages,
				    pgprot_t mask_set, pgprot_t mask_clr)
{
	int ret = __change_page_attr_set_clr(addr, numpages, mask_set,
					     mask_clr);

	/*
	 * On success we use clflush, when the CPU supports it to
	 * avoid the wbindv. If the CPU does not support it and in the
	 * error case we fall back to cpa_flush_all (which uses
	 * wbindv):
	 */
	if (!ret && cpu_has_clflush)
		cpa_flush_range(addr, numpages);
	else
		cpa_flush_all();

	return ret;
}

static inline int change_page_attr_set(unsigned long addr, int numpages,
				       pgprot_t mask)
{
	return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0));
}

static inline int change_page_attr_clear(unsigned long addr, int numpages,
					 pgprot_t mask)
{
	return __change_page_attr_set_clr(addr, numpages, __pgprot(0), mask);

}

int set_memory_uc(unsigned long addr, int numpages)
{
	return change_page_attr_set(addr, numpages,
				    __pgprot(_PAGE_PCD | _PAGE_PWT));
}
EXPORT_SYMBOL(set_memory_uc);

int set_memory_wb(unsigned long addr, int numpages)
{
	return change_page_attr_clear(addr, numpages,
				      __pgprot(_PAGE_PCD | _PAGE_PWT));
}
EXPORT_SYMBOL(set_memory_wb);

int set_memory_x(unsigned long addr, int numpages)
{
	return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_NX));
}
EXPORT_SYMBOL(set_memory_x);

int set_memory_nx(unsigned long addr, int numpages)
{
	return change_page_attr_set(addr, numpages, __pgprot(_PAGE_NX));
}
EXPORT_SYMBOL(set_memory_nx);

int set_memory_ro(unsigned long addr, int numpages)
{
	return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_RW));
}

int set_memory_rw(unsigned long addr, int numpages)
{
	return change_page_attr_set(addr, numpages, __pgprot(_PAGE_RW));
}

int set_memory_np(unsigned long addr, int numpages)
{
	return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_PRESENT));
}

int set_pages_uc(struct page *page, int numpages)
{
	unsigned long addr = (unsigned long)page_address(page);

	return set_memory_uc(addr, numpages);
}
EXPORT_SYMBOL(set_pages_uc);

int set_pages_wb(struct page *page, int numpages)
{
	unsigned long addr = (unsigned long)page_address(page);

	return set_memory_wb(addr, numpages);
}
EXPORT_SYMBOL(set_pages_wb);

int set_pages_x(struct page *page, int numpages)
{
	unsigned long addr = (unsigned long)page_address(page);

	return set_memory_x(addr, numpages);
}
EXPORT_SYMBOL(set_pages_x);

int set_pages_nx(struct page *page, int numpages)
{
	unsigned long addr = (unsigned long)page_address(page);

	return set_memory_nx(addr, numpages);
}
EXPORT_SYMBOL(set_pages_nx);

int set_pages_ro(struct page *page, int numpages)
{
	unsigned long addr = (unsigned long)page_address(page);

	return set_memory_ro(addr, numpages);
}

int set_pages_rw(struct page *page, int numpages)
{
	unsigned long addr = (unsigned long)page_address(page);

	return set_memory_rw(addr, numpages);
}


#if defined(CONFIG_DEBUG_PAGEALLOC) || defined(CONFIG_CPA_DEBUG)
static inline int __change_page_attr_set(unsigned long addr, int numpages,
					 pgprot_t mask)
{
	return __change_page_attr_set_clr(addr, numpages, mask, __pgprot(0));
}

static inline int __change_page_attr_clear(unsigned long addr, int numpages,
					   pgprot_t mask)
{
	return __change_page_attr_set_clr(addr, numpages, __pgprot(0), mask);
}
#endif

#ifdef CONFIG_DEBUG_PAGEALLOC

static int __set_pages_p(struct page *page, int numpages)
{
	unsigned long addr = (unsigned long)page_address(page);

	return __change_page_attr_set(addr, numpages,
				      __pgprot(_PAGE_PRESENT | _PAGE_RW));
}

static int __set_pages_np(struct page *page, int numpages)
{
	unsigned long addr = (unsigned long)page_address(page);

	return __change_page_attr_clear(addr, numpages,
					__pgprot(_PAGE_PRESENT));
}

void kernel_map_pages(struct page *page, int numpages, int enable)
{
	if (PageHighMem(page))
		return;
	if (!enable) {
		debug_check_no_locks_freed(page_address(page),
					   numpages * PAGE_SIZE);
	}

	/*
	 * If page allocator is not up yet then do not call c_p_a():
	 */
	if (!debug_pagealloc_enabled)
		return;

	/*
	 * The return value is ignored - the calls cannot fail,
	 * large pages are disabled at boot time:
	 */
	if (enable)
		__set_pages_p(page, numpages);
	else
		__set_pages_np(page, numpages);

	/*
	 * We should perform an IPI and flush all tlbs,
	 * but that can deadlock->flush only current cpu:
	 */
	__flush_tlb_all();
}
#endif

/*
 * The testcases use internal knowledge of the implementation that shouldn't
 * be exposed to the rest of the kernel. Include these directly here.
 */
#ifdef CONFIG_CPA_DEBUG
#include "pageattr-test.c"
#endif
Commit	Line	Data
9f4c815c IM	1	/*
9f4c815c IM	2	* Copyright 2002 Andi Kleen, SuSE Labs.
1da177e4	3	* Thanks to Ben LaHaise for precious feedback.
9f4c815c	4	*/
1da177e4	5	#include <linux/highmem.h>
8192206d	6	#include <linux/bootmem.h>
1da177e4	7	#include <linux/module.h>
9f4c815c	8	#include <linux/sched.h>
1da177e4	9	#include <linux/slab.h>
9f4c815c IM	10	#include <linux/mm.h>
9f4c815c IM	11
950f9d95	12	#include <asm/e820.h>
1da177e4 LT	13	#include <asm/processor.h>
1da177e4 LT	14	#include <asm/tlbflush.h>
f8af095d	15	#include <asm/sections.h>
9f4c815c IM	16	#include <asm/uaccess.h>
9f4c815c IM	17	#include <asm/pgalloc.h>
1da177e4	18
ed724be6 AV	19	static inline int
ed724be6 AV	20	within(unsigned long addr, unsigned long start, unsigned long end)
687c4825	21	{
ed724be6 AV	22	return addr >= start && addr < end;
	23	}
	24
d7c8f21a TG	25	/*
	26	* Flushing functions
	27	*/
cd8ddf1a TG	28
	29
	30	/**
	31	* clflush_cache_range - flush a cache range with clflush
	32	* @addr: virtual start address
	33	* @size: number of bytes to flush
	34	*
	35	* clflush is an unordered instruction which needs fencing with mfence
	36	* to avoid ordering issues.
	37	*/
d7c8f21a TG	38	void clflush_cache_range(void *addr, int size)
	39	{
	40	int i;
	41
cd8ddf1a	42	mb();
d7c8f21a TG	43	for (i = 0; i < size; i += boot_cpu_data.x86_clflush_size)
d7c8f21a TG	44	clflush(addr+i);
cd8ddf1a	45	mb();
d7c8f21a TG	46	}
d7c8f21a TG	47
af1e6844	48	static void __cpa_flush_all(void *arg)
d7c8f21a TG	49	{
	50	/*
	51	* Flush all to work around Errata in early athlons regarding
	52	* large page flushing.
	53	*/
	54	__flush_tlb_all();
	55
	56	if (boot_cpu_data.x86_model >= 4)
	57	wbinvd();
	58	}
	59
af1e6844	60	static void cpa_flush_all(void)
d7c8f21a TG	61	{
	62	BUG_ON(irqs_disabled());
	63
af1e6844	64	on_each_cpu(__cpa_flush_all, NULL, 1, 1);
d7c8f21a TG	65	}
d7c8f21a TG	66
57a6a46a TG	67	static void __cpa_flush_range(void *arg)
57a6a46a TG	68	{
57a6a46a TG	69	/*
	70	* We could optimize that further and do individual per page
	71	* tlb invalidates for a low number of pages. Caveat: we must
	72	* flush the high aliases on 64bit as well.
	73	*/
	74	__flush_tlb_all();
57a6a46a TG	75	}
	76
	77	static void cpa_flush_range(unsigned long addr, int numpages)
	78	{
57a6a46a TG	79	BUG_ON(irqs_disabled());
57a6a46a TG	80
3b233e52	81	on_each_cpu(__cpa_flush_range, NULL, 1, 1);
57a6a46a	82
3b233e52 TG	83	/*
	84	* We only need to flush on one CPU,
	85	* clflush is a MESI-coherent instruction that
	86	* will cause all other CPUs to flush the same
	87	* cachelines:
	88	*/
	89	clflush_cache_range((void ) addr, numpages PAGE_SIZE);
57a6a46a TG	90	}
57a6a46a TG	91
ed724be6 AV	92	/*
	93	* Certain areas of memory on x86 require very specific protection flags,
	94	* for example the BIOS area or kernel text. Callers don't always get this
	95	* right (again, ioremap() on BIOS memory is not uncommon) so this function
	96	* checks and fixes these known static required protection bits.
	97	*/
	98	static inline pgprot_t static_protections(pgprot_t prot, unsigned long address)
	99	{
	100	pgprot_t forbidden = __pgprot(0);
	101
687c4825	102	/*
ed724be6 AV	103	* The BIOS area between 640k and 1Mb needs to be executable for
ed724be6 AV	104	* PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
687c4825	105	*/
ed724be6 AV	106	if (within(__pa(address), BIOS_BEGIN, BIOS_END))
	107	pgprot_val(forbidden) \|= _PAGE_NX;
	108
	109	/*
	110	* The kernel text needs to be executable for obvious reasons
	111	* Does not cover __inittext since that is gone later on
	112	*/
	113	if (within(address, (unsigned long)_text, (unsigned long)_etext))
	114	pgprot_val(forbidden) \|= _PAGE_NX;
	115
	116	#ifdef CONFIG_DEBUG_RODATA
	117	/* The .rodata section needs to be read-only */
	118	if (within(address, (unsigned long)__start_rodata,
	119	(unsigned long)__end_rodata))
	120	pgprot_val(forbidden) \|= _PAGE_RW;
	121	#endif
	122
	123	prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
687c4825 IM	124
	125	return prot;
	126	}
	127
f0646e43	128	pte_t lookup_address(unsigned long address, int level)
9f4c815c	129	{
1da177e4 LT	130	pgd_t *pgd = pgd_offset_k(address);
	131	pud_t *pud;
	132	pmd_t *pmd;
9f4c815c	133
30551bb3 TG	134	*level = PG_LEVEL_NONE;
30551bb3 TG	135
1da177e4 LT	136	if (pgd_none(*pgd))
	137	return NULL;
	138	pud = pud_offset(pgd, address);
	139	if (pud_none(*pud))
	140	return NULL;
	141	pmd = pmd_offset(pud, address);
	142	if (pmd_none(*pmd))
	143	return NULL;
30551bb3 TG	144
30551bb3 TG	145	*level = PG_LEVEL_2M;
1da177e4 LT	146	if (pmd_large(*pmd))
1da177e4 LT	147	return (pte_t *)pmd;
1da177e4	148
30551bb3	149	*level = PG_LEVEL_4K;
9f4c815c IM	150	return pte_offset_kernel(pmd, address);
	151	}
	152
9a3dc780	153	static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
9f4c815c	154	{
9f4c815c IM	155	/* change init_mm */
9f4c815c IM	156	set_pte_atomic(kpte, pte);
44af6c41	157	#ifdef CONFIG_X86_32
e4b71dcf	158	if (!SHARED_KERNEL_PMD) {
44af6c41 IM	159	struct page *page;
	160
	161	for (page = pgd_list; page; page = (struct page *)page->index) {
	162	pgd_t *pgd;
	163	pud_t *pud;
	164	pmd_t *pmd;
	165
	166	pgd = (pgd_t *)page_address(page) + pgd_index(address);
	167	pud = pud_offset(pgd, address);
	168	pmd = pmd_offset(pud, address);
	169	set_pte_atomic((pte_t *)pmd, pte);
	170	}
1da177e4	171	}
44af6c41	172	#endif
1da177e4 LT	173	}
1da177e4 LT	174
7afe15b9	175	static int split_large_page(pte_t *kpte, unsigned long address)
bb5c2dbd	176	{
7afe15b9	177	pgprot_t ref_prot = pte_pgprot(pte_clrhuge(*kpte));
12d6f21e	178	gfp_t gfp_flags = GFP_KERNEL;
9a3dc780	179	unsigned long flags;
bb5c2dbd IM	180	unsigned long addr;
	181	pte_t pbase, tmp;
	182	struct page *base;
7afe15b9	183	int i, level;
bb5c2dbd	184
12d6f21e IM	185	#ifdef CONFIG_DEBUG_PAGEALLOC
	186	gfp_flags = GFP_ATOMIC;
	187	#endif
	188	base = alloc_pages(gfp_flags, 0);
bb5c2dbd IM	189	if (!base)
	190	return -ENOMEM;
	191
9a3dc780	192	spin_lock_irqsave(&pgd_lock, flags);
bb5c2dbd IM	193	/*
	194	* Check for races, another CPU might have split this page
	195	* up for us already:
	196	*/
	197	tmp = lookup_address(address, &level);
5508a748 IM	198	if (tmp != kpte) {
5508a748 IM	199	WARN_ON_ONCE(1);
bb5c2dbd	200	goto out_unlock;
5508a748	201	}
bb5c2dbd IM	202
	203	address = __pa(address);
	204	addr = address & LARGE_PAGE_MASK;
	205	pbase = (pte_t *)page_address(base);
44af6c41	206	#ifdef CONFIG_X86_32
bb5c2dbd	207	paravirt_alloc_pt(&init_mm, page_to_pfn(base));
44af6c41	208	#endif
bb5c2dbd IM	209
	210	for (i = 0; i < PTRS_PER_PTE; i++, addr += PAGE_SIZE)
	211	set_pte(&pbase[i], pfn_pte(addr >> PAGE_SHIFT, ref_prot));
	212
	213	/*
4c881ca1 HY	214	* Install the new, split up pagetable. Important detail here:
	215	*
	216	* On Intel the NX bit of all levels must be cleared to make a
	217	* page executable. See section 4.13.2 of Intel 64 and IA-32
	218	* Architectures Software Developer's Manual).
bb5c2dbd	219	*/
4c881ca1	220	ref_prot = pte_pgprot(pte_mkexec(pte_clrhuge(*kpte)));
9a3dc780	221	__set_pmd_pte(kpte, address, mk_pte(base, ref_prot));
bb5c2dbd IM	222	base = NULL;
	223
	224	out_unlock:
9a3dc780	225	spin_unlock_irqrestore(&pgd_lock, flags);
bb5c2dbd IM	226
	227	if (base)
	228	__free_pages(base, 0);
	229
	230	return 0;
	231	}
	232
44af6c41	233	static int
8192206d	234	__change_page_attr(unsigned long address, unsigned long pfn, pgprot_t prot)
9f4c815c	235	{
1da177e4	236	struct page *kpte_page;
bb5c2dbd	237	int level, err = 0;
9f4c815c	238	pte_t *kpte;
1da177e4	239
8192206d IM	240	#ifdef CONFIG_X86_32
	241	BUG_ON(pfn > max_low_pfn);
	242	#endif
1da177e4	243
97f99fed	244	repeat:
f0646e43	245	kpte = lookup_address(address, &level);
1da177e4 LT	246	if (!kpte)
1da177e4 LT	247	return -EINVAL;
9f4c815c	248
1da177e4	249	kpte_page = virt_to_page(kpte);
65d2f0bc AK	250	BUG_ON(PageLRU(kpte_page));
	251	BUG_ON(PageCompound(kpte_page));
	252
ed724be6	253	prot = static_protections(prot, address);
65d2f0bc	254
30551bb3	255	if (level == PG_LEVEL_4K) {
a72a08a4	256	WARN_ON_ONCE(pgprot_val(prot) & _PAGE_PSE);
8192206d	257	set_pte_atomic(kpte, pfn_pte(pfn, canon_pgprot(prot)));
78c94aba	258	} else {
a72a08a4 TG	259	/* Clear the PSE bit for the 4k level pages ! */
	260	pgprot_val(prot) = pgprot_val(prot) & ~_PAGE_PSE;
	261
7afe15b9	262	err = split_large_page(kpte, address);
bb5c2dbd IM	263	if (!err)
bb5c2dbd IM	264	goto repeat;
1da177e4	265	}
bb5c2dbd	266	return err;
9f4c815c	267	}
1da177e4	268
44af6c41 IM	269	/**
	270	* change_page_attr_addr - Change page table attributes in linear mapping
	271	* @address: Virtual address in linear mapping.
44af6c41	272	* @prot: New page table attribute (PAGE_*)
1da177e4	273	*
44af6c41 IM	274	* Change page attributes of a page in the direct mapping. This is a variant
	275	* of change_page_attr() that also works on memory holes that do not have
	276	* mem_map entry (pfn_valid() is false).
9f4c815c	277	*
44af6c41	278	* See change_page_attr() documentation for more details.
75cbade8 AV	279	*
75cbade8 AV	280	* Modules and drivers should use the set_memory_* APIs instead.
1da177e4	281	*/
44af6c41	282
488fd995	283	static int change_page_attr_addr(unsigned long address, pgprot_t prot)
1da177e4	284	{
488fd995 AV	285	int err = 0, kernel_map = 0;
488fd995 AV	286	unsigned long pfn = __pa(address) >> PAGE_SHIFT;
44af6c41 IM	287
	288	#ifdef CONFIG_X86_64
	289	if (address >= __START_KERNEL_map &&
	290	address < __START_KERNEL_map + KERNEL_TEXT_SIZE) {
1da177e4	291
44af6c41 IM	292	address = (unsigned long)__va(__pa(address));
	293	kernel_map = 1;
	294	}
	295	#endif
	296
488fd995 AV	297	if (!kernel_map \|\| pte_present(pfn_pte(0, prot))) {
	298	err = __change_page_attr(address, pfn, prot);
	299	if (err)
	300	return err;
	301	}
44af6c41	302
44af6c41	303	#ifdef CONFIG_X86_64
488fd995 AV	304	/*
	305	* Handle kernel mapping too which aliases part of
	306	* lowmem:
	307	*/
	308	if (__pa(address) < KERNEL_TEXT_SIZE) {
	309	unsigned long addr2;
	310	pgprot_t prot2;
	311
	312	addr2 = __START_KERNEL_map + __pa(address);
	313	/* Make sure the kernel mappings stay executable */
	314	prot2 = pte_pgprot(pte_mkexec(pfn_pte(0, prot)));
	315	err = __change_page_attr(addr2, pfn, prot2);
9f4c815c	316	}
488fd995	317	#endif
9f4c815c	318
1da177e4 LT	319	return err;
	320	}
	321
ff31452b TG	322	static int __change_page_attr_set_clr(unsigned long addr, int numpages,
	323	pgprot_t mask_set, pgprot_t mask_clr)
	324	{
	325	pgprot_t new_prot;
	326	int level;
	327	pte_t *pte;
	328	int i, ret;
	329
	330	for (i = 0; i < numpages ; i++) {
	331
	332	pte = lookup_address(addr, &level);
	333	if (!pte)
	334	return -EINVAL;
	335
	336	new_prot = pte_pgprot(*pte);
	337
	338	pgprot_val(new_prot) &= ~pgprot_val(mask_clr);
	339	pgprot_val(new_prot) \|= pgprot_val(mask_set);
	340
	341	ret = change_page_attr_addr(addr, new_prot);
	342	if (ret)
	343	return ret;
	344	addr += PAGE_SIZE;
	345	}
	346
	347	return 0;
	348	}
	349
	350	static int change_page_attr_set_clr(unsigned long addr, int numpages,
	351	pgprot_t mask_set, pgprot_t mask_clr)
	352	{
	353	int ret = __change_page_attr_set_clr(addr, numpages, mask_set,
	354	mask_clr);
	355
57a6a46a TG	356	/*
	357	* On success we use clflush, when the CPU supports it to
	358	* avoid the wbindv. If the CPU does not support it and in the
af1e6844	359	* error case we fall back to cpa_flush_all (which uses
57a6a46a TG	360	* wbindv):
	361	*/
	362	if (!ret && cpu_has_clflush)
	363	cpa_flush_range(addr, numpages);
	364	else
af1e6844	365	cpa_flush_all();
ff31452b TG	366
	367	return ret;
	368	}
	369
56744546 TG	370	static inline int change_page_attr_set(unsigned long addr, int numpages,
56744546 TG	371	pgprot_t mask)
75cbade8	372	{
56744546	373	return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0));
75cbade8 AV	374	}
75cbade8 AV	375
56744546 TG	376	static inline int change_page_attr_clear(unsigned long addr, int numpages,
56744546 TG	377	pgprot_t mask)
72932c7a	378	{
56744546	379	return __change_page_attr_set_clr(addr, numpages, __pgprot(0), mask);
72932c7a TG	380
	381	}
	382
	383	int set_memory_uc(unsigned long addr, int numpages)
	384	{
	385	return change_page_attr_set(addr, numpages,
	386	__pgprot(_PAGE_PCD \| _PAGE_PWT));
75cbade8 AV	387	}
	388	EXPORT_SYMBOL(set_memory_uc);
	389
	390	int set_memory_wb(unsigned long addr, int numpages)
	391	{
72932c7a TG	392	return change_page_attr_clear(addr, numpages,
72932c7a TG	393	__pgprot(_PAGE_PCD \| _PAGE_PWT));
75cbade8 AV	394	}
	395	EXPORT_SYMBOL(set_memory_wb);
	396
	397	int set_memory_x(unsigned long addr, int numpages)
	398	{
72932c7a	399	return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_NX));
75cbade8 AV	400	}
	401	EXPORT_SYMBOL(set_memory_x);
	402
	403	int set_memory_nx(unsigned long addr, int numpages)
	404	{
72932c7a	405	return change_page_attr_set(addr, numpages, __pgprot(_PAGE_NX));
75cbade8 AV	406	}
	407	EXPORT_SYMBOL(set_memory_nx);
	408
	409	int set_memory_ro(unsigned long addr, int numpages)
	410	{
72932c7a	411	return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_RW));
75cbade8	412	}
75cbade8 AV	413
	414	int set_memory_rw(unsigned long addr, int numpages)
	415	{
72932c7a	416	return change_page_attr_set(addr, numpages, __pgprot(_PAGE_RW));
75cbade8	417	}
f62d0f00 IM	418
	419	int set_memory_np(unsigned long addr, int numpages)
	420	{
72932c7a	421	return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_PRESENT));
f62d0f00	422	}
75cbade8 AV	423
	424	int set_pages_uc(struct page *page, int numpages)
	425	{
	426	unsigned long addr = (unsigned long)page_address(page);
75cbade8	427
d7c8f21a	428	return set_memory_uc(addr, numpages);
75cbade8 AV	429	}
	430	EXPORT_SYMBOL(set_pages_uc);
	431
	432	int set_pages_wb(struct page *page, int numpages)
	433	{
	434	unsigned long addr = (unsigned long)page_address(page);
75cbade8	435
d7c8f21a	436	return set_memory_wb(addr, numpages);
75cbade8 AV	437	}
	438	EXPORT_SYMBOL(set_pages_wb);
	439
	440	int set_pages_x(struct page *page, int numpages)
	441	{
	442	unsigned long addr = (unsigned long)page_address(page);
75cbade8	443
d7c8f21a	444	return set_memory_x(addr, numpages);
75cbade8 AV	445	}
	446	EXPORT_SYMBOL(set_pages_x);
	447
	448	int set_pages_nx(struct page *page, int numpages)
	449	{
	450	unsigned long addr = (unsigned long)page_address(page);
75cbade8	451
d7c8f21a	452	return set_memory_nx(addr, numpages);
75cbade8 AV	453	}
	454	EXPORT_SYMBOL(set_pages_nx);
	455
	456	int set_pages_ro(struct page *page, int numpages)
	457	{
	458	unsigned long addr = (unsigned long)page_address(page);
75cbade8	459
d7c8f21a	460	return set_memory_ro(addr, numpages);
75cbade8	461	}
75cbade8 AV	462
	463	int set_pages_rw(struct page *page, int numpages)
	464	{
	465	unsigned long addr = (unsigned long)page_address(page);
e81d5dc4	466
d7c8f21a	467	return set_memory_rw(addr, numpages);
78c94aba IM	468	}
78c94aba IM	469
1da177e4	470
56744546 TG	471	#if defined(CONFIG_DEBUG_PAGEALLOC) \|\| defined(CONFIG_CPA_DEBUG)
	472	static inline int __change_page_attr_set(unsigned long addr, int numpages,
	473	pgprot_t mask)
	474	{
	475	return __change_page_attr_set_clr(addr, numpages, mask, __pgprot(0));
	476	}
	477
	478	static inline int __change_page_attr_clear(unsigned long addr, int numpages,
	479	pgprot_t mask)
	480	{
	481	return __change_page_attr_set_clr(addr, numpages, __pgprot(0), mask);
	482	}
	483	#endif
	484
1da177e4	485	#ifdef CONFIG_DEBUG_PAGEALLOC
f62d0f00 IM	486
	487	static int __set_pages_p(struct page *page, int numpages)
	488	{
	489	unsigned long addr = (unsigned long)page_address(page);
72932c7a TG	490
	491	return __change_page_attr_set(addr, numpages,
	492	__pgprot(_PAGE_PRESENT \| _PAGE_RW));
f62d0f00 IM	493	}
	494
	495	static int __set_pages_np(struct page *page, int numpages)
	496	{
	497	unsigned long addr = (unsigned long)page_address(page);
72932c7a TG	498
	499	return __change_page_attr_clear(addr, numpages,
	500	__pgprot(_PAGE_PRESENT));
f62d0f00 IM	501	}
f62d0f00 IM	502
1da177e4 LT	503	void kernel_map_pages(struct page *page, int numpages, int enable)
	504	{
	505	if (PageHighMem(page))
	506	return;
9f4c815c	507	if (!enable) {
f9b8404c IM	508	debug_check_no_locks_freed(page_address(page),
f9b8404c IM	509	numpages * PAGE_SIZE);
9f4c815c	510	}
de5097c2	511
12d6f21e IM	512	/*
	513	* If page allocator is not up yet then do not call c_p_a():
	514	*/
	515	if (!debug_pagealloc_enabled)
	516	return;
	517
9f4c815c	518	/*
e4b71dcf IM	519	* The return value is ignored - the calls cannot fail,
e4b71dcf IM	520	* large pages are disabled at boot time:
1da177e4	521	*/
f62d0f00 IM	522	if (enable)
	523	__set_pages_p(page, numpages);
	524	else
	525	__set_pages_np(page, numpages);
9f4c815c IM	526
9f4c815c IM	527	/*
e4b71dcf IM	528	* We should perform an IPI and flush all tlbs,
e4b71dcf IM	529	* but that can deadlock->flush only current cpu:
1da177e4 LT	530	*/
	531	__flush_tlb_all();
	532	}
	533	#endif
d1028a15 AV	534
	535	/*
	536	* The testcases use internal knowledge of the implementation that shouldn't
	537	* be exposed to the rest of the kernel. Include these directly here.
	538	*/
	539	#ifdef CONFIG_CPA_DEBUG
	540	#include "pageattr-test.c"
	541	#endif