Commit | Line | Data |
---|---|---|
9f4c815c IM |
1 | /* |
2 | * Copyright 2002 Andi Kleen, SuSE Labs. | |
1da177e4 | 3 | * Thanks to Ben LaHaise for precious feedback. |
9f4c815c | 4 | */ |
1da177e4 | 5 | #include <linux/highmem.h> |
8192206d | 6 | #include <linux/bootmem.h> |
1da177e4 | 7 | #include <linux/module.h> |
9f4c815c | 8 | #include <linux/sched.h> |
1da177e4 | 9 | #include <linux/slab.h> |
9f4c815c IM |
10 | #include <linux/mm.h> |
11 | ||
1da177e4 LT |
12 | #include <asm/processor.h> |
13 | #include <asm/tlbflush.h> | |
f8af095d | 14 | #include <asm/sections.h> |
9f4c815c IM |
15 | #include <asm/uaccess.h> |
16 | #include <asm/pgalloc.h> | |
1da177e4 | 17 | |
687c4825 | 18 | /* |
ed724be6 | 19 | * We must allow the BIOS range to be executable: |
687c4825 IM |
20 | */ |
21 | #define BIOS_BEGIN 0x000a0000 | |
22 | #define BIOS_END 0x00100000 | |
23 | ||
ed724be6 AV |
24 | static inline int |
25 | within(unsigned long addr, unsigned long start, unsigned long end) | |
687c4825 | 26 | { |
ed724be6 AV |
27 | return addr >= start && addr < end; |
28 | } | |
29 | ||
30 | /* | |
31 | * Certain areas of memory on x86 require very specific protection flags, | |
32 | * for example the BIOS area or kernel text. Callers don't always get this | |
33 | * right (again, ioremap() on BIOS memory is not uncommon) so this function | |
34 | * checks and fixes these known static required protection bits. | |
35 | */ | |
36 | static inline pgprot_t static_protections(pgprot_t prot, unsigned long address) | |
37 | { | |
38 | pgprot_t forbidden = __pgprot(0); | |
39 | ||
687c4825 | 40 | /* |
ed724be6 AV |
41 | * The BIOS area between 640k and 1Mb needs to be executable for |
42 | * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support. | |
687c4825 | 43 | */ |
ed724be6 AV |
44 | if (within(__pa(address), BIOS_BEGIN, BIOS_END)) |
45 | pgprot_val(forbidden) |= _PAGE_NX; | |
46 | ||
47 | /* | |
48 | * The kernel text needs to be executable for obvious reasons | |
49 | * Does not cover __inittext since that is gone later on | |
50 | */ | |
51 | if (within(address, (unsigned long)_text, (unsigned long)_etext)) | |
52 | pgprot_val(forbidden) |= _PAGE_NX; | |
53 | ||
54 | #ifdef CONFIG_DEBUG_RODATA | |
55 | /* The .rodata section needs to be read-only */ | |
56 | if (within(address, (unsigned long)__start_rodata, | |
57 | (unsigned long)__end_rodata)) | |
58 | pgprot_val(forbidden) |= _PAGE_RW; | |
59 | #endif | |
60 | ||
61 | prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden)); | |
687c4825 IM |
62 | |
63 | return prot; | |
64 | } | |
65 | ||
f0646e43 | 66 | pte_t *lookup_address(unsigned long address, int *level) |
9f4c815c | 67 | { |
1da177e4 LT |
68 | pgd_t *pgd = pgd_offset_k(address); |
69 | pud_t *pud; | |
70 | pmd_t *pmd; | |
9f4c815c | 71 | |
30551bb3 TG |
72 | *level = PG_LEVEL_NONE; |
73 | ||
1da177e4 LT |
74 | if (pgd_none(*pgd)) |
75 | return NULL; | |
76 | pud = pud_offset(pgd, address); | |
77 | if (pud_none(*pud)) | |
78 | return NULL; | |
79 | pmd = pmd_offset(pud, address); | |
80 | if (pmd_none(*pmd)) | |
81 | return NULL; | |
30551bb3 TG |
82 | |
83 | *level = PG_LEVEL_2M; | |
1da177e4 LT |
84 | if (pmd_large(*pmd)) |
85 | return (pte_t *)pmd; | |
1da177e4 | 86 | |
30551bb3 | 87 | *level = PG_LEVEL_4K; |
9f4c815c IM |
88 | return pte_offset_kernel(pmd, address); |
89 | } | |
90 | ||
9a3dc780 | 91 | static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) |
9f4c815c | 92 | { |
9f4c815c IM |
93 | /* change init_mm */ |
94 | set_pte_atomic(kpte, pte); | |
44af6c41 | 95 | #ifdef CONFIG_X86_32 |
e4b71dcf | 96 | if (!SHARED_KERNEL_PMD) { |
44af6c41 IM |
97 | struct page *page; |
98 | ||
99 | for (page = pgd_list; page; page = (struct page *)page->index) { | |
100 | pgd_t *pgd; | |
101 | pud_t *pud; | |
102 | pmd_t *pmd; | |
103 | ||
104 | pgd = (pgd_t *)page_address(page) + pgd_index(address); | |
105 | pud = pud_offset(pgd, address); | |
106 | pmd = pmd_offset(pud, address); | |
107 | set_pte_atomic((pte_t *)pmd, pte); | |
108 | } | |
1da177e4 | 109 | } |
44af6c41 | 110 | #endif |
1da177e4 LT |
111 | } |
112 | ||
7afe15b9 | 113 | static int split_large_page(pte_t *kpte, unsigned long address) |
bb5c2dbd | 114 | { |
7afe15b9 | 115 | pgprot_t ref_prot = pte_pgprot(pte_clrhuge(*kpte)); |
12d6f21e | 116 | gfp_t gfp_flags = GFP_KERNEL; |
9a3dc780 | 117 | unsigned long flags; |
bb5c2dbd IM |
118 | unsigned long addr; |
119 | pte_t *pbase, *tmp; | |
120 | struct page *base; | |
7afe15b9 | 121 | int i, level; |
bb5c2dbd | 122 | |
12d6f21e IM |
123 | #ifdef CONFIG_DEBUG_PAGEALLOC |
124 | gfp_flags = GFP_ATOMIC; | |
125 | #endif | |
126 | base = alloc_pages(gfp_flags, 0); | |
bb5c2dbd IM |
127 | if (!base) |
128 | return -ENOMEM; | |
129 | ||
9a3dc780 | 130 | spin_lock_irqsave(&pgd_lock, flags); |
bb5c2dbd IM |
131 | /* |
132 | * Check for races, another CPU might have split this page | |
133 | * up for us already: | |
134 | */ | |
135 | tmp = lookup_address(address, &level); | |
5508a748 IM |
136 | if (tmp != kpte) { |
137 | WARN_ON_ONCE(1); | |
bb5c2dbd | 138 | goto out_unlock; |
5508a748 | 139 | } |
bb5c2dbd IM |
140 | |
141 | address = __pa(address); | |
142 | addr = address & LARGE_PAGE_MASK; | |
143 | pbase = (pte_t *)page_address(base); | |
44af6c41 | 144 | #ifdef CONFIG_X86_32 |
bb5c2dbd | 145 | paravirt_alloc_pt(&init_mm, page_to_pfn(base)); |
44af6c41 | 146 | #endif |
bb5c2dbd IM |
147 | |
148 | for (i = 0; i < PTRS_PER_PTE; i++, addr += PAGE_SIZE) | |
149 | set_pte(&pbase[i], pfn_pte(addr >> PAGE_SHIFT, ref_prot)); | |
150 | ||
151 | /* | |
4c881ca1 HY |
152 | * Install the new, split up pagetable. Important detail here: |
153 | * | |
154 | * On Intel the NX bit of all levels must be cleared to make a | |
155 | * page executable. See section 4.13.2 of Intel 64 and IA-32 | |
156 | * Architectures Software Developer's Manual). | |
bb5c2dbd | 157 | */ |
4c881ca1 | 158 | ref_prot = pte_pgprot(pte_mkexec(pte_clrhuge(*kpte))); |
9a3dc780 | 159 | __set_pmd_pte(kpte, address, mk_pte(base, ref_prot)); |
bb5c2dbd IM |
160 | base = NULL; |
161 | ||
162 | out_unlock: | |
9a3dc780 | 163 | spin_unlock_irqrestore(&pgd_lock, flags); |
bb5c2dbd IM |
164 | |
165 | if (base) | |
166 | __free_pages(base, 0); | |
167 | ||
168 | return 0; | |
169 | } | |
170 | ||
44af6c41 | 171 | static int |
8192206d | 172 | __change_page_attr(unsigned long address, unsigned long pfn, pgprot_t prot) |
9f4c815c | 173 | { |
1da177e4 | 174 | struct page *kpte_page; |
bb5c2dbd | 175 | int level, err = 0; |
9f4c815c | 176 | pte_t *kpte; |
1da177e4 | 177 | |
8192206d IM |
178 | #ifdef CONFIG_X86_32 |
179 | BUG_ON(pfn > max_low_pfn); | |
180 | #endif | |
1da177e4 | 181 | |
97f99fed | 182 | repeat: |
f0646e43 | 183 | kpte = lookup_address(address, &level); |
1da177e4 LT |
184 | if (!kpte) |
185 | return -EINVAL; | |
9f4c815c | 186 | |
1da177e4 | 187 | kpte_page = virt_to_page(kpte); |
65d2f0bc AK |
188 | BUG_ON(PageLRU(kpte_page)); |
189 | BUG_ON(PageCompound(kpte_page)); | |
190 | ||
ed724be6 | 191 | prot = static_protections(prot, address); |
65d2f0bc | 192 | |
30551bb3 | 193 | if (level == PG_LEVEL_4K) { |
8192206d | 194 | set_pte_atomic(kpte, pfn_pte(pfn, canon_pgprot(prot))); |
78c94aba | 195 | } else { |
7afe15b9 | 196 | err = split_large_page(kpte, address); |
bb5c2dbd IM |
197 | if (!err) |
198 | goto repeat; | |
1da177e4 | 199 | } |
bb5c2dbd | 200 | return err; |
9f4c815c | 201 | } |
1da177e4 | 202 | |
44af6c41 IM |
203 | /** |
204 | * change_page_attr_addr - Change page table attributes in linear mapping | |
205 | * @address: Virtual address in linear mapping. | |
206 | * @numpages: Number of pages to change | |
207 | * @prot: New page table attribute (PAGE_*) | |
1da177e4 | 208 | * |
44af6c41 IM |
209 | * Change page attributes of a page in the direct mapping. This is a variant |
210 | * of change_page_attr() that also works on memory holes that do not have | |
211 | * mem_map entry (pfn_valid() is false). | |
9f4c815c | 212 | * |
44af6c41 | 213 | * See change_page_attr() documentation for more details. |
75cbade8 AV |
214 | * |
215 | * Modules and drivers should use the set_memory_* APIs instead. | |
1da177e4 | 216 | */ |
44af6c41 IM |
217 | |
218 | int change_page_attr_addr(unsigned long address, int numpages, pgprot_t prot) | |
1da177e4 | 219 | { |
44af6c41 IM |
220 | int err = 0, kernel_map = 0, i; |
221 | ||
222 | #ifdef CONFIG_X86_64 | |
223 | if (address >= __START_KERNEL_map && | |
224 | address < __START_KERNEL_map + KERNEL_TEXT_SIZE) { | |
1da177e4 | 225 | |
44af6c41 IM |
226 | address = (unsigned long)__va(__pa(address)); |
227 | kernel_map = 1; | |
228 | } | |
229 | #endif | |
230 | ||
231 | for (i = 0; i < numpages; i++, address += PAGE_SIZE) { | |
232 | unsigned long pfn = __pa(address) >> PAGE_SHIFT; | |
233 | ||
234 | if (!kernel_map || pte_present(pfn_pte(0, prot))) { | |
8192206d | 235 | err = __change_page_attr(address, pfn, prot); |
44af6c41 IM |
236 | if (err) |
237 | break; | |
238 | } | |
239 | #ifdef CONFIG_X86_64 | |
240 | /* | |
241 | * Handle kernel mapping too which aliases part of | |
242 | * lowmem: | |
243 | */ | |
244 | if (__pa(address) < KERNEL_TEXT_SIZE) { | |
245 | unsigned long addr2; | |
246 | pgprot_t prot2; | |
247 | ||
248 | addr2 = __START_KERNEL_map + __pa(address); | |
249 | /* Make sure the kernel mappings stay executable */ | |
250 | prot2 = pte_pgprot(pte_mkexec(pfn_pte(0, prot))); | |
8192206d | 251 | err = __change_page_attr(addr2, pfn, prot2); |
44af6c41 IM |
252 | } |
253 | #endif | |
9f4c815c | 254 | } |
9f4c815c | 255 | |
1da177e4 LT |
256 | return err; |
257 | } | |
258 | ||
44af6c41 IM |
259 | /** |
260 | * change_page_attr - Change page table attributes in the linear mapping. | |
261 | * @page: First page to change | |
262 | * @numpages: Number of pages to change | |
263 | * @prot: New protection/caching type (PAGE_*) | |
264 | * | |
265 | * Returns 0 on success, otherwise a negated errno. | |
266 | * | |
267 | * This should be used when a page is mapped with a different caching policy | |
268 | * than write-back somewhere - some CPUs do not like it when mappings with | |
269 | * different caching policies exist. This changes the page attributes of the | |
270 | * in kernel linear mapping too. | |
271 | * | |
272 | * Caller must call global_flush_tlb() later to make the changes active. | |
273 | * | |
274 | * The caller needs to ensure that there are no conflicting mappings elsewhere | |
275 | * (e.g. in user space) * This function only deals with the kernel linear map. | |
276 | * | |
277 | * For MMIO areas without mem_map use change_page_attr_addr() instead. | |
75cbade8 AV |
278 | * |
279 | * Modules and drivers should use the set_pages_* APIs instead. | |
44af6c41 IM |
280 | */ |
281 | int change_page_attr(struct page *page, int numpages, pgprot_t prot) | |
626ab0e6 | 282 | { |
44af6c41 | 283 | unsigned long addr = (unsigned long)page_address(page); |
5508a748 | 284 | |
44af6c41 | 285 | return change_page_attr_addr(addr, numpages, prot); |
78c94aba | 286 | } |
e1271f68 | 287 | EXPORT_UNUSED_SYMBOL(change_page_attr); /* to be removed in 2.6.27 */ |
78c94aba | 288 | |
75cbade8 AV |
289 | /** |
290 | * change_page_attr_set - Change page table attributes in the linear mapping. | |
291 | * @addr: Virtual address in linear mapping. | |
292 | * @numpages: Number of pages to change | |
293 | * @prot: Protection/caching type bits to set (PAGE_*) | |
294 | * | |
295 | * Returns 0 on success, otherwise a negated errno. | |
296 | * | |
297 | * This should be used when a page is mapped with a different caching policy | |
298 | * than write-back somewhere - some CPUs do not like it when mappings with | |
299 | * different caching policies exist. This changes the page attributes of the | |
300 | * in kernel linear mapping too. | |
301 | * | |
302 | * Caller must call global_flush_tlb() later to make the changes active. | |
303 | * | |
304 | * The caller needs to ensure that there are no conflicting mappings elsewhere | |
305 | * (e.g. in user space) * This function only deals with the kernel linear map. | |
306 | * | |
307 | * This function is different from change_page_attr() in that only selected bits | |
308 | * are impacted, all other bits remain as is. | |
309 | */ | |
310 | int change_page_attr_set(unsigned long addr, int numpages, pgprot_t prot) | |
311 | { | |
312 | pgprot_t current_prot; | |
313 | int level; | |
314 | pte_t *pte; | |
315 | ||
316 | pte = lookup_address(addr, &level); | |
317 | if (pte) | |
318 | current_prot = pte_pgprot(*pte); | |
319 | else | |
320 | pgprot_val(current_prot) = 0; | |
321 | ||
322 | pgprot_val(prot) = pgprot_val(current_prot) | pgprot_val(prot); | |
323 | ||
324 | return change_page_attr_addr(addr, numpages, prot); | |
325 | } | |
326 | ||
327 | /** | |
328 | * change_page_attr_clear - Change page table attributes in the linear mapping. | |
329 | * @addr: Virtual address in linear mapping. | |
330 | * @numpages: Number of pages to change | |
331 | * @prot: Protection/caching type bits to clear (PAGE_*) | |
332 | * | |
333 | * Returns 0 on success, otherwise a negated errno. | |
334 | * | |
335 | * This should be used when a page is mapped with a different caching policy | |
336 | * than write-back somewhere - some CPUs do not like it when mappings with | |
337 | * different caching policies exist. This changes the page attributes of the | |
338 | * in kernel linear mapping too. | |
339 | * | |
340 | * Caller must call global_flush_tlb() later to make the changes active. | |
341 | * | |
342 | * The caller needs to ensure that there are no conflicting mappings elsewhere | |
343 | * (e.g. in user space) * This function only deals with the kernel linear map. | |
344 | * | |
345 | * This function is different from change_page_attr() in that only selected bits | |
346 | * are impacted, all other bits remain as is. | |
347 | */ | |
348 | int change_page_attr_clear(unsigned long addr, int numpages, pgprot_t prot) | |
349 | { | |
350 | pgprot_t current_prot; | |
351 | int level; | |
352 | pte_t *pte; | |
353 | ||
354 | pte = lookup_address(addr, &level); | |
355 | if (pte) | |
356 | current_prot = pte_pgprot(*pte); | |
357 | else | |
358 | pgprot_val(current_prot) = 0; | |
359 | ||
360 | pgprot_val(prot) = pgprot_val(current_prot) & ~pgprot_val(prot); | |
361 | ||
362 | return change_page_attr_addr(addr, numpages, prot); | |
363 | } | |
364 | ||
365 | ||
366 | ||
367 | int set_memory_uc(unsigned long addr, int numpages) | |
368 | { | |
369 | pgprot_t uncached; | |
370 | ||
371 | pgprot_val(uncached) = _PAGE_PCD | _PAGE_PWT; | |
372 | return change_page_attr_set(addr, numpages, uncached); | |
373 | } | |
374 | EXPORT_SYMBOL(set_memory_uc); | |
375 | ||
376 | int set_memory_wb(unsigned long addr, int numpages) | |
377 | { | |
378 | pgprot_t uncached; | |
379 | ||
380 | pgprot_val(uncached) = _PAGE_PCD | _PAGE_PWT; | |
381 | return change_page_attr_clear(addr, numpages, uncached); | |
382 | } | |
383 | EXPORT_SYMBOL(set_memory_wb); | |
384 | ||
385 | int set_memory_x(unsigned long addr, int numpages) | |
386 | { | |
387 | pgprot_t nx; | |
388 | ||
389 | pgprot_val(nx) = _PAGE_NX; | |
390 | return change_page_attr_clear(addr, numpages, nx); | |
391 | } | |
392 | EXPORT_SYMBOL(set_memory_x); | |
393 | ||
394 | int set_memory_nx(unsigned long addr, int numpages) | |
395 | { | |
396 | pgprot_t nx; | |
397 | ||
398 | pgprot_val(nx) = _PAGE_NX; | |
399 | return change_page_attr_set(addr, numpages, nx); | |
400 | } | |
401 | EXPORT_SYMBOL(set_memory_nx); | |
402 | ||
403 | int set_memory_ro(unsigned long addr, int numpages) | |
404 | { | |
405 | pgprot_t rw; | |
406 | ||
407 | pgprot_val(rw) = _PAGE_RW; | |
408 | return change_page_attr_clear(addr, numpages, rw); | |
409 | } | |
410 | EXPORT_SYMBOL(set_memory_ro); | |
411 | ||
412 | int set_memory_rw(unsigned long addr, int numpages) | |
413 | { | |
414 | pgprot_t rw; | |
415 | ||
416 | pgprot_val(rw) = _PAGE_RW; | |
417 | return change_page_attr_set(addr, numpages, rw); | |
418 | } | |
419 | EXPORT_SYMBOL(set_memory_rw); | |
420 | ||
421 | int set_pages_uc(struct page *page, int numpages) | |
422 | { | |
423 | unsigned long addr = (unsigned long)page_address(page); | |
424 | pgprot_t uncached; | |
425 | ||
426 | pgprot_val(uncached) = _PAGE_PCD | _PAGE_PWT; | |
427 | return change_page_attr_set(addr, numpages, uncached); | |
428 | } | |
429 | EXPORT_SYMBOL(set_pages_uc); | |
430 | ||
431 | int set_pages_wb(struct page *page, int numpages) | |
432 | { | |
433 | unsigned long addr = (unsigned long)page_address(page); | |
434 | pgprot_t uncached; | |
435 | ||
436 | pgprot_val(uncached) = _PAGE_PCD | _PAGE_PWT; | |
437 | return change_page_attr_clear(addr, numpages, uncached); | |
438 | } | |
439 | EXPORT_SYMBOL(set_pages_wb); | |
440 | ||
441 | int set_pages_x(struct page *page, int numpages) | |
442 | { | |
443 | unsigned long addr = (unsigned long)page_address(page); | |
444 | pgprot_t nx; | |
445 | ||
446 | pgprot_val(nx) = _PAGE_NX; | |
447 | return change_page_attr_clear(addr, numpages, nx); | |
448 | } | |
449 | EXPORT_SYMBOL(set_pages_x); | |
450 | ||
451 | int set_pages_nx(struct page *page, int numpages) | |
452 | { | |
453 | unsigned long addr = (unsigned long)page_address(page); | |
454 | pgprot_t nx; | |
455 | ||
456 | pgprot_val(nx) = _PAGE_NX; | |
457 | return change_page_attr_set(addr, numpages, nx); | |
458 | } | |
459 | EXPORT_SYMBOL(set_pages_nx); | |
460 | ||
461 | int set_pages_ro(struct page *page, int numpages) | |
462 | { | |
463 | unsigned long addr = (unsigned long)page_address(page); | |
464 | pgprot_t rw; | |
465 | ||
466 | pgprot_val(rw) = _PAGE_RW; | |
467 | return change_page_attr_clear(addr, numpages, rw); | |
468 | } | |
469 | EXPORT_SYMBOL(set_pages_ro); | |
470 | ||
471 | int set_pages_rw(struct page *page, int numpages) | |
472 | { | |
473 | unsigned long addr = (unsigned long)page_address(page); | |
474 | pgprot_t rw; | |
475 | ||
476 | pgprot_val(rw) = _PAGE_RW; | |
477 | return change_page_attr_set(addr, numpages, rw); | |
478 | } | |
479 | EXPORT_SYMBOL(set_pages_rw); | |
480 | ||
481 | ||
e81d5dc4 IM |
482 | void clflush_cache_range(void *addr, int size) |
483 | { | |
484 | int i; | |
485 | ||
486 | for (i = 0; i < size; i += boot_cpu_data.x86_clflush_size) | |
487 | clflush(addr+i); | |
488 | } | |
489 | ||
78c94aba IM |
490 | static void flush_kernel_map(void *arg) |
491 | { | |
492 | /* | |
493 | * Flush all to work around Errata in early athlons regarding | |
494 | * large page flushing. | |
495 | */ | |
496 | __flush_tlb_all(); | |
497 | ||
498 | if (boot_cpu_data.x86_model >= 4) | |
499 | wbinvd(); | |
500 | } | |
501 | ||
502 | void global_flush_tlb(void) | |
503 | { | |
1da177e4 LT |
504 | BUG_ON(irqs_disabled()); |
505 | ||
78c94aba | 506 | on_each_cpu(flush_kernel_map, NULL, 1, 1); |
626ab0e6 | 507 | } |
9f4c815c | 508 | EXPORT_SYMBOL(global_flush_tlb); |
1da177e4 LT |
509 | |
510 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
511 | void kernel_map_pages(struct page *page, int numpages, int enable) | |
512 | { | |
513 | if (PageHighMem(page)) | |
514 | return; | |
9f4c815c | 515 | if (!enable) { |
f9b8404c IM |
516 | debug_check_no_locks_freed(page_address(page), |
517 | numpages * PAGE_SIZE); | |
9f4c815c | 518 | } |
de5097c2 | 519 | |
12d6f21e IM |
520 | /* |
521 | * If page allocator is not up yet then do not call c_p_a(): | |
522 | */ | |
523 | if (!debug_pagealloc_enabled) | |
524 | return; | |
525 | ||
9f4c815c | 526 | /* |
e4b71dcf IM |
527 | * The return value is ignored - the calls cannot fail, |
528 | * large pages are disabled at boot time: | |
1da177e4 LT |
529 | */ |
530 | change_page_attr(page, numpages, enable ? PAGE_KERNEL : __pgprot(0)); | |
9f4c815c IM |
531 | |
532 | /* | |
e4b71dcf IM |
533 | * We should perform an IPI and flush all tlbs, |
534 | * but that can deadlock->flush only current cpu: | |
1da177e4 LT |
535 | */ |
536 | __flush_tlb_all(); | |
537 | } | |
538 | #endif |