[deliverable/linux.git] / arch / x86 / mm / pageattr.c

/*
 * Copyright 2002 Andi Kleen, SuSE Labs.
 * Thanks to Ben LaHaise for precious feedback.
 */
#include <linux/highmem.h>
#include <linux/bootmem.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/mm.h>

#include <asm/e820.h>
#include <asm/processor.h>
#include <asm/tlbflush.h>
#include <asm/sections.h>
#include <asm/uaccess.h>
#include <asm/pgalloc.h>

static inline int
within(unsigned long addr, unsigned long start, unsigned long end)
{
	return addr >= start && addr < end;
}

/*
 * Flushing functions
 */

/**
 * clflush_cache_range - flush a cache range with clflush
 * @addr:	virtual start address
 * @size:	number of bytes to flush
 *
 * clflush is an unordered instruction which needs fencing with mfence
 * to avoid ordering issues.
 */
void clflush_cache_range(void *vaddr, unsigned int size)
{
	void *vend = vaddr + size - 1;

	mb();

	for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
		clflush(vaddr);
	/*
	 * Flush any possible final partial cacheline:
	 */
	clflush(vend);

	mb();
}

static void __cpa_flush_all(void *arg)
{
	/*
	 * Flush all to work around Errata in early athlons regarding
	 * large page flushing.
	 */
	__flush_tlb_all();

	if (boot_cpu_data.x86_model >= 4)
		wbinvd();
}

static void cpa_flush_all(void)
{
	BUG_ON(irqs_disabled());

	on_each_cpu(__cpa_flush_all, NULL, 1, 1);
}

static void __cpa_flush_range(void *arg)
{
	/*
	 * We could optimize that further and do individual per page
	 * tlb invalidates for a low number of pages. Caveat: we must
	 * flush the high aliases on 64bit as well.
	 */
	__flush_tlb_all();
}

static void cpa_flush_range(unsigned long start, int numpages)
{
	unsigned int i, level;
	unsigned long addr;

	BUG_ON(irqs_disabled());
	WARN_ON(PAGE_ALIGN(start) != start);

	on_each_cpu(__cpa_flush_range, NULL, 1, 1);

	/*
	 * We only need to flush on one CPU,
	 * clflush is a MESI-coherent instruction that
	 * will cause all other CPUs to flush the same
	 * cachelines:
	 */
	for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) {
		pte_t *pte = lookup_address(addr, &level);

		/*
		 * Only flush present addresses:
		 */
		if (pte && pte_present(*pte))
			clflush_cache_range((void *) addr, PAGE_SIZE);
	}
}

#define HIGH_MAP_START	__START_KERNEL_map
#define HIGH_MAP_END	(__START_KERNEL_map + KERNEL_TEXT_SIZE)


/*
 * Converts a virtual address to a X86-64 highmap address
 */
static unsigned long virt_to_highmap(void *address)
{
#ifdef CONFIG_X86_64
	return __pa((unsigned long)address) + HIGH_MAP_START - phys_base;
#else
	return (unsigned long)address;
#endif
}

/*
 * Certain areas of memory on x86 require very specific protection flags,
 * for example the BIOS area or kernel text. Callers don't always get this
 * right (again, ioremap() on BIOS memory is not uncommon) so this function
 * checks and fixes these known static required protection bits.
 */
static inline pgprot_t static_protections(pgprot_t prot, unsigned long address)
{
	pgprot_t forbidden = __pgprot(0);

	/*
	 * The BIOS area between 640k and 1Mb needs to be executable for
	 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
	 */
	if (within(__pa(address), BIOS_BEGIN, BIOS_END))
		pgprot_val(forbidden) |= _PAGE_NX;

	/*
	 * The kernel text needs to be executable for obvious reasons
	 * Does not cover __inittext since that is gone later on
	 */
	if (within(address, (unsigned long)_text, (unsigned long)_etext))
		pgprot_val(forbidden) |= _PAGE_NX;
	/*
	 * Do the same for the x86-64 high kernel mapping
	 */
	if (within(address, virt_to_highmap(_text), virt_to_highmap(_etext)))
		pgprot_val(forbidden) |= _PAGE_NX;


#ifdef CONFIG_DEBUG_RODATA
	/* The .rodata section needs to be read-only */
	if (within(address, (unsigned long)__start_rodata,
				(unsigned long)__end_rodata))
		pgprot_val(forbidden) |= _PAGE_RW;
	/*
	 * Do the same for the x86-64 high kernel mapping
	 */
	if (within(address, virt_to_highmap(__start_rodata),
				virt_to_highmap(__end_rodata)))
		pgprot_val(forbidden) |= _PAGE_RW;
#endif

	prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));

	return prot;
}

pte_t *lookup_address(unsigned long address, int *level)
{
	pgd_t *pgd = pgd_offset_k(address);
	pud_t *pud;
	pmd_t *pmd;

	*level = PG_LEVEL_NONE;

	if (pgd_none(*pgd))
		return NULL;
	pud = pud_offset(pgd, address);
	if (pud_none(*pud))
		return NULL;
	pmd = pmd_offset(pud, address);
	if (pmd_none(*pmd))
		return NULL;

	*level = PG_LEVEL_2M;
	if (pmd_large(*pmd))
		return (pte_t *)pmd;

	*level = PG_LEVEL_4K;
	return pte_offset_kernel(pmd, address);
}

static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
{
	/* change init_mm */
	set_pte_atomic(kpte, pte);
#ifdef CONFIG_X86_32
	if (!SHARED_KERNEL_PMD) {
		struct page *page;

		list_for_each_entry(page, &pgd_list, lru) {
			pgd_t *pgd;
			pud_t *pud;
			pmd_t *pmd;

			pgd = (pgd_t *)page_address(page) + pgd_index(address);
			pud = pud_offset(pgd, address);
			pmd = pmd_offset(pud, address);
			set_pte_atomic((pte_t *)pmd, pte);
		}
	}
#endif
}

static int split_large_page(pte_t *kpte, unsigned long address)
{
	pgprot_t ref_prot = pte_pgprot(pte_clrhuge(*kpte));
	gfp_t gfp_flags = GFP_KERNEL;
	unsigned long flags;
	unsigned long addr;
	pte_t *pbase, *tmp;
	struct page *base;
	unsigned int i, level;

#ifdef CONFIG_DEBUG_PAGEALLOC
	gfp_flags = __GFP_HIGH | __GFP_NOFAIL | __GFP_NOWARN;
	gfp_flags = GFP_ATOMIC | __GFP_NOWARN;
#endif
	base = alloc_pages(gfp_flags, 0);
	if (!base)
		return -ENOMEM;

	spin_lock_irqsave(&pgd_lock, flags);
	/*
	 * Check for races, another CPU might have split this page
	 * up for us already:
	 */
	tmp = lookup_address(address, &level);
	if (tmp != kpte) {
		WARN_ON_ONCE(1);
		goto out_unlock;
	}

	address = __pa(address);
	addr = address & LARGE_PAGE_MASK;
	pbase = (pte_t *)page_address(base);
#ifdef CONFIG_X86_32
	paravirt_alloc_pt(&init_mm, page_to_pfn(base));
#endif

	for (i = 0; i < PTRS_PER_PTE; i++, addr += PAGE_SIZE)
		set_pte(&pbase[i], pfn_pte(addr >> PAGE_SHIFT, ref_prot));

	/*
	 * Install the new, split up pagetable. Important detail here:
	 *
	 * On Intel the NX bit of all levels must be cleared to make a
	 * page executable. See section 4.13.2 of Intel 64 and IA-32
	 * Architectures Software Developer's Manual).
	 */
	ref_prot = pte_pgprot(pte_mkexec(pte_clrhuge(*kpte)));
	__set_pmd_pte(kpte, address, mk_pte(base, ref_prot));
	base = NULL;

out_unlock:
	spin_unlock_irqrestore(&pgd_lock, flags);

	if (base)
		__free_pages(base, 0);

	return 0;
}

static int
__change_page_attr(unsigned long address, pgprot_t mask_set, pgprot_t mask_clr)
{
	struct page *kpte_page;
	int level, err = 0;
	pte_t *kpte;

repeat:
	kpte = lookup_address(address, &level);
	if (!kpte)
		return -EINVAL;

	kpte_page = virt_to_page(kpte);
	BUG_ON(PageLRU(kpte_page));
	BUG_ON(PageCompound(kpte_page));

	if (level == PG_LEVEL_4K) {
		pte_t new_pte, old_pte = *kpte;
		pgprot_t new_prot = pte_pgprot(old_pte);

		if(!pte_val(old_pte)) {
			WARN_ON_ONCE(1);
			return -EINVAL;
		}

		pgprot_val(new_prot) &= ~pgprot_val(mask_clr);
		pgprot_val(new_prot) |= pgprot_val(mask_set);

		new_prot = static_protections(new_prot, address);

		/*
		 * We need to keep the pfn from the existing PTE,
		 * after all we're only going to change it's attributes
		 * not the memory it points to
		 */
		new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot));
		set_pte_atomic(kpte, new_pte);
	} else {
		err = split_large_page(kpte, address);
		if (!err)
			goto repeat;
	}
	return err;
}

/**
 * change_page_attr_addr - Change page table attributes in linear mapping
 * @address: Virtual address in linear mapping.
 * @prot:    New page table attribute (PAGE_*)
 *
 * Change page attributes of a page in the direct mapping. This is a variant
 * of change_page_attr() that also works on memory holes that do not have
 * mem_map entry (pfn_valid() is false).
 *
 * See change_page_attr() documentation for more details.
 *
 * Modules and drivers should use the set_memory_* APIs instead.
 */


static int
change_page_attr_addr(unsigned long address, pgprot_t mask_set,
		      pgprot_t mask_clr)
{
	int err;

#ifdef CONFIG_X86_64
	unsigned long phys_addr = __pa(address);

	/*
	 * If we are inside the high mapped kernel range, then we
	 * fixup the low mapping first. __va() returns the virtual
	 * address in the linear mapping:
	 */
	if (within(address, HIGH_MAP_START, HIGH_MAP_END))
		address = (unsigned long) __va(phys_addr);
#endif

	err = __change_page_attr(address, mask_set, mask_clr);
	if (err)
		return err;

#ifdef CONFIG_X86_64
	/*
	 * If the physical address is inside the kernel map, we need
	 * to touch the high mapped kernel as well:
	 */
	if (within(phys_addr, 0, KERNEL_TEXT_SIZE)) {
		/*
		 * Calc the high mapping address. See __phys_addr()
		 * for the non obvious details.
		 *
		 * Note that NX and other required permissions are
		 * checked in static_protections().
		 */
		address = phys_addr + HIGH_MAP_START - phys_base;

		/*
		 * Our high aliases are imprecise, because we check
		 * everything between 0 and KERNEL_TEXT_SIZE, so do
		 * not propagate lookup failures back to users:
		 */
		__change_page_attr(address, mask_set, mask_clr);
	}
#endif
	return err;
}

static int __change_page_attr_set_clr(unsigned long addr, int numpages,
				      pgprot_t mask_set, pgprot_t mask_clr)
{
	unsigned int i;
	int ret;

	for (i = 0; i < numpages ; i++, addr += PAGE_SIZE) {
		ret = change_page_attr_addr(addr, mask_set, mask_clr);
		if (ret)
			return ret;
	}

	return 0;
}

static int change_page_attr_set_clr(unsigned long addr, int numpages,
				    pgprot_t mask_set, pgprot_t mask_clr)
{
	int ret = __change_page_attr_set_clr(addr, numpages, mask_set,
					     mask_clr);

	/*
	 * On success we use clflush, when the CPU supports it to
	 * avoid the wbindv. If the CPU does not support it and in the
	 * error case we fall back to cpa_flush_all (which uses
	 * wbindv):
	 */
	if (!ret && cpu_has_clflush)
		cpa_flush_range(addr, numpages);
	else
		cpa_flush_all();

	return ret;
}

static inline int change_page_attr_set(unsigned long addr, int numpages,
				       pgprot_t mask)
{
	return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0));
}

static inline int change_page_attr_clear(unsigned long addr, int numpages,
					 pgprot_t mask)
{
	return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask);
}

int set_memory_uc(unsigned long addr, int numpages)
{
	return change_page_attr_set(addr, numpages,
				    __pgprot(_PAGE_PCD | _PAGE_PWT));
}
EXPORT_SYMBOL(set_memory_uc);

int set_memory_wb(unsigned long addr, int numpages)
{
	return change_page_attr_clear(addr, numpages,
				      __pgprot(_PAGE_PCD | _PAGE_PWT));
}
EXPORT_SYMBOL(set_memory_wb);

int set_memory_x(unsigned long addr, int numpages)
{
	return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_NX));
}
EXPORT_SYMBOL(set_memory_x);

int set_memory_nx(unsigned long addr, int numpages)
{
	return change_page_attr_set(addr, numpages, __pgprot(_PAGE_NX));
}
EXPORT_SYMBOL(set_memory_nx);

int set_memory_ro(unsigned long addr, int numpages)
{
	return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_RW));
}

int set_memory_rw(unsigned long addr, int numpages)
{
	return change_page_attr_set(addr, numpages, __pgprot(_PAGE_RW));
}

int set_memory_np(unsigned long addr, int numpages)
{
	return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_PRESENT));
}

int set_pages_uc(struct page *page, int numpages)
{
	unsigned long addr = (unsigned long)page_address(page);

	return set_memory_uc(addr, numpages);
}
EXPORT_SYMBOL(set_pages_uc);

int set_pages_wb(struct page *page, int numpages)
{
	unsigned long addr = (unsigned long)page_address(page);

	return set_memory_wb(addr, numpages);
}
EXPORT_SYMBOL(set_pages_wb);

int set_pages_x(struct page *page, int numpages)
{
	unsigned long addr = (unsigned long)page_address(page);

	return set_memory_x(addr, numpages);
}
EXPORT_SYMBOL(set_pages_x);

int set_pages_nx(struct page *page, int numpages)
{
	unsigned long addr = (unsigned long)page_address(page);

	return set_memory_nx(addr, numpages);
}
EXPORT_SYMBOL(set_pages_nx);

int set_pages_ro(struct page *page, int numpages)
{
	unsigned long addr = (unsigned long)page_address(page);

	return set_memory_ro(addr, numpages);
}

int set_pages_rw(struct page *page, int numpages)
{
	unsigned long addr = (unsigned long)page_address(page);

	return set_memory_rw(addr, numpages);
}


#if defined(CONFIG_DEBUG_PAGEALLOC) || defined(CONFIG_CPA_DEBUG)
static inline int __change_page_attr_set(unsigned long addr, int numpages,
					 pgprot_t mask)
{
	return __change_page_attr_set_clr(addr, numpages, mask, __pgprot(0));
}

static inline int __change_page_attr_clear(unsigned long addr, int numpages,
					   pgprot_t mask)
{
	return __change_page_attr_set_clr(addr, numpages, __pgprot(0), mask);
}
#endif

#ifdef CONFIG_DEBUG_PAGEALLOC

static int __set_pages_p(struct page *page, int numpages)
{
	unsigned long addr = (unsigned long)page_address(page);

	return __change_page_attr_set(addr, numpages,
				      __pgprot(_PAGE_PRESENT | _PAGE_RW));
}

static int __set_pages_np(struct page *page, int numpages)
{
	unsigned long addr = (unsigned long)page_address(page);

	return __change_page_attr_clear(addr, numpages,
					__pgprot(_PAGE_PRESENT));
}

void kernel_map_pages(struct page *page, int numpages, int enable)
{
	if (PageHighMem(page))
		return;
	if (!enable) {
		debug_check_no_locks_freed(page_address(page),
					   numpages * PAGE_SIZE);
	}

	/*
	 * If page allocator is not up yet then do not call c_p_a():
	 */
	if (!debug_pagealloc_enabled)
		return;

	/*
	 * The return value is ignored - the calls cannot fail,
	 * large pages are disabled at boot time:
	 */
	if (enable)
		__set_pages_p(page, numpages);
	else
		__set_pages_np(page, numpages);

	/*
	 * We should perform an IPI and flush all tlbs,
	 * but that can deadlock->flush only current cpu:
	 */
	__flush_tlb_all();
}
#endif

/*
 * The testcases use internal knowledge of the implementation that shouldn't
 * be exposed to the rest of the kernel. Include these directly here.
 */
#ifdef CONFIG_CPA_DEBUG
#include "pageattr-test.c"
#endif
Commit	Line	Data
9f4c815c IM	1	/*
9f4c815c IM	2	* Copyright 2002 Andi Kleen, SuSE Labs.
1da177e4	3	* Thanks to Ben LaHaise for precious feedback.
9f4c815c	4	*/
1da177e4	5	#include <linux/highmem.h>
8192206d	6	#include <linux/bootmem.h>
1da177e4	7	#include <linux/module.h>
9f4c815c	8	#include <linux/sched.h>
1da177e4	9	#include <linux/slab.h>
9f4c815c IM	10	#include <linux/mm.h>
9f4c815c IM	11
950f9d95	12	#include <asm/e820.h>
1da177e4 LT	13	#include <asm/processor.h>
1da177e4 LT	14	#include <asm/tlbflush.h>
f8af095d	15	#include <asm/sections.h>
9f4c815c IM	16	#include <asm/uaccess.h>
9f4c815c IM	17	#include <asm/pgalloc.h>
1da177e4	18
ed724be6 AV	19	static inline int
ed724be6 AV	20	within(unsigned long addr, unsigned long start, unsigned long end)
687c4825	21	{
ed724be6 AV	22	return addr >= start && addr < end;
	23	}
	24
d7c8f21a TG	25	/*
	26	* Flushing functions
	27	*/
cd8ddf1a	28
cd8ddf1a TG	29	/**
	30	* clflush_cache_range - flush a cache range with clflush
	31	* @addr: virtual start address
	32	* @size: number of bytes to flush
	33	*
	34	* clflush is an unordered instruction which needs fencing with mfence
	35	* to avoid ordering issues.
	36	*/
4c61afcd	37	void clflush_cache_range(void *vaddr, unsigned int size)
d7c8f21a	38	{
4c61afcd	39	void *vend = vaddr + size - 1;
d7c8f21a	40
cd8ddf1a	41	mb();
4c61afcd IM	42
	43	for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size)
	44	clflush(vaddr);
	45	/*
	46	* Flush any possible final partial cacheline:
	47	*/
	48	clflush(vend);
	49
cd8ddf1a	50	mb();
d7c8f21a TG	51	}
d7c8f21a TG	52
af1e6844	53	static void __cpa_flush_all(void *arg)
d7c8f21a TG	54	{
	55	/*
	56	* Flush all to work around Errata in early athlons regarding
	57	* large page flushing.
	58	*/
	59	__flush_tlb_all();
	60
	61	if (boot_cpu_data.x86_model >= 4)
	62	wbinvd();
	63	}
	64
af1e6844	65	static void cpa_flush_all(void)
d7c8f21a TG	66	{
	67	BUG_ON(irqs_disabled());
	68
af1e6844	69	on_each_cpu(__cpa_flush_all, NULL, 1, 1);
d7c8f21a TG	70	}
d7c8f21a TG	71
57a6a46a TG	72	static void __cpa_flush_range(void *arg)
57a6a46a TG	73	{
57a6a46a TG	74	/*
	75	* We could optimize that further and do individual per page
	76	* tlb invalidates for a low number of pages. Caveat: we must
	77	* flush the high aliases on 64bit as well.
	78	*/
	79	__flush_tlb_all();
57a6a46a TG	80	}
57a6a46a TG	81
4c61afcd	82	static void cpa_flush_range(unsigned long start, int numpages)
57a6a46a	83	{
4c61afcd IM	84	unsigned int i, level;
	85	unsigned long addr;
	86
57a6a46a	87	BUG_ON(irqs_disabled());
4c61afcd	88	WARN_ON(PAGE_ALIGN(start) != start);
57a6a46a	89
3b233e52	90	on_each_cpu(__cpa_flush_range, NULL, 1, 1);
57a6a46a	91
3b233e52 TG	92	/*
	93	* We only need to flush on one CPU,
	94	* clflush is a MESI-coherent instruction that
	95	* will cause all other CPUs to flush the same
	96	* cachelines:
	97	*/
4c61afcd IM	98	for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) {
	99	pte_t *pte = lookup_address(addr, &level);
	100
	101	/*
	102	* Only flush present addresses:
	103	*/
	104	if (pte && pte_present(*pte))
	105	clflush_cache_range((void *) addr, PAGE_SIZE);
	106	}
57a6a46a TG	107	}
57a6a46a TG	108
cc0f21bb AV	109	#define HIGH_MAP_START __START_KERNEL_map
	110	#define HIGH_MAP_END (__START_KERNEL_map + KERNEL_TEXT_SIZE)
	111
	112
	113	/*
	114	* Converts a virtual address to a X86-64 highmap address
	115	*/
	116	static unsigned long virt_to_highmap(void *address)
	117	{
	118	#ifdef CONFIG_X86_64
	119	return __pa((unsigned long)address) + HIGH_MAP_START - phys_base;
	120	#else
	121	return (unsigned long)address;
	122	#endif
	123	}
	124
ed724be6 AV	125	/*
	126	* Certain areas of memory on x86 require very specific protection flags,
	127	* for example the BIOS area or kernel text. Callers don't always get this
	128	* right (again, ioremap() on BIOS memory is not uncommon) so this function
	129	* checks and fixes these known static required protection bits.
	130	*/
	131	static inline pgprot_t static_protections(pgprot_t prot, unsigned long address)
	132	{
	133	pgprot_t forbidden = __pgprot(0);
	134
687c4825	135	/*
ed724be6 AV	136	* The BIOS area between 640k and 1Mb needs to be executable for
ed724be6 AV	137	* PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
687c4825	138	*/
ed724be6 AV	139	if (within(__pa(address), BIOS_BEGIN, BIOS_END))
	140	pgprot_val(forbidden) \|= _PAGE_NX;
	141
	142	/*
	143	* The kernel text needs to be executable for obvious reasons
	144	* Does not cover __inittext since that is gone later on
	145	*/
	146	if (within(address, (unsigned long)_text, (unsigned long)_etext))
	147	pgprot_val(forbidden) \|= _PAGE_NX;
cc0f21bb AV	148	/*
	149	* Do the same for the x86-64 high kernel mapping
	150	*/
	151	if (within(address, virt_to_highmap(_text), virt_to_highmap(_etext)))
	152	pgprot_val(forbidden) \|= _PAGE_NX;
	153
ed724be6 AV	154
	155	#ifdef CONFIG_DEBUG_RODATA
	156	/* The .rodata section needs to be read-only */
	157	if (within(address, (unsigned long)__start_rodata,
	158	(unsigned long)__end_rodata))
	159	pgprot_val(forbidden) \|= _PAGE_RW;
cc0f21bb AV	160	/*
	161	* Do the same for the x86-64 high kernel mapping
	162	*/
	163	if (within(address, virt_to_highmap(__start_rodata),
	164	virt_to_highmap(__end_rodata)))
	165	pgprot_val(forbidden) \|= _PAGE_RW;
ed724be6 AV	166	#endif
	167
	168	prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
687c4825 IM	169
	170	return prot;
	171	}
	172
f0646e43	173	pte_t lookup_address(unsigned long address, int level)
9f4c815c	174	{
1da177e4 LT	175	pgd_t *pgd = pgd_offset_k(address);
	176	pud_t *pud;
	177	pmd_t *pmd;
9f4c815c	178
30551bb3 TG	179	*level = PG_LEVEL_NONE;
30551bb3 TG	180
1da177e4 LT	181	if (pgd_none(*pgd))
	182	return NULL;
	183	pud = pud_offset(pgd, address);
	184	if (pud_none(*pud))
	185	return NULL;
	186	pmd = pmd_offset(pud, address);
	187	if (pmd_none(*pmd))
	188	return NULL;
30551bb3 TG	189
30551bb3 TG	190	*level = PG_LEVEL_2M;
1da177e4 LT	191	if (pmd_large(*pmd))
1da177e4 LT	192	return (pte_t *)pmd;
1da177e4	193
30551bb3	194	*level = PG_LEVEL_4K;
9f4c815c IM	195	return pte_offset_kernel(pmd, address);
	196	}
	197
9a3dc780	198	static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
9f4c815c	199	{
9f4c815c IM	200	/* change init_mm */
9f4c815c IM	201	set_pte_atomic(kpte, pte);
44af6c41	202	#ifdef CONFIG_X86_32
e4b71dcf	203	if (!SHARED_KERNEL_PMD) {
44af6c41 IM	204	struct page *page;
44af6c41 IM	205
e3ed910d	206	list_for_each_entry(page, &pgd_list, lru) {
44af6c41 IM	207	pgd_t *pgd;
	208	pud_t *pud;
	209	pmd_t *pmd;
	210
	211	pgd = (pgd_t *)page_address(page) + pgd_index(address);
	212	pud = pud_offset(pgd, address);
	213	pmd = pmd_offset(pud, address);
	214	set_pte_atomic((pte_t *)pmd, pte);
	215	}
1da177e4	216	}
44af6c41	217	#endif
1da177e4 LT	218	}
1da177e4 LT	219
7afe15b9	220	static int split_large_page(pte_t *kpte, unsigned long address)
bb5c2dbd	221	{
7afe15b9	222	pgprot_t ref_prot = pte_pgprot(pte_clrhuge(*kpte));
12d6f21e	223	gfp_t gfp_flags = GFP_KERNEL;
9a3dc780	224	unsigned long flags;
bb5c2dbd IM	225	unsigned long addr;
	226	pte_t pbase, tmp;
	227	struct page *base;
86f03989	228	unsigned int i, level;
bb5c2dbd	229
12d6f21e	230	#ifdef CONFIG_DEBUG_PAGEALLOC
86f03989 IM	231	gfp_flags = __GFP_HIGH \| __GFP_NOFAIL \| __GFP_NOWARN;
86f03989 IM	232	gfp_flags = GFP_ATOMIC \| __GFP_NOWARN;
12d6f21e IM	233	#endif
12d6f21e IM	234	base = alloc_pages(gfp_flags, 0);
bb5c2dbd IM	235	if (!base)
	236	return -ENOMEM;
	237
9a3dc780	238	spin_lock_irqsave(&pgd_lock, flags);
bb5c2dbd IM	239	/*
	240	* Check for races, another CPU might have split this page
	241	* up for us already:
	242	*/
	243	tmp = lookup_address(address, &level);
5508a748 IM	244	if (tmp != kpte) {
5508a748 IM	245	WARN_ON_ONCE(1);
bb5c2dbd	246	goto out_unlock;
5508a748	247	}
bb5c2dbd IM	248
	249	address = __pa(address);
	250	addr = address & LARGE_PAGE_MASK;
	251	pbase = (pte_t *)page_address(base);
44af6c41	252	#ifdef CONFIG_X86_32
bb5c2dbd	253	paravirt_alloc_pt(&init_mm, page_to_pfn(base));
44af6c41	254	#endif
bb5c2dbd IM	255
	256	for (i = 0; i < PTRS_PER_PTE; i++, addr += PAGE_SIZE)
	257	set_pte(&pbase[i], pfn_pte(addr >> PAGE_SHIFT, ref_prot));
	258
	259	/*
4c881ca1 HY	260	* Install the new, split up pagetable. Important detail here:
	261	*
	262	* On Intel the NX bit of all levels must be cleared to make a
	263	* page executable. See section 4.13.2 of Intel 64 and IA-32
	264	* Architectures Software Developer's Manual).
bb5c2dbd	265	*/
4c881ca1	266	ref_prot = pte_pgprot(pte_mkexec(pte_clrhuge(*kpte)));
9a3dc780	267	__set_pmd_pte(kpte, address, mk_pte(base, ref_prot));
bb5c2dbd IM	268	base = NULL;
	269
	270	out_unlock:
9a3dc780	271	spin_unlock_irqrestore(&pgd_lock, flags);
bb5c2dbd IM	272
	273	if (base)
	274	__free_pages(base, 0);
	275
	276	return 0;
	277	}
	278
44af6c41	279	static int
626c2c9d	280	__change_page_attr(unsigned long address, pgprot_t mask_set, pgprot_t mask_clr)
9f4c815c	281	{
1da177e4	282	struct page *kpte_page;
bb5c2dbd	283	int level, err = 0;
9f4c815c	284	pte_t *kpte;
1da177e4	285
97f99fed	286	repeat:
f0646e43	287	kpte = lookup_address(address, &level);
1da177e4 LT	288	if (!kpte)
1da177e4 LT	289	return -EINVAL;
9f4c815c	290
1da177e4	291	kpte_page = virt_to_page(kpte);
65d2f0bc AK	292	BUG_ON(PageLRU(kpte_page));
	293	BUG_ON(PageCompound(kpte_page));
	294
30551bb3	295	if (level == PG_LEVEL_4K) {
86f03989	296	pte_t new_pte, old_pte = *kpte;
626c2c9d AV	297	pgprot_t new_prot = pte_pgprot(old_pte);
	298
	299	if(!pte_val(old_pte)) {
	300	WARN_ON_ONCE(1);
	301	return -EINVAL;
	302	}
86f03989 IM	303
	304	pgprot_val(new_prot) &= ~pgprot_val(mask_clr);
	305	pgprot_val(new_prot) \|= pgprot_val(mask_set);
	306
	307	new_prot = static_protections(new_prot, address);
	308
626c2c9d AV	309	/*
	310	* We need to keep the pfn from the existing PTE,
	311	* after all we're only going to change it's attributes
	312	* not the memory it points to
	313	*/
	314	new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot));
86f03989 IM	315	set_pte_atomic(kpte, new_pte);
86f03989 IM	316	} else {
7afe15b9	317	err = split_large_page(kpte, address);
bb5c2dbd IM	318	if (!err)
bb5c2dbd IM	319	goto repeat;
1da177e4	320	}
bb5c2dbd	321	return err;
9f4c815c	322	}
1da177e4	323
44af6c41 IM	324	/**
	325	* change_page_attr_addr - Change page table attributes in linear mapping
	326	* @address: Virtual address in linear mapping.
44af6c41	327	* @prot: New page table attribute (PAGE_*)
1da177e4	328	*
44af6c41 IM	329	* Change page attributes of a page in the direct mapping. This is a variant
	330	* of change_page_attr() that also works on memory holes that do not have
	331	* mem_map entry (pfn_valid() is false).
9f4c815c	332	*
44af6c41	333	* See change_page_attr() documentation for more details.
75cbade8 AV	334	*
75cbade8 AV	335	* Modules and drivers should use the set_memory_* APIs instead.
1da177e4	336	*/
44af6c41	337
0879750f	338
86f03989 IM	339	static int
86f03989 IM	340	change_page_attr_addr(unsigned long address, pgprot_t mask_set,
0879750f	341	pgprot_t mask_clr)
1da177e4	342	{
0879750f	343	int err;
44af6c41 IM	344
44af6c41 IM	345	#ifdef CONFIG_X86_64
626c2c9d AV	346	unsigned long phys_addr = __pa(address);
626c2c9d AV	347
0879750f TG	348	/*
	349	* If we are inside the high mapped kernel range, then we
	350	* fixup the low mapping first. __va() returns the virtual
	351	* address in the linear mapping:
	352	*/
	353	if (within(address, HIGH_MAP_START, HIGH_MAP_END))
	354	address = (unsigned long) __va(phys_addr);
44af6c41 IM	355	#endif
44af6c41 IM	356
626c2c9d	357	err = __change_page_attr(address, mask_set, mask_clr);
0879750f TG	358	if (err)
0879750f TG	359	return err;
44af6c41	360
44af6c41	361	#ifdef CONFIG_X86_64
488fd995	362	/*
0879750f TG	363	* If the physical address is inside the kernel map, we need
0879750f TG	364	* to touch the high mapped kernel as well:
488fd995	365	*/
0879750f TG	366	if (within(phys_addr, 0, KERNEL_TEXT_SIZE)) {
	367	/*
	368	* Calc the high mapping address. See __phys_addr()
	369	* for the non obvious details.
cc0f21bb AV	370	*
	371	* Note that NX and other required permissions are
	372	* checked in static_protections().
0879750f TG	373	*/
0879750f TG	374	address = phys_addr + HIGH_MAP_START - phys_base;
0879750f	375
86f03989	376	/*
0879750f TG	377	* Our high aliases are imprecise, because we check
	378	* everything between 0 and KERNEL_TEXT_SIZE, so do
	379	* not propagate lookup failures back to users:
86f03989	380	*/
626c2c9d	381	__change_page_attr(address, mask_set, mask_clr);
9f4c815c	382	}
488fd995	383	#endif
1da177e4 LT	384	return err;
	385	}
	386
ff31452b TG	387	static int __change_page_attr_set_clr(unsigned long addr, int numpages,
	388	pgprot_t mask_set, pgprot_t mask_clr)
	389	{
86f03989 IM	390	unsigned int i;
86f03989 IM	391	int ret;
ff31452b	392
86f03989 IM	393	for (i = 0; i < numpages ; i++, addr += PAGE_SIZE) {
86f03989 IM	394	ret = change_page_attr_addr(addr, mask_set, mask_clr);
ff31452b TG	395	if (ret)
ff31452b TG	396	return ret;
ff31452b TG	397	}
	398
	399	return 0;
	400	}
	401
	402	static int change_page_attr_set_clr(unsigned long addr, int numpages,
	403	pgprot_t mask_set, pgprot_t mask_clr)
	404	{
	405	int ret = __change_page_attr_set_clr(addr, numpages, mask_set,
	406	mask_clr);
	407
57a6a46a TG	408	/*
	409	* On success we use clflush, when the CPU supports it to
	410	* avoid the wbindv. If the CPU does not support it and in the
af1e6844	411	* error case we fall back to cpa_flush_all (which uses
57a6a46a TG	412	* wbindv):
	413	*/
	414	if (!ret && cpu_has_clflush)
	415	cpa_flush_range(addr, numpages);
	416	else
af1e6844	417	cpa_flush_all();
ff31452b TG	418
	419	return ret;
	420	}
	421
56744546 TG	422	static inline int change_page_attr_set(unsigned long addr, int numpages,
56744546 TG	423	pgprot_t mask)
75cbade8	424	{
56744546	425	return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0));
75cbade8 AV	426	}
75cbade8 AV	427
56744546 TG	428	static inline int change_page_attr_clear(unsigned long addr, int numpages,
56744546 TG	429	pgprot_t mask)
72932c7a	430	{
5827040d	431	return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask);
72932c7a TG	432	}
	433
	434	int set_memory_uc(unsigned long addr, int numpages)
	435	{
	436	return change_page_attr_set(addr, numpages,
	437	__pgprot(_PAGE_PCD \| _PAGE_PWT));
75cbade8 AV	438	}
	439	EXPORT_SYMBOL(set_memory_uc);
	440
	441	int set_memory_wb(unsigned long addr, int numpages)
	442	{
72932c7a TG	443	return change_page_attr_clear(addr, numpages,
72932c7a TG	444	__pgprot(_PAGE_PCD \| _PAGE_PWT));
75cbade8 AV	445	}
	446	EXPORT_SYMBOL(set_memory_wb);
	447
	448	int set_memory_x(unsigned long addr, int numpages)
	449	{
72932c7a	450	return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_NX));
75cbade8 AV	451	}
	452	EXPORT_SYMBOL(set_memory_x);
	453
	454	int set_memory_nx(unsigned long addr, int numpages)
	455	{
72932c7a	456	return change_page_attr_set(addr, numpages, __pgprot(_PAGE_NX));
75cbade8 AV	457	}
	458	EXPORT_SYMBOL(set_memory_nx);
	459
	460	int set_memory_ro(unsigned long addr, int numpages)
	461	{
72932c7a	462	return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_RW));
75cbade8	463	}
75cbade8 AV	464
	465	int set_memory_rw(unsigned long addr, int numpages)
	466	{
72932c7a	467	return change_page_attr_set(addr, numpages, __pgprot(_PAGE_RW));
75cbade8	468	}
f62d0f00 IM	469
	470	int set_memory_np(unsigned long addr, int numpages)
	471	{
72932c7a	472	return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_PRESENT));
f62d0f00	473	}
75cbade8 AV	474
	475	int set_pages_uc(struct page *page, int numpages)
	476	{
	477	unsigned long addr = (unsigned long)page_address(page);
75cbade8	478
d7c8f21a	479	return set_memory_uc(addr, numpages);
75cbade8 AV	480	}
	481	EXPORT_SYMBOL(set_pages_uc);
	482
	483	int set_pages_wb(struct page *page, int numpages)
	484	{
	485	unsigned long addr = (unsigned long)page_address(page);
75cbade8	486
d7c8f21a	487	return set_memory_wb(addr, numpages);
75cbade8 AV	488	}
	489	EXPORT_SYMBOL(set_pages_wb);
	490
	491	int set_pages_x(struct page *page, int numpages)
	492	{
	493	unsigned long addr = (unsigned long)page_address(page);
75cbade8	494
d7c8f21a	495	return set_memory_x(addr, numpages);
75cbade8 AV	496	}
	497	EXPORT_SYMBOL(set_pages_x);
	498
	499	int set_pages_nx(struct page *page, int numpages)
	500	{
	501	unsigned long addr = (unsigned long)page_address(page);
75cbade8	502
d7c8f21a	503	return set_memory_nx(addr, numpages);
75cbade8 AV	504	}
	505	EXPORT_SYMBOL(set_pages_nx);
	506
	507	int set_pages_ro(struct page *page, int numpages)
	508	{
	509	unsigned long addr = (unsigned long)page_address(page);
75cbade8	510
d7c8f21a	511	return set_memory_ro(addr, numpages);
75cbade8	512	}
75cbade8 AV	513
	514	int set_pages_rw(struct page *page, int numpages)
	515	{
	516	unsigned long addr = (unsigned long)page_address(page);
e81d5dc4	517
d7c8f21a	518	return set_memory_rw(addr, numpages);
78c94aba IM	519	}
78c94aba IM	520
1da177e4	521
56744546 TG	522	#if defined(CONFIG_DEBUG_PAGEALLOC) \|\| defined(CONFIG_CPA_DEBUG)
	523	static inline int __change_page_attr_set(unsigned long addr, int numpages,
	524	pgprot_t mask)
	525	{
	526	return __change_page_attr_set_clr(addr, numpages, mask, __pgprot(0));
	527	}
	528
	529	static inline int __change_page_attr_clear(unsigned long addr, int numpages,
	530	pgprot_t mask)
	531	{
	532	return __change_page_attr_set_clr(addr, numpages, __pgprot(0), mask);
	533	}
	534	#endif
	535
1da177e4	536	#ifdef CONFIG_DEBUG_PAGEALLOC
f62d0f00 IM	537
	538	static int __set_pages_p(struct page *page, int numpages)
	539	{
	540	unsigned long addr = (unsigned long)page_address(page);
72932c7a TG	541
	542	return __change_page_attr_set(addr, numpages,
	543	__pgprot(_PAGE_PRESENT \| _PAGE_RW));
f62d0f00 IM	544	}
	545
	546	static int __set_pages_np(struct page *page, int numpages)
	547	{
	548	unsigned long addr = (unsigned long)page_address(page);
72932c7a TG	549
	550	return __change_page_attr_clear(addr, numpages,
	551	__pgprot(_PAGE_PRESENT));
f62d0f00 IM	552	}
f62d0f00 IM	553
1da177e4 LT	554	void kernel_map_pages(struct page *page, int numpages, int enable)
	555	{
	556	if (PageHighMem(page))
	557	return;
9f4c815c	558	if (!enable) {
f9b8404c IM	559	debug_check_no_locks_freed(page_address(page),
f9b8404c IM	560	numpages * PAGE_SIZE);
9f4c815c	561	}
de5097c2	562
12d6f21e IM	563	/*
	564	* If page allocator is not up yet then do not call c_p_a():
	565	*/
	566	if (!debug_pagealloc_enabled)
	567	return;
	568
9f4c815c	569	/*
e4b71dcf IM	570	* The return value is ignored - the calls cannot fail,
e4b71dcf IM	571	* large pages are disabled at boot time:
1da177e4	572	*/
f62d0f00 IM	573	if (enable)
	574	__set_pages_p(page, numpages);
	575	else
	576	__set_pages_np(page, numpages);
9f4c815c IM	577
9f4c815c IM	578	/*
e4b71dcf IM	579	* We should perform an IPI and flush all tlbs,
e4b71dcf IM	580	* but that can deadlock->flush only current cpu:
1da177e4 LT	581	*/
	582	__flush_tlb_all();
	583	}
	584	#endif
d1028a15 AV	585
	586	/*
	587	* The testcases use internal knowledge of the implementation that shouldn't
	588	* be exposed to the rest of the kernel. Include these directly here.
	589	*/
	590	#ifdef CONFIG_CPA_DEBUG
	591	#include "pageattr-test.c"
	592	#endif