Commit | Line | Data |
---|---|---|
9f4c815c IM |
1 | /* |
2 | * Copyright 2002 Andi Kleen, SuSE Labs. | |
1da177e4 | 3 | * Thanks to Ben LaHaise for precious feedback. |
9f4c815c | 4 | */ |
1da177e4 | 5 | #include <linux/highmem.h> |
8192206d | 6 | #include <linux/bootmem.h> |
1da177e4 | 7 | #include <linux/module.h> |
9f4c815c | 8 | #include <linux/sched.h> |
9f4c815c | 9 | #include <linux/mm.h> |
76ebd054 | 10 | #include <linux/interrupt.h> |
ee7ae7a1 TG |
11 | #include <linux/seq_file.h> |
12 | #include <linux/debugfs.h> | |
e59a1bb2 | 13 | #include <linux/pfn.h> |
8c4bfc6e | 14 | #include <linux/percpu.h> |
5a0e3ad6 | 15 | #include <linux/gfp.h> |
5bd5a452 | 16 | #include <linux/pci.h> |
9f4c815c | 17 | |
950f9d95 | 18 | #include <asm/e820.h> |
1da177e4 LT |
19 | #include <asm/processor.h> |
20 | #include <asm/tlbflush.h> | |
f8af095d | 21 | #include <asm/sections.h> |
93dbda7c | 22 | #include <asm/setup.h> |
9f4c815c IM |
23 | #include <asm/uaccess.h> |
24 | #include <asm/pgalloc.h> | |
c31c7d48 | 25 | #include <asm/proto.h> |
1219333d | 26 | #include <asm/pat.h> |
1da177e4 | 27 | |
9df84993 IM |
28 | /* |
29 | * The current flushing context - we pass it instead of 5 arguments: | |
30 | */ | |
72e458df | 31 | struct cpa_data { |
d75586ad | 32 | unsigned long *vaddr; |
72e458df TG |
33 | pgprot_t mask_set; |
34 | pgprot_t mask_clr; | |
65e074df | 35 | int numpages; |
d75586ad | 36 | int flags; |
c31c7d48 | 37 | unsigned long pfn; |
c9caa02c | 38 | unsigned force_split : 1; |
d75586ad | 39 | int curpage; |
9ae28475 | 40 | struct page **pages; |
72e458df TG |
41 | }; |
42 | ||
ad5ca55f SS |
43 | /* |
44 | * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings) | |
45 | * using cpa_lock. So that we don't allow any other cpu, with stale large tlb | |
46 | * entries change the page attribute in parallel to some other cpu | |
47 | * splitting a large page entry along with changing the attribute. | |
48 | */ | |
49 | static DEFINE_SPINLOCK(cpa_lock); | |
50 | ||
d75586ad SL |
51 | #define CPA_FLUSHTLB 1 |
52 | #define CPA_ARRAY 2 | |
9ae28475 | 53 | #define CPA_PAGES_ARRAY 4 |
d75586ad | 54 | |
65280e61 | 55 | #ifdef CONFIG_PROC_FS |
ce0c0e50 AK |
56 | static unsigned long direct_pages_count[PG_LEVEL_NUM]; |
57 | ||
65280e61 | 58 | void update_page_count(int level, unsigned long pages) |
ce0c0e50 | 59 | { |
ce0c0e50 | 60 | unsigned long flags; |
65280e61 | 61 | |
ce0c0e50 AK |
62 | /* Protect against CPA */ |
63 | spin_lock_irqsave(&pgd_lock, flags); | |
64 | direct_pages_count[level] += pages; | |
65 | spin_unlock_irqrestore(&pgd_lock, flags); | |
65280e61 TG |
66 | } |
67 | ||
68 | static void split_page_count(int level) | |
69 | { | |
70 | direct_pages_count[level]--; | |
71 | direct_pages_count[level - 1] += PTRS_PER_PTE; | |
72 | } | |
73 | ||
e1759c21 | 74 | void arch_report_meminfo(struct seq_file *m) |
65280e61 | 75 | { |
b9c3bfc2 | 76 | seq_printf(m, "DirectMap4k: %8lu kB\n", |
a06de630 HD |
77 | direct_pages_count[PG_LEVEL_4K] << 2); |
78 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
b9c3bfc2 | 79 | seq_printf(m, "DirectMap2M: %8lu kB\n", |
a06de630 HD |
80 | direct_pages_count[PG_LEVEL_2M] << 11); |
81 | #else | |
b9c3bfc2 | 82 | seq_printf(m, "DirectMap4M: %8lu kB\n", |
a06de630 HD |
83 | direct_pages_count[PG_LEVEL_2M] << 12); |
84 | #endif | |
65280e61 | 85 | #ifdef CONFIG_X86_64 |
a06de630 | 86 | if (direct_gbpages) |
b9c3bfc2 | 87 | seq_printf(m, "DirectMap1G: %8lu kB\n", |
a06de630 | 88 | direct_pages_count[PG_LEVEL_1G] << 20); |
ce0c0e50 AK |
89 | #endif |
90 | } | |
65280e61 TG |
91 | #else |
92 | static inline void split_page_count(int level) { } | |
93 | #endif | |
ce0c0e50 | 94 | |
c31c7d48 TG |
95 | #ifdef CONFIG_X86_64 |
96 | ||
97 | static inline unsigned long highmap_start_pfn(void) | |
98 | { | |
99 | return __pa(_text) >> PAGE_SHIFT; | |
100 | } | |
101 | ||
102 | static inline unsigned long highmap_end_pfn(void) | |
103 | { | |
93dbda7c | 104 | return __pa(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT; |
c31c7d48 TG |
105 | } |
106 | ||
107 | #endif | |
108 | ||
92cb54a3 IM |
109 | #ifdef CONFIG_DEBUG_PAGEALLOC |
110 | # define debug_pagealloc 1 | |
111 | #else | |
112 | # define debug_pagealloc 0 | |
113 | #endif | |
114 | ||
ed724be6 AV |
115 | static inline int |
116 | within(unsigned long addr, unsigned long start, unsigned long end) | |
687c4825 | 117 | { |
ed724be6 AV |
118 | return addr >= start && addr < end; |
119 | } | |
120 | ||
d7c8f21a TG |
121 | /* |
122 | * Flushing functions | |
123 | */ | |
cd8ddf1a | 124 | |
cd8ddf1a TG |
125 | /** |
126 | * clflush_cache_range - flush a cache range with clflush | |
127 | * @addr: virtual start address | |
128 | * @size: number of bytes to flush | |
129 | * | |
130 | * clflush is an unordered instruction which needs fencing with mfence | |
131 | * to avoid ordering issues. | |
132 | */ | |
4c61afcd | 133 | void clflush_cache_range(void *vaddr, unsigned int size) |
d7c8f21a | 134 | { |
4c61afcd | 135 | void *vend = vaddr + size - 1; |
d7c8f21a | 136 | |
cd8ddf1a | 137 | mb(); |
4c61afcd IM |
138 | |
139 | for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size) | |
140 | clflush(vaddr); | |
141 | /* | |
142 | * Flush any possible final partial cacheline: | |
143 | */ | |
144 | clflush(vend); | |
145 | ||
cd8ddf1a | 146 | mb(); |
d7c8f21a | 147 | } |
e517a5e9 | 148 | EXPORT_SYMBOL_GPL(clflush_cache_range); |
d7c8f21a | 149 | |
af1e6844 | 150 | static void __cpa_flush_all(void *arg) |
d7c8f21a | 151 | { |
6bb8383b AK |
152 | unsigned long cache = (unsigned long)arg; |
153 | ||
d7c8f21a TG |
154 | /* |
155 | * Flush all to work around Errata in early athlons regarding | |
156 | * large page flushing. | |
157 | */ | |
158 | __flush_tlb_all(); | |
159 | ||
0b827537 | 160 | if (cache && boot_cpu_data.x86 >= 4) |
d7c8f21a TG |
161 | wbinvd(); |
162 | } | |
163 | ||
6bb8383b | 164 | static void cpa_flush_all(unsigned long cache) |
d7c8f21a TG |
165 | { |
166 | BUG_ON(irqs_disabled()); | |
167 | ||
15c8b6c1 | 168 | on_each_cpu(__cpa_flush_all, (void *) cache, 1); |
d7c8f21a TG |
169 | } |
170 | ||
57a6a46a TG |
171 | static void __cpa_flush_range(void *arg) |
172 | { | |
57a6a46a TG |
173 | /* |
174 | * We could optimize that further and do individual per page | |
175 | * tlb invalidates for a low number of pages. Caveat: we must | |
176 | * flush the high aliases on 64bit as well. | |
177 | */ | |
178 | __flush_tlb_all(); | |
57a6a46a TG |
179 | } |
180 | ||
6bb8383b | 181 | static void cpa_flush_range(unsigned long start, int numpages, int cache) |
57a6a46a | 182 | { |
4c61afcd IM |
183 | unsigned int i, level; |
184 | unsigned long addr; | |
185 | ||
57a6a46a | 186 | BUG_ON(irqs_disabled()); |
4c61afcd | 187 | WARN_ON(PAGE_ALIGN(start) != start); |
57a6a46a | 188 | |
15c8b6c1 | 189 | on_each_cpu(__cpa_flush_range, NULL, 1); |
57a6a46a | 190 | |
6bb8383b AK |
191 | if (!cache) |
192 | return; | |
193 | ||
3b233e52 TG |
194 | /* |
195 | * We only need to flush on one CPU, | |
196 | * clflush is a MESI-coherent instruction that | |
197 | * will cause all other CPUs to flush the same | |
198 | * cachelines: | |
199 | */ | |
4c61afcd IM |
200 | for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) { |
201 | pte_t *pte = lookup_address(addr, &level); | |
202 | ||
203 | /* | |
204 | * Only flush present addresses: | |
205 | */ | |
7bfb72e8 | 206 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) |
4c61afcd IM |
207 | clflush_cache_range((void *) addr, PAGE_SIZE); |
208 | } | |
57a6a46a TG |
209 | } |
210 | ||
9ae28475 | 211 | static void cpa_flush_array(unsigned long *start, int numpages, int cache, |
212 | int in_flags, struct page **pages) | |
d75586ad SL |
213 | { |
214 | unsigned int i, level; | |
2171787b | 215 | unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */ |
d75586ad SL |
216 | |
217 | BUG_ON(irqs_disabled()); | |
218 | ||
2171787b | 219 | on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1); |
d75586ad | 220 | |
2171787b | 221 | if (!cache || do_wbinvd) |
d75586ad SL |
222 | return; |
223 | ||
d75586ad SL |
224 | /* |
225 | * We only need to flush on one CPU, | |
226 | * clflush is a MESI-coherent instruction that | |
227 | * will cause all other CPUs to flush the same | |
228 | * cachelines: | |
229 | */ | |
9ae28475 | 230 | for (i = 0; i < numpages; i++) { |
231 | unsigned long addr; | |
232 | pte_t *pte; | |
233 | ||
234 | if (in_flags & CPA_PAGES_ARRAY) | |
235 | addr = (unsigned long)page_address(pages[i]); | |
236 | else | |
237 | addr = start[i]; | |
238 | ||
239 | pte = lookup_address(addr, &level); | |
d75586ad SL |
240 | |
241 | /* | |
242 | * Only flush present addresses: | |
243 | */ | |
244 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) | |
9ae28475 | 245 | clflush_cache_range((void *)addr, PAGE_SIZE); |
d75586ad SL |
246 | } |
247 | } | |
248 | ||
ed724be6 AV |
249 | /* |
250 | * Certain areas of memory on x86 require very specific protection flags, | |
251 | * for example the BIOS area or kernel text. Callers don't always get this | |
252 | * right (again, ioremap() on BIOS memory is not uncommon) so this function | |
253 | * checks and fixes these known static required protection bits. | |
254 | */ | |
c31c7d48 TG |
255 | static inline pgprot_t static_protections(pgprot_t prot, unsigned long address, |
256 | unsigned long pfn) | |
ed724be6 AV |
257 | { |
258 | pgprot_t forbidden = __pgprot(0); | |
259 | ||
687c4825 | 260 | /* |
ed724be6 AV |
261 | * The BIOS area between 640k and 1Mb needs to be executable for |
262 | * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support. | |
687c4825 | 263 | */ |
5bd5a452 MC |
264 | #ifdef CONFIG_PCI_BIOS |
265 | if (pcibios_enabled && within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT)) | |
ed724be6 | 266 | pgprot_val(forbidden) |= _PAGE_NX; |
5bd5a452 | 267 | #endif |
ed724be6 AV |
268 | |
269 | /* | |
270 | * The kernel text needs to be executable for obvious reasons | |
c31c7d48 TG |
271 | * Does not cover __inittext since that is gone later on. On |
272 | * 64bit we do not enforce !NX on the low mapping | |
ed724be6 AV |
273 | */ |
274 | if (within(address, (unsigned long)_text, (unsigned long)_etext)) | |
275 | pgprot_val(forbidden) |= _PAGE_NX; | |
cc0f21bb | 276 | |
cc0f21bb | 277 | /* |
c31c7d48 TG |
278 | * The .rodata section needs to be read-only. Using the pfn |
279 | * catches all aliases. | |
cc0f21bb | 280 | */ |
c31c7d48 TG |
281 | if (within(pfn, __pa((unsigned long)__start_rodata) >> PAGE_SHIFT, |
282 | __pa((unsigned long)__end_rodata) >> PAGE_SHIFT)) | |
cc0f21bb | 283 | pgprot_val(forbidden) |= _PAGE_RW; |
ed724be6 | 284 | |
55ca3cc1 | 285 | #if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA) |
74e08179 | 286 | /* |
502f6604 SS |
287 | * Once the kernel maps the text as RO (kernel_set_to_readonly is set), |
288 | * kernel text mappings for the large page aligned text, rodata sections | |
289 | * will be always read-only. For the kernel identity mappings covering | |
290 | * the holes caused by this alignment can be anything that user asks. | |
74e08179 SS |
291 | * |
292 | * This will preserve the large page mappings for kernel text/data | |
293 | * at no extra cost. | |
294 | */ | |
502f6604 SS |
295 | if (kernel_set_to_readonly && |
296 | within(address, (unsigned long)_text, | |
281ff33b SS |
297 | (unsigned long)__end_rodata_hpage_align)) { |
298 | unsigned int level; | |
299 | ||
300 | /* | |
301 | * Don't enforce the !RW mapping for the kernel text mapping, | |
302 | * if the current mapping is already using small page mapping. | |
303 | * No need to work hard to preserve large page mappings in this | |
304 | * case. | |
305 | * | |
306 | * This also fixes the Linux Xen paravirt guest boot failure | |
307 | * (because of unexpected read-only mappings for kernel identity | |
308 | * mappings). In this paravirt guest case, the kernel text | |
309 | * mapping and the kernel identity mapping share the same | |
310 | * page-table pages. Thus we can't really use different | |
311 | * protections for the kernel text and identity mappings. Also, | |
312 | * these shared mappings are made of small page mappings. | |
313 | * Thus this don't enforce !RW mapping for small page kernel | |
314 | * text mapping logic will help Linux Xen parvirt guest boot | |
315 | * aswell. | |
316 | */ | |
317 | if (lookup_address(address, &level) && (level != PG_LEVEL_4K)) | |
318 | pgprot_val(forbidden) |= _PAGE_RW; | |
319 | } | |
74e08179 SS |
320 | #endif |
321 | ||
ed724be6 | 322 | prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden)); |
687c4825 IM |
323 | |
324 | return prot; | |
325 | } | |
326 | ||
9a14aefc TG |
327 | /* |
328 | * Lookup the page table entry for a virtual address. Return a pointer | |
329 | * to the entry and the level of the mapping. | |
330 | * | |
331 | * Note: We return pud and pmd either when the entry is marked large | |
332 | * or when the present bit is not set. Otherwise we would return a | |
333 | * pointer to a nonexisting mapping. | |
334 | */ | |
da7bfc50 | 335 | pte_t *lookup_address(unsigned long address, unsigned int *level) |
9f4c815c | 336 | { |
1da177e4 LT |
337 | pgd_t *pgd = pgd_offset_k(address); |
338 | pud_t *pud; | |
339 | pmd_t *pmd; | |
9f4c815c | 340 | |
30551bb3 TG |
341 | *level = PG_LEVEL_NONE; |
342 | ||
1da177e4 LT |
343 | if (pgd_none(*pgd)) |
344 | return NULL; | |
9df84993 | 345 | |
1da177e4 LT |
346 | pud = pud_offset(pgd, address); |
347 | if (pud_none(*pud)) | |
348 | return NULL; | |
c2f71ee2 AK |
349 | |
350 | *level = PG_LEVEL_1G; | |
351 | if (pud_large(*pud) || !pud_present(*pud)) | |
352 | return (pte_t *)pud; | |
353 | ||
1da177e4 LT |
354 | pmd = pmd_offset(pud, address); |
355 | if (pmd_none(*pmd)) | |
356 | return NULL; | |
30551bb3 TG |
357 | |
358 | *level = PG_LEVEL_2M; | |
9a14aefc | 359 | if (pmd_large(*pmd) || !pmd_present(*pmd)) |
1da177e4 | 360 | return (pte_t *)pmd; |
1da177e4 | 361 | |
30551bb3 | 362 | *level = PG_LEVEL_4K; |
9df84993 | 363 | |
9f4c815c IM |
364 | return pte_offset_kernel(pmd, address); |
365 | } | |
75bb8835 | 366 | EXPORT_SYMBOL_GPL(lookup_address); |
9f4c815c | 367 | |
9df84993 IM |
368 | /* |
369 | * Set the new pmd in all the pgds we know about: | |
370 | */ | |
9a3dc780 | 371 | static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) |
9f4c815c | 372 | { |
9f4c815c IM |
373 | /* change init_mm */ |
374 | set_pte_atomic(kpte, pte); | |
44af6c41 | 375 | #ifdef CONFIG_X86_32 |
e4b71dcf | 376 | if (!SHARED_KERNEL_PMD) { |
44af6c41 IM |
377 | struct page *page; |
378 | ||
e3ed910d | 379 | list_for_each_entry(page, &pgd_list, lru) { |
44af6c41 IM |
380 | pgd_t *pgd; |
381 | pud_t *pud; | |
382 | pmd_t *pmd; | |
383 | ||
384 | pgd = (pgd_t *)page_address(page) + pgd_index(address); | |
385 | pud = pud_offset(pgd, address); | |
386 | pmd = pmd_offset(pud, address); | |
387 | set_pte_atomic((pte_t *)pmd, pte); | |
388 | } | |
1da177e4 | 389 | } |
44af6c41 | 390 | #endif |
1da177e4 LT |
391 | } |
392 | ||
9df84993 IM |
393 | static int |
394 | try_preserve_large_page(pte_t *kpte, unsigned long address, | |
395 | struct cpa_data *cpa) | |
65e074df | 396 | { |
c31c7d48 | 397 | unsigned long nextpage_addr, numpages, pmask, psize, flags, addr, pfn; |
65e074df | 398 | pte_t new_pte, old_pte, *tmp; |
64edc8ed | 399 | pgprot_t old_prot, new_prot, req_prot; |
fac84939 | 400 | int i, do_split = 1; |
da7bfc50 | 401 | unsigned int level; |
65e074df | 402 | |
c9caa02c AK |
403 | if (cpa->force_split) |
404 | return 1; | |
405 | ||
65e074df TG |
406 | spin_lock_irqsave(&pgd_lock, flags); |
407 | /* | |
408 | * Check for races, another CPU might have split this page | |
409 | * up already: | |
410 | */ | |
411 | tmp = lookup_address(address, &level); | |
412 | if (tmp != kpte) | |
413 | goto out_unlock; | |
414 | ||
415 | switch (level) { | |
416 | case PG_LEVEL_2M: | |
31422c51 AK |
417 | psize = PMD_PAGE_SIZE; |
418 | pmask = PMD_PAGE_MASK; | |
65e074df | 419 | break; |
f07333fd | 420 | #ifdef CONFIG_X86_64 |
65e074df | 421 | case PG_LEVEL_1G: |
5d3c8b21 AK |
422 | psize = PUD_PAGE_SIZE; |
423 | pmask = PUD_PAGE_MASK; | |
f07333fd AK |
424 | break; |
425 | #endif | |
65e074df | 426 | default: |
beaff633 | 427 | do_split = -EINVAL; |
65e074df TG |
428 | goto out_unlock; |
429 | } | |
430 | ||
431 | /* | |
432 | * Calculate the number of pages, which fit into this large | |
433 | * page starting at address: | |
434 | */ | |
435 | nextpage_addr = (address + psize) & pmask; | |
436 | numpages = (nextpage_addr - address) >> PAGE_SHIFT; | |
9b5cf48b RW |
437 | if (numpages < cpa->numpages) |
438 | cpa->numpages = numpages; | |
65e074df TG |
439 | |
440 | /* | |
441 | * We are safe now. Check whether the new pgprot is the same: | |
442 | */ | |
443 | old_pte = *kpte; | |
64edc8ed | 444 | old_prot = new_prot = req_prot = pte_pgprot(old_pte); |
65e074df | 445 | |
64edc8ed | 446 | pgprot_val(req_prot) &= ~pgprot_val(cpa->mask_clr); |
447 | pgprot_val(req_prot) |= pgprot_val(cpa->mask_set); | |
c31c7d48 TG |
448 | |
449 | /* | |
450 | * old_pte points to the large page base address. So we need | |
451 | * to add the offset of the virtual address: | |
452 | */ | |
453 | pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT); | |
454 | cpa->pfn = pfn; | |
455 | ||
64edc8ed | 456 | new_prot = static_protections(req_prot, address, pfn); |
65e074df | 457 | |
fac84939 TG |
458 | /* |
459 | * We need to check the full range, whether | |
460 | * static_protection() requires a different pgprot for one of | |
461 | * the pages in the range we try to preserve: | |
462 | */ | |
64edc8ed | 463 | addr = address & pmask; |
464 | pfn = pte_pfn(old_pte); | |
465 | for (i = 0; i < (psize >> PAGE_SHIFT); i++, addr += PAGE_SIZE, pfn++) { | |
466 | pgprot_t chk_prot = static_protections(req_prot, addr, pfn); | |
fac84939 TG |
467 | |
468 | if (pgprot_val(chk_prot) != pgprot_val(new_prot)) | |
469 | goto out_unlock; | |
470 | } | |
471 | ||
65e074df TG |
472 | /* |
473 | * If there are no changes, return. maxpages has been updated | |
474 | * above: | |
475 | */ | |
476 | if (pgprot_val(new_prot) == pgprot_val(old_prot)) { | |
beaff633 | 477 | do_split = 0; |
65e074df TG |
478 | goto out_unlock; |
479 | } | |
480 | ||
481 | /* | |
482 | * We need to change the attributes. Check, whether we can | |
483 | * change the large page in one go. We request a split, when | |
484 | * the address is not aligned and the number of pages is | |
485 | * smaller than the number of pages in the large page. Note | |
486 | * that we limited the number of possible pages already to | |
487 | * the number of pages in the large page. | |
488 | */ | |
64edc8ed | 489 | if (address == (address & pmask) && cpa->numpages == (psize >> PAGE_SHIFT)) { |
65e074df TG |
490 | /* |
491 | * The address is aligned and the number of pages | |
492 | * covers the full page. | |
493 | */ | |
494 | new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot)); | |
495 | __set_pmd_pte(kpte, address, new_pte); | |
d75586ad | 496 | cpa->flags |= CPA_FLUSHTLB; |
beaff633 | 497 | do_split = 0; |
65e074df TG |
498 | } |
499 | ||
500 | out_unlock: | |
501 | spin_unlock_irqrestore(&pgd_lock, flags); | |
9df84993 | 502 | |
beaff633 | 503 | return do_split; |
65e074df TG |
504 | } |
505 | ||
7afe15b9 | 506 | static int split_large_page(pte_t *kpte, unsigned long address) |
bb5c2dbd | 507 | { |
7b610eec | 508 | unsigned long flags, pfn, pfninc = 1; |
9df84993 | 509 | unsigned int i, level; |
bb5c2dbd | 510 | pte_t *pbase, *tmp; |
9df84993 | 511 | pgprot_t ref_prot; |
ad5ca55f SS |
512 | struct page *base; |
513 | ||
514 | if (!debug_pagealloc) | |
515 | spin_unlock(&cpa_lock); | |
9e730237 | 516 | base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0); |
ad5ca55f SS |
517 | if (!debug_pagealloc) |
518 | spin_lock(&cpa_lock); | |
8311eb84 SS |
519 | if (!base) |
520 | return -ENOMEM; | |
bb5c2dbd | 521 | |
eb5b5f02 | 522 | spin_lock_irqsave(&pgd_lock, flags); |
bb5c2dbd IM |
523 | /* |
524 | * Check for races, another CPU might have split this page | |
525 | * up for us already: | |
526 | */ | |
527 | tmp = lookup_address(address, &level); | |
6ce9fc17 | 528 | if (tmp != kpte) |
bb5c2dbd IM |
529 | goto out_unlock; |
530 | ||
bb5c2dbd | 531 | pbase = (pte_t *)page_address(base); |
6944a9c8 | 532 | paravirt_alloc_pte(&init_mm, page_to_pfn(base)); |
07cf89c0 | 533 | ref_prot = pte_pgprot(pte_clrhuge(*kpte)); |
7a5714e0 IM |
534 | /* |
535 | * If we ever want to utilize the PAT bit, we need to | |
536 | * update this function to make sure it's converted from | |
537 | * bit 12 to bit 7 when we cross from the 2MB level to | |
538 | * the 4K level: | |
539 | */ | |
540 | WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE); | |
bb5c2dbd | 541 | |
f07333fd AK |
542 | #ifdef CONFIG_X86_64 |
543 | if (level == PG_LEVEL_1G) { | |
544 | pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT; | |
545 | pgprot_val(ref_prot) |= _PAGE_PSE; | |
f07333fd AK |
546 | } |
547 | #endif | |
548 | ||
63c1dcf4 TG |
549 | /* |
550 | * Get the target pfn from the original entry: | |
551 | */ | |
552 | pfn = pte_pfn(*kpte); | |
f07333fd | 553 | for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc) |
63c1dcf4 | 554 | set_pte(&pbase[i], pfn_pte(pfn, ref_prot)); |
bb5c2dbd | 555 | |
ce0c0e50 | 556 | if (address >= (unsigned long)__va(0) && |
f361a450 YL |
557 | address < (unsigned long)__va(max_low_pfn_mapped << PAGE_SHIFT)) |
558 | split_page_count(level); | |
559 | ||
560 | #ifdef CONFIG_X86_64 | |
561 | if (address >= (unsigned long)__va(1UL<<32) && | |
65280e61 TG |
562 | address < (unsigned long)__va(max_pfn_mapped << PAGE_SHIFT)) |
563 | split_page_count(level); | |
f361a450 | 564 | #endif |
ce0c0e50 | 565 | |
bb5c2dbd | 566 | /* |
07a66d7c | 567 | * Install the new, split up pagetable. |
4c881ca1 | 568 | * |
07a66d7c IM |
569 | * We use the standard kernel pagetable protections for the new |
570 | * pagetable protections, the actual ptes set above control the | |
571 | * primary protection behavior: | |
bb5c2dbd | 572 | */ |
07a66d7c | 573 | __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); |
211b3d03 IM |
574 | |
575 | /* | |
576 | * Intel Atom errata AAH41 workaround. | |
577 | * | |
578 | * The real fix should be in hw or in a microcode update, but | |
579 | * we also probabilistically try to reduce the window of having | |
580 | * a large TLB mixed with 4K TLBs while instruction fetches are | |
581 | * going on. | |
582 | */ | |
583 | __flush_tlb_all(); | |
584 | ||
bb5c2dbd IM |
585 | base = NULL; |
586 | ||
587 | out_unlock: | |
eb5b5f02 TG |
588 | /* |
589 | * If we dropped out via the lookup_address check under | |
590 | * pgd_lock then stick the page back into the pool: | |
591 | */ | |
8311eb84 SS |
592 | if (base) |
593 | __free_page(base); | |
9a3dc780 | 594 | spin_unlock_irqrestore(&pgd_lock, flags); |
bb5c2dbd | 595 | |
bb5c2dbd IM |
596 | return 0; |
597 | } | |
598 | ||
a1e46212 SS |
599 | static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr, |
600 | int primary) | |
601 | { | |
602 | /* | |
603 | * Ignore all non primary paths. | |
604 | */ | |
605 | if (!primary) | |
606 | return 0; | |
607 | ||
608 | /* | |
609 | * Ignore the NULL PTE for kernel identity mapping, as it is expected | |
610 | * to have holes. | |
611 | * Also set numpages to '1' indicating that we processed cpa req for | |
612 | * one virtual address page and its pfn. TBD: numpages can be set based | |
613 | * on the initial value and the level returned by lookup_address(). | |
614 | */ | |
615 | if (within(vaddr, PAGE_OFFSET, | |
616 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) { | |
617 | cpa->numpages = 1; | |
618 | cpa->pfn = __pa(vaddr) >> PAGE_SHIFT; | |
619 | return 0; | |
620 | } else { | |
621 | WARN(1, KERN_WARNING "CPA: called for zero pte. " | |
622 | "vaddr = %lx cpa->vaddr = %lx\n", vaddr, | |
623 | *cpa->vaddr); | |
624 | ||
625 | return -EFAULT; | |
626 | } | |
627 | } | |
628 | ||
c31c7d48 | 629 | static int __change_page_attr(struct cpa_data *cpa, int primary) |
9f4c815c | 630 | { |
d75586ad | 631 | unsigned long address; |
da7bfc50 HH |
632 | int do_split, err; |
633 | unsigned int level; | |
c31c7d48 | 634 | pte_t *kpte, old_pte; |
1da177e4 | 635 | |
8523acfe TH |
636 | if (cpa->flags & CPA_PAGES_ARRAY) { |
637 | struct page *page = cpa->pages[cpa->curpage]; | |
638 | if (unlikely(PageHighMem(page))) | |
639 | return 0; | |
640 | address = (unsigned long)page_address(page); | |
641 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
642 | address = cpa->vaddr[cpa->curpage]; |
643 | else | |
644 | address = *cpa->vaddr; | |
97f99fed | 645 | repeat: |
f0646e43 | 646 | kpte = lookup_address(address, &level); |
1da177e4 | 647 | if (!kpte) |
a1e46212 | 648 | return __cpa_process_fault(cpa, address, primary); |
c31c7d48 TG |
649 | |
650 | old_pte = *kpte; | |
a1e46212 SS |
651 | if (!pte_val(old_pte)) |
652 | return __cpa_process_fault(cpa, address, primary); | |
9f4c815c | 653 | |
30551bb3 | 654 | if (level == PG_LEVEL_4K) { |
c31c7d48 | 655 | pte_t new_pte; |
626c2c9d | 656 | pgprot_t new_prot = pte_pgprot(old_pte); |
c31c7d48 | 657 | unsigned long pfn = pte_pfn(old_pte); |
86f03989 | 658 | |
72e458df TG |
659 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); |
660 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
86f03989 | 661 | |
c31c7d48 | 662 | new_prot = static_protections(new_prot, address, pfn); |
86f03989 | 663 | |
626c2c9d AV |
664 | /* |
665 | * We need to keep the pfn from the existing PTE, | |
666 | * after all we're only going to change it's attributes | |
667 | * not the memory it points to | |
668 | */ | |
c31c7d48 TG |
669 | new_pte = pfn_pte(pfn, canon_pgprot(new_prot)); |
670 | cpa->pfn = pfn; | |
f4ae5da0 TG |
671 | /* |
672 | * Do we really change anything ? | |
673 | */ | |
674 | if (pte_val(old_pte) != pte_val(new_pte)) { | |
675 | set_pte_atomic(kpte, new_pte); | |
d75586ad | 676 | cpa->flags |= CPA_FLUSHTLB; |
f4ae5da0 | 677 | } |
9b5cf48b | 678 | cpa->numpages = 1; |
65e074df | 679 | return 0; |
1da177e4 | 680 | } |
65e074df TG |
681 | |
682 | /* | |
683 | * Check, whether we can keep the large page intact | |
684 | * and just change the pte: | |
685 | */ | |
beaff633 | 686 | do_split = try_preserve_large_page(kpte, address, cpa); |
65e074df TG |
687 | /* |
688 | * When the range fits into the existing large page, | |
9b5cf48b | 689 | * return. cp->numpages and cpa->tlbflush have been updated in |
65e074df TG |
690 | * try_large_page: |
691 | */ | |
87f7f8fe IM |
692 | if (do_split <= 0) |
693 | return do_split; | |
65e074df TG |
694 | |
695 | /* | |
696 | * We have to split the large page: | |
697 | */ | |
87f7f8fe IM |
698 | err = split_large_page(kpte, address); |
699 | if (!err) { | |
ad5ca55f SS |
700 | /* |
701 | * Do a global flush tlb after splitting the large page | |
702 | * and before we do the actual change page attribute in the PTE. | |
703 | * | |
704 | * With out this, we violate the TLB application note, that says | |
705 | * "The TLBs may contain both ordinary and large-page | |
706 | * translations for a 4-KByte range of linear addresses. This | |
707 | * may occur if software modifies the paging structures so that | |
708 | * the page size used for the address range changes. If the two | |
709 | * translations differ with respect to page frame or attributes | |
710 | * (e.g., permissions), processor behavior is undefined and may | |
711 | * be implementation-specific." | |
712 | * | |
713 | * We do this global tlb flush inside the cpa_lock, so that we | |
714 | * don't allow any other cpu, with stale tlb entries change the | |
715 | * page attribute in parallel, that also falls into the | |
716 | * just split large page entry. | |
717 | */ | |
718 | flush_tlb_all(); | |
87f7f8fe IM |
719 | goto repeat; |
720 | } | |
beaff633 | 721 | |
87f7f8fe | 722 | return err; |
9f4c815c | 723 | } |
1da177e4 | 724 | |
c31c7d48 TG |
725 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias); |
726 | ||
727 | static int cpa_process_alias(struct cpa_data *cpa) | |
1da177e4 | 728 | { |
c31c7d48 | 729 | struct cpa_data alias_cpa; |
992f4c1c | 730 | unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT); |
e933a73f | 731 | unsigned long vaddr; |
992f4c1c | 732 | int ret; |
44af6c41 | 733 | |
965194c1 | 734 | if (cpa->pfn >= max_pfn_mapped) |
c31c7d48 | 735 | return 0; |
626c2c9d | 736 | |
f361a450 | 737 | #ifdef CONFIG_X86_64 |
965194c1 | 738 | if (cpa->pfn >= max_low_pfn_mapped && cpa->pfn < (1UL<<(32-PAGE_SHIFT))) |
f361a450 YL |
739 | return 0; |
740 | #endif | |
f34b439f TG |
741 | /* |
742 | * No need to redo, when the primary call touched the direct | |
743 | * mapping already: | |
744 | */ | |
8523acfe TH |
745 | if (cpa->flags & CPA_PAGES_ARRAY) { |
746 | struct page *page = cpa->pages[cpa->curpage]; | |
747 | if (unlikely(PageHighMem(page))) | |
748 | return 0; | |
749 | vaddr = (unsigned long)page_address(page); | |
750 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
751 | vaddr = cpa->vaddr[cpa->curpage]; |
752 | else | |
753 | vaddr = *cpa->vaddr; | |
754 | ||
755 | if (!(within(vaddr, PAGE_OFFSET, | |
a1e46212 | 756 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) { |
44af6c41 | 757 | |
f34b439f | 758 | alias_cpa = *cpa; |
992f4c1c | 759 | alias_cpa.vaddr = &laddr; |
9ae28475 | 760 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); |
d75586ad | 761 | |
f34b439f | 762 | ret = __change_page_attr_set_clr(&alias_cpa, 0); |
992f4c1c TH |
763 | if (ret) |
764 | return ret; | |
f34b439f | 765 | } |
44af6c41 | 766 | |
44af6c41 | 767 | #ifdef CONFIG_X86_64 |
488fd995 | 768 | /* |
992f4c1c TH |
769 | * If the primary call didn't touch the high mapping already |
770 | * and the physical address is inside the kernel map, we need | |
0879750f | 771 | * to touch the high mapped kernel as well: |
488fd995 | 772 | */ |
992f4c1c TH |
773 | if (!within(vaddr, (unsigned long)_text, _brk_end) && |
774 | within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) { | |
775 | unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) + | |
776 | __START_KERNEL_map - phys_base; | |
777 | alias_cpa = *cpa; | |
778 | alias_cpa.vaddr = &temp_cpa_vaddr; | |
779 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); | |
c31c7d48 | 780 | |
992f4c1c TH |
781 | /* |
782 | * The high mapping range is imprecise, so ignore the | |
783 | * return value. | |
784 | */ | |
785 | __change_page_attr_set_clr(&alias_cpa, 0); | |
786 | } | |
488fd995 | 787 | #endif |
992f4c1c TH |
788 | |
789 | return 0; | |
1da177e4 LT |
790 | } |
791 | ||
c31c7d48 | 792 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias) |
ff31452b | 793 | { |
65e074df | 794 | int ret, numpages = cpa->numpages; |
ff31452b | 795 | |
65e074df TG |
796 | while (numpages) { |
797 | /* | |
798 | * Store the remaining nr of pages for the large page | |
799 | * preservation check. | |
800 | */ | |
9b5cf48b | 801 | cpa->numpages = numpages; |
d75586ad | 802 | /* for array changes, we can't use large page */ |
9ae28475 | 803 | if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
d75586ad | 804 | cpa->numpages = 1; |
c31c7d48 | 805 | |
ad5ca55f SS |
806 | if (!debug_pagealloc) |
807 | spin_lock(&cpa_lock); | |
c31c7d48 | 808 | ret = __change_page_attr(cpa, checkalias); |
ad5ca55f SS |
809 | if (!debug_pagealloc) |
810 | spin_unlock(&cpa_lock); | |
ff31452b TG |
811 | if (ret) |
812 | return ret; | |
ff31452b | 813 | |
c31c7d48 TG |
814 | if (checkalias) { |
815 | ret = cpa_process_alias(cpa); | |
816 | if (ret) | |
817 | return ret; | |
818 | } | |
819 | ||
65e074df TG |
820 | /* |
821 | * Adjust the number of pages with the result of the | |
822 | * CPA operation. Either a large page has been | |
823 | * preserved or a single page update happened. | |
824 | */ | |
9b5cf48b RW |
825 | BUG_ON(cpa->numpages > numpages); |
826 | numpages -= cpa->numpages; | |
9ae28475 | 827 | if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) |
d75586ad SL |
828 | cpa->curpage++; |
829 | else | |
830 | *cpa->vaddr += cpa->numpages * PAGE_SIZE; | |
831 | ||
65e074df | 832 | } |
ff31452b TG |
833 | return 0; |
834 | } | |
835 | ||
6bb8383b AK |
836 | static inline int cache_attr(pgprot_t attr) |
837 | { | |
838 | return pgprot_val(attr) & | |
839 | (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD); | |
840 | } | |
841 | ||
d75586ad | 842 | static int change_page_attr_set_clr(unsigned long *addr, int numpages, |
c9caa02c | 843 | pgprot_t mask_set, pgprot_t mask_clr, |
9ae28475 | 844 | int force_split, int in_flag, |
845 | struct page **pages) | |
ff31452b | 846 | { |
72e458df | 847 | struct cpa_data cpa; |
cacf8906 | 848 | int ret, cache, checkalias; |
fa526d0d | 849 | unsigned long baddr = 0; |
331e4065 TG |
850 | |
851 | /* | |
852 | * Check, if we are requested to change a not supported | |
853 | * feature: | |
854 | */ | |
855 | mask_set = canon_pgprot(mask_set); | |
856 | mask_clr = canon_pgprot(mask_clr); | |
c9caa02c | 857 | if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split) |
331e4065 TG |
858 | return 0; |
859 | ||
69b1415e | 860 | /* Ensure we are PAGE_SIZE aligned */ |
9ae28475 | 861 | if (in_flag & CPA_ARRAY) { |
d75586ad SL |
862 | int i; |
863 | for (i = 0; i < numpages; i++) { | |
864 | if (addr[i] & ~PAGE_MASK) { | |
865 | addr[i] &= PAGE_MASK; | |
866 | WARN_ON_ONCE(1); | |
867 | } | |
868 | } | |
9ae28475 | 869 | } else if (!(in_flag & CPA_PAGES_ARRAY)) { |
870 | /* | |
871 | * in_flag of CPA_PAGES_ARRAY implies it is aligned. | |
872 | * No need to cehck in that case | |
873 | */ | |
874 | if (*addr & ~PAGE_MASK) { | |
875 | *addr &= PAGE_MASK; | |
876 | /* | |
877 | * People should not be passing in unaligned addresses: | |
878 | */ | |
879 | WARN_ON_ONCE(1); | |
880 | } | |
fa526d0d JS |
881 | /* |
882 | * Save address for cache flush. *addr is modified in the call | |
883 | * to __change_page_attr_set_clr() below. | |
884 | */ | |
885 | baddr = *addr; | |
69b1415e TG |
886 | } |
887 | ||
5843d9a4 NP |
888 | /* Must avoid aliasing mappings in the highmem code */ |
889 | kmap_flush_unused(); | |
890 | ||
db64fe02 NP |
891 | vm_unmap_aliases(); |
892 | ||
72e458df | 893 | cpa.vaddr = addr; |
9ae28475 | 894 | cpa.pages = pages; |
72e458df TG |
895 | cpa.numpages = numpages; |
896 | cpa.mask_set = mask_set; | |
897 | cpa.mask_clr = mask_clr; | |
d75586ad SL |
898 | cpa.flags = 0; |
899 | cpa.curpage = 0; | |
c9caa02c | 900 | cpa.force_split = force_split; |
72e458df | 901 | |
9ae28475 | 902 | if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
903 | cpa.flags |= in_flag; | |
d75586ad | 904 | |
af96e443 TG |
905 | /* No alias checking for _NX bit modifications */ |
906 | checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX; | |
907 | ||
908 | ret = __change_page_attr_set_clr(&cpa, checkalias); | |
ff31452b | 909 | |
f4ae5da0 TG |
910 | /* |
911 | * Check whether we really changed something: | |
912 | */ | |
d75586ad | 913 | if (!(cpa.flags & CPA_FLUSHTLB)) |
1ac2f7d5 | 914 | goto out; |
cacf8906 | 915 | |
6bb8383b AK |
916 | /* |
917 | * No need to flush, when we did not set any of the caching | |
918 | * attributes: | |
919 | */ | |
920 | cache = cache_attr(mask_set); | |
921 | ||
57a6a46a TG |
922 | /* |
923 | * On success we use clflush, when the CPU supports it to | |
924 | * avoid the wbindv. If the CPU does not support it and in the | |
af1e6844 | 925 | * error case we fall back to cpa_flush_all (which uses |
57a6a46a TG |
926 | * wbindv): |
927 | */ | |
d75586ad | 928 | if (!ret && cpu_has_clflush) { |
9ae28475 | 929 | if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) { |
930 | cpa_flush_array(addr, numpages, cache, | |
931 | cpa.flags, pages); | |
932 | } else | |
fa526d0d | 933 | cpa_flush_range(baddr, numpages, cache); |
d75586ad | 934 | } else |
6bb8383b | 935 | cpa_flush_all(cache); |
cacf8906 | 936 | |
76ebd054 | 937 | out: |
ff31452b TG |
938 | return ret; |
939 | } | |
940 | ||
d75586ad SL |
941 | static inline int change_page_attr_set(unsigned long *addr, int numpages, |
942 | pgprot_t mask, int array) | |
75cbade8 | 943 | { |
d75586ad | 944 | return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0, |
9ae28475 | 945 | (array ? CPA_ARRAY : 0), NULL); |
75cbade8 AV |
946 | } |
947 | ||
d75586ad SL |
948 | static inline int change_page_attr_clear(unsigned long *addr, int numpages, |
949 | pgprot_t mask, int array) | |
72932c7a | 950 | { |
d75586ad | 951 | return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0, |
9ae28475 | 952 | (array ? CPA_ARRAY : 0), NULL); |
72932c7a TG |
953 | } |
954 | ||
0f350755 | 955 | static inline int cpa_set_pages_array(struct page **pages, int numpages, |
956 | pgprot_t mask) | |
957 | { | |
958 | return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0, | |
959 | CPA_PAGES_ARRAY, pages); | |
960 | } | |
961 | ||
962 | static inline int cpa_clear_pages_array(struct page **pages, int numpages, | |
963 | pgprot_t mask) | |
964 | { | |
965 | return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0, | |
966 | CPA_PAGES_ARRAY, pages); | |
967 | } | |
968 | ||
1219333d | 969 | int _set_memory_uc(unsigned long addr, int numpages) |
72932c7a | 970 | { |
de33c442 SS |
971 | /* |
972 | * for now UC MINUS. see comments in ioremap_nocache() | |
973 | */ | |
d75586ad SL |
974 | return change_page_attr_set(&addr, numpages, |
975 | __pgprot(_PAGE_CACHE_UC_MINUS), 0); | |
75cbade8 | 976 | } |
1219333d | 977 | |
978 | int set_memory_uc(unsigned long addr, int numpages) | |
979 | { | |
9fa3ab39 | 980 | int ret; |
981 | ||
de33c442 SS |
982 | /* |
983 | * for now UC MINUS. see comments in ioremap_nocache() | |
984 | */ | |
9fa3ab39 | 985 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
986 | _PAGE_CACHE_UC_MINUS, NULL); | |
987 | if (ret) | |
988 | goto out_err; | |
989 | ||
990 | ret = _set_memory_uc(addr, numpages); | |
991 | if (ret) | |
992 | goto out_free; | |
993 | ||
994 | return 0; | |
1219333d | 995 | |
9fa3ab39 | 996 | out_free: |
997 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
998 | out_err: | |
999 | return ret; | |
1219333d | 1000 | } |
75cbade8 AV |
1001 | EXPORT_SYMBOL(set_memory_uc); |
1002 | ||
4f646254 PN |
1003 | int _set_memory_array(unsigned long *addr, int addrinarray, |
1004 | unsigned long new_type) | |
d75586ad | 1005 | { |
9fa3ab39 | 1006 | int i, j; |
1007 | int ret; | |
1008 | ||
d75586ad SL |
1009 | /* |
1010 | * for now UC MINUS. see comments in ioremap_nocache() | |
1011 | */ | |
1012 | for (i = 0; i < addrinarray; i++) { | |
9fa3ab39 | 1013 | ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE, |
4f646254 | 1014 | new_type, NULL); |
9fa3ab39 | 1015 | if (ret) |
1016 | goto out_free; | |
d75586ad SL |
1017 | } |
1018 | ||
9fa3ab39 | 1019 | ret = change_page_attr_set(addr, addrinarray, |
d75586ad | 1020 | __pgprot(_PAGE_CACHE_UC_MINUS), 1); |
4f646254 PN |
1021 | |
1022 | if (!ret && new_type == _PAGE_CACHE_WC) | |
1023 | ret = change_page_attr_set_clr(addr, addrinarray, | |
1024 | __pgprot(_PAGE_CACHE_WC), | |
1025 | __pgprot(_PAGE_CACHE_MASK), | |
1026 | 0, CPA_ARRAY, NULL); | |
9fa3ab39 | 1027 | if (ret) |
1028 | goto out_free; | |
1029 | ||
1030 | return 0; | |
1031 | ||
1032 | out_free: | |
1033 | for (j = 0; j < i; j++) | |
1034 | free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE); | |
1035 | ||
1036 | return ret; | |
d75586ad | 1037 | } |
4f646254 PN |
1038 | |
1039 | int set_memory_array_uc(unsigned long *addr, int addrinarray) | |
1040 | { | |
1041 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_UC_MINUS); | |
1042 | } | |
d75586ad SL |
1043 | EXPORT_SYMBOL(set_memory_array_uc); |
1044 | ||
4f646254 PN |
1045 | int set_memory_array_wc(unsigned long *addr, int addrinarray) |
1046 | { | |
1047 | return _set_memory_array(addr, addrinarray, _PAGE_CACHE_WC); | |
1048 | } | |
1049 | EXPORT_SYMBOL(set_memory_array_wc); | |
1050 | ||
ef354af4 | 1051 | int _set_memory_wc(unsigned long addr, int numpages) |
1052 | { | |
3869c4aa | 1053 | int ret; |
bdc6340f PV |
1054 | unsigned long addr_copy = addr; |
1055 | ||
3869c4aa | 1056 | ret = change_page_attr_set(&addr, numpages, |
1057 | __pgprot(_PAGE_CACHE_UC_MINUS), 0); | |
3869c4aa | 1058 | if (!ret) { |
bdc6340f PV |
1059 | ret = change_page_attr_set_clr(&addr_copy, numpages, |
1060 | __pgprot(_PAGE_CACHE_WC), | |
1061 | __pgprot(_PAGE_CACHE_MASK), | |
1062 | 0, 0, NULL); | |
3869c4aa | 1063 | } |
1064 | return ret; | |
ef354af4 | 1065 | } |
1066 | ||
1067 | int set_memory_wc(unsigned long addr, int numpages) | |
1068 | { | |
9fa3ab39 | 1069 | int ret; |
1070 | ||
499f8f84 | 1071 | if (!pat_enabled) |
ef354af4 | 1072 | return set_memory_uc(addr, numpages); |
1073 | ||
9fa3ab39 | 1074 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
1075 | _PAGE_CACHE_WC, NULL); | |
1076 | if (ret) | |
1077 | goto out_err; | |
ef354af4 | 1078 | |
9fa3ab39 | 1079 | ret = _set_memory_wc(addr, numpages); |
1080 | if (ret) | |
1081 | goto out_free; | |
1082 | ||
1083 | return 0; | |
1084 | ||
1085 | out_free: | |
1086 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
1087 | out_err: | |
1088 | return ret; | |
ef354af4 | 1089 | } |
1090 | EXPORT_SYMBOL(set_memory_wc); | |
1091 | ||
1219333d | 1092 | int _set_memory_wb(unsigned long addr, int numpages) |
75cbade8 | 1093 | { |
d75586ad SL |
1094 | return change_page_attr_clear(&addr, numpages, |
1095 | __pgprot(_PAGE_CACHE_MASK), 0); | |
75cbade8 | 1096 | } |
1219333d | 1097 | |
1098 | int set_memory_wb(unsigned long addr, int numpages) | |
1099 | { | |
9fa3ab39 | 1100 | int ret; |
1101 | ||
1102 | ret = _set_memory_wb(addr, numpages); | |
1103 | if (ret) | |
1104 | return ret; | |
1105 | ||
c15238df | 1106 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
9fa3ab39 | 1107 | return 0; |
1219333d | 1108 | } |
75cbade8 AV |
1109 | EXPORT_SYMBOL(set_memory_wb); |
1110 | ||
d75586ad SL |
1111 | int set_memory_array_wb(unsigned long *addr, int addrinarray) |
1112 | { | |
1113 | int i; | |
a5593e0b | 1114 | int ret; |
1115 | ||
1116 | ret = change_page_attr_clear(addr, addrinarray, | |
1117 | __pgprot(_PAGE_CACHE_MASK), 1); | |
9fa3ab39 | 1118 | if (ret) |
1119 | return ret; | |
d75586ad | 1120 | |
9fa3ab39 | 1121 | for (i = 0; i < addrinarray; i++) |
1122 | free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE); | |
c5e147cf | 1123 | |
9fa3ab39 | 1124 | return 0; |
d75586ad SL |
1125 | } |
1126 | EXPORT_SYMBOL(set_memory_array_wb); | |
1127 | ||
75cbade8 AV |
1128 | int set_memory_x(unsigned long addr, int numpages) |
1129 | { | |
583140af PA |
1130 | if (!(__supported_pte_mask & _PAGE_NX)) |
1131 | return 0; | |
1132 | ||
d75586ad | 1133 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1134 | } |
1135 | EXPORT_SYMBOL(set_memory_x); | |
1136 | ||
1137 | int set_memory_nx(unsigned long addr, int numpages) | |
1138 | { | |
583140af PA |
1139 | if (!(__supported_pte_mask & _PAGE_NX)) |
1140 | return 0; | |
1141 | ||
d75586ad | 1142 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1143 | } |
1144 | EXPORT_SYMBOL(set_memory_nx); | |
1145 | ||
1146 | int set_memory_ro(unsigned long addr, int numpages) | |
1147 | { | |
d75586ad | 1148 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1149 | } |
a03352d2 | 1150 | EXPORT_SYMBOL_GPL(set_memory_ro); |
75cbade8 AV |
1151 | |
1152 | int set_memory_rw(unsigned long addr, int numpages) | |
1153 | { | |
d75586ad | 1154 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1155 | } |
a03352d2 | 1156 | EXPORT_SYMBOL_GPL(set_memory_rw); |
f62d0f00 IM |
1157 | |
1158 | int set_memory_np(unsigned long addr, int numpages) | |
1159 | { | |
d75586ad | 1160 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0); |
f62d0f00 | 1161 | } |
75cbade8 | 1162 | |
c9caa02c AK |
1163 | int set_memory_4k(unsigned long addr, int numpages) |
1164 | { | |
d75586ad | 1165 | return change_page_attr_set_clr(&addr, numpages, __pgprot(0), |
9ae28475 | 1166 | __pgprot(0), 1, 0, NULL); |
c9caa02c AK |
1167 | } |
1168 | ||
75cbade8 AV |
1169 | int set_pages_uc(struct page *page, int numpages) |
1170 | { | |
1171 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1172 | |
d7c8f21a | 1173 | return set_memory_uc(addr, numpages); |
75cbade8 AV |
1174 | } |
1175 | EXPORT_SYMBOL(set_pages_uc); | |
1176 | ||
4f646254 PN |
1177 | static int _set_pages_array(struct page **pages, int addrinarray, |
1178 | unsigned long new_type) | |
0f350755 | 1179 | { |
1180 | unsigned long start; | |
1181 | unsigned long end; | |
1182 | int i; | |
1183 | int free_idx; | |
4f646254 | 1184 | int ret; |
0f350755 | 1185 | |
1186 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1187 | if (PageHighMem(pages[i])) |
1188 | continue; | |
1189 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1190 | end = start + PAGE_SIZE; |
4f646254 | 1191 | if (reserve_memtype(start, end, new_type, NULL)) |
0f350755 | 1192 | goto err_out; |
1193 | } | |
1194 | ||
4f646254 PN |
1195 | ret = cpa_set_pages_array(pages, addrinarray, |
1196 | __pgprot(_PAGE_CACHE_UC_MINUS)); | |
1197 | if (!ret && new_type == _PAGE_CACHE_WC) | |
1198 | ret = change_page_attr_set_clr(NULL, addrinarray, | |
1199 | __pgprot(_PAGE_CACHE_WC), | |
1200 | __pgprot(_PAGE_CACHE_MASK), | |
1201 | 0, CPA_PAGES_ARRAY, pages); | |
1202 | if (ret) | |
1203 | goto err_out; | |
1204 | return 0; /* Success */ | |
0f350755 | 1205 | err_out: |
1206 | free_idx = i; | |
1207 | for (i = 0; i < free_idx; i++) { | |
8523acfe TH |
1208 | if (PageHighMem(pages[i])) |
1209 | continue; | |
1210 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1211 | end = start + PAGE_SIZE; |
1212 | free_memtype(start, end); | |
1213 | } | |
1214 | return -EINVAL; | |
1215 | } | |
4f646254 PN |
1216 | |
1217 | int set_pages_array_uc(struct page **pages, int addrinarray) | |
1218 | { | |
1219 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_UC_MINUS); | |
1220 | } | |
0f350755 | 1221 | EXPORT_SYMBOL(set_pages_array_uc); |
1222 | ||
4f646254 PN |
1223 | int set_pages_array_wc(struct page **pages, int addrinarray) |
1224 | { | |
1225 | return _set_pages_array(pages, addrinarray, _PAGE_CACHE_WC); | |
1226 | } | |
1227 | EXPORT_SYMBOL(set_pages_array_wc); | |
1228 | ||
75cbade8 AV |
1229 | int set_pages_wb(struct page *page, int numpages) |
1230 | { | |
1231 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1232 | |
d7c8f21a | 1233 | return set_memory_wb(addr, numpages); |
75cbade8 AV |
1234 | } |
1235 | EXPORT_SYMBOL(set_pages_wb); | |
1236 | ||
0f350755 | 1237 | int set_pages_array_wb(struct page **pages, int addrinarray) |
1238 | { | |
1239 | int retval; | |
1240 | unsigned long start; | |
1241 | unsigned long end; | |
1242 | int i; | |
1243 | ||
1244 | retval = cpa_clear_pages_array(pages, addrinarray, | |
1245 | __pgprot(_PAGE_CACHE_MASK)); | |
9fa3ab39 | 1246 | if (retval) |
1247 | return retval; | |
0f350755 | 1248 | |
1249 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1250 | if (PageHighMem(pages[i])) |
1251 | continue; | |
1252 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1253 | end = start + PAGE_SIZE; |
1254 | free_memtype(start, end); | |
1255 | } | |
1256 | ||
9fa3ab39 | 1257 | return 0; |
0f350755 | 1258 | } |
1259 | EXPORT_SYMBOL(set_pages_array_wb); | |
1260 | ||
75cbade8 AV |
1261 | int set_pages_x(struct page *page, int numpages) |
1262 | { | |
1263 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1264 | |
d7c8f21a | 1265 | return set_memory_x(addr, numpages); |
75cbade8 AV |
1266 | } |
1267 | EXPORT_SYMBOL(set_pages_x); | |
1268 | ||
1269 | int set_pages_nx(struct page *page, int numpages) | |
1270 | { | |
1271 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1272 | |
d7c8f21a | 1273 | return set_memory_nx(addr, numpages); |
75cbade8 AV |
1274 | } |
1275 | EXPORT_SYMBOL(set_pages_nx); | |
1276 | ||
1277 | int set_pages_ro(struct page *page, int numpages) | |
1278 | { | |
1279 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1280 | |
d7c8f21a | 1281 | return set_memory_ro(addr, numpages); |
75cbade8 | 1282 | } |
75cbade8 AV |
1283 | |
1284 | int set_pages_rw(struct page *page, int numpages) | |
1285 | { | |
1286 | unsigned long addr = (unsigned long)page_address(page); | |
e81d5dc4 | 1287 | |
d7c8f21a | 1288 | return set_memory_rw(addr, numpages); |
78c94aba IM |
1289 | } |
1290 | ||
1da177e4 | 1291 | #ifdef CONFIG_DEBUG_PAGEALLOC |
f62d0f00 IM |
1292 | |
1293 | static int __set_pages_p(struct page *page, int numpages) | |
1294 | { | |
d75586ad SL |
1295 | unsigned long tempaddr = (unsigned long) page_address(page); |
1296 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
72e458df TG |
1297 | .numpages = numpages, |
1298 | .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW), | |
d75586ad SL |
1299 | .mask_clr = __pgprot(0), |
1300 | .flags = 0}; | |
72932c7a | 1301 | |
55121b43 SS |
1302 | /* |
1303 | * No alias checking needed for setting present flag. otherwise, | |
1304 | * we may need to break large pages for 64-bit kernel text | |
1305 | * mappings (this adds to complexity if we want to do this from | |
1306 | * atomic context especially). Let's keep it simple! | |
1307 | */ | |
1308 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1309 | } |
1310 | ||
1311 | static int __set_pages_np(struct page *page, int numpages) | |
1312 | { | |
d75586ad SL |
1313 | unsigned long tempaddr = (unsigned long) page_address(page); |
1314 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
72e458df TG |
1315 | .numpages = numpages, |
1316 | .mask_set = __pgprot(0), | |
d75586ad SL |
1317 | .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW), |
1318 | .flags = 0}; | |
72932c7a | 1319 | |
55121b43 SS |
1320 | /* |
1321 | * No alias checking needed for setting not present flag. otherwise, | |
1322 | * we may need to break large pages for 64-bit kernel text | |
1323 | * mappings (this adds to complexity if we want to do this from | |
1324 | * atomic context especially). Let's keep it simple! | |
1325 | */ | |
1326 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1327 | } |
1328 | ||
1da177e4 LT |
1329 | void kernel_map_pages(struct page *page, int numpages, int enable) |
1330 | { | |
1331 | if (PageHighMem(page)) | |
1332 | return; | |
9f4c815c | 1333 | if (!enable) { |
f9b8404c IM |
1334 | debug_check_no_locks_freed(page_address(page), |
1335 | numpages * PAGE_SIZE); | |
9f4c815c | 1336 | } |
de5097c2 | 1337 | |
12d6f21e IM |
1338 | /* |
1339 | * If page allocator is not up yet then do not call c_p_a(): | |
1340 | */ | |
1341 | if (!debug_pagealloc_enabled) | |
1342 | return; | |
1343 | ||
9f4c815c | 1344 | /* |
f8d8406b | 1345 | * The return value is ignored as the calls cannot fail. |
55121b43 SS |
1346 | * Large pages for identity mappings are not used at boot time |
1347 | * and hence no memory allocations during large page split. | |
1da177e4 | 1348 | */ |
f62d0f00 IM |
1349 | if (enable) |
1350 | __set_pages_p(page, numpages); | |
1351 | else | |
1352 | __set_pages_np(page, numpages); | |
9f4c815c IM |
1353 | |
1354 | /* | |
e4b71dcf IM |
1355 | * We should perform an IPI and flush all tlbs, |
1356 | * but that can deadlock->flush only current cpu: | |
1da177e4 LT |
1357 | */ |
1358 | __flush_tlb_all(); | |
ee7ae7a1 TG |
1359 | } |
1360 | ||
8a235efa RW |
1361 | #ifdef CONFIG_HIBERNATION |
1362 | ||
1363 | bool kernel_page_present(struct page *page) | |
1364 | { | |
1365 | unsigned int level; | |
1366 | pte_t *pte; | |
1367 | ||
1368 | if (PageHighMem(page)) | |
1369 | return false; | |
1370 | ||
1371 | pte = lookup_address((unsigned long)page_address(page), &level); | |
1372 | return (pte_val(*pte) & _PAGE_PRESENT); | |
1373 | } | |
1374 | ||
1375 | #endif /* CONFIG_HIBERNATION */ | |
1376 | ||
1377 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
d1028a15 AV |
1378 | |
1379 | /* | |
1380 | * The testcases use internal knowledge of the implementation that shouldn't | |
1381 | * be exposed to the rest of the kernel. Include these directly here. | |
1382 | */ | |
1383 | #ifdef CONFIG_CPA_DEBUG | |
1384 | #include "pageattr-test.c" | |
1385 | #endif |