Commit | Line | Data |
---|---|---|
9f4c815c IM |
1 | /* |
2 | * Copyright 2002 Andi Kleen, SuSE Labs. | |
1da177e4 | 3 | * Thanks to Ben LaHaise for precious feedback. |
9f4c815c | 4 | */ |
1da177e4 | 5 | #include <linux/highmem.h> |
8192206d | 6 | #include <linux/bootmem.h> |
1da177e4 | 7 | #include <linux/module.h> |
9f4c815c | 8 | #include <linux/sched.h> |
1da177e4 | 9 | #include <linux/slab.h> |
9f4c815c | 10 | #include <linux/mm.h> |
76ebd054 | 11 | #include <linux/interrupt.h> |
ee7ae7a1 TG |
12 | #include <linux/seq_file.h> |
13 | #include <linux/debugfs.h> | |
e59a1bb2 | 14 | #include <linux/pfn.h> |
8c4bfc6e | 15 | #include <linux/percpu.h> |
9f4c815c | 16 | |
950f9d95 | 17 | #include <asm/e820.h> |
1da177e4 LT |
18 | #include <asm/processor.h> |
19 | #include <asm/tlbflush.h> | |
f8af095d | 20 | #include <asm/sections.h> |
93dbda7c | 21 | #include <asm/setup.h> |
9f4c815c IM |
22 | #include <asm/uaccess.h> |
23 | #include <asm/pgalloc.h> | |
c31c7d48 | 24 | #include <asm/proto.h> |
1219333d | 25 | #include <asm/pat.h> |
1da177e4 | 26 | |
9df84993 IM |
27 | /* |
28 | * The current flushing context - we pass it instead of 5 arguments: | |
29 | */ | |
72e458df | 30 | struct cpa_data { |
d75586ad | 31 | unsigned long *vaddr; |
72e458df TG |
32 | pgprot_t mask_set; |
33 | pgprot_t mask_clr; | |
65e074df | 34 | int numpages; |
d75586ad | 35 | int flags; |
c31c7d48 | 36 | unsigned long pfn; |
c9caa02c | 37 | unsigned force_split : 1; |
d75586ad | 38 | int curpage; |
9ae28475 | 39 | struct page **pages; |
72e458df TG |
40 | }; |
41 | ||
ad5ca55f SS |
42 | /* |
43 | * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings) | |
44 | * using cpa_lock. So that we don't allow any other cpu, with stale large tlb | |
45 | * entries change the page attribute in parallel to some other cpu | |
46 | * splitting a large page entry along with changing the attribute. | |
47 | */ | |
48 | static DEFINE_SPINLOCK(cpa_lock); | |
49 | ||
d75586ad SL |
50 | #define CPA_FLUSHTLB 1 |
51 | #define CPA_ARRAY 2 | |
9ae28475 | 52 | #define CPA_PAGES_ARRAY 4 |
d75586ad | 53 | |
65280e61 | 54 | #ifdef CONFIG_PROC_FS |
ce0c0e50 AK |
55 | static unsigned long direct_pages_count[PG_LEVEL_NUM]; |
56 | ||
65280e61 | 57 | void update_page_count(int level, unsigned long pages) |
ce0c0e50 | 58 | { |
ce0c0e50 | 59 | unsigned long flags; |
65280e61 | 60 | |
ce0c0e50 AK |
61 | /* Protect against CPA */ |
62 | spin_lock_irqsave(&pgd_lock, flags); | |
63 | direct_pages_count[level] += pages; | |
64 | spin_unlock_irqrestore(&pgd_lock, flags); | |
65280e61 TG |
65 | } |
66 | ||
67 | static void split_page_count(int level) | |
68 | { | |
69 | direct_pages_count[level]--; | |
70 | direct_pages_count[level - 1] += PTRS_PER_PTE; | |
71 | } | |
72 | ||
e1759c21 | 73 | void arch_report_meminfo(struct seq_file *m) |
65280e61 | 74 | { |
b9c3bfc2 | 75 | seq_printf(m, "DirectMap4k: %8lu kB\n", |
a06de630 HD |
76 | direct_pages_count[PG_LEVEL_4K] << 2); |
77 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
b9c3bfc2 | 78 | seq_printf(m, "DirectMap2M: %8lu kB\n", |
a06de630 HD |
79 | direct_pages_count[PG_LEVEL_2M] << 11); |
80 | #else | |
b9c3bfc2 | 81 | seq_printf(m, "DirectMap4M: %8lu kB\n", |
a06de630 HD |
82 | direct_pages_count[PG_LEVEL_2M] << 12); |
83 | #endif | |
65280e61 | 84 | #ifdef CONFIG_X86_64 |
a06de630 | 85 | if (direct_gbpages) |
b9c3bfc2 | 86 | seq_printf(m, "DirectMap1G: %8lu kB\n", |
a06de630 | 87 | direct_pages_count[PG_LEVEL_1G] << 20); |
ce0c0e50 AK |
88 | #endif |
89 | } | |
65280e61 TG |
90 | #else |
91 | static inline void split_page_count(int level) { } | |
92 | #endif | |
ce0c0e50 | 93 | |
c31c7d48 TG |
94 | #ifdef CONFIG_X86_64 |
95 | ||
96 | static inline unsigned long highmap_start_pfn(void) | |
97 | { | |
98 | return __pa(_text) >> PAGE_SHIFT; | |
99 | } | |
100 | ||
101 | static inline unsigned long highmap_end_pfn(void) | |
102 | { | |
93dbda7c | 103 | return __pa(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT; |
c31c7d48 TG |
104 | } |
105 | ||
106 | #endif | |
107 | ||
92cb54a3 IM |
108 | #ifdef CONFIG_DEBUG_PAGEALLOC |
109 | # define debug_pagealloc 1 | |
110 | #else | |
111 | # define debug_pagealloc 0 | |
112 | #endif | |
113 | ||
ed724be6 AV |
114 | static inline int |
115 | within(unsigned long addr, unsigned long start, unsigned long end) | |
687c4825 | 116 | { |
ed724be6 AV |
117 | return addr >= start && addr < end; |
118 | } | |
119 | ||
d7c8f21a TG |
120 | /* |
121 | * Flushing functions | |
122 | */ | |
cd8ddf1a | 123 | |
cd8ddf1a TG |
124 | /** |
125 | * clflush_cache_range - flush a cache range with clflush | |
126 | * @addr: virtual start address | |
127 | * @size: number of bytes to flush | |
128 | * | |
129 | * clflush is an unordered instruction which needs fencing with mfence | |
130 | * to avoid ordering issues. | |
131 | */ | |
4c61afcd | 132 | void clflush_cache_range(void *vaddr, unsigned int size) |
d7c8f21a | 133 | { |
4c61afcd | 134 | void *vend = vaddr + size - 1; |
d7c8f21a | 135 | |
cd8ddf1a | 136 | mb(); |
4c61afcd IM |
137 | |
138 | for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size) | |
139 | clflush(vaddr); | |
140 | /* | |
141 | * Flush any possible final partial cacheline: | |
142 | */ | |
143 | clflush(vend); | |
144 | ||
cd8ddf1a | 145 | mb(); |
d7c8f21a | 146 | } |
e517a5e9 | 147 | EXPORT_SYMBOL_GPL(clflush_cache_range); |
d7c8f21a | 148 | |
af1e6844 | 149 | static void __cpa_flush_all(void *arg) |
d7c8f21a | 150 | { |
6bb8383b AK |
151 | unsigned long cache = (unsigned long)arg; |
152 | ||
d7c8f21a TG |
153 | /* |
154 | * Flush all to work around Errata in early athlons regarding | |
155 | * large page flushing. | |
156 | */ | |
157 | __flush_tlb_all(); | |
158 | ||
0b827537 | 159 | if (cache && boot_cpu_data.x86 >= 4) |
d7c8f21a TG |
160 | wbinvd(); |
161 | } | |
162 | ||
6bb8383b | 163 | static void cpa_flush_all(unsigned long cache) |
d7c8f21a TG |
164 | { |
165 | BUG_ON(irqs_disabled()); | |
166 | ||
15c8b6c1 | 167 | on_each_cpu(__cpa_flush_all, (void *) cache, 1); |
d7c8f21a TG |
168 | } |
169 | ||
57a6a46a TG |
170 | static void __cpa_flush_range(void *arg) |
171 | { | |
57a6a46a TG |
172 | /* |
173 | * We could optimize that further and do individual per page | |
174 | * tlb invalidates for a low number of pages. Caveat: we must | |
175 | * flush the high aliases on 64bit as well. | |
176 | */ | |
177 | __flush_tlb_all(); | |
57a6a46a TG |
178 | } |
179 | ||
6bb8383b | 180 | static void cpa_flush_range(unsigned long start, int numpages, int cache) |
57a6a46a | 181 | { |
4c61afcd IM |
182 | unsigned int i, level; |
183 | unsigned long addr; | |
184 | ||
57a6a46a | 185 | BUG_ON(irqs_disabled()); |
4c61afcd | 186 | WARN_ON(PAGE_ALIGN(start) != start); |
57a6a46a | 187 | |
15c8b6c1 | 188 | on_each_cpu(__cpa_flush_range, NULL, 1); |
57a6a46a | 189 | |
6bb8383b AK |
190 | if (!cache) |
191 | return; | |
192 | ||
3b233e52 TG |
193 | /* |
194 | * We only need to flush on one CPU, | |
195 | * clflush is a MESI-coherent instruction that | |
196 | * will cause all other CPUs to flush the same | |
197 | * cachelines: | |
198 | */ | |
4c61afcd IM |
199 | for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) { |
200 | pte_t *pte = lookup_address(addr, &level); | |
201 | ||
202 | /* | |
203 | * Only flush present addresses: | |
204 | */ | |
7bfb72e8 | 205 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) |
4c61afcd IM |
206 | clflush_cache_range((void *) addr, PAGE_SIZE); |
207 | } | |
57a6a46a TG |
208 | } |
209 | ||
9ae28475 | 210 | static void cpa_flush_array(unsigned long *start, int numpages, int cache, |
211 | int in_flags, struct page **pages) | |
d75586ad SL |
212 | { |
213 | unsigned int i, level; | |
2171787b | 214 | unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */ |
d75586ad SL |
215 | |
216 | BUG_ON(irqs_disabled()); | |
217 | ||
2171787b | 218 | on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1); |
d75586ad | 219 | |
2171787b | 220 | if (!cache || do_wbinvd) |
d75586ad SL |
221 | return; |
222 | ||
d75586ad SL |
223 | /* |
224 | * We only need to flush on one CPU, | |
225 | * clflush is a MESI-coherent instruction that | |
226 | * will cause all other CPUs to flush the same | |
227 | * cachelines: | |
228 | */ | |
9ae28475 | 229 | for (i = 0; i < numpages; i++) { |
230 | unsigned long addr; | |
231 | pte_t *pte; | |
232 | ||
233 | if (in_flags & CPA_PAGES_ARRAY) | |
234 | addr = (unsigned long)page_address(pages[i]); | |
235 | else | |
236 | addr = start[i]; | |
237 | ||
238 | pte = lookup_address(addr, &level); | |
d75586ad SL |
239 | |
240 | /* | |
241 | * Only flush present addresses: | |
242 | */ | |
243 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) | |
9ae28475 | 244 | clflush_cache_range((void *)addr, PAGE_SIZE); |
d75586ad SL |
245 | } |
246 | } | |
247 | ||
ed724be6 AV |
248 | /* |
249 | * Certain areas of memory on x86 require very specific protection flags, | |
250 | * for example the BIOS area or kernel text. Callers don't always get this | |
251 | * right (again, ioremap() on BIOS memory is not uncommon) so this function | |
252 | * checks and fixes these known static required protection bits. | |
253 | */ | |
c31c7d48 TG |
254 | static inline pgprot_t static_protections(pgprot_t prot, unsigned long address, |
255 | unsigned long pfn) | |
ed724be6 AV |
256 | { |
257 | pgprot_t forbidden = __pgprot(0); | |
258 | ||
687c4825 | 259 | /* |
ed724be6 AV |
260 | * The BIOS area between 640k and 1Mb needs to be executable for |
261 | * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support. | |
687c4825 | 262 | */ |
c31c7d48 | 263 | if (within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT)) |
ed724be6 AV |
264 | pgprot_val(forbidden) |= _PAGE_NX; |
265 | ||
266 | /* | |
267 | * The kernel text needs to be executable for obvious reasons | |
c31c7d48 TG |
268 | * Does not cover __inittext since that is gone later on. On |
269 | * 64bit we do not enforce !NX on the low mapping | |
ed724be6 AV |
270 | */ |
271 | if (within(address, (unsigned long)_text, (unsigned long)_etext)) | |
272 | pgprot_val(forbidden) |= _PAGE_NX; | |
cc0f21bb | 273 | |
cc0f21bb | 274 | /* |
c31c7d48 TG |
275 | * The .rodata section needs to be read-only. Using the pfn |
276 | * catches all aliases. | |
cc0f21bb | 277 | */ |
c31c7d48 TG |
278 | if (within(pfn, __pa((unsigned long)__start_rodata) >> PAGE_SHIFT, |
279 | __pa((unsigned long)__end_rodata) >> PAGE_SHIFT)) | |
cc0f21bb | 280 | pgprot_val(forbidden) |= _PAGE_RW; |
ed724be6 AV |
281 | |
282 | prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden)); | |
687c4825 IM |
283 | |
284 | return prot; | |
285 | } | |
286 | ||
9a14aefc TG |
287 | /* |
288 | * Lookup the page table entry for a virtual address. Return a pointer | |
289 | * to the entry and the level of the mapping. | |
290 | * | |
291 | * Note: We return pud and pmd either when the entry is marked large | |
292 | * or when the present bit is not set. Otherwise we would return a | |
293 | * pointer to a nonexisting mapping. | |
294 | */ | |
da7bfc50 | 295 | pte_t *lookup_address(unsigned long address, unsigned int *level) |
9f4c815c | 296 | { |
1da177e4 LT |
297 | pgd_t *pgd = pgd_offset_k(address); |
298 | pud_t *pud; | |
299 | pmd_t *pmd; | |
9f4c815c | 300 | |
30551bb3 TG |
301 | *level = PG_LEVEL_NONE; |
302 | ||
1da177e4 LT |
303 | if (pgd_none(*pgd)) |
304 | return NULL; | |
9df84993 | 305 | |
1da177e4 LT |
306 | pud = pud_offset(pgd, address); |
307 | if (pud_none(*pud)) | |
308 | return NULL; | |
c2f71ee2 AK |
309 | |
310 | *level = PG_LEVEL_1G; | |
311 | if (pud_large(*pud) || !pud_present(*pud)) | |
312 | return (pte_t *)pud; | |
313 | ||
1da177e4 LT |
314 | pmd = pmd_offset(pud, address); |
315 | if (pmd_none(*pmd)) | |
316 | return NULL; | |
30551bb3 TG |
317 | |
318 | *level = PG_LEVEL_2M; | |
9a14aefc | 319 | if (pmd_large(*pmd) || !pmd_present(*pmd)) |
1da177e4 | 320 | return (pte_t *)pmd; |
1da177e4 | 321 | |
30551bb3 | 322 | *level = PG_LEVEL_4K; |
9df84993 | 323 | |
9f4c815c IM |
324 | return pte_offset_kernel(pmd, address); |
325 | } | |
75bb8835 | 326 | EXPORT_SYMBOL_GPL(lookup_address); |
9f4c815c | 327 | |
9df84993 IM |
328 | /* |
329 | * Set the new pmd in all the pgds we know about: | |
330 | */ | |
9a3dc780 | 331 | static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) |
9f4c815c | 332 | { |
9f4c815c IM |
333 | /* change init_mm */ |
334 | set_pte_atomic(kpte, pte); | |
44af6c41 | 335 | #ifdef CONFIG_X86_32 |
e4b71dcf | 336 | if (!SHARED_KERNEL_PMD) { |
44af6c41 IM |
337 | struct page *page; |
338 | ||
e3ed910d | 339 | list_for_each_entry(page, &pgd_list, lru) { |
44af6c41 IM |
340 | pgd_t *pgd; |
341 | pud_t *pud; | |
342 | pmd_t *pmd; | |
343 | ||
344 | pgd = (pgd_t *)page_address(page) + pgd_index(address); | |
345 | pud = pud_offset(pgd, address); | |
346 | pmd = pmd_offset(pud, address); | |
347 | set_pte_atomic((pte_t *)pmd, pte); | |
348 | } | |
1da177e4 | 349 | } |
44af6c41 | 350 | #endif |
1da177e4 LT |
351 | } |
352 | ||
9df84993 IM |
353 | static int |
354 | try_preserve_large_page(pte_t *kpte, unsigned long address, | |
355 | struct cpa_data *cpa) | |
65e074df | 356 | { |
c31c7d48 | 357 | unsigned long nextpage_addr, numpages, pmask, psize, flags, addr, pfn; |
65e074df TG |
358 | pte_t new_pte, old_pte, *tmp; |
359 | pgprot_t old_prot, new_prot; | |
fac84939 | 360 | int i, do_split = 1; |
da7bfc50 | 361 | unsigned int level; |
65e074df | 362 | |
c9caa02c AK |
363 | if (cpa->force_split) |
364 | return 1; | |
365 | ||
65e074df TG |
366 | spin_lock_irqsave(&pgd_lock, flags); |
367 | /* | |
368 | * Check for races, another CPU might have split this page | |
369 | * up already: | |
370 | */ | |
371 | tmp = lookup_address(address, &level); | |
372 | if (tmp != kpte) | |
373 | goto out_unlock; | |
374 | ||
375 | switch (level) { | |
376 | case PG_LEVEL_2M: | |
31422c51 AK |
377 | psize = PMD_PAGE_SIZE; |
378 | pmask = PMD_PAGE_MASK; | |
65e074df | 379 | break; |
f07333fd | 380 | #ifdef CONFIG_X86_64 |
65e074df | 381 | case PG_LEVEL_1G: |
5d3c8b21 AK |
382 | psize = PUD_PAGE_SIZE; |
383 | pmask = PUD_PAGE_MASK; | |
f07333fd AK |
384 | break; |
385 | #endif | |
65e074df | 386 | default: |
beaff633 | 387 | do_split = -EINVAL; |
65e074df TG |
388 | goto out_unlock; |
389 | } | |
390 | ||
391 | /* | |
392 | * Calculate the number of pages, which fit into this large | |
393 | * page starting at address: | |
394 | */ | |
395 | nextpage_addr = (address + psize) & pmask; | |
396 | numpages = (nextpage_addr - address) >> PAGE_SHIFT; | |
9b5cf48b RW |
397 | if (numpages < cpa->numpages) |
398 | cpa->numpages = numpages; | |
65e074df TG |
399 | |
400 | /* | |
401 | * We are safe now. Check whether the new pgprot is the same: | |
402 | */ | |
403 | old_pte = *kpte; | |
404 | old_prot = new_prot = pte_pgprot(old_pte); | |
405 | ||
406 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); | |
407 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
c31c7d48 TG |
408 | |
409 | /* | |
410 | * old_pte points to the large page base address. So we need | |
411 | * to add the offset of the virtual address: | |
412 | */ | |
413 | pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT); | |
414 | cpa->pfn = pfn; | |
415 | ||
416 | new_prot = static_protections(new_prot, address, pfn); | |
65e074df | 417 | |
fac84939 TG |
418 | /* |
419 | * We need to check the full range, whether | |
420 | * static_protection() requires a different pgprot for one of | |
421 | * the pages in the range we try to preserve: | |
422 | */ | |
423 | addr = address + PAGE_SIZE; | |
c31c7d48 | 424 | pfn++; |
9b5cf48b | 425 | for (i = 1; i < cpa->numpages; i++, addr += PAGE_SIZE, pfn++) { |
c31c7d48 | 426 | pgprot_t chk_prot = static_protections(new_prot, addr, pfn); |
fac84939 TG |
427 | |
428 | if (pgprot_val(chk_prot) != pgprot_val(new_prot)) | |
429 | goto out_unlock; | |
430 | } | |
431 | ||
65e074df TG |
432 | /* |
433 | * If there are no changes, return. maxpages has been updated | |
434 | * above: | |
435 | */ | |
436 | if (pgprot_val(new_prot) == pgprot_val(old_prot)) { | |
beaff633 | 437 | do_split = 0; |
65e074df TG |
438 | goto out_unlock; |
439 | } | |
440 | ||
441 | /* | |
442 | * We need to change the attributes. Check, whether we can | |
443 | * change the large page in one go. We request a split, when | |
444 | * the address is not aligned and the number of pages is | |
445 | * smaller than the number of pages in the large page. Note | |
446 | * that we limited the number of possible pages already to | |
447 | * the number of pages in the large page. | |
448 | */ | |
9b5cf48b | 449 | if (address == (nextpage_addr - psize) && cpa->numpages == numpages) { |
65e074df TG |
450 | /* |
451 | * The address is aligned and the number of pages | |
452 | * covers the full page. | |
453 | */ | |
454 | new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot)); | |
455 | __set_pmd_pte(kpte, address, new_pte); | |
d75586ad | 456 | cpa->flags |= CPA_FLUSHTLB; |
beaff633 | 457 | do_split = 0; |
65e074df TG |
458 | } |
459 | ||
460 | out_unlock: | |
461 | spin_unlock_irqrestore(&pgd_lock, flags); | |
9df84993 | 462 | |
beaff633 | 463 | return do_split; |
65e074df TG |
464 | } |
465 | ||
7afe15b9 | 466 | static int split_large_page(pte_t *kpte, unsigned long address) |
bb5c2dbd | 467 | { |
7b610eec | 468 | unsigned long flags, pfn, pfninc = 1; |
9df84993 | 469 | unsigned int i, level; |
bb5c2dbd | 470 | pte_t *pbase, *tmp; |
9df84993 | 471 | pgprot_t ref_prot; |
ad5ca55f SS |
472 | struct page *base; |
473 | ||
474 | if (!debug_pagealloc) | |
475 | spin_unlock(&cpa_lock); | |
9e730237 | 476 | base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0); |
ad5ca55f SS |
477 | if (!debug_pagealloc) |
478 | spin_lock(&cpa_lock); | |
8311eb84 SS |
479 | if (!base) |
480 | return -ENOMEM; | |
bb5c2dbd | 481 | |
eb5b5f02 | 482 | spin_lock_irqsave(&pgd_lock, flags); |
bb5c2dbd IM |
483 | /* |
484 | * Check for races, another CPU might have split this page | |
485 | * up for us already: | |
486 | */ | |
487 | tmp = lookup_address(address, &level); | |
6ce9fc17 | 488 | if (tmp != kpte) |
bb5c2dbd IM |
489 | goto out_unlock; |
490 | ||
bb5c2dbd | 491 | pbase = (pte_t *)page_address(base); |
6944a9c8 | 492 | paravirt_alloc_pte(&init_mm, page_to_pfn(base)); |
07cf89c0 | 493 | ref_prot = pte_pgprot(pte_clrhuge(*kpte)); |
7a5714e0 IM |
494 | /* |
495 | * If we ever want to utilize the PAT bit, we need to | |
496 | * update this function to make sure it's converted from | |
497 | * bit 12 to bit 7 when we cross from the 2MB level to | |
498 | * the 4K level: | |
499 | */ | |
500 | WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE); | |
bb5c2dbd | 501 | |
f07333fd AK |
502 | #ifdef CONFIG_X86_64 |
503 | if (level == PG_LEVEL_1G) { | |
504 | pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT; | |
505 | pgprot_val(ref_prot) |= _PAGE_PSE; | |
f07333fd AK |
506 | } |
507 | #endif | |
508 | ||
63c1dcf4 TG |
509 | /* |
510 | * Get the target pfn from the original entry: | |
511 | */ | |
512 | pfn = pte_pfn(*kpte); | |
f07333fd | 513 | for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc) |
63c1dcf4 | 514 | set_pte(&pbase[i], pfn_pte(pfn, ref_prot)); |
bb5c2dbd | 515 | |
ce0c0e50 | 516 | if (address >= (unsigned long)__va(0) && |
f361a450 YL |
517 | address < (unsigned long)__va(max_low_pfn_mapped << PAGE_SHIFT)) |
518 | split_page_count(level); | |
519 | ||
520 | #ifdef CONFIG_X86_64 | |
521 | if (address >= (unsigned long)__va(1UL<<32) && | |
65280e61 TG |
522 | address < (unsigned long)__va(max_pfn_mapped << PAGE_SHIFT)) |
523 | split_page_count(level); | |
f361a450 | 524 | #endif |
ce0c0e50 | 525 | |
bb5c2dbd | 526 | /* |
07a66d7c | 527 | * Install the new, split up pagetable. |
4c881ca1 | 528 | * |
07a66d7c IM |
529 | * We use the standard kernel pagetable protections for the new |
530 | * pagetable protections, the actual ptes set above control the | |
531 | * primary protection behavior: | |
bb5c2dbd | 532 | */ |
07a66d7c | 533 | __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); |
211b3d03 IM |
534 | |
535 | /* | |
536 | * Intel Atom errata AAH41 workaround. | |
537 | * | |
538 | * The real fix should be in hw or in a microcode update, but | |
539 | * we also probabilistically try to reduce the window of having | |
540 | * a large TLB mixed with 4K TLBs while instruction fetches are | |
541 | * going on. | |
542 | */ | |
543 | __flush_tlb_all(); | |
544 | ||
bb5c2dbd IM |
545 | base = NULL; |
546 | ||
547 | out_unlock: | |
eb5b5f02 TG |
548 | /* |
549 | * If we dropped out via the lookup_address check under | |
550 | * pgd_lock then stick the page back into the pool: | |
551 | */ | |
8311eb84 SS |
552 | if (base) |
553 | __free_page(base); | |
9a3dc780 | 554 | spin_unlock_irqrestore(&pgd_lock, flags); |
bb5c2dbd | 555 | |
bb5c2dbd IM |
556 | return 0; |
557 | } | |
558 | ||
a1e46212 SS |
559 | static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr, |
560 | int primary) | |
561 | { | |
562 | /* | |
563 | * Ignore all non primary paths. | |
564 | */ | |
565 | if (!primary) | |
566 | return 0; | |
567 | ||
568 | /* | |
569 | * Ignore the NULL PTE for kernel identity mapping, as it is expected | |
570 | * to have holes. | |
571 | * Also set numpages to '1' indicating that we processed cpa req for | |
572 | * one virtual address page and its pfn. TBD: numpages can be set based | |
573 | * on the initial value and the level returned by lookup_address(). | |
574 | */ | |
575 | if (within(vaddr, PAGE_OFFSET, | |
576 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) { | |
577 | cpa->numpages = 1; | |
578 | cpa->pfn = __pa(vaddr) >> PAGE_SHIFT; | |
579 | return 0; | |
580 | } else { | |
581 | WARN(1, KERN_WARNING "CPA: called for zero pte. " | |
582 | "vaddr = %lx cpa->vaddr = %lx\n", vaddr, | |
583 | *cpa->vaddr); | |
584 | ||
585 | return -EFAULT; | |
586 | } | |
587 | } | |
588 | ||
c31c7d48 | 589 | static int __change_page_attr(struct cpa_data *cpa, int primary) |
9f4c815c | 590 | { |
d75586ad | 591 | unsigned long address; |
da7bfc50 HH |
592 | int do_split, err; |
593 | unsigned int level; | |
c31c7d48 | 594 | pte_t *kpte, old_pte; |
1da177e4 | 595 | |
8523acfe TH |
596 | if (cpa->flags & CPA_PAGES_ARRAY) { |
597 | struct page *page = cpa->pages[cpa->curpage]; | |
598 | if (unlikely(PageHighMem(page))) | |
599 | return 0; | |
600 | address = (unsigned long)page_address(page); | |
601 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
602 | address = cpa->vaddr[cpa->curpage]; |
603 | else | |
604 | address = *cpa->vaddr; | |
97f99fed | 605 | repeat: |
f0646e43 | 606 | kpte = lookup_address(address, &level); |
1da177e4 | 607 | if (!kpte) |
a1e46212 | 608 | return __cpa_process_fault(cpa, address, primary); |
c31c7d48 TG |
609 | |
610 | old_pte = *kpte; | |
a1e46212 SS |
611 | if (!pte_val(old_pte)) |
612 | return __cpa_process_fault(cpa, address, primary); | |
9f4c815c | 613 | |
30551bb3 | 614 | if (level == PG_LEVEL_4K) { |
c31c7d48 | 615 | pte_t new_pte; |
626c2c9d | 616 | pgprot_t new_prot = pte_pgprot(old_pte); |
c31c7d48 | 617 | unsigned long pfn = pte_pfn(old_pte); |
86f03989 | 618 | |
72e458df TG |
619 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); |
620 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
86f03989 | 621 | |
c31c7d48 | 622 | new_prot = static_protections(new_prot, address, pfn); |
86f03989 | 623 | |
626c2c9d AV |
624 | /* |
625 | * We need to keep the pfn from the existing PTE, | |
626 | * after all we're only going to change it's attributes | |
627 | * not the memory it points to | |
628 | */ | |
c31c7d48 TG |
629 | new_pte = pfn_pte(pfn, canon_pgprot(new_prot)); |
630 | cpa->pfn = pfn; | |
f4ae5da0 TG |
631 | /* |
632 | * Do we really change anything ? | |
633 | */ | |
634 | if (pte_val(old_pte) != pte_val(new_pte)) { | |
635 | set_pte_atomic(kpte, new_pte); | |
d75586ad | 636 | cpa->flags |= CPA_FLUSHTLB; |
f4ae5da0 | 637 | } |
9b5cf48b | 638 | cpa->numpages = 1; |
65e074df | 639 | return 0; |
1da177e4 | 640 | } |
65e074df TG |
641 | |
642 | /* | |
643 | * Check, whether we can keep the large page intact | |
644 | * and just change the pte: | |
645 | */ | |
beaff633 | 646 | do_split = try_preserve_large_page(kpte, address, cpa); |
65e074df TG |
647 | /* |
648 | * When the range fits into the existing large page, | |
9b5cf48b | 649 | * return. cp->numpages and cpa->tlbflush have been updated in |
65e074df TG |
650 | * try_large_page: |
651 | */ | |
87f7f8fe IM |
652 | if (do_split <= 0) |
653 | return do_split; | |
65e074df TG |
654 | |
655 | /* | |
656 | * We have to split the large page: | |
657 | */ | |
87f7f8fe IM |
658 | err = split_large_page(kpte, address); |
659 | if (!err) { | |
ad5ca55f SS |
660 | /* |
661 | * Do a global flush tlb after splitting the large page | |
662 | * and before we do the actual change page attribute in the PTE. | |
663 | * | |
664 | * With out this, we violate the TLB application note, that says | |
665 | * "The TLBs may contain both ordinary and large-page | |
666 | * translations for a 4-KByte range of linear addresses. This | |
667 | * may occur if software modifies the paging structures so that | |
668 | * the page size used for the address range changes. If the two | |
669 | * translations differ with respect to page frame or attributes | |
670 | * (e.g., permissions), processor behavior is undefined and may | |
671 | * be implementation-specific." | |
672 | * | |
673 | * We do this global tlb flush inside the cpa_lock, so that we | |
674 | * don't allow any other cpu, with stale tlb entries change the | |
675 | * page attribute in parallel, that also falls into the | |
676 | * just split large page entry. | |
677 | */ | |
678 | flush_tlb_all(); | |
87f7f8fe IM |
679 | goto repeat; |
680 | } | |
beaff633 | 681 | |
87f7f8fe | 682 | return err; |
9f4c815c | 683 | } |
1da177e4 | 684 | |
c31c7d48 TG |
685 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias); |
686 | ||
687 | static int cpa_process_alias(struct cpa_data *cpa) | |
1da177e4 | 688 | { |
c31c7d48 | 689 | struct cpa_data alias_cpa; |
992f4c1c | 690 | unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT); |
e933a73f | 691 | unsigned long vaddr; |
992f4c1c | 692 | int ret; |
44af6c41 | 693 | |
965194c1 | 694 | if (cpa->pfn >= max_pfn_mapped) |
c31c7d48 | 695 | return 0; |
626c2c9d | 696 | |
f361a450 | 697 | #ifdef CONFIG_X86_64 |
965194c1 | 698 | if (cpa->pfn >= max_low_pfn_mapped && cpa->pfn < (1UL<<(32-PAGE_SHIFT))) |
f361a450 YL |
699 | return 0; |
700 | #endif | |
f34b439f TG |
701 | /* |
702 | * No need to redo, when the primary call touched the direct | |
703 | * mapping already: | |
704 | */ | |
8523acfe TH |
705 | if (cpa->flags & CPA_PAGES_ARRAY) { |
706 | struct page *page = cpa->pages[cpa->curpage]; | |
707 | if (unlikely(PageHighMem(page))) | |
708 | return 0; | |
709 | vaddr = (unsigned long)page_address(page); | |
710 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
711 | vaddr = cpa->vaddr[cpa->curpage]; |
712 | else | |
713 | vaddr = *cpa->vaddr; | |
714 | ||
715 | if (!(within(vaddr, PAGE_OFFSET, | |
a1e46212 | 716 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) { |
44af6c41 | 717 | |
f34b439f | 718 | alias_cpa = *cpa; |
992f4c1c | 719 | alias_cpa.vaddr = &laddr; |
9ae28475 | 720 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); |
d75586ad | 721 | |
f34b439f | 722 | ret = __change_page_attr_set_clr(&alias_cpa, 0); |
992f4c1c TH |
723 | if (ret) |
724 | return ret; | |
f34b439f | 725 | } |
44af6c41 | 726 | |
44af6c41 | 727 | #ifdef CONFIG_X86_64 |
488fd995 | 728 | /* |
992f4c1c TH |
729 | * If the primary call didn't touch the high mapping already |
730 | * and the physical address is inside the kernel map, we need | |
0879750f | 731 | * to touch the high mapped kernel as well: |
488fd995 | 732 | */ |
992f4c1c TH |
733 | if (!within(vaddr, (unsigned long)_text, _brk_end) && |
734 | within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) { | |
735 | unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) + | |
736 | __START_KERNEL_map - phys_base; | |
737 | alias_cpa = *cpa; | |
738 | alias_cpa.vaddr = &temp_cpa_vaddr; | |
739 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); | |
c31c7d48 | 740 | |
992f4c1c TH |
741 | /* |
742 | * The high mapping range is imprecise, so ignore the | |
743 | * return value. | |
744 | */ | |
745 | __change_page_attr_set_clr(&alias_cpa, 0); | |
746 | } | |
488fd995 | 747 | #endif |
992f4c1c TH |
748 | |
749 | return 0; | |
1da177e4 LT |
750 | } |
751 | ||
c31c7d48 | 752 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias) |
ff31452b | 753 | { |
65e074df | 754 | int ret, numpages = cpa->numpages; |
ff31452b | 755 | |
65e074df TG |
756 | while (numpages) { |
757 | /* | |
758 | * Store the remaining nr of pages for the large page | |
759 | * preservation check. | |
760 | */ | |
9b5cf48b | 761 | cpa->numpages = numpages; |
d75586ad | 762 | /* for array changes, we can't use large page */ |
9ae28475 | 763 | if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
d75586ad | 764 | cpa->numpages = 1; |
c31c7d48 | 765 | |
ad5ca55f SS |
766 | if (!debug_pagealloc) |
767 | spin_lock(&cpa_lock); | |
c31c7d48 | 768 | ret = __change_page_attr(cpa, checkalias); |
ad5ca55f SS |
769 | if (!debug_pagealloc) |
770 | spin_unlock(&cpa_lock); | |
ff31452b TG |
771 | if (ret) |
772 | return ret; | |
ff31452b | 773 | |
c31c7d48 TG |
774 | if (checkalias) { |
775 | ret = cpa_process_alias(cpa); | |
776 | if (ret) | |
777 | return ret; | |
778 | } | |
779 | ||
65e074df TG |
780 | /* |
781 | * Adjust the number of pages with the result of the | |
782 | * CPA operation. Either a large page has been | |
783 | * preserved or a single page update happened. | |
784 | */ | |
9b5cf48b RW |
785 | BUG_ON(cpa->numpages > numpages); |
786 | numpages -= cpa->numpages; | |
9ae28475 | 787 | if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) |
d75586ad SL |
788 | cpa->curpage++; |
789 | else | |
790 | *cpa->vaddr += cpa->numpages * PAGE_SIZE; | |
791 | ||
65e074df | 792 | } |
ff31452b TG |
793 | return 0; |
794 | } | |
795 | ||
6bb8383b AK |
796 | static inline int cache_attr(pgprot_t attr) |
797 | { | |
798 | return pgprot_val(attr) & | |
799 | (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD); | |
800 | } | |
801 | ||
d75586ad | 802 | static int change_page_attr_set_clr(unsigned long *addr, int numpages, |
c9caa02c | 803 | pgprot_t mask_set, pgprot_t mask_clr, |
9ae28475 | 804 | int force_split, int in_flag, |
805 | struct page **pages) | |
ff31452b | 806 | { |
72e458df | 807 | struct cpa_data cpa; |
cacf8906 | 808 | int ret, cache, checkalias; |
fa526d0d | 809 | unsigned long baddr = 0; |
331e4065 TG |
810 | |
811 | /* | |
812 | * Check, if we are requested to change a not supported | |
813 | * feature: | |
814 | */ | |
815 | mask_set = canon_pgprot(mask_set); | |
816 | mask_clr = canon_pgprot(mask_clr); | |
c9caa02c | 817 | if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split) |
331e4065 TG |
818 | return 0; |
819 | ||
69b1415e | 820 | /* Ensure we are PAGE_SIZE aligned */ |
9ae28475 | 821 | if (in_flag & CPA_ARRAY) { |
d75586ad SL |
822 | int i; |
823 | for (i = 0; i < numpages; i++) { | |
824 | if (addr[i] & ~PAGE_MASK) { | |
825 | addr[i] &= PAGE_MASK; | |
826 | WARN_ON_ONCE(1); | |
827 | } | |
828 | } | |
9ae28475 | 829 | } else if (!(in_flag & CPA_PAGES_ARRAY)) { |
830 | /* | |
831 | * in_flag of CPA_PAGES_ARRAY implies it is aligned. | |
832 | * No need to cehck in that case | |
833 | */ | |
834 | if (*addr & ~PAGE_MASK) { | |
835 | *addr &= PAGE_MASK; | |
836 | /* | |
837 | * People should not be passing in unaligned addresses: | |
838 | */ | |
839 | WARN_ON_ONCE(1); | |
840 | } | |
fa526d0d JS |
841 | /* |
842 | * Save address for cache flush. *addr is modified in the call | |
843 | * to __change_page_attr_set_clr() below. | |
844 | */ | |
845 | baddr = *addr; | |
69b1415e TG |
846 | } |
847 | ||
5843d9a4 NP |
848 | /* Must avoid aliasing mappings in the highmem code */ |
849 | kmap_flush_unused(); | |
850 | ||
db64fe02 NP |
851 | vm_unmap_aliases(); |
852 | ||
72e458df | 853 | cpa.vaddr = addr; |
9ae28475 | 854 | cpa.pages = pages; |
72e458df TG |
855 | cpa.numpages = numpages; |
856 | cpa.mask_set = mask_set; | |
857 | cpa.mask_clr = mask_clr; | |
d75586ad SL |
858 | cpa.flags = 0; |
859 | cpa.curpage = 0; | |
c9caa02c | 860 | cpa.force_split = force_split; |
72e458df | 861 | |
9ae28475 | 862 | if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
863 | cpa.flags |= in_flag; | |
d75586ad | 864 | |
af96e443 TG |
865 | /* No alias checking for _NX bit modifications */ |
866 | checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX; | |
867 | ||
868 | ret = __change_page_attr_set_clr(&cpa, checkalias); | |
ff31452b | 869 | |
f4ae5da0 TG |
870 | /* |
871 | * Check whether we really changed something: | |
872 | */ | |
d75586ad | 873 | if (!(cpa.flags & CPA_FLUSHTLB)) |
1ac2f7d5 | 874 | goto out; |
cacf8906 | 875 | |
6bb8383b AK |
876 | /* |
877 | * No need to flush, when we did not set any of the caching | |
878 | * attributes: | |
879 | */ | |
880 | cache = cache_attr(mask_set); | |
881 | ||
57a6a46a TG |
882 | /* |
883 | * On success we use clflush, when the CPU supports it to | |
884 | * avoid the wbindv. If the CPU does not support it and in the | |
af1e6844 | 885 | * error case we fall back to cpa_flush_all (which uses |
57a6a46a TG |
886 | * wbindv): |
887 | */ | |
d75586ad | 888 | if (!ret && cpu_has_clflush) { |
9ae28475 | 889 | if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) { |
890 | cpa_flush_array(addr, numpages, cache, | |
891 | cpa.flags, pages); | |
892 | } else | |
fa526d0d | 893 | cpa_flush_range(baddr, numpages, cache); |
d75586ad | 894 | } else |
6bb8383b | 895 | cpa_flush_all(cache); |
cacf8906 | 896 | |
76ebd054 | 897 | out: |
ff31452b TG |
898 | return ret; |
899 | } | |
900 | ||
d75586ad SL |
901 | static inline int change_page_attr_set(unsigned long *addr, int numpages, |
902 | pgprot_t mask, int array) | |
75cbade8 | 903 | { |
d75586ad | 904 | return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0, |
9ae28475 | 905 | (array ? CPA_ARRAY : 0), NULL); |
75cbade8 AV |
906 | } |
907 | ||
d75586ad SL |
908 | static inline int change_page_attr_clear(unsigned long *addr, int numpages, |
909 | pgprot_t mask, int array) | |
72932c7a | 910 | { |
d75586ad | 911 | return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0, |
9ae28475 | 912 | (array ? CPA_ARRAY : 0), NULL); |
72932c7a TG |
913 | } |
914 | ||
0f350755 | 915 | static inline int cpa_set_pages_array(struct page **pages, int numpages, |
916 | pgprot_t mask) | |
917 | { | |
918 | return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0, | |
919 | CPA_PAGES_ARRAY, pages); | |
920 | } | |
921 | ||
922 | static inline int cpa_clear_pages_array(struct page **pages, int numpages, | |
923 | pgprot_t mask) | |
924 | { | |
925 | return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0, | |
926 | CPA_PAGES_ARRAY, pages); | |
927 | } | |
928 | ||
1219333d | 929 | int _set_memory_uc(unsigned long addr, int numpages) |
72932c7a | 930 | { |
de33c442 SS |
931 | /* |
932 | * for now UC MINUS. see comments in ioremap_nocache() | |
933 | */ | |
d75586ad SL |
934 | return change_page_attr_set(&addr, numpages, |
935 | __pgprot(_PAGE_CACHE_UC_MINUS), 0); | |
75cbade8 | 936 | } |
1219333d | 937 | |
938 | int set_memory_uc(unsigned long addr, int numpages) | |
939 | { | |
9fa3ab39 | 940 | int ret; |
941 | ||
de33c442 SS |
942 | /* |
943 | * for now UC MINUS. see comments in ioremap_nocache() | |
944 | */ | |
9fa3ab39 | 945 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
946 | _PAGE_CACHE_UC_MINUS, NULL); | |
947 | if (ret) | |
948 | goto out_err; | |
949 | ||
950 | ret = _set_memory_uc(addr, numpages); | |
951 | if (ret) | |
952 | goto out_free; | |
953 | ||
954 | return 0; | |
1219333d | 955 | |
9fa3ab39 | 956 | out_free: |
957 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
958 | out_err: | |
959 | return ret; | |
1219333d | 960 | } |
75cbade8 AV |
961 | EXPORT_SYMBOL(set_memory_uc); |
962 | ||
d75586ad SL |
963 | int set_memory_array_uc(unsigned long *addr, int addrinarray) |
964 | { | |
9fa3ab39 | 965 | int i, j; |
966 | int ret; | |
967 | ||
d75586ad SL |
968 | /* |
969 | * for now UC MINUS. see comments in ioremap_nocache() | |
970 | */ | |
971 | for (i = 0; i < addrinarray; i++) { | |
9fa3ab39 | 972 | ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE, |
973 | _PAGE_CACHE_UC_MINUS, NULL); | |
974 | if (ret) | |
975 | goto out_free; | |
d75586ad SL |
976 | } |
977 | ||
9fa3ab39 | 978 | ret = change_page_attr_set(addr, addrinarray, |
d75586ad | 979 | __pgprot(_PAGE_CACHE_UC_MINUS), 1); |
9fa3ab39 | 980 | if (ret) |
981 | goto out_free; | |
982 | ||
983 | return 0; | |
984 | ||
985 | out_free: | |
986 | for (j = 0; j < i; j++) | |
987 | free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE); | |
988 | ||
989 | return ret; | |
d75586ad SL |
990 | } |
991 | EXPORT_SYMBOL(set_memory_array_uc); | |
992 | ||
ef354af4 | 993 | int _set_memory_wc(unsigned long addr, int numpages) |
994 | { | |
3869c4aa | 995 | int ret; |
bdc6340f PV |
996 | unsigned long addr_copy = addr; |
997 | ||
3869c4aa | 998 | ret = change_page_attr_set(&addr, numpages, |
999 | __pgprot(_PAGE_CACHE_UC_MINUS), 0); | |
3869c4aa | 1000 | if (!ret) { |
bdc6340f PV |
1001 | ret = change_page_attr_set_clr(&addr_copy, numpages, |
1002 | __pgprot(_PAGE_CACHE_WC), | |
1003 | __pgprot(_PAGE_CACHE_MASK), | |
1004 | 0, 0, NULL); | |
3869c4aa | 1005 | } |
1006 | return ret; | |
ef354af4 | 1007 | } |
1008 | ||
1009 | int set_memory_wc(unsigned long addr, int numpages) | |
1010 | { | |
9fa3ab39 | 1011 | int ret; |
1012 | ||
499f8f84 | 1013 | if (!pat_enabled) |
ef354af4 | 1014 | return set_memory_uc(addr, numpages); |
1015 | ||
9fa3ab39 | 1016 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
1017 | _PAGE_CACHE_WC, NULL); | |
1018 | if (ret) | |
1019 | goto out_err; | |
ef354af4 | 1020 | |
9fa3ab39 | 1021 | ret = _set_memory_wc(addr, numpages); |
1022 | if (ret) | |
1023 | goto out_free; | |
1024 | ||
1025 | return 0; | |
1026 | ||
1027 | out_free: | |
1028 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
1029 | out_err: | |
1030 | return ret; | |
ef354af4 | 1031 | } |
1032 | EXPORT_SYMBOL(set_memory_wc); | |
1033 | ||
1219333d | 1034 | int _set_memory_wb(unsigned long addr, int numpages) |
75cbade8 | 1035 | { |
d75586ad SL |
1036 | return change_page_attr_clear(&addr, numpages, |
1037 | __pgprot(_PAGE_CACHE_MASK), 0); | |
75cbade8 | 1038 | } |
1219333d | 1039 | |
1040 | int set_memory_wb(unsigned long addr, int numpages) | |
1041 | { | |
9fa3ab39 | 1042 | int ret; |
1043 | ||
1044 | ret = _set_memory_wb(addr, numpages); | |
1045 | if (ret) | |
1046 | return ret; | |
1047 | ||
c15238df | 1048 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
9fa3ab39 | 1049 | return 0; |
1219333d | 1050 | } |
75cbade8 AV |
1051 | EXPORT_SYMBOL(set_memory_wb); |
1052 | ||
d75586ad SL |
1053 | int set_memory_array_wb(unsigned long *addr, int addrinarray) |
1054 | { | |
1055 | int i; | |
a5593e0b | 1056 | int ret; |
1057 | ||
1058 | ret = change_page_attr_clear(addr, addrinarray, | |
1059 | __pgprot(_PAGE_CACHE_MASK), 1); | |
9fa3ab39 | 1060 | if (ret) |
1061 | return ret; | |
d75586ad | 1062 | |
9fa3ab39 | 1063 | for (i = 0; i < addrinarray; i++) |
1064 | free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE); | |
c5e147cf | 1065 | |
9fa3ab39 | 1066 | return 0; |
d75586ad SL |
1067 | } |
1068 | EXPORT_SYMBOL(set_memory_array_wb); | |
1069 | ||
75cbade8 AV |
1070 | int set_memory_x(unsigned long addr, int numpages) |
1071 | { | |
d75586ad | 1072 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1073 | } |
1074 | EXPORT_SYMBOL(set_memory_x); | |
1075 | ||
1076 | int set_memory_nx(unsigned long addr, int numpages) | |
1077 | { | |
d75586ad | 1078 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1079 | } |
1080 | EXPORT_SYMBOL(set_memory_nx); | |
1081 | ||
1082 | int set_memory_ro(unsigned long addr, int numpages) | |
1083 | { | |
d75586ad | 1084 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1085 | } |
a03352d2 | 1086 | EXPORT_SYMBOL_GPL(set_memory_ro); |
75cbade8 AV |
1087 | |
1088 | int set_memory_rw(unsigned long addr, int numpages) | |
1089 | { | |
d75586ad | 1090 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1091 | } |
a03352d2 | 1092 | EXPORT_SYMBOL_GPL(set_memory_rw); |
f62d0f00 IM |
1093 | |
1094 | int set_memory_np(unsigned long addr, int numpages) | |
1095 | { | |
d75586ad | 1096 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0); |
f62d0f00 | 1097 | } |
75cbade8 | 1098 | |
c9caa02c AK |
1099 | int set_memory_4k(unsigned long addr, int numpages) |
1100 | { | |
d75586ad | 1101 | return change_page_attr_set_clr(&addr, numpages, __pgprot(0), |
9ae28475 | 1102 | __pgprot(0), 1, 0, NULL); |
c9caa02c AK |
1103 | } |
1104 | ||
75cbade8 AV |
1105 | int set_pages_uc(struct page *page, int numpages) |
1106 | { | |
1107 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1108 | |
d7c8f21a | 1109 | return set_memory_uc(addr, numpages); |
75cbade8 AV |
1110 | } |
1111 | EXPORT_SYMBOL(set_pages_uc); | |
1112 | ||
0f350755 | 1113 | int set_pages_array_uc(struct page **pages, int addrinarray) |
1114 | { | |
1115 | unsigned long start; | |
1116 | unsigned long end; | |
1117 | int i; | |
1118 | int free_idx; | |
1119 | ||
1120 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1121 | if (PageHighMem(pages[i])) |
1122 | continue; | |
1123 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1124 | end = start + PAGE_SIZE; |
1125 | if (reserve_memtype(start, end, _PAGE_CACHE_UC_MINUS, NULL)) | |
1126 | goto err_out; | |
1127 | } | |
1128 | ||
1129 | if (cpa_set_pages_array(pages, addrinarray, | |
1130 | __pgprot(_PAGE_CACHE_UC_MINUS)) == 0) { | |
1131 | return 0; /* Success */ | |
1132 | } | |
1133 | err_out: | |
1134 | free_idx = i; | |
1135 | for (i = 0; i < free_idx; i++) { | |
8523acfe TH |
1136 | if (PageHighMem(pages[i])) |
1137 | continue; | |
1138 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1139 | end = start + PAGE_SIZE; |
1140 | free_memtype(start, end); | |
1141 | } | |
1142 | return -EINVAL; | |
1143 | } | |
1144 | EXPORT_SYMBOL(set_pages_array_uc); | |
1145 | ||
75cbade8 AV |
1146 | int set_pages_wb(struct page *page, int numpages) |
1147 | { | |
1148 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1149 | |
d7c8f21a | 1150 | return set_memory_wb(addr, numpages); |
75cbade8 AV |
1151 | } |
1152 | EXPORT_SYMBOL(set_pages_wb); | |
1153 | ||
0f350755 | 1154 | int set_pages_array_wb(struct page **pages, int addrinarray) |
1155 | { | |
1156 | int retval; | |
1157 | unsigned long start; | |
1158 | unsigned long end; | |
1159 | int i; | |
1160 | ||
1161 | retval = cpa_clear_pages_array(pages, addrinarray, | |
1162 | __pgprot(_PAGE_CACHE_MASK)); | |
9fa3ab39 | 1163 | if (retval) |
1164 | return retval; | |
0f350755 | 1165 | |
1166 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1167 | if (PageHighMem(pages[i])) |
1168 | continue; | |
1169 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1170 | end = start + PAGE_SIZE; |
1171 | free_memtype(start, end); | |
1172 | } | |
1173 | ||
9fa3ab39 | 1174 | return 0; |
0f350755 | 1175 | } |
1176 | EXPORT_SYMBOL(set_pages_array_wb); | |
1177 | ||
75cbade8 AV |
1178 | int set_pages_x(struct page *page, int numpages) |
1179 | { | |
1180 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1181 | |
d7c8f21a | 1182 | return set_memory_x(addr, numpages); |
75cbade8 AV |
1183 | } |
1184 | EXPORT_SYMBOL(set_pages_x); | |
1185 | ||
1186 | int set_pages_nx(struct page *page, int numpages) | |
1187 | { | |
1188 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1189 | |
d7c8f21a | 1190 | return set_memory_nx(addr, numpages); |
75cbade8 AV |
1191 | } |
1192 | EXPORT_SYMBOL(set_pages_nx); | |
1193 | ||
1194 | int set_pages_ro(struct page *page, int numpages) | |
1195 | { | |
1196 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1197 | |
d7c8f21a | 1198 | return set_memory_ro(addr, numpages); |
75cbade8 | 1199 | } |
75cbade8 AV |
1200 | |
1201 | int set_pages_rw(struct page *page, int numpages) | |
1202 | { | |
1203 | unsigned long addr = (unsigned long)page_address(page); | |
e81d5dc4 | 1204 | |
d7c8f21a | 1205 | return set_memory_rw(addr, numpages); |
78c94aba IM |
1206 | } |
1207 | ||
1da177e4 | 1208 | #ifdef CONFIG_DEBUG_PAGEALLOC |
f62d0f00 IM |
1209 | |
1210 | static int __set_pages_p(struct page *page, int numpages) | |
1211 | { | |
d75586ad SL |
1212 | unsigned long tempaddr = (unsigned long) page_address(page); |
1213 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
72e458df TG |
1214 | .numpages = numpages, |
1215 | .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW), | |
d75586ad SL |
1216 | .mask_clr = __pgprot(0), |
1217 | .flags = 0}; | |
72932c7a | 1218 | |
55121b43 SS |
1219 | /* |
1220 | * No alias checking needed for setting present flag. otherwise, | |
1221 | * we may need to break large pages for 64-bit kernel text | |
1222 | * mappings (this adds to complexity if we want to do this from | |
1223 | * atomic context especially). Let's keep it simple! | |
1224 | */ | |
1225 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1226 | } |
1227 | ||
1228 | static int __set_pages_np(struct page *page, int numpages) | |
1229 | { | |
d75586ad SL |
1230 | unsigned long tempaddr = (unsigned long) page_address(page); |
1231 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
72e458df TG |
1232 | .numpages = numpages, |
1233 | .mask_set = __pgprot(0), | |
d75586ad SL |
1234 | .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW), |
1235 | .flags = 0}; | |
72932c7a | 1236 | |
55121b43 SS |
1237 | /* |
1238 | * No alias checking needed for setting not present flag. otherwise, | |
1239 | * we may need to break large pages for 64-bit kernel text | |
1240 | * mappings (this adds to complexity if we want to do this from | |
1241 | * atomic context especially). Let's keep it simple! | |
1242 | */ | |
1243 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1244 | } |
1245 | ||
1da177e4 LT |
1246 | void kernel_map_pages(struct page *page, int numpages, int enable) |
1247 | { | |
1248 | if (PageHighMem(page)) | |
1249 | return; | |
9f4c815c | 1250 | if (!enable) { |
f9b8404c IM |
1251 | debug_check_no_locks_freed(page_address(page), |
1252 | numpages * PAGE_SIZE); | |
9f4c815c | 1253 | } |
de5097c2 | 1254 | |
12d6f21e IM |
1255 | /* |
1256 | * If page allocator is not up yet then do not call c_p_a(): | |
1257 | */ | |
1258 | if (!debug_pagealloc_enabled) | |
1259 | return; | |
1260 | ||
9f4c815c | 1261 | /* |
f8d8406b | 1262 | * The return value is ignored as the calls cannot fail. |
55121b43 SS |
1263 | * Large pages for identity mappings are not used at boot time |
1264 | * and hence no memory allocations during large page split. | |
1da177e4 | 1265 | */ |
f62d0f00 IM |
1266 | if (enable) |
1267 | __set_pages_p(page, numpages); | |
1268 | else | |
1269 | __set_pages_np(page, numpages); | |
9f4c815c IM |
1270 | |
1271 | /* | |
e4b71dcf IM |
1272 | * We should perform an IPI and flush all tlbs, |
1273 | * but that can deadlock->flush only current cpu: | |
1da177e4 LT |
1274 | */ |
1275 | __flush_tlb_all(); | |
ee7ae7a1 TG |
1276 | } |
1277 | ||
8a235efa RW |
1278 | #ifdef CONFIG_HIBERNATION |
1279 | ||
1280 | bool kernel_page_present(struct page *page) | |
1281 | { | |
1282 | unsigned int level; | |
1283 | pte_t *pte; | |
1284 | ||
1285 | if (PageHighMem(page)) | |
1286 | return false; | |
1287 | ||
1288 | pte = lookup_address((unsigned long)page_address(page), &level); | |
1289 | return (pte_val(*pte) & _PAGE_PRESENT); | |
1290 | } | |
1291 | ||
1292 | #endif /* CONFIG_HIBERNATION */ | |
1293 | ||
1294 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
d1028a15 AV |
1295 | |
1296 | /* | |
1297 | * The testcases use internal knowledge of the implementation that shouldn't | |
1298 | * be exposed to the rest of the kernel. Include these directly here. | |
1299 | */ | |
1300 | #ifdef CONFIG_CPA_DEBUG | |
1301 | #include "pageattr-test.c" | |
1302 | #endif |