[deliverable/linux.git] / arch / x86 / mm / pageattr.c

/*
 * Copyright 2002 Andi Kleen, SuSE Labs.
 * Thanks to Ben LaHaise for precious feedback.
 */
#include <linux/highmem.h>
#include <linux/bootmem.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/mm.h>

#include <asm/e820.h>
#include <asm/processor.h>
#include <asm/tlbflush.h>
#include <asm/sections.h>
#include <asm/uaccess.h>
#include <asm/pgalloc.h>

static inline int
within(unsigned long addr, unsigned long start, unsigned long end)
{
	return addr >= start && addr < end;
}

/*
 * Flushing functions
 */


/**
 * clflush_cache_range - flush a cache range with clflush
 * @addr:	virtual start address
 * @size:	number of bytes to flush
 *
 * clflush is an unordered instruction which needs fencing with mfence
 * to avoid ordering issues.
 */
void clflush_cache_range(void *addr, int size)
{
	int i;

	mb();
	for (i = 0; i < size; i += boot_cpu_data.x86_clflush_size)
		clflush(addr+i);
	mb();
}

static void __cpa_flush_all(void *arg)
{
	/*
	 * Flush all to work around Errata in early athlons regarding
	 * large page flushing.
	 */
	__flush_tlb_all();

	if (boot_cpu_data.x86_model >= 4)
		wbinvd();
}

static void cpa_flush_all(void)
{
	BUG_ON(irqs_disabled());

	on_each_cpu(__cpa_flush_all, NULL, 1, 1);
}

struct clflush_data {
	unsigned long addr;
	int numpages;
};

static void __cpa_flush_range(void *arg)
{
	struct clflush_data *cld = arg;

	/*
	 * We could optimize that further and do individual per page
	 * tlb invalidates for a low number of pages. Caveat: we must
	 * flush the high aliases on 64bit as well.
	 */
	__flush_tlb_all();

	clflush_cache_range((void *) cld->addr, cld->numpages * PAGE_SIZE);
}

static void cpa_flush_range(unsigned long addr, int numpages)
{
	struct clflush_data cld;

	BUG_ON(irqs_disabled());

	cld.addr = addr;
	cld.numpages = numpages;

	on_each_cpu(__cpa_flush_range, &cld, 1, 1);
}

/*
 * Certain areas of memory on x86 require very specific protection flags,
 * for example the BIOS area or kernel text. Callers don't always get this
 * right (again, ioremap() on BIOS memory is not uncommon) so this function
 * checks and fixes these known static required protection bits.
 */
static inline pgprot_t static_protections(pgprot_t prot, unsigned long address)
{
	pgprot_t forbidden = __pgprot(0);

	/*
	 * The BIOS area between 640k and 1Mb needs to be executable for
	 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
	 */
	if (within(__pa(address), BIOS_BEGIN, BIOS_END))
		pgprot_val(forbidden) |= _PAGE_NX;

	/*
	 * The kernel text needs to be executable for obvious reasons
	 * Does not cover __inittext since that is gone later on
	 */
	if (within(address, (unsigned long)_text, (unsigned long)_etext))
		pgprot_val(forbidden) |= _PAGE_NX;

#ifdef CONFIG_DEBUG_RODATA
	/* The .rodata section needs to be read-only */
	if (within(address, (unsigned long)__start_rodata,
				(unsigned long)__end_rodata))
		pgprot_val(forbidden) |= _PAGE_RW;
#endif

	prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));

	return prot;
}

pte_t *lookup_address(unsigned long address, int *level)
{
	pgd_t *pgd = pgd_offset_k(address);
	pud_t *pud;
	pmd_t *pmd;

	*level = PG_LEVEL_NONE;

	if (pgd_none(*pgd))
		return NULL;
	pud = pud_offset(pgd, address);
	if (pud_none(*pud))
		return NULL;
	pmd = pmd_offset(pud, address);
	if (pmd_none(*pmd))
		return NULL;

	*level = PG_LEVEL_2M;
	if (pmd_large(*pmd))
		return (pte_t *)pmd;

	*level = PG_LEVEL_4K;
	return pte_offset_kernel(pmd, address);
}

static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
{
	/* change init_mm */
	set_pte_atomic(kpte, pte);
#ifdef CONFIG_X86_32
	if (!SHARED_KERNEL_PMD) {
		struct page *page;

		for (page = pgd_list; page; page = (struct page *)page->index) {
			pgd_t *pgd;
			pud_t *pud;
			pmd_t *pmd;

			pgd = (pgd_t *)page_address(page) + pgd_index(address);
			pud = pud_offset(pgd, address);
			pmd = pmd_offset(pud, address);
			set_pte_atomic((pte_t *)pmd, pte);
		}
	}
#endif
}

static int split_large_page(pte_t *kpte, unsigned long address)
{
	pgprot_t ref_prot = pte_pgprot(pte_clrhuge(*kpte));
	gfp_t gfp_flags = GFP_KERNEL;
	unsigned long flags;
	unsigned long addr;
	pte_t *pbase, *tmp;
	struct page *base;
	int i, level;

#ifdef CONFIG_DEBUG_PAGEALLOC
	gfp_flags = GFP_ATOMIC;
#endif
	base = alloc_pages(gfp_flags, 0);
	if (!base)
		return -ENOMEM;

	spin_lock_irqsave(&pgd_lock, flags);
	/*
	 * Check for races, another CPU might have split this page
	 * up for us already:
	 */
	tmp = lookup_address(address, &level);
	if (tmp != kpte) {
		WARN_ON_ONCE(1);
		goto out_unlock;
	}

	address = __pa(address);
	addr = address & LARGE_PAGE_MASK;
	pbase = (pte_t *)page_address(base);
#ifdef CONFIG_X86_32
	paravirt_alloc_pt(&init_mm, page_to_pfn(base));
#endif

	for (i = 0; i < PTRS_PER_PTE; i++, addr += PAGE_SIZE)
		set_pte(&pbase[i], pfn_pte(addr >> PAGE_SHIFT, ref_prot));

	/*
	 * Install the new, split up pagetable. Important detail here:
	 *
	 * On Intel the NX bit of all levels must be cleared to make a
	 * page executable. See section 4.13.2 of Intel 64 and IA-32
	 * Architectures Software Developer's Manual).
	 */
	ref_prot = pte_pgprot(pte_mkexec(pte_clrhuge(*kpte)));
	__set_pmd_pte(kpte, address, mk_pte(base, ref_prot));
	base = NULL;

out_unlock:
	spin_unlock_irqrestore(&pgd_lock, flags);

	if (base)
		__free_pages(base, 0);

	return 0;
}

static int
__change_page_attr(unsigned long address, unsigned long pfn, pgprot_t prot)
{
	struct page *kpte_page;
	int level, err = 0;
	pte_t *kpte;

#ifdef CONFIG_X86_32
	BUG_ON(pfn > max_low_pfn);
#endif

repeat:
	kpte = lookup_address(address, &level);
	if (!kpte)
		return -EINVAL;

	kpte_page = virt_to_page(kpte);
	BUG_ON(PageLRU(kpte_page));
	BUG_ON(PageCompound(kpte_page));

	prot = static_protections(prot, address);

	if (level == PG_LEVEL_4K) {
		WARN_ON_ONCE(pgprot_val(prot) & _PAGE_PSE);
		set_pte_atomic(kpte, pfn_pte(pfn, canon_pgprot(prot)));
	} else {
		/* Clear the PSE bit for the 4k level pages ! */
		pgprot_val(prot) = pgprot_val(prot) & ~_PAGE_PSE;

		err = split_large_page(kpte, address);
		if (!err)
			goto repeat;
	}
	return err;
}

/**
 * change_page_attr_addr - Change page table attributes in linear mapping
 * @address: Virtual address in linear mapping.
 * @prot:    New page table attribute (PAGE_*)
 *
 * Change page attributes of a page in the direct mapping. This is a variant
 * of change_page_attr() that also works on memory holes that do not have
 * mem_map entry (pfn_valid() is false).
 *
 * See change_page_attr() documentation for more details.
 *
 * Modules and drivers should use the set_memory_* APIs instead.
 */

static int change_page_attr_addr(unsigned long address, pgprot_t prot)
{
	int err = 0, kernel_map = 0;
	unsigned long pfn = __pa(address) >> PAGE_SHIFT;

#ifdef CONFIG_X86_64
	if (address >= __START_KERNEL_map &&
			address < __START_KERNEL_map + KERNEL_TEXT_SIZE) {

		address = (unsigned long)__va(__pa(address));
		kernel_map = 1;
	}
#endif

	if (!kernel_map || pte_present(pfn_pte(0, prot))) {
		err = __change_page_attr(address, pfn, prot);
		if (err)
			return err;
	}

#ifdef CONFIG_X86_64
	/*
	 * Handle kernel mapping too which aliases part of
	 * lowmem:
	 */
	if (__pa(address) < KERNEL_TEXT_SIZE) {
		unsigned long addr2;
		pgprot_t prot2;

		addr2 = __START_KERNEL_map + __pa(address);
		/* Make sure the kernel mappings stay executable */
		prot2 = pte_pgprot(pte_mkexec(pfn_pte(0, prot)));
		err = __change_page_attr(addr2, pfn, prot2);
	}
#endif

	return err;
}

static int __change_page_attr_set_clr(unsigned long addr, int numpages,
				      pgprot_t mask_set, pgprot_t mask_clr)
{
	pgprot_t new_prot;
	int level;
	pte_t *pte;
	int i, ret;

	for (i = 0; i < numpages ; i++) {

		pte = lookup_address(addr, &level);
		if (!pte)
			return -EINVAL;

		new_prot = pte_pgprot(*pte);

		pgprot_val(new_prot) &= ~pgprot_val(mask_clr);
		pgprot_val(new_prot) |= pgprot_val(mask_set);

		ret = change_page_attr_addr(addr, new_prot);
		if (ret)
			return ret;
		addr += PAGE_SIZE;
	}

	return 0;
}

static int change_page_attr_set_clr(unsigned long addr, int numpages,
				    pgprot_t mask_set, pgprot_t mask_clr)
{
	int ret = __change_page_attr_set_clr(addr, numpages, mask_set,
					     mask_clr);

	/*
	 * On success we use clflush, when the CPU supports it to
	 * avoid the wbindv. If the CPU does not support it and in the
	 * error case we fall back to cpa_flush_all (which uses
	 * wbindv):
	 */
	if (!ret && cpu_has_clflush)
		cpa_flush_range(addr, numpages);
	else
		cpa_flush_all();

	return ret;
}

static inline int change_page_attr_set(unsigned long addr, int numpages,
				       pgprot_t mask)
{
	return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0));
}

static inline int change_page_attr_clear(unsigned long addr, int numpages,
					 pgprot_t mask)
{
	return __change_page_attr_set_clr(addr, numpages, __pgprot(0), mask);

}

int set_memory_uc(unsigned long addr, int numpages)
{
	return change_page_attr_set(addr, numpages,
				    __pgprot(_PAGE_PCD | _PAGE_PWT));
}
EXPORT_SYMBOL(set_memory_uc);

int set_memory_wb(unsigned long addr, int numpages)
{
	return change_page_attr_clear(addr, numpages,
				      __pgprot(_PAGE_PCD | _PAGE_PWT));
}
EXPORT_SYMBOL(set_memory_wb);

int set_memory_x(unsigned long addr, int numpages)
{
	return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_NX));
}
EXPORT_SYMBOL(set_memory_x);

int set_memory_nx(unsigned long addr, int numpages)
{
	return change_page_attr_set(addr, numpages, __pgprot(_PAGE_NX));
}
EXPORT_SYMBOL(set_memory_nx);

int set_memory_ro(unsigned long addr, int numpages)
{
	return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_RW));
}

int set_memory_rw(unsigned long addr, int numpages)
{
	return change_page_attr_set(addr, numpages, __pgprot(_PAGE_RW));
}

int set_memory_np(unsigned long addr, int numpages)
{
	return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_PRESENT));
}

int set_pages_uc(struct page *page, int numpages)
{
	unsigned long addr = (unsigned long)page_address(page);

	return set_memory_uc(addr, numpages);
}
EXPORT_SYMBOL(set_pages_uc);

int set_pages_wb(struct page *page, int numpages)
{
	unsigned long addr = (unsigned long)page_address(page);

	return set_memory_wb(addr, numpages);
}
EXPORT_SYMBOL(set_pages_wb);

int set_pages_x(struct page *page, int numpages)
{
	unsigned long addr = (unsigned long)page_address(page);

	return set_memory_x(addr, numpages);
}
EXPORT_SYMBOL(set_pages_x);

int set_pages_nx(struct page *page, int numpages)
{
	unsigned long addr = (unsigned long)page_address(page);

	return set_memory_nx(addr, numpages);
}
EXPORT_SYMBOL(set_pages_nx);

int set_pages_ro(struct page *page, int numpages)
{
	unsigned long addr = (unsigned long)page_address(page);

	return set_memory_ro(addr, numpages);
}

int set_pages_rw(struct page *page, int numpages)
{
	unsigned long addr = (unsigned long)page_address(page);

	return set_memory_rw(addr, numpages);
}


#if defined(CONFIG_DEBUG_PAGEALLOC) || defined(CONFIG_CPA_DEBUG)
static inline int __change_page_attr_set(unsigned long addr, int numpages,
					 pgprot_t mask)
{
	return __change_page_attr_set_clr(addr, numpages, mask, __pgprot(0));
}

static inline int __change_page_attr_clear(unsigned long addr, int numpages,
					   pgprot_t mask)
{
	return __change_page_attr_set_clr(addr, numpages, __pgprot(0), mask);
}
#endif

#ifdef CONFIG_DEBUG_PAGEALLOC

static int __set_pages_p(struct page *page, int numpages)
{
	unsigned long addr = (unsigned long)page_address(page);

	return __change_page_attr_set(addr, numpages,
				      __pgprot(_PAGE_PRESENT | _PAGE_RW));
}

static int __set_pages_np(struct page *page, int numpages)
{
	unsigned long addr = (unsigned long)page_address(page);

	return __change_page_attr_clear(addr, numpages,
					__pgprot(_PAGE_PRESENT));
}

void kernel_map_pages(struct page *page, int numpages, int enable)
{
	if (PageHighMem(page))
		return;
	if (!enable) {
		debug_check_no_locks_freed(page_address(page),
					   numpages * PAGE_SIZE);
	}

	/*
	 * If page allocator is not up yet then do not call c_p_a():
	 */
	if (!debug_pagealloc_enabled)
		return;

	/*
	 * The return value is ignored - the calls cannot fail,
	 * large pages are disabled at boot time:
	 */
	if (enable)
		__set_pages_p(page, numpages);
	else
		__set_pages_np(page, numpages);

	/*
	 * We should perform an IPI and flush all tlbs,
	 * but that can deadlock->flush only current cpu:
	 */
	__flush_tlb_all();
}
#endif

/*
 * The testcases use internal knowledge of the implementation that shouldn't
 * be exposed to the rest of the kernel. Include these directly here.
 */
#ifdef CONFIG_CPA_DEBUG
#include "pageattr-test.c"
#endif
Commit	Line	Data
9f4c815c IM	1	/*
9f4c815c IM	2	* Copyright 2002 Andi Kleen, SuSE Labs.
1da177e4	3	* Thanks to Ben LaHaise for precious feedback.
9f4c815c	4	*/
1da177e4	5	#include <linux/highmem.h>
8192206d	6	#include <linux/bootmem.h>
1da177e4	7	#include <linux/module.h>
9f4c815c	8	#include <linux/sched.h>
1da177e4	9	#include <linux/slab.h>
9f4c815c IM	10	#include <linux/mm.h>
9f4c815c IM	11
950f9d95	12	#include <asm/e820.h>
1da177e4 LT	13	#include <asm/processor.h>
1da177e4 LT	14	#include <asm/tlbflush.h>
f8af095d	15	#include <asm/sections.h>
9f4c815c IM	16	#include <asm/uaccess.h>
9f4c815c IM	17	#include <asm/pgalloc.h>
1da177e4	18
ed724be6 AV	19	static inline int
ed724be6 AV	20	within(unsigned long addr, unsigned long start, unsigned long end)
687c4825	21	{
ed724be6 AV	22	return addr >= start && addr < end;
	23	}
	24
d7c8f21a TG	25	/*
	26	* Flushing functions
	27	*/
cd8ddf1a TG	28
	29
	30	/**
	31	* clflush_cache_range - flush a cache range with clflush
	32	* @addr: virtual start address
	33	* @size: number of bytes to flush
	34	*
	35	* clflush is an unordered instruction which needs fencing with mfence
	36	* to avoid ordering issues.
	37	*/
d7c8f21a TG	38	void clflush_cache_range(void *addr, int size)
	39	{
	40	int i;
	41
cd8ddf1a	42	mb();
d7c8f21a TG	43	for (i = 0; i < size; i += boot_cpu_data.x86_clflush_size)
d7c8f21a TG	44	clflush(addr+i);
cd8ddf1a	45	mb();
d7c8f21a TG	46	}
d7c8f21a TG	47
af1e6844	48	static void __cpa_flush_all(void *arg)
d7c8f21a TG	49	{
	50	/*
	51	* Flush all to work around Errata in early athlons regarding
	52	* large page flushing.
	53	*/
	54	__flush_tlb_all();
	55
	56	if (boot_cpu_data.x86_model >= 4)
	57	wbinvd();
	58	}
	59
af1e6844	60	static void cpa_flush_all(void)
d7c8f21a TG	61	{
	62	BUG_ON(irqs_disabled());
	63
af1e6844	64	on_each_cpu(__cpa_flush_all, NULL, 1, 1);
d7c8f21a TG	65	}
d7c8f21a TG	66
57a6a46a TG	67	struct clflush_data {
	68	unsigned long addr;
	69	int numpages;
	70	};
	71
	72	static void __cpa_flush_range(void *arg)
	73	{
	74	struct clflush_data *cld = arg;
	75
	76	/*
	77	* We could optimize that further and do individual per page
	78	* tlb invalidates for a low number of pages. Caveat: we must
	79	* flush the high aliases on 64bit as well.
	80	*/
	81	__flush_tlb_all();
	82
	83	clflush_cache_range((void ) cld->addr, cld->numpages PAGE_SIZE);
	84	}
	85
	86	static void cpa_flush_range(unsigned long addr, int numpages)
	87	{
	88	struct clflush_data cld;
	89
	90	BUG_ON(irqs_disabled());
	91
	92	cld.addr = addr;
	93	cld.numpages = numpages;
	94
	95	on_each_cpu(__cpa_flush_range, &cld, 1, 1);
	96	}
	97
ed724be6 AV	98	/*
	99	* Certain areas of memory on x86 require very specific protection flags,
	100	* for example the BIOS area or kernel text. Callers don't always get this
	101	* right (again, ioremap() on BIOS memory is not uncommon) so this function
	102	* checks and fixes these known static required protection bits.
	103	*/
	104	static inline pgprot_t static_protections(pgprot_t prot, unsigned long address)
	105	{
	106	pgprot_t forbidden = __pgprot(0);
	107
687c4825	108	/*
ed724be6 AV	109	* The BIOS area between 640k and 1Mb needs to be executable for
ed724be6 AV	110	* PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
687c4825	111	*/
ed724be6 AV	112	if (within(__pa(address), BIOS_BEGIN, BIOS_END))
	113	pgprot_val(forbidden) \|= _PAGE_NX;
	114
	115	/*
	116	* The kernel text needs to be executable for obvious reasons
	117	* Does not cover __inittext since that is gone later on
	118	*/
	119	if (within(address, (unsigned long)_text, (unsigned long)_etext))
	120	pgprot_val(forbidden) \|= _PAGE_NX;
	121
	122	#ifdef CONFIG_DEBUG_RODATA
	123	/* The .rodata section needs to be read-only */
	124	if (within(address, (unsigned long)__start_rodata,
	125	(unsigned long)__end_rodata))
	126	pgprot_val(forbidden) \|= _PAGE_RW;
	127	#endif
	128
	129	prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden));
687c4825 IM	130
	131	return prot;
	132	}
	133
f0646e43	134	pte_t lookup_address(unsigned long address, int level)
9f4c815c	135	{
1da177e4 LT	136	pgd_t *pgd = pgd_offset_k(address);
	137	pud_t *pud;
	138	pmd_t *pmd;
9f4c815c	139
30551bb3 TG	140	*level = PG_LEVEL_NONE;
30551bb3 TG	141
1da177e4 LT	142	if (pgd_none(*pgd))
	143	return NULL;
	144	pud = pud_offset(pgd, address);
	145	if (pud_none(*pud))
	146	return NULL;
	147	pmd = pmd_offset(pud, address);
	148	if (pmd_none(*pmd))
	149	return NULL;
30551bb3 TG	150
30551bb3 TG	151	*level = PG_LEVEL_2M;
1da177e4 LT	152	if (pmd_large(*pmd))
1da177e4 LT	153	return (pte_t *)pmd;
1da177e4	154
30551bb3	155	*level = PG_LEVEL_4K;
9f4c815c IM	156	return pte_offset_kernel(pmd, address);
	157	}
	158
9a3dc780	159	static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
9f4c815c	160	{
9f4c815c IM	161	/* change init_mm */
9f4c815c IM	162	set_pte_atomic(kpte, pte);
44af6c41	163	#ifdef CONFIG_X86_32
e4b71dcf	164	if (!SHARED_KERNEL_PMD) {
44af6c41 IM	165	struct page *page;
	166
	167	for (page = pgd_list; page; page = (struct page *)page->index) {
	168	pgd_t *pgd;
	169	pud_t *pud;
	170	pmd_t *pmd;
	171
	172	pgd = (pgd_t *)page_address(page) + pgd_index(address);
	173	pud = pud_offset(pgd, address);
	174	pmd = pmd_offset(pud, address);
	175	set_pte_atomic((pte_t *)pmd, pte);
	176	}
1da177e4	177	}
44af6c41	178	#endif
1da177e4 LT	179	}
1da177e4 LT	180
7afe15b9	181	static int split_large_page(pte_t *kpte, unsigned long address)
bb5c2dbd	182	{
7afe15b9	183	pgprot_t ref_prot = pte_pgprot(pte_clrhuge(*kpte));
12d6f21e	184	gfp_t gfp_flags = GFP_KERNEL;
9a3dc780	185	unsigned long flags;
bb5c2dbd IM	186	unsigned long addr;
	187	pte_t pbase, tmp;
	188	struct page *base;
7afe15b9	189	int i, level;
bb5c2dbd	190
12d6f21e IM	191	#ifdef CONFIG_DEBUG_PAGEALLOC
	192	gfp_flags = GFP_ATOMIC;
	193	#endif
	194	base = alloc_pages(gfp_flags, 0);
bb5c2dbd IM	195	if (!base)
	196	return -ENOMEM;
	197
9a3dc780	198	spin_lock_irqsave(&pgd_lock, flags);
bb5c2dbd IM	199	/*
	200	* Check for races, another CPU might have split this page
	201	* up for us already:
	202	*/
	203	tmp = lookup_address(address, &level);
5508a748 IM	204	if (tmp != kpte) {
5508a748 IM	205	WARN_ON_ONCE(1);
bb5c2dbd	206	goto out_unlock;
5508a748	207	}
bb5c2dbd IM	208
	209	address = __pa(address);
	210	addr = address & LARGE_PAGE_MASK;
	211	pbase = (pte_t *)page_address(base);
44af6c41	212	#ifdef CONFIG_X86_32
bb5c2dbd	213	paravirt_alloc_pt(&init_mm, page_to_pfn(base));
44af6c41	214	#endif
bb5c2dbd IM	215
	216	for (i = 0; i < PTRS_PER_PTE; i++, addr += PAGE_SIZE)
	217	set_pte(&pbase[i], pfn_pte(addr >> PAGE_SHIFT, ref_prot));
	218
	219	/*
4c881ca1 HY	220	* Install the new, split up pagetable. Important detail here:
	221	*
	222	* On Intel the NX bit of all levels must be cleared to make a
	223	* page executable. See section 4.13.2 of Intel 64 and IA-32
	224	* Architectures Software Developer's Manual).
bb5c2dbd	225	*/
4c881ca1	226	ref_prot = pte_pgprot(pte_mkexec(pte_clrhuge(*kpte)));
9a3dc780	227	__set_pmd_pte(kpte, address, mk_pte(base, ref_prot));
bb5c2dbd IM	228	base = NULL;
	229
	230	out_unlock:
9a3dc780	231	spin_unlock_irqrestore(&pgd_lock, flags);
bb5c2dbd IM	232
	233	if (base)
	234	__free_pages(base, 0);
	235
	236	return 0;
	237	}
	238
44af6c41	239	static int
8192206d	240	__change_page_attr(unsigned long address, unsigned long pfn, pgprot_t prot)
9f4c815c	241	{
1da177e4	242	struct page *kpte_page;
bb5c2dbd	243	int level, err = 0;
9f4c815c	244	pte_t *kpte;
1da177e4	245
8192206d IM	246	#ifdef CONFIG_X86_32
	247	BUG_ON(pfn > max_low_pfn);
	248	#endif
1da177e4	249
97f99fed	250	repeat:
f0646e43	251	kpte = lookup_address(address, &level);
1da177e4 LT	252	if (!kpte)
1da177e4 LT	253	return -EINVAL;
9f4c815c	254
1da177e4	255	kpte_page = virt_to_page(kpte);
65d2f0bc AK	256	BUG_ON(PageLRU(kpte_page));
	257	BUG_ON(PageCompound(kpte_page));
	258
ed724be6	259	prot = static_protections(prot, address);
65d2f0bc	260
30551bb3	261	if (level == PG_LEVEL_4K) {
a72a08a4	262	WARN_ON_ONCE(pgprot_val(prot) & _PAGE_PSE);
8192206d	263	set_pte_atomic(kpte, pfn_pte(pfn, canon_pgprot(prot)));
78c94aba	264	} else {
a72a08a4 TG	265	/* Clear the PSE bit for the 4k level pages ! */
	266	pgprot_val(prot) = pgprot_val(prot) & ~_PAGE_PSE;
	267
7afe15b9	268	err = split_large_page(kpte, address);
bb5c2dbd IM	269	if (!err)
bb5c2dbd IM	270	goto repeat;
1da177e4	271	}
bb5c2dbd	272	return err;
9f4c815c	273	}
1da177e4	274
44af6c41 IM	275	/**
	276	* change_page_attr_addr - Change page table attributes in linear mapping
	277	* @address: Virtual address in linear mapping.
44af6c41	278	* @prot: New page table attribute (PAGE_*)
1da177e4	279	*
44af6c41 IM	280	* Change page attributes of a page in the direct mapping. This is a variant
	281	* of change_page_attr() that also works on memory holes that do not have
	282	* mem_map entry (pfn_valid() is false).
9f4c815c	283	*
44af6c41	284	* See change_page_attr() documentation for more details.
75cbade8 AV	285	*
75cbade8 AV	286	* Modules and drivers should use the set_memory_* APIs instead.
1da177e4	287	*/
44af6c41	288
488fd995	289	static int change_page_attr_addr(unsigned long address, pgprot_t prot)
1da177e4	290	{
488fd995 AV	291	int err = 0, kernel_map = 0;
488fd995 AV	292	unsigned long pfn = __pa(address) >> PAGE_SHIFT;
44af6c41 IM	293
	294	#ifdef CONFIG_X86_64
	295	if (address >= __START_KERNEL_map &&
	296	address < __START_KERNEL_map + KERNEL_TEXT_SIZE) {
1da177e4	297
44af6c41 IM	298	address = (unsigned long)__va(__pa(address));
	299	kernel_map = 1;
	300	}
	301	#endif
	302
488fd995 AV	303	if (!kernel_map \|\| pte_present(pfn_pte(0, prot))) {
	304	err = __change_page_attr(address, pfn, prot);
	305	if (err)
	306	return err;
	307	}
44af6c41	308
44af6c41	309	#ifdef CONFIG_X86_64
488fd995 AV	310	/*
	311	* Handle kernel mapping too which aliases part of
	312	* lowmem:
	313	*/
	314	if (__pa(address) < KERNEL_TEXT_SIZE) {
	315	unsigned long addr2;
	316	pgprot_t prot2;
	317
	318	addr2 = __START_KERNEL_map + __pa(address);
	319	/* Make sure the kernel mappings stay executable */
	320	prot2 = pte_pgprot(pte_mkexec(pfn_pte(0, prot)));
	321	err = __change_page_attr(addr2, pfn, prot2);
9f4c815c	322	}
488fd995	323	#endif
9f4c815c	324
1da177e4 LT	325	return err;
	326	}
	327
ff31452b TG	328	static int __change_page_attr_set_clr(unsigned long addr, int numpages,
	329	pgprot_t mask_set, pgprot_t mask_clr)
	330	{
	331	pgprot_t new_prot;
	332	int level;
	333	pte_t *pte;
	334	int i, ret;
	335
	336	for (i = 0; i < numpages ; i++) {
	337
	338	pte = lookup_address(addr, &level);
	339	if (!pte)
	340	return -EINVAL;
	341
	342	new_prot = pte_pgprot(*pte);
	343
	344	pgprot_val(new_prot) &= ~pgprot_val(mask_clr);
	345	pgprot_val(new_prot) \|= pgprot_val(mask_set);
	346
	347	ret = change_page_attr_addr(addr, new_prot);
	348	if (ret)
	349	return ret;
	350	addr += PAGE_SIZE;
	351	}
	352
	353	return 0;
	354	}
	355
	356	static int change_page_attr_set_clr(unsigned long addr, int numpages,
	357	pgprot_t mask_set, pgprot_t mask_clr)
	358	{
	359	int ret = __change_page_attr_set_clr(addr, numpages, mask_set,
	360	mask_clr);
	361
57a6a46a TG	362	/*
	363	* On success we use clflush, when the CPU supports it to
	364	* avoid the wbindv. If the CPU does not support it and in the
af1e6844	365	* error case we fall back to cpa_flush_all (which uses
57a6a46a TG	366	* wbindv):
	367	*/
	368	if (!ret && cpu_has_clflush)
	369	cpa_flush_range(addr, numpages);
	370	else
af1e6844	371	cpa_flush_all();
ff31452b TG	372
	373	return ret;
	374	}
	375
56744546 TG	376	static inline int change_page_attr_set(unsigned long addr, int numpages,
56744546 TG	377	pgprot_t mask)
75cbade8	378	{
56744546	379	return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0));
75cbade8 AV	380	}
75cbade8 AV	381
56744546 TG	382	static inline int change_page_attr_clear(unsigned long addr, int numpages,
56744546 TG	383	pgprot_t mask)
72932c7a	384	{
56744546	385	return __change_page_attr_set_clr(addr, numpages, __pgprot(0), mask);
72932c7a TG	386
	387	}
	388
	389	int set_memory_uc(unsigned long addr, int numpages)
	390	{
	391	return change_page_attr_set(addr, numpages,
	392	__pgprot(_PAGE_PCD \| _PAGE_PWT));
75cbade8 AV	393	}
	394	EXPORT_SYMBOL(set_memory_uc);
	395
	396	int set_memory_wb(unsigned long addr, int numpages)
	397	{
72932c7a TG	398	return change_page_attr_clear(addr, numpages,
72932c7a TG	399	__pgprot(_PAGE_PCD \| _PAGE_PWT));
75cbade8 AV	400	}
	401	EXPORT_SYMBOL(set_memory_wb);
	402
	403	int set_memory_x(unsigned long addr, int numpages)
	404	{
72932c7a	405	return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_NX));
75cbade8 AV	406	}
	407	EXPORT_SYMBOL(set_memory_x);
	408
	409	int set_memory_nx(unsigned long addr, int numpages)
	410	{
72932c7a	411	return change_page_attr_set(addr, numpages, __pgprot(_PAGE_NX));
75cbade8 AV	412	}
	413	EXPORT_SYMBOL(set_memory_nx);
	414
	415	int set_memory_ro(unsigned long addr, int numpages)
	416	{
72932c7a	417	return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_RW));
75cbade8	418	}
75cbade8 AV	419
	420	int set_memory_rw(unsigned long addr, int numpages)
	421	{
72932c7a	422	return change_page_attr_set(addr, numpages, __pgprot(_PAGE_RW));
75cbade8	423	}
f62d0f00 IM	424
	425	int set_memory_np(unsigned long addr, int numpages)
	426	{
72932c7a	427	return change_page_attr_clear(addr, numpages, __pgprot(_PAGE_PRESENT));
f62d0f00	428	}
75cbade8 AV	429
	430	int set_pages_uc(struct page *page, int numpages)
	431	{
	432	unsigned long addr = (unsigned long)page_address(page);
75cbade8	433
d7c8f21a	434	return set_memory_uc(addr, numpages);
75cbade8 AV	435	}
	436	EXPORT_SYMBOL(set_pages_uc);
	437
	438	int set_pages_wb(struct page *page, int numpages)
	439	{
	440	unsigned long addr = (unsigned long)page_address(page);
75cbade8	441
d7c8f21a	442	return set_memory_wb(addr, numpages);
75cbade8 AV	443	}
	444	EXPORT_SYMBOL(set_pages_wb);
	445
	446	int set_pages_x(struct page *page, int numpages)
	447	{
	448	unsigned long addr = (unsigned long)page_address(page);
75cbade8	449
d7c8f21a	450	return set_memory_x(addr, numpages);
75cbade8 AV	451	}
	452	EXPORT_SYMBOL(set_pages_x);
	453
	454	int set_pages_nx(struct page *page, int numpages)
	455	{
	456	unsigned long addr = (unsigned long)page_address(page);
75cbade8	457
d7c8f21a	458	return set_memory_nx(addr, numpages);
75cbade8 AV	459	}
	460	EXPORT_SYMBOL(set_pages_nx);
	461
	462	int set_pages_ro(struct page *page, int numpages)
	463	{
	464	unsigned long addr = (unsigned long)page_address(page);
75cbade8	465
d7c8f21a	466	return set_memory_ro(addr, numpages);
75cbade8	467	}
75cbade8 AV	468
	469	int set_pages_rw(struct page *page, int numpages)
	470	{
	471	unsigned long addr = (unsigned long)page_address(page);
e81d5dc4	472
d7c8f21a	473	return set_memory_rw(addr, numpages);
78c94aba IM	474	}
78c94aba IM	475
1da177e4	476
56744546 TG	477	#if defined(CONFIG_DEBUG_PAGEALLOC) \|\| defined(CONFIG_CPA_DEBUG)
	478	static inline int __change_page_attr_set(unsigned long addr, int numpages,
	479	pgprot_t mask)
	480	{
	481	return __change_page_attr_set_clr(addr, numpages, mask, __pgprot(0));
	482	}
	483
	484	static inline int __change_page_attr_clear(unsigned long addr, int numpages,
	485	pgprot_t mask)
	486	{
	487	return __change_page_attr_set_clr(addr, numpages, __pgprot(0), mask);
	488	}
	489	#endif
	490
1da177e4	491	#ifdef CONFIG_DEBUG_PAGEALLOC
f62d0f00 IM	492
	493	static int __set_pages_p(struct page *page, int numpages)
	494	{
	495	unsigned long addr = (unsigned long)page_address(page);
72932c7a TG	496
	497	return __change_page_attr_set(addr, numpages,
	498	__pgprot(_PAGE_PRESENT \| _PAGE_RW));
f62d0f00 IM	499	}
	500
	501	static int __set_pages_np(struct page *page, int numpages)
	502	{
	503	unsigned long addr = (unsigned long)page_address(page);
72932c7a TG	504
	505	return __change_page_attr_clear(addr, numpages,
	506	__pgprot(_PAGE_PRESENT));
f62d0f00 IM	507	}
f62d0f00 IM	508
1da177e4 LT	509	void kernel_map_pages(struct page *page, int numpages, int enable)
	510	{
	511	if (PageHighMem(page))
	512	return;
9f4c815c	513	if (!enable) {
f9b8404c IM	514	debug_check_no_locks_freed(page_address(page),
f9b8404c IM	515	numpages * PAGE_SIZE);
9f4c815c	516	}
de5097c2	517
12d6f21e IM	518	/*
	519	* If page allocator is not up yet then do not call c_p_a():
	520	*/
	521	if (!debug_pagealloc_enabled)
	522	return;
	523
9f4c815c	524	/*
e4b71dcf IM	525	* The return value is ignored - the calls cannot fail,
e4b71dcf IM	526	* large pages are disabled at boot time:
1da177e4	527	*/
f62d0f00 IM	528	if (enable)
	529	__set_pages_p(page, numpages);
	530	else
	531	__set_pages_np(page, numpages);
9f4c815c IM	532
9f4c815c IM	533	/*
e4b71dcf IM	534	* We should perform an IPI and flush all tlbs,
e4b71dcf IM	535	* but that can deadlock->flush only current cpu:
1da177e4 LT	536	*/
	537	__flush_tlb_all();
	538	}
	539	#endif
d1028a15 AV	540
	541	/*
	542	* The testcases use internal knowledge of the implementation that shouldn't
	543	* be exposed to the rest of the kernel. Include these directly here.
	544	*/
	545	#ifdef CONFIG_CPA_DEBUG
	546	#include "pageattr-test.c"
	547	#endif