[deliverable/linux.git] / arch / x86 / oprofile / nmi_int.c

/**
 * @file nmi_int.c
 *
 * @remark Copyright 2002-2008 OProfile authors
 * @remark Read the file COPYING
 *
 * @author John Levon <levon@movementarian.org>
 * @author Robert Richter <robert.richter@amd.com>
 */

#include <linux/init.h>
#include <linux/notifier.h>
#include <linux/smp.h>
#include <linux/oprofile.h>
#include <linux/sysdev.h>
#include <linux/slab.h>
#include <linux/moduleparam.h>
#include <linux/kdebug.h>
#include <linux/cpu.h>
#include <asm/nmi.h>
#include <asm/msr.h>
#include <asm/apic.h>

#include "op_counter.h"
#include "op_x86_model.h"

static struct op_x86_model_spec const *model;
static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
static DEFINE_PER_CPU(unsigned long, saved_lvtpc);

/* 0 == registered but off, 1 == registered and on */
static int nmi_enabled = 0;

static int profile_exceptions_notify(struct notifier_block *self,
				     unsigned long val, void *data)
{
	struct die_args *args = (struct die_args *)data;
	int ret = NOTIFY_DONE;
	int cpu = smp_processor_id();

	switch (val) {
	case DIE_NMI:
		if (model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu)))
			ret = NOTIFY_STOP;
		break;
	default:
		break;
	}
	return ret;
}

static void nmi_cpu_save_registers(struct op_msrs *msrs)
{
	unsigned int const nr_ctrs = model->num_counters;
	unsigned int const nr_ctrls = model->num_controls;
	struct op_msr *counters = msrs->counters;
	struct op_msr *controls = msrs->controls;
	unsigned int i;

	for (i = 0; i < nr_ctrs; ++i) {
		if (counters[i].addr) {
			rdmsr(counters[i].addr,
				counters[i].saved.low,
				counters[i].saved.high);
		}
	}

	for (i = 0; i < nr_ctrls; ++i) {
		if (controls[i].addr) {
			rdmsr(controls[i].addr,
				controls[i].saved.low,
				controls[i].saved.high);
		}
	}
}

static void nmi_save_registers(void *dummy)
{
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
	nmi_cpu_save_registers(msrs);
}

static void free_msrs(void)
{
	int i;
	for_each_possible_cpu(i) {
		kfree(per_cpu(cpu_msrs, i).counters);
		per_cpu(cpu_msrs, i).counters = NULL;
		kfree(per_cpu(cpu_msrs, i).controls);
		per_cpu(cpu_msrs, i).controls = NULL;
	}
}

static int allocate_msrs(void)
{
	int success = 1;
	size_t controls_size = sizeof(struct op_msr) * model->num_controls;
	size_t counters_size = sizeof(struct op_msr) * model->num_counters;

	int i;
	for_each_possible_cpu(i) {
		per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
								GFP_KERNEL);
		if (!per_cpu(cpu_msrs, i).counters) {
			success = 0;
			break;
		}
		per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
								GFP_KERNEL);
		if (!per_cpu(cpu_msrs, i).controls) {
			success = 0;
			break;
		}
	}

	if (!success)
		free_msrs();

	return success;
}

static void nmi_cpu_setup(void *dummy)
{
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
	spin_lock(&oprofilefs_lock);
	model->setup_ctrs(msrs);
	spin_unlock(&oprofilefs_lock);
	per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
	apic_write(APIC_LVTPC, APIC_DM_NMI);
}

static struct notifier_block profile_exceptions_nb = {
	.notifier_call = profile_exceptions_notify,
	.next = NULL,
	.priority = 0
};

static int nmi_setup(void)
{
	int err = 0;
	int cpu;

	if (!allocate_msrs())
		return -ENOMEM;

	err = register_die_notifier(&profile_exceptions_nb);
	if (err) {
		free_msrs();
		return err;
	}

	/* We need to serialize save and setup for HT because the subset
	 * of msrs are distinct for save and setup operations
	 */

	/* Assume saved/restored counters are the same on all CPUs */
	model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
	for_each_possible_cpu(cpu) {
		if (cpu != 0) {
			memcpy(per_cpu(cpu_msrs, cpu).counters,
				per_cpu(cpu_msrs, 0).counters,
				sizeof(struct op_msr) * model->num_counters);

			memcpy(per_cpu(cpu_msrs, cpu).controls,
				per_cpu(cpu_msrs, 0).controls,
				sizeof(struct op_msr) * model->num_controls);
		}

	}
	on_each_cpu(nmi_save_registers, NULL, 1);
	on_each_cpu(nmi_cpu_setup, NULL, 1);
	nmi_enabled = 1;
	return 0;
}

static void nmi_restore_registers(struct op_msrs *msrs)
{
	unsigned int const nr_ctrs = model->num_counters;
	unsigned int const nr_ctrls = model->num_controls;
	struct op_msr *counters = msrs->counters;
	struct op_msr *controls = msrs->controls;
	unsigned int i;

	for (i = 0; i < nr_ctrls; ++i) {
		if (controls[i].addr) {
			wrmsr(controls[i].addr,
				controls[i].saved.low,
				controls[i].saved.high);
		}
	}

	for (i = 0; i < nr_ctrs; ++i) {
		if (counters[i].addr) {
			wrmsr(counters[i].addr,
				counters[i].saved.low,
				counters[i].saved.high);
		}
	}
}

static void nmi_cpu_shutdown(void *dummy)
{
	unsigned int v;
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);

	/* restoring APIC_LVTPC can trigger an apic error because the delivery
	 * mode and vector nr combination can be illegal. That's by design: on
	 * power on apic lvt contain a zero vector nr which are legal only for
	 * NMI delivery mode. So inhibit apic err before restoring lvtpc
	 */
	v = apic_read(APIC_LVTERR);
	apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
	apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
	apic_write(APIC_LVTERR, v);
	nmi_restore_registers(msrs);
}

static void nmi_shutdown(void)
{
	struct op_msrs *msrs;

	nmi_enabled = 0;
	on_each_cpu(nmi_cpu_shutdown, NULL, 1);
	unregister_die_notifier(&profile_exceptions_nb);
	msrs = &get_cpu_var(cpu_msrs);
	model->shutdown(msrs);
	free_msrs();
	put_cpu_var(cpu_msrs);
}

static void nmi_cpu_start(void *dummy)
{
	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
	model->start(msrs);
}

static int nmi_start(void)
{
	on_each_cpu(nmi_cpu_start, NULL, 1);
	return 0;
}

static void nmi_cpu_stop(void *dummy)
{
	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
	model->stop(msrs);
}

static void nmi_stop(void)
{
	on_each_cpu(nmi_cpu_stop, NULL, 1);
}

struct op_counter_config counter_config[OP_MAX_COUNTER];

static int nmi_create_files(struct super_block *sb, struct dentry *root)
{
	unsigned int i;

	for (i = 0; i < model->num_counters; ++i) {
		struct dentry *dir;
		char buf[4];

		/* quick little hack to _not_ expose a counter if it is not
		 * available for use.  This should protect userspace app.
		 * NOTE:  assumes 1:1 mapping here (that counters are organized
		 *        sequentially in their struct assignment).
		 */
		if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
			continue;

		snprintf(buf,  sizeof(buf), "%d", i);
		dir = oprofilefs_mkdir(sb, root, buf);
		oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
		oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
		oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
		oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
		oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
		oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
	}

	return 0;
}

#ifdef CONFIG_SMP
static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
				 void *data)
{
	int cpu = (unsigned long)data;
	switch (action) {
	case CPU_DOWN_FAILED:
	case CPU_ONLINE:
		smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
		break;
	case CPU_DOWN_PREPARE:
		smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
		break;
	}
	return NOTIFY_DONE;
}

static struct notifier_block oprofile_cpu_nb = {
	.notifier_call = oprofile_cpu_notifier
};
#endif

#ifdef CONFIG_PM

static int nmi_suspend(struct sys_device *dev, pm_message_t state)
{
	/* Only one CPU left, just stop that one */
	if (nmi_enabled == 1)
		nmi_cpu_stop(NULL);
	return 0;
}

static int nmi_resume(struct sys_device *dev)
{
	if (nmi_enabled == 1)
		nmi_cpu_start(NULL);
	return 0;
}

static struct sysdev_class oprofile_sysclass = {
	.name		= "oprofile",
	.resume		= nmi_resume,
	.suspend	= nmi_suspend,
};

static struct sys_device device_oprofile = {
	.id	= 0,
	.cls	= &oprofile_sysclass,
};

static int __init init_sysfs(void)
{
	int error;

	error = sysdev_class_register(&oprofile_sysclass);
	if (!error)
		error = sysdev_register(&device_oprofile);
	return error;
}

static void exit_sysfs(void)
{
	sysdev_unregister(&device_oprofile);
	sysdev_class_unregister(&oprofile_sysclass);
}

#else
#define init_sysfs() do { } while (0)
#define exit_sysfs() do { } while (0)
#endif /* CONFIG_PM */

static int __init p4_init(char **cpu_type)
{
	__u8 cpu_model = boot_cpu_data.x86_model;

	if (cpu_model > 6 || cpu_model == 5)
		return 0;

#ifndef CONFIG_SMP
	*cpu_type = "i386/p4";
	model = &op_p4_spec;
	return 1;
#else
	switch (smp_num_siblings) {
	case 1:
		*cpu_type = "i386/p4";
		model = &op_p4_spec;
		return 1;

	case 2:
		*cpu_type = "i386/p4-ht";
		model = &op_p4_ht2_spec;
		return 1;
	}
#endif

	printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
	printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
	return 0;
}

int force_arch_perfmon;
module_param(force_arch_perfmon, int, 0);

static int __init ppro_init(char **cpu_type)
{
	__u8 cpu_model = boot_cpu_data.x86_model;

	if (force_arch_perfmon && cpu_has_arch_perfmon)
		return 0;

	switch (cpu_model) {
	case 0 ... 2:
		*cpu_type = "i386/ppro";
		break;
	case 3 ... 5:
		*cpu_type = "i386/pii";
		break;
	case 6 ... 8:
	case 10 ... 11:
		*cpu_type = "i386/piii";
		break;
	case 9:
	case 13:
		*cpu_type = "i386/p6_mobile";
		break;
	case 14:
		*cpu_type = "i386/core";
		break;
	case 15: case 23:
		*cpu_type = "i386/core_2";
		break;
	default:
		/* Unknown */
		return 0;
	}

	model = &op_ppro_spec;
	return 1;
}

static int __init arch_perfmon_init(char **cpu_type)
{
	if (!cpu_has_arch_perfmon)
		return 0;
	*cpu_type = "i386/arch_perfmon";
	model = &op_arch_perfmon_spec;
	arch_perfmon_setup_counters();
	return 1;
}

/* in order to get sysfs right */
static int using_nmi;

int __init op_nmi_init(struct oprofile_operations *ops)
{
	__u8 vendor = boot_cpu_data.x86_vendor;
	__u8 family = boot_cpu_data.x86;
	char *cpu_type = NULL;
	int ret = 0;

	if (!cpu_has_apic)
		return -ENODEV;

	switch (vendor) {
	case X86_VENDOR_AMD:
		/* Needs to be at least an Athlon (or hammer in 32bit mode) */

		switch (family) {
		default:
			return -ENODEV;
		case 6:
			model = &op_amd_spec;
			cpu_type = "i386/athlon";
			break;
		case 0xf:
			model = &op_amd_spec;
			/* Actually it could be i386/hammer too, but give
			 user space an consistent name. */
			cpu_type = "x86-64/hammer";
			break;
		case 0x10:
			model = &op_amd_spec;
			cpu_type = "x86-64/family10";
			break;
		case 0x11:
			model = &op_amd_spec;
			cpu_type = "x86-64/family11h";
			break;
		}
		break;

	case X86_VENDOR_INTEL:
		switch (family) {
			/* Pentium IV */
		case 0xf:
			p4_init(&cpu_type);
			break;

			/* A P6-class processor */
		case 6:
			ppro_init(&cpu_type);
			break;

		default:
			break;
		}

		if (!cpu_type && !arch_perfmon_init(&cpu_type))
			return -ENODEV;
		break;

	default:
		return -ENODEV;
	}

#ifdef CONFIG_SMP
	register_cpu_notifier(&oprofile_cpu_nb);
#endif
	/* default values, can be overwritten by model */
	ops->create_files = nmi_create_files;
	ops->setup = nmi_setup;
	ops->shutdown = nmi_shutdown;
	ops->start = nmi_start;
	ops->stop = nmi_stop;
	ops->cpu_type = cpu_type;

	if (model->init)
		ret = model->init(ops);
	if (ret)
		return ret;

	init_sysfs();
	using_nmi = 1;
	printk(KERN_INFO "oprofile: using NMI interrupt.\n");
	return 0;
}

void op_nmi_exit(void)
{
	if (using_nmi) {
		exit_sysfs();
#ifdef CONFIG_SMP
		unregister_cpu_notifier(&oprofile_cpu_nb);
#endif
	}
	if (model->exit)
		model->exit();
}
Commit	Line	Data
1da177e4 LT	1	/**
	2	* @file nmi_int.c
	3	*
adf5ec0b	4	* @remark Copyright 2002-2008 OProfile authors
1da177e4 LT	5	* @remark Read the file COPYING
	6	*
	7	* @author John Levon <levon@movementarian.org>
adf5ec0b	8	* @author Robert Richter <robert.richter@amd.com>
1da177e4 LT	9	*/
	10
	11	#include <linux/init.h>
	12	#include <linux/notifier.h>
	13	#include <linux/smp.h>
	14	#include <linux/oprofile.h>
	15	#include <linux/sysdev.h>
	16	#include <linux/slab.h>
1cfcea1b	17	#include <linux/moduleparam.h>
1eeb66a1	18	#include <linux/kdebug.h>
80a8c9ff	19	#include <linux/cpu.h>
1da177e4 LT	20	#include <asm/nmi.h>
	21	#include <asm/msr.h>
	22	#include <asm/apic.h>
b75f53db	23
1da177e4 LT	24	#include "op_counter.h"
1da177e4 LT	25	#include "op_x86_model.h"
2fbe7b25	26
b75f53db	27	static struct op_x86_model_spec const *model;
d18d00f5 MT	28	static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
d18d00f5 MT	29	static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
2fbe7b25	30
1da177e4 LT	31	/* 0 == registered but off, 1 == registered and on */
	32	static int nmi_enabled = 0;
	33
c7c19f8e AB	34	static int profile_exceptions_notify(struct notifier_block *self,
c7c19f8e AB	35	unsigned long val, void *data)
1da177e4	36	{
2fbe7b25 DZ	37	struct die_args args = (struct die_args )data;
	38	int ret = NOTIFY_DONE;
	39	int cpu = smp_processor_id();
	40
b75f53db	41	switch (val) {
2fbe7b25	42	case DIE_NMI:
d18d00f5	43	if (model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu)))
2fbe7b25 DZ	44	ret = NOTIFY_STOP;
	45	break;
	46	default:
	47	break;
	48	}
	49	return ret;
1da177e4	50	}
2fbe7b25	51
b75f53db	52	static void nmi_cpu_save_registers(struct op_msrs *msrs)
1da177e4 LT	53	{
1da177e4 LT	54	unsigned int const nr_ctrs = model->num_counters;
b75f53db CM	55	unsigned int const nr_ctrls = model->num_controls;
	56	struct op_msr *counters = msrs->counters;
	57	struct op_msr *controls = msrs->controls;
1da177e4 LT	58	unsigned int i;
	59
	60	for (i = 0; i < nr_ctrs; ++i) {
b75f53db	61	if (counters[i].addr) {
cb9c448c DZ	62	rdmsr(counters[i].addr,
	63	counters[i].saved.low,
	64	counters[i].saved.high);
	65	}
1da177e4	66	}
b75f53db	67
1da177e4	68	for (i = 0; i < nr_ctrls; ++i) {
b75f53db	69	if (controls[i].addr) {
cb9c448c DZ	70	rdmsr(controls[i].addr,
	71	controls[i].saved.low,
	72	controls[i].saved.high);
	73	}
1da177e4 LT	74	}
	75	}
	76
b75f53db	77	static void nmi_save_registers(void *dummy)
1da177e4 LT	78	{
1da177e4 LT	79	int cpu = smp_processor_id();
d18d00f5	80	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
1da177e4 LT	81	nmi_cpu_save_registers(msrs);
	82	}
	83
1da177e4 LT	84	static void free_msrs(void)
	85	{
	86	int i;
c8912599	87	for_each_possible_cpu(i) {
d18d00f5 MT	88	kfree(per_cpu(cpu_msrs, i).counters);
	89	per_cpu(cpu_msrs, i).counters = NULL;
	90	kfree(per_cpu(cpu_msrs, i).controls);
	91	per_cpu(cpu_msrs, i).controls = NULL;
1da177e4 LT	92	}
	93	}
	94
1da177e4 LT	95	static int allocate_msrs(void)
1da177e4 LT	96	{
4c168eaf	97	int success = 1;
1da177e4 LT	98	size_t controls_size = sizeof(struct op_msr) * model->num_controls;
	99	size_t counters_size = sizeof(struct op_msr) * model->num_counters;
	100
4c168eaf	101	int i;
0939c17c	102	for_each_possible_cpu(i) {
d18d00f5 MT	103	per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
	104	GFP_KERNEL);
	105	if (!per_cpu(cpu_msrs, i).counters) {
1da177e4 LT	106	success = 0;
	107	break;
	108	}
4c168eaf RR	109	per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
4c168eaf RR	110	GFP_KERNEL);
d18d00f5	111	if (!per_cpu(cpu_msrs, i).controls) {
1da177e4 LT	112	success = 0;
	113	break;
	114	}
	115	}
	116
	117	if (!success)
	118	free_msrs();
	119
	120	return success;
	121	}
	122
b75f53db	123	static void nmi_cpu_setup(void *dummy)
1da177e4 LT	124	{
1da177e4 LT	125	int cpu = smp_processor_id();
d18d00f5	126	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
1da177e4 LT	127	spin_lock(&oprofilefs_lock);
	128	model->setup_ctrs(msrs);
	129	spin_unlock(&oprofilefs_lock);
d18d00f5	130	per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
1da177e4 LT	131	apic_write(APIC_LVTPC, APIC_DM_NMI);
	132	}
	133
2fbe7b25 DZ	134	static struct notifier_block profile_exceptions_nb = {
	135	.notifier_call = profile_exceptions_notify,
	136	.next = NULL,
	137	.priority = 0
	138	};
1da177e4 LT	139
	140	static int nmi_setup(void)
	141	{
b75f53db	142	int err = 0;
6c977aad	143	int cpu;
2fbe7b25	144
1da177e4 LT	145	if (!allocate_msrs())
	146	return -ENOMEM;
	147
b75f53db CM	148	err = register_die_notifier(&profile_exceptions_nb);
b75f53db CM	149	if (err) {
1da177e4	150	free_msrs();
2fbe7b25	151	return err;
1da177e4	152	}
2fbe7b25	153
4c168eaf	154	/* We need to serialize save and setup for HT because the subset
1da177e4 LT	155	* of msrs are distinct for save and setup operations
1da177e4 LT	156	*/
6c977aad AK	157
6c977aad AK	158	/* Assume saved/restored counters are the same on all CPUs */
d18d00f5	159	model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
b75f53db	160	for_each_possible_cpu(cpu) {
0939c17c	161	if (cpu != 0) {
d18d00f5 MT	162	memcpy(per_cpu(cpu_msrs, cpu).counters,
d18d00f5 MT	163	per_cpu(cpu_msrs, 0).counters,
0939c17c CW	164	sizeof(struct op_msr) * model->num_counters);
0939c17c CW	165
d18d00f5 MT	166	memcpy(per_cpu(cpu_msrs, cpu).controls,
d18d00f5 MT	167	per_cpu(cpu_msrs, 0).controls,
0939c17c CW	168	sizeof(struct op_msr) * model->num_controls);
0939c17c CW	169	}
4c168eaf	170
6c977aad	171	}
15c8b6c1 JA	172	on_each_cpu(nmi_save_registers, NULL, 1);
15c8b6c1 JA	173	on_each_cpu(nmi_cpu_setup, NULL, 1);
1da177e4 LT	174	nmi_enabled = 1;
	175	return 0;
	176	}
	177
4c168eaf	178	static void nmi_restore_registers(struct op_msrs *msrs)
1da177e4 LT	179	{
1da177e4 LT	180	unsigned int const nr_ctrs = model->num_counters;
b75f53db CM	181	unsigned int const nr_ctrls = model->num_controls;
	182	struct op_msr *counters = msrs->counters;
	183	struct op_msr *controls = msrs->controls;
1da177e4 LT	184	unsigned int i;
	185
	186	for (i = 0; i < nr_ctrls; ++i) {
b75f53db	187	if (controls[i].addr) {
cb9c448c DZ	188	wrmsr(controls[i].addr,
	189	controls[i].saved.low,
	190	controls[i].saved.high);
	191	}
1da177e4	192	}
b75f53db	193
1da177e4	194	for (i = 0; i < nr_ctrs; ++i) {
b75f53db	195	if (counters[i].addr) {
cb9c448c DZ	196	wrmsr(counters[i].addr,
	197	counters[i].saved.low,
	198	counters[i].saved.high);
	199	}
1da177e4 LT	200	}
1da177e4 LT	201	}
1da177e4	202
b75f53db	203	static void nmi_cpu_shutdown(void *dummy)
1da177e4 LT	204	{
	205	unsigned int v;
	206	int cpu = smp_processor_id();
d18d00f5	207	struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);
b75f53db	208
1da177e4 LT	209	/* restoring APIC_LVTPC can trigger an apic error because the delivery
	210	* mode and vector nr combination can be illegal. That's by design: on
	211	* power on apic lvt contain a zero vector nr which are legal only for
	212	* NMI delivery mode. So inhibit apic err before restoring lvtpc
	213	*/
	214	v = apic_read(APIC_LVTERR);
	215	apic_write(APIC_LVTERR, v \| APIC_LVT_MASKED);
d18d00f5	216	apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
1da177e4	217	apic_write(APIC_LVTERR, v);
4c168eaf	218	nmi_restore_registers(msrs);
1da177e4 LT	219	}
1da177e4 LT	220
1da177e4 LT	221	static void nmi_shutdown(void)
1da177e4 LT	222	{
b61e06f2 AR	223	struct op_msrs *msrs;
b61e06f2 AR	224
1da177e4	225	nmi_enabled = 0;
15c8b6c1	226	on_each_cpu(nmi_cpu_shutdown, NULL, 1);
2fbe7b25	227	unregister_die_notifier(&profile_exceptions_nb);
b61e06f2	228	msrs = &get_cpu_var(cpu_msrs);
d18d00f5	229	model->shutdown(msrs);
1da177e4	230	free_msrs();
93e1ade5	231	put_cpu_var(cpu_msrs);
1da177e4 LT	232	}
1da177e4 LT	233
b75f53db	234	static void nmi_cpu_start(void *dummy)
1da177e4	235	{
d18d00f5	236	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
1da177e4 LT	237	model->start(msrs);
1da177e4 LT	238	}
1da177e4 LT	239
	240	static int nmi_start(void)
	241	{
15c8b6c1	242	on_each_cpu(nmi_cpu_start, NULL, 1);
1da177e4 LT	243	return 0;
1da177e4 LT	244	}
b75f53db CM	245
b75f53db CM	246	static void nmi_cpu_stop(void *dummy)
1da177e4	247	{
d18d00f5	248	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
1da177e4 LT	249	model->stop(msrs);
1da177e4 LT	250	}
b75f53db	251
1da177e4 LT	252	static void nmi_stop(void)
1da177e4 LT	253	{
15c8b6c1	254	on_each_cpu(nmi_cpu_stop, NULL, 1);
1da177e4 LT	255	}
1da177e4 LT	256
1da177e4 LT	257	struct op_counter_config counter_config[OP_MAX_COUNTER];
1da177e4 LT	258
b75f53db	259	static int nmi_create_files(struct super_block sb, struct dentry root)
1da177e4 LT	260	{
	261	unsigned int i;
	262
	263	for (i = 0; i < model->num_counters; ++i) {
b75f53db	264	struct dentry *dir;
0c6856f7	265	char buf[4];
b75f53db CM	266
b75f53db CM	267	/* quick little hack to _not_ expose a counter if it is not
cb9c448c DZ	268	* available for use. This should protect userspace app.
	269	* NOTE: assumes 1:1 mapping here (that counters are organized
	270	* sequentially in their struct assignment).
	271	*/
	272	if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
	273	continue;
	274
0c6856f7	275	snprintf(buf, sizeof(buf), "%d", i);
1da177e4	276	dir = oprofilefs_mkdir(sb, root, buf);
b75f53db CM	277	oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
	278	oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
	279	oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
	280	oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
	281	oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
	282	oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
1da177e4 LT	283	}
	284
	285	return 0;
	286	}
b75f53db	287
69046d43 RR	288	#ifdef CONFIG_SMP
	289	static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
	290	void *data)
	291	{
	292	int cpu = (unsigned long)data;
	293	switch (action) {
	294	case CPU_DOWN_FAILED:
	295	case CPU_ONLINE:
	296	smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
	297	break;
	298	case CPU_DOWN_PREPARE:
	299	smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
	300	break;
	301	}
	302	return NOTIFY_DONE;
	303	}
	304
	305	static struct notifier_block oprofile_cpu_nb = {
	306	.notifier_call = oprofile_cpu_notifier
	307	};
	308	#endif
	309
	310	#ifdef CONFIG_PM
	311
	312	static int nmi_suspend(struct sys_device *dev, pm_message_t state)
	313	{
	314	/* Only one CPU left, just stop that one */
	315	if (nmi_enabled == 1)
	316	nmi_cpu_stop(NULL);
	317	return 0;
	318	}
	319
	320	static int nmi_resume(struct sys_device *dev)
	321	{
	322	if (nmi_enabled == 1)
	323	nmi_cpu_start(NULL);
	324	return 0;
	325	}
	326
	327	static struct sysdev_class oprofile_sysclass = {
	328	.name = "oprofile",
	329	.resume = nmi_resume,
	330	.suspend = nmi_suspend,
	331	};
	332
	333	static struct sys_device device_oprofile = {
	334	.id = 0,
	335	.cls = &oprofile_sysclass,
	336	};
	337
	338	static int __init init_sysfs(void)
	339	{
	340	int error;
	341
	342	error = sysdev_class_register(&oprofile_sysclass);
	343	if (!error)
	344	error = sysdev_register(&device_oprofile);
	345	return error;
	346	}
	347
	348	static void exit_sysfs(void)
	349	{
	350	sysdev_unregister(&device_oprofile);
	351	sysdev_class_unregister(&oprofile_sysclass);
352	}
353
354	#else
355	#define init_sysfs() do { } while (0)
356	#define exit_sysfs() do { } while (0)
357	#endif /* CONFIG_PM */
358
b75f53db	359	static int __init p4_init(char **cpu_type)
1da177e4 LT	360	{
	361	__u8 cpu_model = boot_cpu_data.x86_model;
	362
1f3d7b60	363	if (cpu_model > 6 \|\| cpu_model == 5)
1da177e4 LT	364	return 0;
	365
	366	#ifndef CONFIG_SMP
	367	*cpu_type = "i386/p4";
	368	model = &op_p4_spec;
	369	return 1;
	370	#else
	371	switch (smp_num_siblings) {
b75f53db CM	372	case 1:
	373	*cpu_type = "i386/p4";
	374	model = &op_p4_spec;
	375	return 1;
	376
	377	case 2:
	378	*cpu_type = "i386/p4-ht";
	379	model = &op_p4_ht2_spec;
	380	return 1;
1da177e4 LT	381	}
	382	#endif
	383
	384	printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
	385	printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
	386	return 0;
	387	}
	388
1dcdb5a9 AK	389	int force_arch_perfmon;
	390	module_param(force_arch_perfmon, int, 0);
	391
b75f53db	392	static int __init ppro_init(char **cpu_type)
1da177e4 LT	393	{
	394	__u8 cpu_model = boot_cpu_data.x86_model;
	395
1dcdb5a9 AK	396	if (force_arch_perfmon && cpu_has_arch_perfmon)
	397	return 0;
	398
4b9f12a3 LT	399	switch (cpu_model) {
	400	case 0 ... 2:
	401	*cpu_type = "i386/ppro";
	402	break;
	403	case 3 ... 5:
	404	*cpu_type = "i386/pii";
	405	break;
	406	case 6 ... 8:
3d337c65	407	case 10 ... 11:
4b9f12a3 LT	408	*cpu_type = "i386/piii";
	409	break;
	410	case 9:
3d337c65	411	case 13:
4b9f12a3 LT	412	*cpu_type = "i386/p6_mobile";
4b9f12a3 LT	413	break;
4b9f12a3	414	case 14:
64471ebe	415	*cpu_type = "i386/core";
4b9f12a3 LT	416	break;
	417	case 15: case 23:
	418	*cpu_type = "i386/core_2";
	419	break;
4b9f12a3 LT	420	default:
4b9f12a3 LT	421	/* Unknown */
1da177e4	422	return 0;
1da177e4 LT	423	}
	424
	425	model = &op_ppro_spec;
	426	return 1;
	427	}
	428
b9917028 AK	429	static int __init arch_perfmon_init(char **cpu_type)
	430	{
	431	if (!cpu_has_arch_perfmon)
	432	return 0;
	433	*cpu_type = "i386/arch_perfmon";
	434	model = &op_arch_perfmon_spec;
	435	arch_perfmon_setup_counters();
	436	return 1;
	437	}
	438
405ae7d3	439	/* in order to get sysfs right */
1da177e4 LT	440	static int using_nmi;
1da177e4 LT	441
96d0821c	442	int __init op_nmi_init(struct oprofile_operations *ops)
1da177e4 LT	443	{
	444	__u8 vendor = boot_cpu_data.x86_vendor;
	445	__u8 family = boot_cpu_data.x86;
b9917028	446	char *cpu_type = NULL;
adf5ec0b	447	int ret = 0;
1da177e4 LT	448
	449	if (!cpu_has_apic)
	450	return -ENODEV;
b75f53db	451
1da177e4	452	switch (vendor) {
b75f53db CM	453	case X86_VENDOR_AMD:
b75f53db CM	454	/* Needs to be at least an Athlon (or hammer in 32bit mode) */
1da177e4	455
b75f53db CM	456	switch (family) {
	457	default:
	458	return -ENODEV;
	459	case 6:
6657fe4f	460	model = &op_amd_spec;
b75f53db CM	461	cpu_type = "i386/athlon";
	462	break;
	463	case 0xf:
6657fe4f	464	model = &op_amd_spec;
b75f53db CM	465	/* Actually it could be i386/hammer too, but give
	466	user space an consistent name. */
	467	cpu_type = "x86-64/hammer";
	468	break;
	469	case 0x10:
6657fe4f	470	model = &op_amd_spec;
b75f53db CM	471	cpu_type = "x86-64/family10";
b75f53db CM	472	break;
12f2b261	473	case 0x11:
6657fe4f	474	model = &op_amd_spec;
12f2b261 BK	475	cpu_type = "x86-64/family11h";
12f2b261 BK	476	break;
b75f53db CM	477	}
	478	break;
	479
	480	case X86_VENDOR_INTEL:
	481	switch (family) {
	482	/* Pentium IV */
	483	case 0xf:
b9917028	484	p4_init(&cpu_type);
1da177e4	485	break;
b75f53db CM	486
	487	/* A P6-class processor */
	488	case 6:
b9917028	489	ppro_init(&cpu_type);
1da177e4 LT	490	break;
	491
	492	default:
b9917028	493	break;
b75f53db	494	}
b9917028 AK	495
	496	if (!cpu_type && !arch_perfmon_init(&cpu_type))
	497	return -ENODEV;
b75f53db CM	498	break;
	499
	500	default:
	501	return -ENODEV;
1da177e4 LT	502	}
1da177e4 LT	503
80a8c9ff AK	504	#ifdef CONFIG_SMP
	505	register_cpu_notifier(&oprofile_cpu_nb);
	506	#endif
270d3e1a RR	507	/* default values, can be overwritten by model */
	508	ops->create_files = nmi_create_files;
	509	ops->setup = nmi_setup;
	510	ops->shutdown = nmi_shutdown;
	511	ops->start = nmi_start;
	512	ops->stop = nmi_stop;
	513	ops->cpu_type = cpu_type;
	514
adf5ec0b RR	515	if (model->init)
	516	ret = model->init(ops);
	517	if (ret)
	518	return ret;
	519
405ae7d3	520	init_sysfs();
1da177e4	521	using_nmi = 1;
1da177e4 LT	522	printk(KERN_INFO "oprofile: using NMI interrupt.\n");
	523	return 0;
	524	}
	525
96d0821c	526	void op_nmi_exit(void)
1da177e4	527	{
80a8c9ff	528	if (using_nmi) {
405ae7d3	529	exit_sysfs();
80a8c9ff AK	530	#ifdef CONFIG_SMP
	531	unregister_cpu_notifier(&oprofile_cpu_nb);
	532	#endif
	533	}
adf5ec0b RR	534	if (model->exit)
adf5ec0b RR	535	model->exit();
1da177e4	536	}