[deliverable/linux.git] / arch / x86 / oprofile / nmi_int.c

/**
 * @file nmi_int.c
 *
 * @remark Copyright 2002-2009 OProfile authors
 * @remark Read the file COPYING
 *
 * @author John Levon <levon@movementarian.org>
 * @author Robert Richter <robert.richter@amd.com>
 * @author Barry Kasindorf <barry.kasindorf@amd.com>
 * @author Jason Yeh <jason.yeh@amd.com>
 * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
 */

#include <linux/init.h>
#include <linux/notifier.h>
#include <linux/smp.h>
#include <linux/oprofile.h>
#include <linux/sysdev.h>
#include <linux/slab.h>
#include <linux/moduleparam.h>
#include <linux/kdebug.h>
#include <linux/cpu.h>
#include <asm/nmi.h>
#include <asm/msr.h>
#include <asm/apic.h>

#include "op_counter.h"
#include "op_x86_model.h"

static struct op_x86_model_spec *model;
static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
static DEFINE_PER_CPU(unsigned long, saved_lvtpc);

/* 0 == registered but off, 1 == registered and on */
static int nmi_enabled = 0;


#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
extern atomic_t multiplex_counter;
#endif

struct op_counter_config counter_config[OP_MAX_COUNTER];

/* common functions */

u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
		    struct op_counter_config *counter_config)
{
	u64 val = 0;
	u16 event = (u16)counter_config->event;

	val |= ARCH_PERFMON_EVENTSEL_INT;
	val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
	val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
	val |= (counter_config->unit_mask & 0xFF) << 8;
	event &= model->event_mask ? model->event_mask : 0xFF;
	val |= event & 0xFF;
	val |= (event & 0x0F00) << 24;

	return val;
}


static int profile_exceptions_notify(struct notifier_block *self,
				     unsigned long val, void *data)
{
	struct die_args *args = (struct die_args *)data;
	int ret = NOTIFY_DONE;
	int cpu = smp_processor_id();

	switch (val) {
	case DIE_NMI:
	case DIE_NMI_IPI:
		model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu));
		ret = NOTIFY_STOP;
		break;
	default:
		break;
	}
	return ret;
}

static void nmi_cpu_save_registers(struct op_msrs *msrs)
{
	struct op_msr *counters = msrs->counters;
	struct op_msr *controls = msrs->controls;
	unsigned int i;

	for (i = 0; i < model->num_counters; ++i) {
		if (counters[i].addr)
			rdmsrl(counters[i].addr, counters[i].saved);
	}

	for (i = 0; i < model->num_controls; ++i) {
		if (controls[i].addr)
			rdmsrl(controls[i].addr, controls[i].saved);
	}
}

static void nmi_cpu_start(void *dummy)
{
	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
	model->start(msrs);
}

static int nmi_start(void)
{
	on_each_cpu(nmi_cpu_start, NULL, 1);
	return 0;
}

static void nmi_cpu_stop(void *dummy)
{
	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
	model->stop(msrs);
}

static void nmi_stop(void)
{
	on_each_cpu(nmi_cpu_stop, NULL, 1);
}

#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX

static DEFINE_PER_CPU(int, switch_index);

inline int op_x86_phys_to_virt(int phys)
{
	return __get_cpu_var(switch_index) + phys;
}

static void nmi_shutdown_mux(void)
{
	int i;
	for_each_possible_cpu(i) {
		kfree(per_cpu(cpu_msrs, i).multiplex);
		per_cpu(cpu_msrs, i).multiplex = NULL;
		per_cpu(switch_index, i) = 0;
	}
}

static int nmi_setup_mux(void)
{
	size_t multiplex_size =
		sizeof(struct op_msr) * model->num_virt_counters;
	int i;
	for_each_possible_cpu(i) {
		per_cpu(cpu_msrs, i).multiplex =
			kmalloc(multiplex_size, GFP_KERNEL);
		if (!per_cpu(cpu_msrs, i).multiplex)
			return 0;
	}
	return 1;
}

static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
{
	int i;
	struct op_msr *multiplex = msrs->multiplex;

	for (i = 0; i < model->num_virt_counters; ++i) {
		if (counter_config[i].enabled) {
			multiplex[i].saved = -(u64)counter_config[i].count;
		} else {
			multiplex[i].addr  = 0;
			multiplex[i].saved = 0;
		}
	}

	per_cpu(switch_index, cpu) = 0;
}

static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
{
	struct op_msr *multiplex = msrs->multiplex;
	int i;

	for (i = 0; i < model->num_counters; ++i) {
		int virt = op_x86_phys_to_virt(i);
		if (multiplex[virt].addr)
			rdmsrl(multiplex[virt].addr, multiplex[virt].saved);
	}
}

static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
{
	struct op_msr *multiplex = msrs->multiplex;
	int i;

	for (i = 0; i < model->num_counters; ++i) {
		int virt = op_x86_phys_to_virt(i);
		if (multiplex[virt].addr)
			wrmsrl(multiplex[virt].addr, multiplex[virt].saved);
	}
}

static void nmi_cpu_switch(void *dummy)
{
	int cpu = smp_processor_id();
	int si = per_cpu(switch_index, cpu);
	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);

	nmi_cpu_stop(NULL);
	nmi_cpu_save_mpx_registers(msrs);

	/* move to next set */
	si += model->num_counters;
	if ((si > model->num_virt_counters) || (counter_config[si].count == 0))
		per_cpu(switch_index, cpu) = 0;
	else
		per_cpu(switch_index, cpu) = si;

	model->switch_ctrl(model, msrs);
	nmi_cpu_restore_mpx_registers(msrs);

	nmi_cpu_start(NULL);
}


/*
 * Quick check to see if multiplexing is necessary.
 * The check should be sufficient since counters are used
 * in ordre.
 */
static int nmi_multiplex_on(void)
{
	return counter_config[model->num_counters].count ? 0 : -EINVAL;
}

static int nmi_switch_event(void)
{
	if (!model->switch_ctrl)
		return -ENOSYS;		/* not implemented */
	if (nmi_multiplex_on() < 0)
		return -EINVAL;		/* not necessary */

	on_each_cpu(nmi_cpu_switch, NULL, 1);

	atomic_inc(&multiplex_counter);

	return 0;
}

#else

inline int op_x86_phys_to_virt(int phys) { return phys; }
static inline void nmi_shutdown_mux(void) { }
static inline int nmi_setup_mux(void) { return 1; }
static inline void
nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { }

#endif

static void free_msrs(void)
{
	int i;
	for_each_possible_cpu(i) {
		kfree(per_cpu(cpu_msrs, i).counters);
		per_cpu(cpu_msrs, i).counters = NULL;
		kfree(per_cpu(cpu_msrs, i).controls);
		per_cpu(cpu_msrs, i).controls = NULL;
	}
}

static int allocate_msrs(void)
{
	size_t controls_size = sizeof(struct op_msr) * model->num_controls;
	size_t counters_size = sizeof(struct op_msr) * model->num_counters;

	int i;
	for_each_possible_cpu(i) {
		per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
							GFP_KERNEL);
		if (!per_cpu(cpu_msrs, i).counters)
			return 0;
		per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
							GFP_KERNEL);
		if (!per_cpu(cpu_msrs, i).controls)
			return 0;
	}

	return 1;
}

static void nmi_cpu_setup(void *dummy)
{
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
	nmi_cpu_save_registers(msrs);
	spin_lock(&oprofilefs_lock);
	model->setup_ctrs(model, msrs);
	nmi_cpu_setup_mux(cpu, msrs);
	spin_unlock(&oprofilefs_lock);
	per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
	apic_write(APIC_LVTPC, APIC_DM_NMI);
}

static struct notifier_block profile_exceptions_nb = {
	.notifier_call = profile_exceptions_notify,
	.next = NULL,
	.priority = 2
};

static int nmi_setup(void)
{
	int err = 0;
	int cpu;

	if (!allocate_msrs())
		err = -ENOMEM;
	else if (!nmi_setup_mux())
		err = -ENOMEM;
	else
		err = register_die_notifier(&profile_exceptions_nb);

	if (err) {
		free_msrs();
		nmi_shutdown_mux();
		return err;
	}

	/* We need to serialize save and setup for HT because the subset
	 * of msrs are distinct for save and setup operations
	 */

	/* Assume saved/restored counters are the same on all CPUs */
	model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
	for_each_possible_cpu(cpu) {
		if (cpu != 0) {
			memcpy(per_cpu(cpu_msrs, cpu).counters,
				per_cpu(cpu_msrs, 0).counters,
				sizeof(struct op_msr) * model->num_counters);

			memcpy(per_cpu(cpu_msrs, cpu).controls,
				per_cpu(cpu_msrs, 0).controls,
				sizeof(struct op_msr) * model->num_controls);
#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
			memcpy(per_cpu(cpu_msrs, cpu).multiplex,
				per_cpu(cpu_msrs, 0).multiplex,
				sizeof(struct op_msr) * model->num_virt_counters);
#endif
		}
	}
	on_each_cpu(nmi_cpu_setup, NULL, 1);
	nmi_enabled = 1;
	return 0;
}

static void nmi_cpu_restore_registers(struct op_msrs *msrs)
{
	struct op_msr *counters = msrs->counters;
	struct op_msr *controls = msrs->controls;
	unsigned int i;

	for (i = 0; i < model->num_controls; ++i) {
		if (controls[i].addr)
			wrmsrl(controls[i].addr, controls[i].saved);
	}

	for (i = 0; i < model->num_counters; ++i) {
		if (counters[i].addr)
			wrmsrl(counters[i].addr, counters[i].saved);
	}
}

static void nmi_cpu_shutdown(void *dummy)
{
	unsigned int v;
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);

	/* restoring APIC_LVTPC can trigger an apic error because the delivery
	 * mode and vector nr combination can be illegal. That's by design: on
	 * power on apic lvt contain a zero vector nr which are legal only for
	 * NMI delivery mode. So inhibit apic err before restoring lvtpc
	 */
	v = apic_read(APIC_LVTERR);
	apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
	apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
	apic_write(APIC_LVTERR, v);
	nmi_cpu_restore_registers(msrs);
}

static void nmi_shutdown(void)
{
	struct op_msrs *msrs;

	nmi_enabled = 0;
	on_each_cpu(nmi_cpu_shutdown, NULL, 1);
	unregister_die_notifier(&profile_exceptions_nb);
	nmi_shutdown_mux();
	msrs = &get_cpu_var(cpu_msrs);
	model->shutdown(msrs);
	free_msrs();
	put_cpu_var(cpu_msrs);
}

static int nmi_create_files(struct super_block *sb, struct dentry *root)
{
	unsigned int i;

	for (i = 0; i < model->num_virt_counters; ++i) {
		struct dentry *dir;
		char buf[4];

#ifndef CONFIG_OPROFILE_EVENT_MULTIPLEX
		/* quick little hack to _not_ expose a counter if it is not
		 * available for use.  This should protect userspace app.
		 * NOTE:  assumes 1:1 mapping here (that counters are organized
		 *        sequentially in their struct assignment).
		 */
		if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
			continue;
#endif /* CONFIG_OPROFILE_EVENT_MULTIPLEX */

		snprintf(buf,  sizeof(buf), "%d", i);
		dir = oprofilefs_mkdir(sb, root, buf);
		oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
		oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
		oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
		oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
		oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
		oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
	}

	return 0;
}

#ifdef CONFIG_SMP
static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
				 void *data)
{
	int cpu = (unsigned long)data;
	switch (action) {
	case CPU_DOWN_FAILED:
	case CPU_ONLINE:
		smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
		break;
	case CPU_DOWN_PREPARE:
		smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
		break;
	}
	return NOTIFY_DONE;
}

static struct notifier_block oprofile_cpu_nb = {
	.notifier_call = oprofile_cpu_notifier
};
#endif

#ifdef CONFIG_PM

static int nmi_suspend(struct sys_device *dev, pm_message_t state)
{
	/* Only one CPU left, just stop that one */
	if (nmi_enabled == 1)
		nmi_cpu_stop(NULL);
	return 0;
}

static int nmi_resume(struct sys_device *dev)
{
	if (nmi_enabled == 1)
		nmi_cpu_start(NULL);
	return 0;
}

static struct sysdev_class oprofile_sysclass = {
	.name		= "oprofile",
	.resume		= nmi_resume,
	.suspend	= nmi_suspend,
};

static struct sys_device device_oprofile = {
	.id	= 0,
	.cls	= &oprofile_sysclass,
};

static int __init init_sysfs(void)
{
	int error;

	error = sysdev_class_register(&oprofile_sysclass);
	if (!error)
		error = sysdev_register(&device_oprofile);
	return error;
}

static void exit_sysfs(void)
{
	sysdev_unregister(&device_oprofile);
	sysdev_class_unregister(&oprofile_sysclass);
}

#else
#define init_sysfs() do { } while (0)
#define exit_sysfs() do { } while (0)
#endif /* CONFIG_PM */

static int __init p4_init(char **cpu_type)
{
	__u8 cpu_model = boot_cpu_data.x86_model;

	if (cpu_model > 6 || cpu_model == 5)
		return 0;

#ifndef CONFIG_SMP
	*cpu_type = "i386/p4";
	model = &op_p4_spec;
	return 1;
#else
	switch (smp_num_siblings) {
	case 1:
		*cpu_type = "i386/p4";
		model = &op_p4_spec;
		return 1;

	case 2:
		*cpu_type = "i386/p4-ht";
		model = &op_p4_ht2_spec;
		return 1;
	}
#endif

	printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
	printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
	return 0;
}

static int force_arch_perfmon;
static int force_cpu_type(const char *str, struct kernel_param *kp)
{
	if (!strcmp(str, "arch_perfmon")) {
		force_arch_perfmon = 1;
		printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
	}

	return 0;
}
module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);

static int __init ppro_init(char **cpu_type)
{
	__u8 cpu_model = boot_cpu_data.x86_model;
	struct op_x86_model_spec *spec = &op_ppro_spec;	/* default */

	if (force_arch_perfmon && cpu_has_arch_perfmon)
		return 0;

	switch (cpu_model) {
	case 0 ... 2:
		*cpu_type = "i386/ppro";
		break;
	case 3 ... 5:
		*cpu_type = "i386/pii";
		break;
	case 6 ... 8:
	case 10 ... 11:
		*cpu_type = "i386/piii";
		break;
	case 9:
	case 13:
		*cpu_type = "i386/p6_mobile";
		break;
	case 14:
		*cpu_type = "i386/core";
		break;
	case 15: case 23:
		*cpu_type = "i386/core_2";
		break;
	case 26:
		spec = &op_arch_perfmon_spec;
		*cpu_type = "i386/core_i7";
		break;
	case 28:
		*cpu_type = "i386/atom";
		break;
	default:
		/* Unknown */
		return 0;
	}

	model = spec;
	return 1;
}

/* in order to get sysfs right */
static int using_nmi;

int __init op_nmi_init(struct oprofile_operations *ops)
{
	__u8 vendor = boot_cpu_data.x86_vendor;
	__u8 family = boot_cpu_data.x86;
	char *cpu_type = NULL;
	int ret = 0;

	if (!cpu_has_apic)
		return -ENODEV;

	switch (vendor) {
	case X86_VENDOR_AMD:
		/* Needs to be at least an Athlon (or hammer in 32bit mode) */

		switch (family) {
		case 6:
			cpu_type = "i386/athlon";
			break;
		case 0xf:
			/*
			 * Actually it could be i386/hammer too, but
			 * give user space an consistent name.
			 */
			cpu_type = "x86-64/hammer";
			break;
		case 0x10:
			cpu_type = "x86-64/family10";
			break;
		case 0x11:
			cpu_type = "x86-64/family11h";
			break;
		default:
			return -ENODEV;
		}
		model = &op_amd_spec;
		break;

	case X86_VENDOR_INTEL:
		switch (family) {
			/* Pentium IV */
		case 0xf:
			p4_init(&cpu_type);
			break;

			/* A P6-class processor */
		case 6:
			ppro_init(&cpu_type);
			break;

		default:
			break;
		}

		if (cpu_type)
			break;

		if (!cpu_has_arch_perfmon)
			return -ENODEV;

		/* use arch perfmon as fallback */
		cpu_type = "i386/arch_perfmon";
		model = &op_arch_perfmon_spec;
		break;

	default:
		return -ENODEV;
	}

#ifdef CONFIG_SMP
	register_cpu_notifier(&oprofile_cpu_nb);
#endif
	/* default values, can be overwritten by model */
	ops->create_files	= nmi_create_files;
	ops->setup		= nmi_setup;
	ops->shutdown		= nmi_shutdown;
	ops->start		= nmi_start;
	ops->stop		= nmi_stop;
	ops->cpu_type		= cpu_type;
#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
	ops->switch_events	= nmi_switch_event;
#endif

	if (model->init)
		ret = model->init(ops);
	if (ret)
		return ret;

	init_sysfs();
	using_nmi = 1;
	printk(KERN_INFO "oprofile: using NMI interrupt.\n");
	return 0;
}

void op_nmi_exit(void)
{
	if (using_nmi) {
		exit_sysfs();
#ifdef CONFIG_SMP
		unregister_cpu_notifier(&oprofile_cpu_nb);
#endif
	}
	if (model->exit)
		model->exit();
}
Commit	Line	Data
1da177e4 LT	1	/**
	2	* @file nmi_int.c
	3	*
4d4036e0	4	* @remark Copyright 2002-2009 OProfile authors
1da177e4 LT	5	* @remark Read the file COPYING
	6	*
	7	* @author John Levon <levon@movementarian.org>
adf5ec0b	8	* @author Robert Richter <robert.richter@amd.com>
4d4036e0 JY	9	* @author Barry Kasindorf <barry.kasindorf@amd.com>
	10	* @author Jason Yeh <jason.yeh@amd.com>
	11	* @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
1da177e4 LT	12	*/
	13
	14	#include <linux/init.h>
	15	#include <linux/notifier.h>
	16	#include <linux/smp.h>
	17	#include <linux/oprofile.h>
	18	#include <linux/sysdev.h>
	19	#include <linux/slab.h>
1cfcea1b	20	#include <linux/moduleparam.h>
1eeb66a1	21	#include <linux/kdebug.h>
80a8c9ff	22	#include <linux/cpu.h>
1da177e4 LT	23	#include <asm/nmi.h>
	24	#include <asm/msr.h>
	25	#include <asm/apic.h>
b75f53db	26
1da177e4 LT	27	#include "op_counter.h"
1da177e4 LT	28	#include "op_x86_model.h"
2fbe7b25	29
259a83a8	30	static struct op_x86_model_spec *model;
d18d00f5 MT	31	static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
d18d00f5 MT	32	static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
2fbe7b25	33
1da177e4 LT	34	/* 0 == registered but off, 1 == registered and on */
	35	static int nmi_enabled = 0;
	36
4d4036e0 JY	37
	38	#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
	39	extern atomic_t multiplex_counter;
	40	#endif
	41
	42	struct op_counter_config counter_config[OP_MAX_COUNTER];
	43
3370d358 RR	44	/* common functions */
	45
	46	u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
	47	struct op_counter_config *counter_config)
	48	{
	49	u64 val = 0;
	50	u16 event = (u16)counter_config->event;
	51
	52	val \|= ARCH_PERFMON_EVENTSEL_INT;
	53	val \|= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
	54	val \|= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
	55	val \|= (counter_config->unit_mask & 0xFF) << 8;
	56	event &= model->event_mask ? model->event_mask : 0xFF;
	57	val \|= event & 0xFF;
	58	val \|= (event & 0x0F00) << 24;
	59
	60	return val;
	61	}
	62
	63
c7c19f8e AB	64	static int profile_exceptions_notify(struct notifier_block *self,
c7c19f8e AB	65	unsigned long val, void *data)
1da177e4	66	{
2fbe7b25 DZ	67	struct die_args args = (struct die_args )data;
	68	int ret = NOTIFY_DONE;
	69	int cpu = smp_processor_id();
	70
b75f53db	71	switch (val) {
2fbe7b25	72	case DIE_NMI:
5b75af0a MG	73	case DIE_NMI_IPI:
	74	model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu));
	75	ret = NOTIFY_STOP;
2fbe7b25 DZ	76	break;
	77	default:
	78	break;
	79	}
	80	return ret;
1da177e4	81	}
2fbe7b25	82
b75f53db	83	static void nmi_cpu_save_registers(struct op_msrs *msrs)
1da177e4	84	{
b75f53db CM	85	struct op_msr *counters = msrs->counters;
b75f53db CM	86	struct op_msr *controls = msrs->controls;
1da177e4 LT	87	unsigned int i;
1da177e4 LT	88
1a245c45	89	for (i = 0; i < model->num_counters; ++i) {
95e74e62 RR	90	if (counters[i].addr)
95e74e62 RR	91	rdmsrl(counters[i].addr, counters[i].saved);
1da177e4	92	}
b75f53db	93
1a245c45	94	for (i = 0; i < model->num_controls; ++i) {
95e74e62 RR	95	if (controls[i].addr)
95e74e62 RR	96	rdmsrl(controls[i].addr, controls[i].saved);
1da177e4 LT	97	}
	98	}
	99
b28d1b92 RR	100	static void nmi_cpu_start(void *dummy)
	101	{
	102	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
	103	model->start(msrs);
	104	}
	105
	106	static int nmi_start(void)
	107	{
	108	on_each_cpu(nmi_cpu_start, NULL, 1);
	109	return 0;
	110	}
	111
	112	static void nmi_cpu_stop(void *dummy)
	113	{
	114	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
	115	model->stop(msrs);
	116	}
	117
	118	static void nmi_stop(void)
	119	{
	120	on_each_cpu(nmi_cpu_stop, NULL, 1);
	121	}
	122
d8471ad3 RR	123	#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
	124
	125	static DEFINE_PER_CPU(int, switch_index);
	126
	127	inline int op_x86_phys_to_virt(int phys)
	128	{
	129	return __get_cpu_var(switch_index) + phys;
	130	}
	131
6ab82f95 RR	132	static void nmi_shutdown_mux(void)
	133	{
	134	int i;
	135	for_each_possible_cpu(i) {
	136	kfree(per_cpu(cpu_msrs, i).multiplex);
	137	per_cpu(cpu_msrs, i).multiplex = NULL;
	138	per_cpu(switch_index, i) = 0;
	139	}
	140	}
	141
	142	static int nmi_setup_mux(void)
	143	{
	144	size_t multiplex_size =
	145	sizeof(struct op_msr) * model->num_virt_counters;
	146	int i;
	147	for_each_possible_cpu(i) {
	148	per_cpu(cpu_msrs, i).multiplex =
	149	kmalloc(multiplex_size, GFP_KERNEL);
	150	if (!per_cpu(cpu_msrs, i).multiplex)
	151	return 0;
	152	}
	153	return 1;
	154	}
	155
48fb4b46 RR	156	static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
	157	{
	158	int i;
	159	struct op_msr *multiplex = msrs->multiplex;
	160
	161	for (i = 0; i < model->num_virt_counters; ++i) {
	162	if (counter_config[i].enabled) {
	163	multiplex[i].saved = -(u64)counter_config[i].count;
	164	} else {
	165	multiplex[i].addr = 0;
	166	multiplex[i].saved = 0;
	167	}
	168	}
	169
	170	per_cpu(switch_index, cpu) = 0;
	171	}
	172
d0f585dd RR	173	static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
	174	{
	175	struct op_msr *multiplex = msrs->multiplex;
	176	int i;
	177
	178	for (i = 0; i < model->num_counters; ++i) {
	179	int virt = op_x86_phys_to_virt(i);
	180	if (multiplex[virt].addr)
	181	rdmsrl(multiplex[virt].addr, multiplex[virt].saved);
	182	}
	183	}
	184
	185	static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
	186	{
	187	struct op_msr *multiplex = msrs->multiplex;
	188	int i;
	189
	190	for (i = 0; i < model->num_counters; ++i) {
	191	int virt = op_x86_phys_to_virt(i);
	192	if (multiplex[virt].addr)
	193	wrmsrl(multiplex[virt].addr, multiplex[virt].saved);
	194	}
	195	}
	196
b28d1b92 RR	197	static void nmi_cpu_switch(void *dummy)
	198	{
	199	int cpu = smp_processor_id();
	200	int si = per_cpu(switch_index, cpu);
	201	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
	202
	203	nmi_cpu_stop(NULL);
	204	nmi_cpu_save_mpx_registers(msrs);
	205
	206	/* move to next set */
	207	si += model->num_counters;
	208	if ((si > model->num_virt_counters) \|\| (counter_config[si].count == 0))
	209	per_cpu(switch_index, cpu) = 0;
	210	else
	211	per_cpu(switch_index, cpu) = si;
	212
	213	model->switch_ctrl(model, msrs);
	214	nmi_cpu_restore_mpx_registers(msrs);
	215
	216	nmi_cpu_start(NULL);
	217	}
	218
	219
	220	/*
	221	* Quick check to see if multiplexing is necessary.
	222	* The check should be sufficient since counters are used
	223	* in ordre.
	224	*/
	225	static int nmi_multiplex_on(void)
	226	{
	227	return counter_config[model->num_counters].count ? 0 : -EINVAL;
	228	}
	229
	230	static int nmi_switch_event(void)
	231	{
	232	if (!model->switch_ctrl)
	233	return -ENOSYS; /* not implemented */
	234	if (nmi_multiplex_on() < 0)
	235	return -EINVAL; /* not necessary */
	236
	237	on_each_cpu(nmi_cpu_switch, NULL, 1);
	238
	239	atomic_inc(&multiplex_counter);
	240
	241	return 0;
	242	}
	243
d8471ad3 RR	244	#else
	245
	246	inline int op_x86_phys_to_virt(int phys) { return phys; }
6ab82f95 RR	247	static inline void nmi_shutdown_mux(void) { }
6ab82f95 RR	248	static inline int nmi_setup_mux(void) { return 1; }
48fb4b46 RR	249	static inline void
48fb4b46 RR	250	nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { }
d8471ad3 RR	251
	252	#endif
	253
1da177e4 LT	254	static void free_msrs(void)
	255	{
	256	int i;
c8912599	257	for_each_possible_cpu(i) {
d18d00f5 MT	258	kfree(per_cpu(cpu_msrs, i).counters);
	259	per_cpu(cpu_msrs, i).counters = NULL;
	260	kfree(per_cpu(cpu_msrs, i).controls);
	261	per_cpu(cpu_msrs, i).controls = NULL;
1da177e4 LT	262	}
	263	}
	264
1da177e4 LT	265	static int allocate_msrs(void)
1da177e4 LT	266	{
1da177e4 LT	267	size_t controls_size = sizeof(struct op_msr) * model->num_controls;
	268	size_t counters_size = sizeof(struct op_msr) * model->num_counters;
	269
4c168eaf	270	int i;
0939c17c	271	for_each_possible_cpu(i) {
d18d00f5	272	per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
6ab82f95 RR	273	GFP_KERNEL);
	274	if (!per_cpu(cpu_msrs, i).counters)
	275	return 0;
4c168eaf	276	per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
6ab82f95 RR	277	GFP_KERNEL);
	278	if (!per_cpu(cpu_msrs, i).controls)
	279	return 0;
1da177e4 LT	280	}
1da177e4 LT	281
6ab82f95	282	return 1;
1da177e4 LT	283	}
1da177e4 LT	284
b75f53db	285	static void nmi_cpu_setup(void *dummy)
1da177e4 LT	286	{
1da177e4 LT	287	int cpu = smp_processor_id();
d18d00f5	288	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
44ab9a6b	289	nmi_cpu_save_registers(msrs);
1da177e4	290	spin_lock(&oprofilefs_lock);
ef8828dd	291	model->setup_ctrs(model, msrs);
6bfccd09	292	nmi_cpu_setup_mux(cpu, msrs);
1da177e4	293	spin_unlock(&oprofilefs_lock);
d18d00f5	294	per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
1da177e4 LT	295	apic_write(APIC_LVTPC, APIC_DM_NMI);
	296	}
	297
2fbe7b25 DZ	298	static struct notifier_block profile_exceptions_nb = {
	299	.notifier_call = profile_exceptions_notify,
	300	.next = NULL,
5b75af0a	301	.priority = 2
2fbe7b25	302	};
1da177e4 LT	303
	304	static int nmi_setup(void)
	305	{
b75f53db	306	int err = 0;
6c977aad	307	int cpu;
2fbe7b25	308
1da177e4	309	if (!allocate_msrs())
6ab82f95 RR	310	err = -ENOMEM;
	311	else if (!nmi_setup_mux())
	312	err = -ENOMEM;
	313	else
	314	err = register_die_notifier(&profile_exceptions_nb);
1da177e4	315
b75f53db	316	if (err) {
1da177e4	317	free_msrs();
6ab82f95	318	nmi_shutdown_mux();
2fbe7b25	319	return err;
1da177e4	320	}
2fbe7b25	321
4c168eaf	322	/* We need to serialize save and setup for HT because the subset
1da177e4 LT	323	* of msrs are distinct for save and setup operations
1da177e4 LT	324	*/
6c977aad AK	325
6c977aad AK	326	/* Assume saved/restored counters are the same on all CPUs */
d18d00f5	327	model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
b75f53db	328	for_each_possible_cpu(cpu) {
0939c17c	329	if (cpu != 0) {
d18d00f5 MT	330	memcpy(per_cpu(cpu_msrs, cpu).counters,
d18d00f5 MT	331	per_cpu(cpu_msrs, 0).counters,
0939c17c CW	332	sizeof(struct op_msr) * model->num_counters);
0939c17c CW	333
d18d00f5 MT	334	memcpy(per_cpu(cpu_msrs, cpu).controls,
d18d00f5 MT	335	per_cpu(cpu_msrs, 0).controls,
0939c17c	336	sizeof(struct op_msr) * model->num_controls);
4d4036e0 JY	337	#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
	338	memcpy(per_cpu(cpu_msrs, cpu).multiplex,
	339	per_cpu(cpu_msrs, 0).multiplex,
	340	sizeof(struct op_msr) * model->num_virt_counters);
	341	#endif
0939c17c	342	}
6c977aad	343	}
15c8b6c1	344	on_each_cpu(nmi_cpu_setup, NULL, 1);
1da177e4 LT	345	nmi_enabled = 1;
	346	return 0;
	347	}
	348
44ab9a6b	349	static void nmi_cpu_restore_registers(struct op_msrs *msrs)
1da177e4	350	{
b75f53db CM	351	struct op_msr *counters = msrs->counters;
b75f53db CM	352	struct op_msr *controls = msrs->controls;
1da177e4 LT	353	unsigned int i;
1da177e4 LT	354
1a245c45	355	for (i = 0; i < model->num_controls; ++i) {
95e74e62 RR	356	if (controls[i].addr)
95e74e62 RR	357	wrmsrl(controls[i].addr, controls[i].saved);
1da177e4	358	}
b75f53db	359
1a245c45	360	for (i = 0; i < model->num_counters; ++i) {
95e74e62 RR	361	if (counters[i].addr)
95e74e62 RR	362	wrmsrl(counters[i].addr, counters[i].saved);
1da177e4 LT	363	}
1da177e4 LT	364	}
1da177e4	365
b75f53db	366	static void nmi_cpu_shutdown(void *dummy)
1da177e4 LT	367	{
	368	unsigned int v;
	369	int cpu = smp_processor_id();
82a22528	370	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
b75f53db	371
1da177e4 LT	372	/* restoring APIC_LVTPC can trigger an apic error because the delivery
	373	* mode and vector nr combination can be illegal. That's by design: on
	374	* power on apic lvt contain a zero vector nr which are legal only for
	375	* NMI delivery mode. So inhibit apic err before restoring lvtpc
	376	*/
	377	v = apic_read(APIC_LVTERR);
	378	apic_write(APIC_LVTERR, v \| APIC_LVT_MASKED);
d18d00f5	379	apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
1da177e4	380	apic_write(APIC_LVTERR, v);
44ab9a6b	381	nmi_cpu_restore_registers(msrs);
1da177e4 LT	382	}
1da177e4 LT	383
1da177e4 LT	384	static void nmi_shutdown(void)
1da177e4 LT	385	{
b61e06f2 AR	386	struct op_msrs *msrs;
b61e06f2 AR	387
1da177e4	388	nmi_enabled = 0;
15c8b6c1	389	on_each_cpu(nmi_cpu_shutdown, NULL, 1);
2fbe7b25	390	unregister_die_notifier(&profile_exceptions_nb);
6ab82f95	391	nmi_shutdown_mux();
b61e06f2	392	msrs = &get_cpu_var(cpu_msrs);
d18d00f5	393	model->shutdown(msrs);
1da177e4	394	free_msrs();
93e1ade5	395	put_cpu_var(cpu_msrs);
1da177e4 LT	396	}
1da177e4 LT	397
b75f53db	398	static int nmi_create_files(struct super_block sb, struct dentry root)
1da177e4 LT	399	{
	400	unsigned int i;
	401
4d4036e0	402	for (i = 0; i < model->num_virt_counters; ++i) {
b75f53db	403	struct dentry *dir;
0c6856f7	404	char buf[4];
b75f53db	405
4d4036e0	406	#ifndef CONFIG_OPROFILE_EVENT_MULTIPLEX
b75f53db	407	/* quick little hack to _not_ expose a counter if it is not
cb9c448c DZ	408	* available for use. This should protect userspace app.
	409	* NOTE: assumes 1:1 mapping here (that counters are organized
	410	* sequentially in their struct assignment).
	411	*/
	412	if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
	413	continue;
4d4036e0	414	#endif /* CONFIG_OPROFILE_EVENT_MULTIPLEX */
cb9c448c	415
0c6856f7	416	snprintf(buf, sizeof(buf), "%d", i);
1da177e4	417	dir = oprofilefs_mkdir(sb, root, buf);
b75f53db CM	418	oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
	419	oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
	420	oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
	421	oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
	422	oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
	423	oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
1da177e4 LT	424	}
	425
	426	return 0;
	427	}
b75f53db	428
69046d43 RR	429	#ifdef CONFIG_SMP
	430	static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
	431	void *data)
	432	{
	433	int cpu = (unsigned long)data;
	434	switch (action) {
	435	case CPU_DOWN_FAILED:
	436	case CPU_ONLINE:
	437	smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
	438	break;
	439	case CPU_DOWN_PREPARE:
	440	smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
	441	break;
	442	}
	443	return NOTIFY_DONE;
	444	}
	445
	446	static struct notifier_block oprofile_cpu_nb = {
	447	.notifier_call = oprofile_cpu_notifier
	448	};
	449	#endif
	450
	451	#ifdef CONFIG_PM
	452
	453	static int nmi_suspend(struct sys_device *dev, pm_message_t state)
	454	{
	455	/* Only one CPU left, just stop that one */
	456	if (nmi_enabled == 1)
	457	nmi_cpu_stop(NULL);
	458	return 0;
	459	}
	460
	461	static int nmi_resume(struct sys_device *dev)
	462	{
	463	if (nmi_enabled == 1)
	464	nmi_cpu_start(NULL);
	465	return 0;
	466	}
	467
	468	static struct sysdev_class oprofile_sysclass = {
	469	.name = "oprofile",
	470	.resume = nmi_resume,
	471	.suspend = nmi_suspend,
	472	};
	473
	474	static struct sys_device device_oprofile = {
	475	.id = 0,
	476	.cls = &oprofile_sysclass,
	477	};
	478
	479	static int __init init_sysfs(void)
	480	{
	481	int error;
	482
	483	error = sysdev_class_register(&oprofile_sysclass);
	484	if (!error)
	485	error = sysdev_register(&device_oprofile);
	486	return error;
	487	}
	488
	489	static void exit_sysfs(void)
	490	{
	491	sysdev_unregister(&device_oprofile);
	492	sysdev_class_unregister(&oprofile_sysclass);
493	}
494
495	#else
496	#define init_sysfs() do { } while (0)
497	#define exit_sysfs() do { } while (0)
498	#endif /* CONFIG_PM */
499
b75f53db	500	static int __init p4_init(char **cpu_type)
1da177e4 LT	501	{
	502	__u8 cpu_model = boot_cpu_data.x86_model;
	503
1f3d7b60	504	if (cpu_model > 6 \|\| cpu_model == 5)
1da177e4 LT	505	return 0;
	506
	507	#ifndef CONFIG_SMP
	508	*cpu_type = "i386/p4";
	509	model = &op_p4_spec;
	510	return 1;
	511	#else
	512	switch (smp_num_siblings) {
b75f53db CM	513	case 1:
	514	*cpu_type = "i386/p4";
	515	model = &op_p4_spec;
	516	return 1;
	517
	518	case 2:
	519	*cpu_type = "i386/p4-ht";
	520	model = &op_p4_ht2_spec;
	521	return 1;
1da177e4 LT	522	}
	523	#endif
	524
	525	printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
	526	printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
	527	return 0;
	528	}
	529
7e4e0bd5 RR	530	static int force_arch_perfmon;
	531	static int force_cpu_type(const char str, struct kernel_param kp)
	532	{
8d7ff4f2	533	if (!strcmp(str, "arch_perfmon")) {
7e4e0bd5 RR	534	force_arch_perfmon = 1;
	535	printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
	536	}
	537
	538	return 0;
	539	}
	540	module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);
1dcdb5a9	541
b75f53db	542	static int __init ppro_init(char **cpu_type)
1da177e4 LT	543	{
1da177e4 LT	544	__u8 cpu_model = boot_cpu_data.x86_model;
259a83a8	545	struct op_x86_model_spec spec = &op_ppro_spec; / default */
1da177e4	546
1dcdb5a9 AK	547	if (force_arch_perfmon && cpu_has_arch_perfmon)
	548	return 0;
	549
4b9f12a3 LT	550	switch (cpu_model) {
	551	case 0 ... 2:
	552	*cpu_type = "i386/ppro";
	553	break;
	554	case 3 ... 5:
	555	*cpu_type = "i386/pii";
	556	break;
	557	case 6 ... 8:
3d337c65	558	case 10 ... 11:
4b9f12a3 LT	559	*cpu_type = "i386/piii";
	560	break;
	561	case 9:
3d337c65	562	case 13:
4b9f12a3 LT	563	*cpu_type = "i386/p6_mobile";
4b9f12a3 LT	564	break;
4b9f12a3	565	case 14:
64471ebe	566	*cpu_type = "i386/core";
4b9f12a3 LT	567	break;
	568	case 15: case 23:
	569	*cpu_type = "i386/core_2";
	570	break;
6adf406f	571	case 26:
802070f5	572	spec = &op_arch_perfmon_spec;
6adf406f AK	573	*cpu_type = "i386/core_i7";
	574	break;
	575	case 28:
	576	*cpu_type = "i386/atom";
	577	break;
4b9f12a3 LT	578	default:
4b9f12a3 LT	579	/* Unknown */
1da177e4	580	return 0;
1da177e4 LT	581	}
1da177e4 LT	582
802070f5	583	model = spec;
1da177e4 LT	584	return 1;
	585	}
	586
405ae7d3	587	/* in order to get sysfs right */
1da177e4 LT	588	static int using_nmi;
1da177e4 LT	589
96d0821c	590	int __init op_nmi_init(struct oprofile_operations *ops)
1da177e4 LT	591	{
	592	__u8 vendor = boot_cpu_data.x86_vendor;
	593	__u8 family = boot_cpu_data.x86;
b9917028	594	char *cpu_type = NULL;
adf5ec0b	595	int ret = 0;
1da177e4 LT	596
	597	if (!cpu_has_apic)
	598	return -ENODEV;
b75f53db	599
1da177e4	600	switch (vendor) {
b75f53db CM	601	case X86_VENDOR_AMD:
b75f53db CM	602	/* Needs to be at least an Athlon (or hammer in 32bit mode) */
1da177e4	603
b75f53db	604	switch (family) {
b75f53db	605	case 6:
b75f53db CM	606	cpu_type = "i386/athlon";
	607	break;
	608	case 0xf:
d20f24c6 RR	609	/*
	610	* Actually it could be i386/hammer too, but
	611	* give user space an consistent name.
	612	*/
b75f53db CM	613	cpu_type = "x86-64/hammer";
	614	break;
	615	case 0x10:
b75f53db CM	616	cpu_type = "x86-64/family10";
b75f53db CM	617	break;
12f2b261	618	case 0x11:
12f2b261 BK	619	cpu_type = "x86-64/family11h";
12f2b261 BK	620	break;
d20f24c6 RR	621	default:
d20f24c6 RR	622	return -ENODEV;
b75f53db	623	}
d20f24c6	624	model = &op_amd_spec;
b75f53db CM	625	break;
	626
	627	case X86_VENDOR_INTEL:
	628	switch (family) {
	629	/* Pentium IV */
	630	case 0xf:
b9917028	631	p4_init(&cpu_type);
1da177e4	632	break;
b75f53db CM	633
	634	/* A P6-class processor */
	635	case 6:
b9917028	636	ppro_init(&cpu_type);
1da177e4 LT	637	break;
	638
	639	default:
b9917028	640	break;
b75f53db	641	}
b9917028	642
e419294e RR	643	if (cpu_type)
	644	break;
	645
	646	if (!cpu_has_arch_perfmon)
b9917028	647	return -ENODEV;
e419294e RR	648
	649	/* use arch perfmon as fallback */
	650	cpu_type = "i386/arch_perfmon";
	651	model = &op_arch_perfmon_spec;
b75f53db CM	652	break;
	653
	654	default:
	655	return -ENODEV;
1da177e4 LT	656	}
1da177e4 LT	657
80a8c9ff AK	658	#ifdef CONFIG_SMP
	659	register_cpu_notifier(&oprofile_cpu_nb);
	660	#endif
270d3e1a	661	/* default values, can be overwritten by model */
6e63ea4b RR	662	ops->create_files = nmi_create_files;
	663	ops->setup = nmi_setup;
	664	ops->shutdown = nmi_shutdown;
	665	ops->start = nmi_start;
	666	ops->stop = nmi_stop;
	667	ops->cpu_type = cpu_type;
4d4036e0 JY	668	#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
	669	ops->switch_events = nmi_switch_event;
	670	#endif
270d3e1a	671
adf5ec0b RR	672	if (model->init)
	673	ret = model->init(ops);
	674	if (ret)
	675	return ret;
	676
405ae7d3	677	init_sysfs();
1da177e4	678	using_nmi = 1;
1da177e4 LT	679	printk(KERN_INFO "oprofile: using NMI interrupt.\n");
	680	return 0;
	681	}
	682
96d0821c	683	void op_nmi_exit(void)
1da177e4	684	{
80a8c9ff	685	if (using_nmi) {
405ae7d3	686	exit_sysfs();
80a8c9ff AK	687	#ifdef CONFIG_SMP
	688	unregister_cpu_notifier(&oprofile_cpu_nb);
	689	#endif
	690	}
adf5ec0b RR	691	if (model->exit)
adf5ec0b RR	692	model->exit();
1da177e4	693	}