[deliverable/linux.git] / arch / x86 / oprofile / nmi_int.c

/**
 * @file nmi_int.c
 *
 * @remark Copyright 2002-2009 OProfile authors
 * @remark Read the file COPYING
 *
 * @author John Levon <levon@movementarian.org>
 * @author Robert Richter <robert.richter@amd.com>
 * @author Barry Kasindorf <barry.kasindorf@amd.com>
 * @author Jason Yeh <jason.yeh@amd.com>
 * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
 */

#include <linux/init.h>
#include <linux/notifier.h>
#include <linux/smp.h>
#include <linux/oprofile.h>
#include <linux/sysdev.h>
#include <linux/slab.h>
#include <linux/moduleparam.h>
#include <linux/kdebug.h>
#include <linux/cpu.h>
#include <asm/nmi.h>
#include <asm/msr.h>
#include <asm/apic.h>

#include "op_counter.h"
#include "op_x86_model.h"

static struct op_x86_model_spec const *model;
static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
static DEFINE_PER_CPU(unsigned long, saved_lvtpc);

/* 0 == registered but off, 1 == registered and on */
static int nmi_enabled = 0;


#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
extern atomic_t multiplex_counter;
#endif

struct op_counter_config counter_config[OP_MAX_COUNTER];

/* common functions */

u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
		    struct op_counter_config *counter_config)
{
	u64 val = 0;
	u16 event = (u16)counter_config->event;

	val |= ARCH_PERFMON_EVENTSEL_INT;
	val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
	val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
	val |= (counter_config->unit_mask & 0xFF) << 8;
	event &= model->event_mask ? model->event_mask : 0xFF;
	val |= event & 0xFF;
	val |= (event & 0x0F00) << 24;

	return val;
}


static int profile_exceptions_notify(struct notifier_block *self,
				     unsigned long val, void *data)
{
	struct die_args *args = (struct die_args *)data;
	int ret = NOTIFY_DONE;
	int cpu = smp_processor_id();

	switch (val) {
	case DIE_NMI:
	case DIE_NMI_IPI:
		model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu));
		ret = NOTIFY_STOP;
		break;
	default:
		break;
	}
	return ret;
}

static void nmi_cpu_save_registers(struct op_msrs *msrs)
{
	struct op_msr *counters = msrs->counters;
	struct op_msr *controls = msrs->controls;
	unsigned int i;

	for (i = 0; i < model->num_counters; ++i) {
		if (counters[i].addr)
			rdmsrl(counters[i].addr, counters[i].saved);
	}

	for (i = 0; i < model->num_controls; ++i) {
		if (controls[i].addr)
			rdmsrl(controls[i].addr, controls[i].saved);
	}
}

#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX

static DEFINE_PER_CPU(int, switch_index);

inline int op_x86_phys_to_virt(int phys)
{
	return __get_cpu_var(switch_index) + phys;
}

static void nmi_shutdown_mux(void)
{
	int i;
	for_each_possible_cpu(i) {
		kfree(per_cpu(cpu_msrs, i).multiplex);
		per_cpu(cpu_msrs, i).multiplex = NULL;
		per_cpu(switch_index, i) = 0;
	}
}

static int nmi_setup_mux(void)
{
	size_t multiplex_size =
		sizeof(struct op_msr) * model->num_virt_counters;
	int i;
	for_each_possible_cpu(i) {
		per_cpu(cpu_msrs, i).multiplex =
			kmalloc(multiplex_size, GFP_KERNEL);
		if (!per_cpu(cpu_msrs, i).multiplex)
			return 0;
	}
	return 1;
}

static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
{
	int i;
	struct op_msr *multiplex = msrs->multiplex;

	for (i = 0; i < model->num_virt_counters; ++i) {
		if (counter_config[i].enabled) {
			multiplex[i].saved = -(u64)counter_config[i].count;
		} else {
			multiplex[i].addr  = 0;
			multiplex[i].saved = 0;
		}
	}

	per_cpu(switch_index, cpu) = 0;
}

#else

inline int op_x86_phys_to_virt(int phys) { return phys; }
static inline void nmi_shutdown_mux(void) { }
static inline int nmi_setup_mux(void) { return 1; }
static inline void
nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { }

#endif

static void free_msrs(void)
{
	int i;
	for_each_possible_cpu(i) {
		kfree(per_cpu(cpu_msrs, i).counters);
		per_cpu(cpu_msrs, i).counters = NULL;
		kfree(per_cpu(cpu_msrs, i).controls);
		per_cpu(cpu_msrs, i).controls = NULL;
	}
}

static int allocate_msrs(void)
{
	size_t controls_size = sizeof(struct op_msr) * model->num_controls;
	size_t counters_size = sizeof(struct op_msr) * model->num_counters;

	int i;
	for_each_possible_cpu(i) {
		per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
							GFP_KERNEL);
		if (!per_cpu(cpu_msrs, i).counters)
			return 0;
		per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
							GFP_KERNEL);
		if (!per_cpu(cpu_msrs, i).controls)
			return 0;
	}

	return 1;
}

static void nmi_cpu_setup(void *dummy)
{
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
	nmi_cpu_save_registers(msrs);
	spin_lock(&oprofilefs_lock);
	model->setup_ctrs(model, msrs);
	nmi_cpu_setup_mux(cpu, msrs);
	spin_unlock(&oprofilefs_lock);
	per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
	apic_write(APIC_LVTPC, APIC_DM_NMI);
}

static struct notifier_block profile_exceptions_nb = {
	.notifier_call = profile_exceptions_notify,
	.next = NULL,
	.priority = 2
};

static int nmi_setup(void)
{
	int err = 0;
	int cpu;

	if (!allocate_msrs())
		err = -ENOMEM;
	else if (!nmi_setup_mux())
		err = -ENOMEM;
	else
		err = register_die_notifier(&profile_exceptions_nb);

	if (err) {
		free_msrs();
		nmi_shutdown_mux();
		return err;
	}

	/* We need to serialize save and setup for HT because the subset
	 * of msrs are distinct for save and setup operations
	 */

	/* Assume saved/restored counters are the same on all CPUs */
	model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
	for_each_possible_cpu(cpu) {
		if (cpu != 0) {
			memcpy(per_cpu(cpu_msrs, cpu).counters,
				per_cpu(cpu_msrs, 0).counters,
				sizeof(struct op_msr) * model->num_counters);

			memcpy(per_cpu(cpu_msrs, cpu).controls,
				per_cpu(cpu_msrs, 0).controls,
				sizeof(struct op_msr) * model->num_controls);
#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
			memcpy(per_cpu(cpu_msrs, cpu).multiplex,
				per_cpu(cpu_msrs, 0).multiplex,
				sizeof(struct op_msr) * model->num_virt_counters);
#endif
		}
	}
	on_each_cpu(nmi_cpu_setup, NULL, 1);
	nmi_enabled = 1;
	return 0;
}

#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX

static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
{
	struct op_msr *multiplex = msrs->multiplex;
	int i;

	for (i = 0; i < model->num_counters; ++i) {
		int virt = op_x86_phys_to_virt(i);
		if (multiplex[virt].addr)
			rdmsrl(multiplex[virt].addr, multiplex[virt].saved);
	}
}

static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
{
	struct op_msr *multiplex = msrs->multiplex;
	int i;

	for (i = 0; i < model->num_counters; ++i) {
		int virt = op_x86_phys_to_virt(i);
		if (multiplex[virt].addr)
			wrmsrl(multiplex[virt].addr, multiplex[virt].saved);
	}
}

#endif

static void nmi_cpu_restore_registers(struct op_msrs *msrs)
{
	struct op_msr *counters = msrs->counters;
	struct op_msr *controls = msrs->controls;
	unsigned int i;

	for (i = 0; i < model->num_controls; ++i) {
		if (controls[i].addr)
			wrmsrl(controls[i].addr, controls[i].saved);
	}

	for (i = 0; i < model->num_counters; ++i) {
		if (counters[i].addr)
			wrmsrl(counters[i].addr, counters[i].saved);
	}
}

static void nmi_cpu_shutdown(void *dummy)
{
	unsigned int v;
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);

	/* restoring APIC_LVTPC can trigger an apic error because the delivery
	 * mode and vector nr combination can be illegal. That's by design: on
	 * power on apic lvt contain a zero vector nr which are legal only for
	 * NMI delivery mode. So inhibit apic err before restoring lvtpc
	 */
	v = apic_read(APIC_LVTERR);
	apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
	apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
	apic_write(APIC_LVTERR, v);
	nmi_cpu_restore_registers(msrs);
}

static void nmi_shutdown(void)
{
	struct op_msrs *msrs;

	nmi_enabled = 0;
	on_each_cpu(nmi_cpu_shutdown, NULL, 1);
	unregister_die_notifier(&profile_exceptions_nb);
	nmi_shutdown_mux();
	msrs = &get_cpu_var(cpu_msrs);
	model->shutdown(msrs);
	free_msrs();
	put_cpu_var(cpu_msrs);
}

static void nmi_cpu_start(void *dummy)
{
	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
	model->start(msrs);
}

static int nmi_start(void)
{
	on_each_cpu(nmi_cpu_start, NULL, 1);
	return 0;
}

static void nmi_cpu_stop(void *dummy)
{
	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
	model->stop(msrs);
}

static void nmi_stop(void)
{
	on_each_cpu(nmi_cpu_stop, NULL, 1);
}

static int nmi_create_files(struct super_block *sb, struct dentry *root)
{
	unsigned int i;

	for (i = 0; i < model->num_virt_counters; ++i) {
		struct dentry *dir;
		char buf[4];

#ifndef CONFIG_OPROFILE_EVENT_MULTIPLEX
		/* quick little hack to _not_ expose a counter if it is not
		 * available for use.  This should protect userspace app.
		 * NOTE:  assumes 1:1 mapping here (that counters are organized
		 *        sequentially in their struct assignment).
		 */
		if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
			continue;
#endif /* CONFIG_OPROFILE_EVENT_MULTIPLEX */

		snprintf(buf,  sizeof(buf), "%d", i);
		dir = oprofilefs_mkdir(sb, root, buf);
		oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
		oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
		oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
		oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
		oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
		oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
	}

	return 0;
}

#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX

static void nmi_cpu_switch(void *dummy)
{
	int cpu = smp_processor_id();
	int si = per_cpu(switch_index, cpu);
	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);

	nmi_cpu_stop(NULL);
	nmi_cpu_save_mpx_registers(msrs);

	/* move to next set */
	si += model->num_counters;
	if ((si > model->num_virt_counters) || (counter_config[si].count == 0))
		per_cpu(switch_index, cpu) = 0;
	else
		per_cpu(switch_index, cpu) = si;

	model->switch_ctrl(model, msrs);
	nmi_cpu_restore_mpx_registers(msrs);

	nmi_cpu_start(NULL);
}


/*
 * Quick check to see if multiplexing is necessary.
 * The check should be sufficient since counters are used
 * in ordre.
 */
static int nmi_multiplex_on(void)
{
	return counter_config[model->num_counters].count ? 0 : -EINVAL;
}

static int nmi_switch_event(void)
{
	if (!model->switch_ctrl)
		return -ENOSYS;		/* not implemented */
	if (nmi_multiplex_on() < 0)
		return -EINVAL;		/* not necessary */

	on_each_cpu(nmi_cpu_switch, NULL, 1);

	atomic_inc(&multiplex_counter);

	return 0;
}

#endif

#ifdef CONFIG_SMP
static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
				 void *data)
{
	int cpu = (unsigned long)data;
	switch (action) {
	case CPU_DOWN_FAILED:
	case CPU_ONLINE:
		smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
		break;
	case CPU_DOWN_PREPARE:
		smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
		break;
	}
	return NOTIFY_DONE;
}

static struct notifier_block oprofile_cpu_nb = {
	.notifier_call = oprofile_cpu_notifier
};
#endif

#ifdef CONFIG_PM

static int nmi_suspend(struct sys_device *dev, pm_message_t state)
{
	/* Only one CPU left, just stop that one */
	if (nmi_enabled == 1)
		nmi_cpu_stop(NULL);
	return 0;
}

static int nmi_resume(struct sys_device *dev)
{
	if (nmi_enabled == 1)
		nmi_cpu_start(NULL);
	return 0;
}

static struct sysdev_class oprofile_sysclass = {
	.name		= "oprofile",
	.resume		= nmi_resume,
	.suspend	= nmi_suspend,
};

static struct sys_device device_oprofile = {
	.id	= 0,
	.cls	= &oprofile_sysclass,
};

static int __init init_sysfs(void)
{
	int error;

	error = sysdev_class_register(&oprofile_sysclass);
	if (!error)
		error = sysdev_register(&device_oprofile);
	return error;
}

static void exit_sysfs(void)
{
	sysdev_unregister(&device_oprofile);
	sysdev_class_unregister(&oprofile_sysclass);
}

#else
#define init_sysfs() do { } while (0)
#define exit_sysfs() do { } while (0)
#endif /* CONFIG_PM */

static int __init p4_init(char **cpu_type)
{
	__u8 cpu_model = boot_cpu_data.x86_model;

	if (cpu_model > 6 || cpu_model == 5)
		return 0;

#ifndef CONFIG_SMP
	*cpu_type = "i386/p4";
	model = &op_p4_spec;
	return 1;
#else
	switch (smp_num_siblings) {
	case 1:
		*cpu_type = "i386/p4";
		model = &op_p4_spec;
		return 1;

	case 2:
		*cpu_type = "i386/p4-ht";
		model = &op_p4_ht2_spec;
		return 1;
	}
#endif

	printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
	printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
	return 0;
}

static int force_arch_perfmon;
static int force_cpu_type(const char *str, struct kernel_param *kp)
{
	if (!strcmp(str, "arch_perfmon")) {
		force_arch_perfmon = 1;
		printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
	}

	return 0;
}
module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);

static int __init ppro_init(char **cpu_type)
{
	__u8 cpu_model = boot_cpu_data.x86_model;
	struct op_x86_model_spec const *spec = &op_ppro_spec;	/* default */

	if (force_arch_perfmon && cpu_has_arch_perfmon)
		return 0;

	switch (cpu_model) {
	case 0 ... 2:
		*cpu_type = "i386/ppro";
		break;
	case 3 ... 5:
		*cpu_type = "i386/pii";
		break;
	case 6 ... 8:
	case 10 ... 11:
		*cpu_type = "i386/piii";
		break;
	case 9:
	case 13:
		*cpu_type = "i386/p6_mobile";
		break;
	case 14:
		*cpu_type = "i386/core";
		break;
	case 15: case 23:
		*cpu_type = "i386/core_2";
		break;
	case 26:
		spec = &op_arch_perfmon_spec;
		*cpu_type = "i386/core_i7";
		break;
	case 28:
		*cpu_type = "i386/atom";
		break;
	default:
		/* Unknown */
		return 0;
	}

	model = spec;
	return 1;
}

/* in order to get sysfs right */
static int using_nmi;

int __init op_nmi_init(struct oprofile_operations *ops)
{
	__u8 vendor = boot_cpu_data.x86_vendor;
	__u8 family = boot_cpu_data.x86;
	char *cpu_type = NULL;
	int ret = 0;

	if (!cpu_has_apic)
		return -ENODEV;

	switch (vendor) {
	case X86_VENDOR_AMD:
		/* Needs to be at least an Athlon (or hammer in 32bit mode) */

		switch (family) {
		case 6:
			cpu_type = "i386/athlon";
			break;
		case 0xf:
			/*
			 * Actually it could be i386/hammer too, but
			 * give user space an consistent name.
			 */
			cpu_type = "x86-64/hammer";
			break;
		case 0x10:
			cpu_type = "x86-64/family10";
			break;
		case 0x11:
			cpu_type = "x86-64/family11h";
			break;
		default:
			return -ENODEV;
		}
		model = &op_amd_spec;
		break;

	case X86_VENDOR_INTEL:
		switch (family) {
			/* Pentium IV */
		case 0xf:
			p4_init(&cpu_type);
			break;

			/* A P6-class processor */
		case 6:
			ppro_init(&cpu_type);
			break;

		default:
			break;
		}

		if (cpu_type)
			break;

		if (!cpu_has_arch_perfmon)
			return -ENODEV;

		/* use arch perfmon as fallback */
		cpu_type = "i386/arch_perfmon";
		model = &op_arch_perfmon_spec;
		break;

	default:
		return -ENODEV;
	}

#ifdef CONFIG_SMP
	register_cpu_notifier(&oprofile_cpu_nb);
#endif
	/* default values, can be overwritten by model */
	ops->create_files	= nmi_create_files;
	ops->setup		= nmi_setup;
	ops->shutdown		= nmi_shutdown;
	ops->start		= nmi_start;
	ops->stop		= nmi_stop;
	ops->cpu_type		= cpu_type;
#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
	ops->switch_events	= nmi_switch_event;
#endif

	if (model->init)
		ret = model->init(ops);
	if (ret)
		return ret;

	init_sysfs();
	using_nmi = 1;
	printk(KERN_INFO "oprofile: using NMI interrupt.\n");
	return 0;
}

void op_nmi_exit(void)
{
	if (using_nmi) {
		exit_sysfs();
#ifdef CONFIG_SMP
		unregister_cpu_notifier(&oprofile_cpu_nb);
#endif
	}
	if (model->exit)
		model->exit();
}
Commit	Line	Data
1da177e4 LT	1	/**
	2	* @file nmi_int.c
	3	*
4d4036e0	4	* @remark Copyright 2002-2009 OProfile authors
1da177e4 LT	5	* @remark Read the file COPYING
	6	*
	7	* @author John Levon <levon@movementarian.org>
adf5ec0b	8	* @author Robert Richter <robert.richter@amd.com>
4d4036e0 JY	9	* @author Barry Kasindorf <barry.kasindorf@amd.com>
	10	* @author Jason Yeh <jason.yeh@amd.com>
	11	* @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
1da177e4 LT	12	*/
	13
	14	#include <linux/init.h>
	15	#include <linux/notifier.h>
	16	#include <linux/smp.h>
	17	#include <linux/oprofile.h>
	18	#include <linux/sysdev.h>
	19	#include <linux/slab.h>
1cfcea1b	20	#include <linux/moduleparam.h>
1eeb66a1	21	#include <linux/kdebug.h>
80a8c9ff	22	#include <linux/cpu.h>
1da177e4 LT	23	#include <asm/nmi.h>
	24	#include <asm/msr.h>
	25	#include <asm/apic.h>
b75f53db	26
1da177e4 LT	27	#include "op_counter.h"
1da177e4 LT	28	#include "op_x86_model.h"
2fbe7b25	29
b75f53db	30	static struct op_x86_model_spec const *model;
d18d00f5 MT	31	static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
d18d00f5 MT	32	static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
2fbe7b25	33
1da177e4 LT	34	/* 0 == registered but off, 1 == registered and on */
	35	static int nmi_enabled = 0;
	36
4d4036e0 JY	37
	38	#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
	39	extern atomic_t multiplex_counter;
	40	#endif
	41
	42	struct op_counter_config counter_config[OP_MAX_COUNTER];
	43
3370d358 RR	44	/* common functions */
	45
	46	u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
	47	struct op_counter_config *counter_config)
	48	{
	49	u64 val = 0;
	50	u16 event = (u16)counter_config->event;
	51
	52	val \|= ARCH_PERFMON_EVENTSEL_INT;
	53	val \|= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
	54	val \|= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
	55	val \|= (counter_config->unit_mask & 0xFF) << 8;
	56	event &= model->event_mask ? model->event_mask : 0xFF;
	57	val \|= event & 0xFF;
	58	val \|= (event & 0x0F00) << 24;
	59
	60	return val;
	61	}
	62
	63
c7c19f8e AB	64	static int profile_exceptions_notify(struct notifier_block *self,
c7c19f8e AB	65	unsigned long val, void *data)
1da177e4	66	{
2fbe7b25 DZ	67	struct die_args args = (struct die_args )data;
	68	int ret = NOTIFY_DONE;
	69	int cpu = smp_processor_id();
	70
b75f53db	71	switch (val) {
2fbe7b25	72	case DIE_NMI:
5b75af0a MG	73	case DIE_NMI_IPI:
	74	model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu));
	75	ret = NOTIFY_STOP;
2fbe7b25 DZ	76	break;
	77	default:
	78	break;
	79	}
	80	return ret;
1da177e4	81	}
2fbe7b25	82
b75f53db	83	static void nmi_cpu_save_registers(struct op_msrs *msrs)
1da177e4	84	{
b75f53db CM	85	struct op_msr *counters = msrs->counters;
b75f53db CM	86	struct op_msr *controls = msrs->controls;
1da177e4 LT	87	unsigned int i;
1da177e4 LT	88
1a245c45	89	for (i = 0; i < model->num_counters; ++i) {
95e74e62 RR	90	if (counters[i].addr)
95e74e62 RR	91	rdmsrl(counters[i].addr, counters[i].saved);
1da177e4	92	}
b75f53db	93
1a245c45	94	for (i = 0; i < model->num_controls; ++i) {
95e74e62 RR	95	if (controls[i].addr)
95e74e62 RR	96	rdmsrl(controls[i].addr, controls[i].saved);
1da177e4 LT	97	}
	98	}
	99
d8471ad3 RR	100	#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
	101
	102	static DEFINE_PER_CPU(int, switch_index);
	103
	104	inline int op_x86_phys_to_virt(int phys)
	105	{
	106	return __get_cpu_var(switch_index) + phys;
	107	}
	108
6ab82f95 RR	109	static void nmi_shutdown_mux(void)
	110	{
	111	int i;
	112	for_each_possible_cpu(i) {
	113	kfree(per_cpu(cpu_msrs, i).multiplex);
	114	per_cpu(cpu_msrs, i).multiplex = NULL;
	115	per_cpu(switch_index, i) = 0;
	116	}
	117	}
	118
	119	static int nmi_setup_mux(void)
	120	{
	121	size_t multiplex_size =
	122	sizeof(struct op_msr) * model->num_virt_counters;
	123	int i;
	124	for_each_possible_cpu(i) {
	125	per_cpu(cpu_msrs, i).multiplex =
	126	kmalloc(multiplex_size, GFP_KERNEL);
	127	if (!per_cpu(cpu_msrs, i).multiplex)
	128	return 0;
	129	}
	130	return 1;
	131	}
	132
48fb4b46 RR	133	static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
	134	{
	135	int i;
	136	struct op_msr *multiplex = msrs->multiplex;
	137
	138	for (i = 0; i < model->num_virt_counters; ++i) {
	139	if (counter_config[i].enabled) {
	140	multiplex[i].saved = -(u64)counter_config[i].count;
	141	} else {
	142	multiplex[i].addr = 0;
	143	multiplex[i].saved = 0;
	144	}
	145	}
	146
	147	per_cpu(switch_index, cpu) = 0;
	148	}
	149
d8471ad3 RR	150	#else
	151
	152	inline int op_x86_phys_to_virt(int phys) { return phys; }
6ab82f95 RR	153	static inline void nmi_shutdown_mux(void) { }
6ab82f95 RR	154	static inline int nmi_setup_mux(void) { return 1; }
48fb4b46 RR	155	static inline void
48fb4b46 RR	156	nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { }
d8471ad3 RR	157
	158	#endif
	159
1da177e4 LT	160	static void free_msrs(void)
	161	{
	162	int i;
c8912599	163	for_each_possible_cpu(i) {
d18d00f5 MT	164	kfree(per_cpu(cpu_msrs, i).counters);
	165	per_cpu(cpu_msrs, i).counters = NULL;
	166	kfree(per_cpu(cpu_msrs, i).controls);
	167	per_cpu(cpu_msrs, i).controls = NULL;
1da177e4 LT	168	}
	169	}
	170
1da177e4 LT	171	static int allocate_msrs(void)
1da177e4 LT	172	{
1da177e4 LT	173	size_t controls_size = sizeof(struct op_msr) * model->num_controls;
	174	size_t counters_size = sizeof(struct op_msr) * model->num_counters;
	175
4c168eaf	176	int i;
0939c17c	177	for_each_possible_cpu(i) {
d18d00f5	178	per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
6ab82f95 RR	179	GFP_KERNEL);
	180	if (!per_cpu(cpu_msrs, i).counters)
	181	return 0;
4c168eaf	182	per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
6ab82f95 RR	183	GFP_KERNEL);
	184	if (!per_cpu(cpu_msrs, i).controls)
	185	return 0;
1da177e4 LT	186	}
1da177e4 LT	187
6ab82f95	188	return 1;
1da177e4 LT	189	}
1da177e4 LT	190
b75f53db	191	static void nmi_cpu_setup(void *dummy)
1da177e4 LT	192	{
1da177e4 LT	193	int cpu = smp_processor_id();
d18d00f5	194	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
44ab9a6b	195	nmi_cpu_save_registers(msrs);
1da177e4	196	spin_lock(&oprofilefs_lock);
ef8828dd	197	model->setup_ctrs(model, msrs);
6bfccd09	198	nmi_cpu_setup_mux(cpu, msrs);
1da177e4	199	spin_unlock(&oprofilefs_lock);
d18d00f5	200	per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
1da177e4 LT	201	apic_write(APIC_LVTPC, APIC_DM_NMI);
	202	}
	203
2fbe7b25 DZ	204	static struct notifier_block profile_exceptions_nb = {
	205	.notifier_call = profile_exceptions_notify,
	206	.next = NULL,
5b75af0a	207	.priority = 2
2fbe7b25	208	};
1da177e4 LT	209
	210	static int nmi_setup(void)
	211	{
b75f53db	212	int err = 0;
6c977aad	213	int cpu;
2fbe7b25	214
1da177e4	215	if (!allocate_msrs())
6ab82f95 RR	216	err = -ENOMEM;
	217	else if (!nmi_setup_mux())
	218	err = -ENOMEM;
	219	else
	220	err = register_die_notifier(&profile_exceptions_nb);
1da177e4	221
b75f53db	222	if (err) {
1da177e4	223	free_msrs();
6ab82f95	224	nmi_shutdown_mux();
2fbe7b25	225	return err;
1da177e4	226	}
2fbe7b25	227
4c168eaf	228	/* We need to serialize save and setup for HT because the subset
1da177e4 LT	229	* of msrs are distinct for save and setup operations
1da177e4 LT	230	*/
6c977aad AK	231
6c977aad AK	232	/* Assume saved/restored counters are the same on all CPUs */
d18d00f5	233	model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
b75f53db	234	for_each_possible_cpu(cpu) {
0939c17c	235	if (cpu != 0) {
d18d00f5 MT	236	memcpy(per_cpu(cpu_msrs, cpu).counters,
d18d00f5 MT	237	per_cpu(cpu_msrs, 0).counters,
0939c17c CW	238	sizeof(struct op_msr) * model->num_counters);
0939c17c CW	239
d18d00f5 MT	240	memcpy(per_cpu(cpu_msrs, cpu).controls,
d18d00f5 MT	241	per_cpu(cpu_msrs, 0).controls,
0939c17c	242	sizeof(struct op_msr) * model->num_controls);
4d4036e0 JY	243	#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
	244	memcpy(per_cpu(cpu_msrs, cpu).multiplex,
	245	per_cpu(cpu_msrs, 0).multiplex,
	246	sizeof(struct op_msr) * model->num_virt_counters);
	247	#endif
0939c17c	248	}
6c977aad	249	}
15c8b6c1	250	on_each_cpu(nmi_cpu_setup, NULL, 1);
1da177e4 LT	251	nmi_enabled = 1;
	252	return 0;
	253	}
	254
4d4036e0 JY	255	#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
	256
	257	static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
	258	{
4d4036e0	259	struct op_msr *multiplex = msrs->multiplex;
d8471ad3	260	int i;
4d4036e0 JY	261
4d4036e0 JY	262	for (i = 0; i < model->num_counters; ++i) {
d8471ad3 RR	263	int virt = op_x86_phys_to_virt(i);
	264	if (multiplex[virt].addr)
	265	rdmsrl(multiplex[virt].addr, multiplex[virt].saved);
4d4036e0 JY	266	}
	267	}
	268
	269	static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
	270	{
4d4036e0	271	struct op_msr *multiplex = msrs->multiplex;
d8471ad3	272	int i;
4d4036e0 JY	273
4d4036e0 JY	274	for (i = 0; i < model->num_counters; ++i) {
d8471ad3 RR	275	int virt = op_x86_phys_to_virt(i);
	276	if (multiplex[virt].addr)
	277	wrmsrl(multiplex[virt].addr, multiplex[virt].saved);
4d4036e0 JY	278	}
	279	}
	280
	281	#endif
	282
44ab9a6b	283	static void nmi_cpu_restore_registers(struct op_msrs *msrs)
1da177e4	284	{
b75f53db CM	285	struct op_msr *counters = msrs->counters;
b75f53db CM	286	struct op_msr *controls = msrs->controls;
1da177e4 LT	287	unsigned int i;
1da177e4 LT	288
1a245c45	289	for (i = 0; i < model->num_controls; ++i) {
95e74e62 RR	290	if (controls[i].addr)
95e74e62 RR	291	wrmsrl(controls[i].addr, controls[i].saved);
1da177e4	292	}
b75f53db	293
1a245c45	294	for (i = 0; i < model->num_counters; ++i) {
95e74e62 RR	295	if (counters[i].addr)
95e74e62 RR	296	wrmsrl(counters[i].addr, counters[i].saved);
1da177e4 LT	297	}
1da177e4 LT	298	}
1da177e4	299
b75f53db	300	static void nmi_cpu_shutdown(void *dummy)
1da177e4 LT	301	{
	302	unsigned int v;
	303	int cpu = smp_processor_id();
82a22528	304	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
b75f53db	305
1da177e4 LT	306	/* restoring APIC_LVTPC can trigger an apic error because the delivery
	307	* mode and vector nr combination can be illegal. That's by design: on
	308	* power on apic lvt contain a zero vector nr which are legal only for
	309	* NMI delivery mode. So inhibit apic err before restoring lvtpc
	310	*/
	311	v = apic_read(APIC_LVTERR);
	312	apic_write(APIC_LVTERR, v \| APIC_LVT_MASKED);
d18d00f5	313	apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
1da177e4	314	apic_write(APIC_LVTERR, v);
44ab9a6b	315	nmi_cpu_restore_registers(msrs);
1da177e4 LT	316	}
1da177e4 LT	317
1da177e4 LT	318	static void nmi_shutdown(void)
1da177e4 LT	319	{
b61e06f2 AR	320	struct op_msrs *msrs;
b61e06f2 AR	321
1da177e4	322	nmi_enabled = 0;
15c8b6c1	323	on_each_cpu(nmi_cpu_shutdown, NULL, 1);
2fbe7b25	324	unregister_die_notifier(&profile_exceptions_nb);
6ab82f95	325	nmi_shutdown_mux();
b61e06f2	326	msrs = &get_cpu_var(cpu_msrs);
d18d00f5	327	model->shutdown(msrs);
1da177e4	328	free_msrs();
93e1ade5	329	put_cpu_var(cpu_msrs);
1da177e4 LT	330	}
1da177e4 LT	331
b75f53db	332	static void nmi_cpu_start(void *dummy)
1da177e4	333	{
d18d00f5	334	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
1da177e4 LT	335	model->start(msrs);
1da177e4 LT	336	}
1da177e4 LT	337
	338	static int nmi_start(void)
	339	{
15c8b6c1	340	on_each_cpu(nmi_cpu_start, NULL, 1);
1da177e4 LT	341	return 0;
1da177e4 LT	342	}
b75f53db CM	343
b75f53db CM	344	static void nmi_cpu_stop(void *dummy)
1da177e4	345	{
d18d00f5	346	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
1da177e4 LT	347	model->stop(msrs);
1da177e4 LT	348	}
b75f53db	349
1da177e4 LT	350	static void nmi_stop(void)
1da177e4 LT	351	{
15c8b6c1	352	on_each_cpu(nmi_cpu_stop, NULL, 1);
1da177e4 LT	353	}
1da177e4 LT	354
b75f53db	355	static int nmi_create_files(struct super_block sb, struct dentry root)
1da177e4 LT	356	{
	357	unsigned int i;
	358
4d4036e0	359	for (i = 0; i < model->num_virt_counters; ++i) {
b75f53db	360	struct dentry *dir;
0c6856f7	361	char buf[4];
b75f53db	362
4d4036e0	363	#ifndef CONFIG_OPROFILE_EVENT_MULTIPLEX
b75f53db	364	/* quick little hack to _not_ expose a counter if it is not
cb9c448c DZ	365	* available for use. This should protect userspace app.
	366	* NOTE: assumes 1:1 mapping here (that counters are organized
	367	* sequentially in their struct assignment).
	368	*/
	369	if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
	370	continue;
4d4036e0	371	#endif /* CONFIG_OPROFILE_EVENT_MULTIPLEX */
cb9c448c	372
0c6856f7	373	snprintf(buf, sizeof(buf), "%d", i);
1da177e4	374	dir = oprofilefs_mkdir(sb, root, buf);
b75f53db CM	375	oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
	376	oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
	377	oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
	378	oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
	379	oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
	380	oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
1da177e4 LT	381	}
	382
	383	return 0;
	384	}
b75f53db	385
4d4036e0 JY	386	#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
	387
	388	static void nmi_cpu_switch(void *dummy)
	389	{
	390	int cpu = smp_processor_id();
	391	int si = per_cpu(switch_index, cpu);
	392	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
	393
	394	nmi_cpu_stop(NULL);
	395	nmi_cpu_save_mpx_registers(msrs);
	396
	397	/* move to next set */
	398	si += model->num_counters;
	399	if ((si > model->num_virt_counters) \|\| (counter_config[si].count == 0))
	400	per_cpu(switch_index, cpu) = 0;
	401	else
	402	per_cpu(switch_index, cpu) = si;
	403
	404	model->switch_ctrl(model, msrs);
	405	nmi_cpu_restore_mpx_registers(msrs);
	406
	407	nmi_cpu_start(NULL);
	408	}
	409
	410
	411	/*
	412	* Quick check to see if multiplexing is necessary.
	413	* The check should be sufficient since counters are used
	414	* in ordre.
	415	*/
	416	static int nmi_multiplex_on(void)
	417	{
	418	return counter_config[model->num_counters].count ? 0 : -EINVAL;
	419	}
	420
	421	static int nmi_switch_event(void)
	422	{
	423	if (!model->switch_ctrl)
	424	return -ENOSYS; /* not implemented */
	425	if (nmi_multiplex_on() < 0)
	426	return -EINVAL; /* not necessary */
	427
	428	on_each_cpu(nmi_cpu_switch, NULL, 1);
	429
	430	atomic_inc(&multiplex_counter);
	431
	432	return 0;
	433	}
	434
	435	#endif
	436
69046d43 RR	437	#ifdef CONFIG_SMP
	438	static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
	439	void *data)
	440	{
	441	int cpu = (unsigned long)data;
	442	switch (action) {
	443	case CPU_DOWN_FAILED:
	444	case CPU_ONLINE:
	445	smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
	446	break;
	447	case CPU_DOWN_PREPARE:
	448	smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
	449	break;
	450	}
	451	return NOTIFY_DONE;
	452	}
	453
	454	static struct notifier_block oprofile_cpu_nb = {
	455	.notifier_call = oprofile_cpu_notifier
	456	};
	457	#endif
	458
	459	#ifdef CONFIG_PM
	460
	461	static int nmi_suspend(struct sys_device *dev, pm_message_t state)
	462	{
	463	/* Only one CPU left, just stop that one */
	464	if (nmi_enabled == 1)
	465	nmi_cpu_stop(NULL);
	466	return 0;
	467	}
	468
	469	static int nmi_resume(struct sys_device *dev)
	470	{
	471	if (nmi_enabled == 1)
	472	nmi_cpu_start(NULL);
	473	return 0;
	474	}
	475
	476	static struct sysdev_class oprofile_sysclass = {
	477	.name = "oprofile",
	478	.resume = nmi_resume,
	479	.suspend = nmi_suspend,
	480	};
	481
	482	static struct sys_device device_oprofile = {
	483	.id = 0,
	484	.cls = &oprofile_sysclass,
	485	};
	486
	487	static int __init init_sysfs(void)
	488	{
	489	int error;
	490
	491	error = sysdev_class_register(&oprofile_sysclass);
	492	if (!error)
	493	error = sysdev_register(&device_oprofile);
	494	return error;
	495	}
	496
	497	static void exit_sysfs(void)
	498	{
	499	sysdev_unregister(&device_oprofile);
	500	sysdev_class_unregister(&oprofile_sysclass);
501	}
502
503	#else
504	#define init_sysfs() do { } while (0)
505	#define exit_sysfs() do { } while (0)
506	#endif /* CONFIG_PM */
507
b75f53db	508	static int __init p4_init(char **cpu_type)
1da177e4 LT	509	{
	510	__u8 cpu_model = boot_cpu_data.x86_model;
	511
1f3d7b60	512	if (cpu_model > 6 \|\| cpu_model == 5)
1da177e4 LT	513	return 0;
	514
	515	#ifndef CONFIG_SMP
	516	*cpu_type = "i386/p4";
	517	model = &op_p4_spec;
	518	return 1;
	519	#else
	520	switch (smp_num_siblings) {
b75f53db CM	521	case 1:
	522	*cpu_type = "i386/p4";
	523	model = &op_p4_spec;
	524	return 1;
	525
	526	case 2:
	527	*cpu_type = "i386/p4-ht";
	528	model = &op_p4_ht2_spec;
	529	return 1;
1da177e4 LT	530	}
	531	#endif
	532
	533	printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
	534	printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
	535	return 0;
	536	}
	537
7e4e0bd5 RR	538	static int force_arch_perfmon;
	539	static int force_cpu_type(const char str, struct kernel_param kp)
	540	{
8d7ff4f2	541	if (!strcmp(str, "arch_perfmon")) {
7e4e0bd5 RR	542	force_arch_perfmon = 1;
	543	printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
	544	}
	545
	546	return 0;
	547	}
	548	module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);
1dcdb5a9	549
b75f53db	550	static int __init ppro_init(char **cpu_type)
1da177e4 LT	551	{
1da177e4 LT	552	__u8 cpu_model = boot_cpu_data.x86_model;
802070f5	553	struct op_x86_model_spec const spec = &op_ppro_spec; / default */
1da177e4	554
1dcdb5a9 AK	555	if (force_arch_perfmon && cpu_has_arch_perfmon)
	556	return 0;
	557
4b9f12a3 LT	558	switch (cpu_model) {
	559	case 0 ... 2:
	560	*cpu_type = "i386/ppro";
	561	break;
	562	case 3 ... 5:
	563	*cpu_type = "i386/pii";
	564	break;
	565	case 6 ... 8:
3d337c65	566	case 10 ... 11:
4b9f12a3 LT	567	*cpu_type = "i386/piii";
	568	break;
	569	case 9:
3d337c65	570	case 13:
4b9f12a3 LT	571	*cpu_type = "i386/p6_mobile";
4b9f12a3 LT	572	break;
4b9f12a3	573	case 14:
64471ebe	574	*cpu_type = "i386/core";
4b9f12a3 LT	575	break;
	576	case 15: case 23:
	577	*cpu_type = "i386/core_2";
	578	break;
6adf406f	579	case 26:
802070f5	580	spec = &op_arch_perfmon_spec;
6adf406f AK	581	*cpu_type = "i386/core_i7";
	582	break;
	583	case 28:
	584	*cpu_type = "i386/atom";
	585	break;
4b9f12a3 LT	586	default:
4b9f12a3 LT	587	/* Unknown */
1da177e4	588	return 0;
1da177e4 LT	589	}
1da177e4 LT	590
802070f5	591	model = spec;
1da177e4 LT	592	return 1;
	593	}
	594
405ae7d3	595	/* in order to get sysfs right */
1da177e4 LT	596	static int using_nmi;
1da177e4 LT	597
96d0821c	598	int __init op_nmi_init(struct oprofile_operations *ops)
1da177e4 LT	599	{
	600	__u8 vendor = boot_cpu_data.x86_vendor;
	601	__u8 family = boot_cpu_data.x86;
b9917028	602	char *cpu_type = NULL;
adf5ec0b	603	int ret = 0;
1da177e4 LT	604
	605	if (!cpu_has_apic)
	606	return -ENODEV;
b75f53db	607
1da177e4	608	switch (vendor) {
b75f53db CM	609	case X86_VENDOR_AMD:
b75f53db CM	610	/* Needs to be at least an Athlon (or hammer in 32bit mode) */
1da177e4	611
b75f53db	612	switch (family) {
b75f53db	613	case 6:
b75f53db CM	614	cpu_type = "i386/athlon";
	615	break;
	616	case 0xf:
d20f24c6 RR	617	/*
	618	* Actually it could be i386/hammer too, but
	619	* give user space an consistent name.
	620	*/
b75f53db CM	621	cpu_type = "x86-64/hammer";
	622	break;
	623	case 0x10:
b75f53db CM	624	cpu_type = "x86-64/family10";
b75f53db CM	625	break;
12f2b261	626	case 0x11:
12f2b261 BK	627	cpu_type = "x86-64/family11h";
12f2b261 BK	628	break;
d20f24c6 RR	629	default:
d20f24c6 RR	630	return -ENODEV;
b75f53db	631	}
d20f24c6	632	model = &op_amd_spec;
b75f53db CM	633	break;
	634
	635	case X86_VENDOR_INTEL:
	636	switch (family) {
	637	/* Pentium IV */
	638	case 0xf:
b9917028	639	p4_init(&cpu_type);
1da177e4	640	break;
b75f53db CM	641
	642	/* A P6-class processor */
	643	case 6:
b9917028	644	ppro_init(&cpu_type);
1da177e4 LT	645	break;
	646
	647	default:
b9917028	648	break;
b75f53db	649	}
b9917028	650
e419294e RR	651	if (cpu_type)
	652	break;
	653
	654	if (!cpu_has_arch_perfmon)
b9917028	655	return -ENODEV;
e419294e RR	656
	657	/* use arch perfmon as fallback */
	658	cpu_type = "i386/arch_perfmon";
	659	model = &op_arch_perfmon_spec;
b75f53db CM	660	break;
	661
	662	default:
	663	return -ENODEV;
1da177e4 LT	664	}
1da177e4 LT	665
80a8c9ff AK	666	#ifdef CONFIG_SMP
	667	register_cpu_notifier(&oprofile_cpu_nb);
	668	#endif
270d3e1a	669	/* default values, can be overwritten by model */
6e63ea4b RR	670	ops->create_files = nmi_create_files;
	671	ops->setup = nmi_setup;
	672	ops->shutdown = nmi_shutdown;
	673	ops->start = nmi_start;
	674	ops->stop = nmi_stop;
	675	ops->cpu_type = cpu_type;
4d4036e0 JY	676	#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
	677	ops->switch_events = nmi_switch_event;
	678	#endif
270d3e1a	679
adf5ec0b RR	680	if (model->init)
	681	ret = model->init(ops);
	682	if (ret)
	683	return ret;
	684
405ae7d3	685	init_sysfs();
1da177e4	686	using_nmi = 1;
1da177e4 LT	687	printk(KERN_INFO "oprofile: using NMI interrupt.\n");
	688	return 0;
	689	}
	690
96d0821c	691	void op_nmi_exit(void)
1da177e4	692	{
80a8c9ff	693	if (using_nmi) {
405ae7d3	694	exit_sysfs();
80a8c9ff AK	695	#ifdef CONFIG_SMP
	696	unregister_cpu_notifier(&oprofile_cpu_nb);
	697	#endif
	698	}
adf5ec0b RR	699	if (model->exit)
adf5ec0b RR	700	model->exit();
1da177e4	701	}