[deliverable/linux.git] / arch / x86 / oprofile / nmi_int.c

/**
 * @file nmi_int.c
 *
 * @remark Copyright 2002-2009 OProfile authors
 * @remark Read the file COPYING
 *
 * @author John Levon <levon@movementarian.org>
 * @author Robert Richter <robert.richter@amd.com>
 * @author Barry Kasindorf <barry.kasindorf@amd.com>
 * @author Jason Yeh <jason.yeh@amd.com>
 * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
 */

#include <linux/init.h>
#include <linux/notifier.h>
#include <linux/smp.h>
#include <linux/oprofile.h>
#include <linux/sysdev.h>
#include <linux/slab.h>
#include <linux/moduleparam.h>
#include <linux/kdebug.h>
#include <linux/cpu.h>
#include <asm/nmi.h>
#include <asm/msr.h>
#include <asm/apic.h>

#include "op_counter.h"
#include "op_x86_model.h"

static struct op_x86_model_spec *model;
static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
static DEFINE_PER_CPU(unsigned long, saved_lvtpc);

/* 0 == registered but off, 1 == registered and on */
static int nmi_enabled = 0;


#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
extern atomic_t multiplex_counter;
#endif

struct op_counter_config counter_config[OP_MAX_COUNTER];

/* common functions */

u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
		    struct op_counter_config *counter_config)
{
	u64 val = 0;
	u16 event = (u16)counter_config->event;

	val |= ARCH_PERFMON_EVENTSEL_INT;
	val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
	val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
	val |= (counter_config->unit_mask & 0xFF) << 8;
	event &= model->event_mask ? model->event_mask : 0xFF;
	val |= event & 0xFF;
	val |= (event & 0x0F00) << 24;

	return val;
}


static int profile_exceptions_notify(struct notifier_block *self,
				     unsigned long val, void *data)
{
	struct die_args *args = (struct die_args *)data;
	int ret = NOTIFY_DONE;
	int cpu = smp_processor_id();

	switch (val) {
	case DIE_NMI:
	case DIE_NMI_IPI:
		model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu));
		ret = NOTIFY_STOP;
		break;
	default:
		break;
	}
	return ret;
}

static void nmi_cpu_save_registers(struct op_msrs *msrs)
{
	struct op_msr *counters = msrs->counters;
	struct op_msr *controls = msrs->controls;
	unsigned int i;

	for (i = 0; i < model->num_counters; ++i) {
		if (counters[i].addr)
			rdmsrl(counters[i].addr, counters[i].saved);
	}

	for (i = 0; i < model->num_controls; ++i) {
		if (controls[i].addr)
			rdmsrl(controls[i].addr, controls[i].saved);
	}
}

static void nmi_cpu_start(void *dummy)
{
	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
	model->start(msrs);
}

static int nmi_start(void)
{
	on_each_cpu(nmi_cpu_start, NULL, 1);
	return 0;
}

static void nmi_cpu_stop(void *dummy)
{
	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
	model->stop(msrs);
}

static void nmi_stop(void)
{
	on_each_cpu(nmi_cpu_stop, NULL, 1);
}

#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX

static DEFINE_PER_CPU(int, switch_index);

static inline int has_mux(void)
{
	return !!model->switch_ctrl;
}

inline int op_x86_phys_to_virt(int phys)
{
	return __get_cpu_var(switch_index) + phys;
}

static void nmi_shutdown_mux(void)
{
	int i;

	if (!has_mux())
		return;

	for_each_possible_cpu(i) {
		kfree(per_cpu(cpu_msrs, i).multiplex);
		per_cpu(cpu_msrs, i).multiplex = NULL;
		per_cpu(switch_index, i) = 0;
	}
}

static int nmi_setup_mux(void)
{
	size_t multiplex_size =
		sizeof(struct op_msr) * model->num_virt_counters;
	int i;

	if (!has_mux())
		return 1;

	for_each_possible_cpu(i) {
		per_cpu(cpu_msrs, i).multiplex =
			kmalloc(multiplex_size, GFP_KERNEL);
		if (!per_cpu(cpu_msrs, i).multiplex)
			return 0;
	}

	return 1;
}

static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
{
	int i;
	struct op_msr *multiplex = msrs->multiplex;

	if (!has_mux())
		return;

	for (i = 0; i < model->num_virt_counters; ++i) {
		if (counter_config[i].enabled) {
			multiplex[i].saved = -(u64)counter_config[i].count;
		} else {
			multiplex[i].addr  = 0;
			multiplex[i].saved = 0;
		}
	}

	per_cpu(switch_index, cpu) = 0;
}

static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
{
	struct op_msr *multiplex = msrs->multiplex;
	int i;

	for (i = 0; i < model->num_counters; ++i) {
		int virt = op_x86_phys_to_virt(i);
		if (multiplex[virt].addr)
			rdmsrl(multiplex[virt].addr, multiplex[virt].saved);
	}
}

static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
{
	struct op_msr *multiplex = msrs->multiplex;
	int i;

	for (i = 0; i < model->num_counters; ++i) {
		int virt = op_x86_phys_to_virt(i);
		if (multiplex[virt].addr)
			wrmsrl(multiplex[virt].addr, multiplex[virt].saved);
	}
}

static void nmi_cpu_switch(void *dummy)
{
	int cpu = smp_processor_id();
	int si = per_cpu(switch_index, cpu);
	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);

	nmi_cpu_stop(NULL);
	nmi_cpu_save_mpx_registers(msrs);

	/* move to next set */
	si += model->num_counters;
	if ((si > model->num_virt_counters) || (counter_config[si].count == 0))
		per_cpu(switch_index, cpu) = 0;
	else
		per_cpu(switch_index, cpu) = si;

	model->switch_ctrl(model, msrs);
	nmi_cpu_restore_mpx_registers(msrs);

	nmi_cpu_start(NULL);
}


/*
 * Quick check to see if multiplexing is necessary.
 * The check should be sufficient since counters are used
 * in ordre.
 */
static int nmi_multiplex_on(void)
{
	return counter_config[model->num_counters].count ? 0 : -EINVAL;
}

static int nmi_switch_event(void)
{
	if (!has_mux())
		return -ENOSYS;		/* not implemented */
	if (nmi_multiplex_on() < 0)
		return -EINVAL;		/* not necessary */

	on_each_cpu(nmi_cpu_switch, NULL, 1);

	atomic_inc(&multiplex_counter);

	return 0;
}

static inline void mux_init(struct oprofile_operations *ops)
{
	if (has_mux())
		ops->switch_events = nmi_switch_event;
}

static void mux_clone(int cpu)
{
	if (!has_mux())
		return;

	memcpy(per_cpu(cpu_msrs, cpu).multiplex,
	       per_cpu(cpu_msrs, 0).multiplex,
	       sizeof(struct op_msr) * model->num_virt_counters);
}

#else

inline int op_x86_phys_to_virt(int phys) { return phys; }
static inline void nmi_shutdown_mux(void) { }
static inline int nmi_setup_mux(void) { return 1; }
static inline void
nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { }
static inline void mux_init(struct oprofile_operations *ops) { }
static void mux_clone(int cpu) { }

#endif

static void free_msrs(void)
{
	int i;
	for_each_possible_cpu(i) {
		kfree(per_cpu(cpu_msrs, i).counters);
		per_cpu(cpu_msrs, i).counters = NULL;
		kfree(per_cpu(cpu_msrs, i).controls);
		per_cpu(cpu_msrs, i).controls = NULL;
	}
}

static int allocate_msrs(void)
{
	size_t controls_size = sizeof(struct op_msr) * model->num_controls;
	size_t counters_size = sizeof(struct op_msr) * model->num_counters;

	int i;
	for_each_possible_cpu(i) {
		per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
							GFP_KERNEL);
		if (!per_cpu(cpu_msrs, i).counters)
			return 0;
		per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
							GFP_KERNEL);
		if (!per_cpu(cpu_msrs, i).controls)
			return 0;
	}

	return 1;
}

static void nmi_cpu_setup(void *dummy)
{
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
	nmi_cpu_save_registers(msrs);
	spin_lock(&oprofilefs_lock);
	model->setup_ctrs(model, msrs);
	nmi_cpu_setup_mux(cpu, msrs);
	spin_unlock(&oprofilefs_lock);
	per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
	apic_write(APIC_LVTPC, APIC_DM_NMI);
}

static struct notifier_block profile_exceptions_nb = {
	.notifier_call = profile_exceptions_notify,
	.next = NULL,
	.priority = 2
};

static int nmi_setup(void)
{
	int err = 0;
	int cpu;

	if (!allocate_msrs())
		err = -ENOMEM;
	else if (!nmi_setup_mux())
		err = -ENOMEM;
	else
		err = register_die_notifier(&profile_exceptions_nb);

	if (err) {
		free_msrs();
		nmi_shutdown_mux();
		return err;
	}

	/* We need to serialize save and setup for HT because the subset
	 * of msrs are distinct for save and setup operations
	 */

	/* Assume saved/restored counters are the same on all CPUs */
	model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
	for_each_possible_cpu(cpu) {
		if (!cpu)
			continue;

		memcpy(per_cpu(cpu_msrs, cpu).counters,
		       per_cpu(cpu_msrs, 0).counters,
		       sizeof(struct op_msr) * model->num_counters);

		memcpy(per_cpu(cpu_msrs, cpu).controls,
		       per_cpu(cpu_msrs, 0).controls,
		       sizeof(struct op_msr) * model->num_controls);

		mux_clone(cpu);
	}
	on_each_cpu(nmi_cpu_setup, NULL, 1);
	nmi_enabled = 1;
	return 0;
}

static void nmi_cpu_restore_registers(struct op_msrs *msrs)
{
	struct op_msr *counters = msrs->counters;
	struct op_msr *controls = msrs->controls;
	unsigned int i;

	for (i = 0; i < model->num_controls; ++i) {
		if (controls[i].addr)
			wrmsrl(controls[i].addr, controls[i].saved);
	}

	for (i = 0; i < model->num_counters; ++i) {
		if (counters[i].addr)
			wrmsrl(counters[i].addr, counters[i].saved);
	}
}

static void nmi_cpu_shutdown(void *dummy)
{
	unsigned int v;
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);

	/* restoring APIC_LVTPC can trigger an apic error because the delivery
	 * mode and vector nr combination can be illegal. That's by design: on
	 * power on apic lvt contain a zero vector nr which are legal only for
	 * NMI delivery mode. So inhibit apic err before restoring lvtpc
	 */
	v = apic_read(APIC_LVTERR);
	apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
	apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
	apic_write(APIC_LVTERR, v);
	nmi_cpu_restore_registers(msrs);
}

static void nmi_shutdown(void)
{
	struct op_msrs *msrs;

	nmi_enabled = 0;
	on_each_cpu(nmi_cpu_shutdown, NULL, 1);
	unregister_die_notifier(&profile_exceptions_nb);
	nmi_shutdown_mux();
	msrs = &get_cpu_var(cpu_msrs);
	model->shutdown(msrs);
	free_msrs();
	put_cpu_var(cpu_msrs);
}

static int nmi_create_files(struct super_block *sb, struct dentry *root)
{
	unsigned int i;

	for (i = 0; i < model->num_virt_counters; ++i) {
		struct dentry *dir;
		char buf[4];

#ifndef CONFIG_OPROFILE_EVENT_MULTIPLEX
		/* quick little hack to _not_ expose a counter if it is not
		 * available for use.  This should protect userspace app.
		 * NOTE:  assumes 1:1 mapping here (that counters are organized
		 *        sequentially in their struct assignment).
		 */
		if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
			continue;
#endif /* CONFIG_OPROFILE_EVENT_MULTIPLEX */

		snprintf(buf,  sizeof(buf), "%d", i);
		dir = oprofilefs_mkdir(sb, root, buf);
		oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
		oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
		oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
		oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
		oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
		oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
	}

	return 0;
}

#ifdef CONFIG_SMP
static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
				 void *data)
{
	int cpu = (unsigned long)data;
	switch (action) {
	case CPU_DOWN_FAILED:
	case CPU_ONLINE:
		smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
		break;
	case CPU_DOWN_PREPARE:
		smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
		break;
	}
	return NOTIFY_DONE;
}

static struct notifier_block oprofile_cpu_nb = {
	.notifier_call = oprofile_cpu_notifier
};
#endif

#ifdef CONFIG_PM

static int nmi_suspend(struct sys_device *dev, pm_message_t state)
{
	/* Only one CPU left, just stop that one */
	if (nmi_enabled == 1)
		nmi_cpu_stop(NULL);
	return 0;
}

static int nmi_resume(struct sys_device *dev)
{
	if (nmi_enabled == 1)
		nmi_cpu_start(NULL);
	return 0;
}

static struct sysdev_class oprofile_sysclass = {
	.name		= "oprofile",
	.resume		= nmi_resume,
	.suspend	= nmi_suspend,
};

static struct sys_device device_oprofile = {
	.id	= 0,
	.cls	= &oprofile_sysclass,
};

static int __init init_sysfs(void)
{
	int error;

	error = sysdev_class_register(&oprofile_sysclass);
	if (!error)
		error = sysdev_register(&device_oprofile);
	return error;
}

static void exit_sysfs(void)
{
	sysdev_unregister(&device_oprofile);
	sysdev_class_unregister(&oprofile_sysclass);
}

#else
#define init_sysfs() do { } while (0)
#define exit_sysfs() do { } while (0)
#endif /* CONFIG_PM */

static int __init p4_init(char **cpu_type)
{
	__u8 cpu_model = boot_cpu_data.x86_model;

	if (cpu_model > 6 || cpu_model == 5)
		return 0;

#ifndef CONFIG_SMP
	*cpu_type = "i386/p4";
	model = &op_p4_spec;
	return 1;
#else
	switch (smp_num_siblings) {
	case 1:
		*cpu_type = "i386/p4";
		model = &op_p4_spec;
		return 1;

	case 2:
		*cpu_type = "i386/p4-ht";
		model = &op_p4_ht2_spec;
		return 1;
	}
#endif

	printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
	printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
	return 0;
}

static int force_arch_perfmon;
static int force_cpu_type(const char *str, struct kernel_param *kp)
{
	if (!strcmp(str, "arch_perfmon")) {
		force_arch_perfmon = 1;
		printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
	}

	return 0;
}
module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);

static int __init ppro_init(char **cpu_type)
{
	__u8 cpu_model = boot_cpu_data.x86_model;
	struct op_x86_model_spec *spec = &op_ppro_spec;	/* default */

	if (force_arch_perfmon && cpu_has_arch_perfmon)
		return 0;

	switch (cpu_model) {
	case 0 ... 2:
		*cpu_type = "i386/ppro";
		break;
	case 3 ... 5:
		*cpu_type = "i386/pii";
		break;
	case 6 ... 8:
	case 10 ... 11:
		*cpu_type = "i386/piii";
		break;
	case 9:
	case 13:
		*cpu_type = "i386/p6_mobile";
		break;
	case 14:
		*cpu_type = "i386/core";
		break;
	case 15: case 23:
		*cpu_type = "i386/core_2";
		break;
	case 26:
		spec = &op_arch_perfmon_spec;
		*cpu_type = "i386/core_i7";
		break;
	case 28:
		*cpu_type = "i386/atom";
		break;
	default:
		/* Unknown */
		return 0;
	}

	model = spec;
	return 1;
}

/* in order to get sysfs right */
static int using_nmi;

int __init op_nmi_init(struct oprofile_operations *ops)
{
	__u8 vendor = boot_cpu_data.x86_vendor;
	__u8 family = boot_cpu_data.x86;
	char *cpu_type = NULL;
	int ret = 0;

	if (!cpu_has_apic)
		return -ENODEV;

	switch (vendor) {
	case X86_VENDOR_AMD:
		/* Needs to be at least an Athlon (or hammer in 32bit mode) */

		switch (family) {
		case 6:
			cpu_type = "i386/athlon";
			break;
		case 0xf:
			/*
			 * Actually it could be i386/hammer too, but
			 * give user space an consistent name.
			 */
			cpu_type = "x86-64/hammer";
			break;
		case 0x10:
			cpu_type = "x86-64/family10";
			break;
		case 0x11:
			cpu_type = "x86-64/family11h";
			break;
		default:
			return -ENODEV;
		}
		model = &op_amd_spec;
		break;

	case X86_VENDOR_INTEL:
		switch (family) {
			/* Pentium IV */
		case 0xf:
			p4_init(&cpu_type);
			break;

			/* A P6-class processor */
		case 6:
			ppro_init(&cpu_type);
			break;

		default:
			break;
		}

		if (cpu_type)
			break;

		if (!cpu_has_arch_perfmon)
			return -ENODEV;

		/* use arch perfmon as fallback */
		cpu_type = "i386/arch_perfmon";
		model = &op_arch_perfmon_spec;
		break;

	default:
		return -ENODEV;
	}

#ifdef CONFIG_SMP
	register_cpu_notifier(&oprofile_cpu_nb);
#endif
	/* default values, can be overwritten by model */
	ops->create_files	= nmi_create_files;
	ops->setup		= nmi_setup;
	ops->shutdown		= nmi_shutdown;
	ops->start		= nmi_start;
	ops->stop		= nmi_stop;
	ops->cpu_type		= cpu_type;

	if (model->init)
		ret = model->init(ops);
	if (ret)
		return ret;

	if (!model->num_virt_counters)
		model->num_virt_counters = model->num_counters;

	mux_init(ops);

	init_sysfs();
	using_nmi = 1;
	printk(KERN_INFO "oprofile: using NMI interrupt.\n");
	return 0;
}

void op_nmi_exit(void)
{
	if (using_nmi) {
		exit_sysfs();
#ifdef CONFIG_SMP
		unregister_cpu_notifier(&oprofile_cpu_nb);
#endif
	}
	if (model->exit)
		model->exit();
}
Commit	Line	Data
1da177e4 LT	1	/**
	2	* @file nmi_int.c
	3	*
4d4036e0	4	* @remark Copyright 2002-2009 OProfile authors
1da177e4 LT	5	* @remark Read the file COPYING
	6	*
	7	* @author John Levon <levon@movementarian.org>
adf5ec0b	8	* @author Robert Richter <robert.richter@amd.com>
4d4036e0 JY	9	* @author Barry Kasindorf <barry.kasindorf@amd.com>
	10	* @author Jason Yeh <jason.yeh@amd.com>
	11	* @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
1da177e4 LT	12	*/
	13
	14	#include <linux/init.h>
	15	#include <linux/notifier.h>
	16	#include <linux/smp.h>
	17	#include <linux/oprofile.h>
	18	#include <linux/sysdev.h>
	19	#include <linux/slab.h>
1cfcea1b	20	#include <linux/moduleparam.h>
1eeb66a1	21	#include <linux/kdebug.h>
80a8c9ff	22	#include <linux/cpu.h>
1da177e4 LT	23	#include <asm/nmi.h>
	24	#include <asm/msr.h>
	25	#include <asm/apic.h>
b75f53db	26
1da177e4 LT	27	#include "op_counter.h"
1da177e4 LT	28	#include "op_x86_model.h"
2fbe7b25	29
259a83a8	30	static struct op_x86_model_spec *model;
d18d00f5 MT	31	static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
d18d00f5 MT	32	static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
2fbe7b25	33
1da177e4 LT	34	/* 0 == registered but off, 1 == registered and on */
	35	static int nmi_enabled = 0;
	36
4d4036e0 JY	37
	38	#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
	39	extern atomic_t multiplex_counter;
	40	#endif
	41
	42	struct op_counter_config counter_config[OP_MAX_COUNTER];
	43
3370d358 RR	44	/* common functions */
	45
	46	u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
	47	struct op_counter_config *counter_config)
	48	{
	49	u64 val = 0;
	50	u16 event = (u16)counter_config->event;
	51
	52	val \|= ARCH_PERFMON_EVENTSEL_INT;
	53	val \|= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
	54	val \|= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
	55	val \|= (counter_config->unit_mask & 0xFF) << 8;
	56	event &= model->event_mask ? model->event_mask : 0xFF;
	57	val \|= event & 0xFF;
	58	val \|= (event & 0x0F00) << 24;
	59
	60	return val;
	61	}
	62
	63
c7c19f8e AB	64	static int profile_exceptions_notify(struct notifier_block *self,
c7c19f8e AB	65	unsigned long val, void *data)
1da177e4	66	{
2fbe7b25 DZ	67	struct die_args args = (struct die_args )data;
	68	int ret = NOTIFY_DONE;
	69	int cpu = smp_processor_id();
	70
b75f53db	71	switch (val) {
2fbe7b25	72	case DIE_NMI:
5b75af0a MG	73	case DIE_NMI_IPI:
	74	model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu));
	75	ret = NOTIFY_STOP;
2fbe7b25 DZ	76	break;
	77	default:
	78	break;
	79	}
	80	return ret;
1da177e4	81	}
2fbe7b25	82
b75f53db	83	static void nmi_cpu_save_registers(struct op_msrs *msrs)
1da177e4	84	{
b75f53db CM	85	struct op_msr *counters = msrs->counters;
b75f53db CM	86	struct op_msr *controls = msrs->controls;
1da177e4 LT	87	unsigned int i;
1da177e4 LT	88
1a245c45	89	for (i = 0; i < model->num_counters; ++i) {
95e74e62 RR	90	if (counters[i].addr)
95e74e62 RR	91	rdmsrl(counters[i].addr, counters[i].saved);
1da177e4	92	}
b75f53db	93
1a245c45	94	for (i = 0; i < model->num_controls; ++i) {
95e74e62 RR	95	if (controls[i].addr)
95e74e62 RR	96	rdmsrl(controls[i].addr, controls[i].saved);
1da177e4 LT	97	}
	98	}
	99
b28d1b92 RR	100	static void nmi_cpu_start(void *dummy)
	101	{
	102	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
	103	model->start(msrs);
	104	}
	105
	106	static int nmi_start(void)
	107	{
	108	on_each_cpu(nmi_cpu_start, NULL, 1);
	109	return 0;
	110	}
	111
	112	static void nmi_cpu_stop(void *dummy)
	113	{
	114	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
	115	model->stop(msrs);
	116	}
	117
	118	static void nmi_stop(void)
	119	{
	120	on_each_cpu(nmi_cpu_stop, NULL, 1);
	121	}
	122
d8471ad3 RR	123	#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
	124
	125	static DEFINE_PER_CPU(int, switch_index);
	126
39e97f40 RR	127	static inline int has_mux(void)
	128	{
	129	return !!model->switch_ctrl;
	130	}
	131
d8471ad3 RR	132	inline int op_x86_phys_to_virt(int phys)
	133	{
	134	return __get_cpu_var(switch_index) + phys;
	135	}
	136
6ab82f95 RR	137	static void nmi_shutdown_mux(void)
	138	{
	139	int i;
39e97f40 RR	140
	141	if (!has_mux())
	142	return;
	143
6ab82f95 RR	144	for_each_possible_cpu(i) {
	145	kfree(per_cpu(cpu_msrs, i).multiplex);
	146	per_cpu(cpu_msrs, i).multiplex = NULL;
	147	per_cpu(switch_index, i) = 0;
	148	}
	149	}
	150
	151	static int nmi_setup_mux(void)
	152	{
	153	size_t multiplex_size =
	154	sizeof(struct op_msr) * model->num_virt_counters;
	155	int i;
39e97f40 RR	156
	157	if (!has_mux())
	158	return 1;
	159
6ab82f95 RR	160	for_each_possible_cpu(i) {
	161	per_cpu(cpu_msrs, i).multiplex =
	162	kmalloc(multiplex_size, GFP_KERNEL);
	163	if (!per_cpu(cpu_msrs, i).multiplex)
	164	return 0;
	165	}
39e97f40	166
6ab82f95 RR	167	return 1;
	168	}
	169
48fb4b46 RR	170	static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
	171	{
	172	int i;
	173	struct op_msr *multiplex = msrs->multiplex;
	174
39e97f40 RR	175	if (!has_mux())
	176	return;
	177
48fb4b46 RR	178	for (i = 0; i < model->num_virt_counters; ++i) {
	179	if (counter_config[i].enabled) {
	180	multiplex[i].saved = -(u64)counter_config[i].count;
	181	} else {
	182	multiplex[i].addr = 0;
	183	multiplex[i].saved = 0;
	184	}
	185	}
	186
	187	per_cpu(switch_index, cpu) = 0;
	188	}
	189
d0f585dd RR	190	static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
	191	{
	192	struct op_msr *multiplex = msrs->multiplex;
	193	int i;
	194
	195	for (i = 0; i < model->num_counters; ++i) {
	196	int virt = op_x86_phys_to_virt(i);
	197	if (multiplex[virt].addr)
	198	rdmsrl(multiplex[virt].addr, multiplex[virt].saved);
	199	}
	200	}
	201
	202	static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
	203	{
	204	struct op_msr *multiplex = msrs->multiplex;
	205	int i;
	206
	207	for (i = 0; i < model->num_counters; ++i) {
	208	int virt = op_x86_phys_to_virt(i);
	209	if (multiplex[virt].addr)
	210	wrmsrl(multiplex[virt].addr, multiplex[virt].saved);
	211	}
	212	}
	213
b28d1b92 RR	214	static void nmi_cpu_switch(void *dummy)
	215	{
	216	int cpu = smp_processor_id();
	217	int si = per_cpu(switch_index, cpu);
	218	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
	219
	220	nmi_cpu_stop(NULL);
	221	nmi_cpu_save_mpx_registers(msrs);
	222
	223	/* move to next set */
	224	si += model->num_counters;
	225	if ((si > model->num_virt_counters) \|\| (counter_config[si].count == 0))
	226	per_cpu(switch_index, cpu) = 0;
	227	else
	228	per_cpu(switch_index, cpu) = si;
	229
	230	model->switch_ctrl(model, msrs);
	231	nmi_cpu_restore_mpx_registers(msrs);
	232
	233	nmi_cpu_start(NULL);
	234	}
	235
	236
	237	/*
	238	* Quick check to see if multiplexing is necessary.
	239	* The check should be sufficient since counters are used
	240	* in ordre.
	241	*/
	242	static int nmi_multiplex_on(void)
	243	{
	244	return counter_config[model->num_counters].count ? 0 : -EINVAL;
	245	}
	246
	247	static int nmi_switch_event(void)
	248	{
39e97f40	249	if (!has_mux())
b28d1b92 RR	250	return -ENOSYS; /* not implemented */
	251	if (nmi_multiplex_on() < 0)
	252	return -EINVAL; /* not necessary */
	253
	254	on_each_cpu(nmi_cpu_switch, NULL, 1);
	255
	256	atomic_inc(&multiplex_counter);
	257
	258	return 0;
	259	}
	260
52805144 RR	261	static inline void mux_init(struct oprofile_operations *ops)
	262	{
	263	if (has_mux())
	264	ops->switch_events = nmi_switch_event;
	265	}
	266
4d015f79 RR	267	static void mux_clone(int cpu)
	268	{
	269	if (!has_mux())
	270	return;
	271
	272	memcpy(per_cpu(cpu_msrs, cpu).multiplex,
	273	per_cpu(cpu_msrs, 0).multiplex,
	274	sizeof(struct op_msr) * model->num_virt_counters);
	275	}
	276
d8471ad3 RR	277	#else
	278
	279	inline int op_x86_phys_to_virt(int phys) { return phys; }
6ab82f95 RR	280	static inline void nmi_shutdown_mux(void) { }
6ab82f95 RR	281	static inline int nmi_setup_mux(void) { return 1; }
48fb4b46 RR	282	static inline void
48fb4b46 RR	283	nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { }
52805144	284	static inline void mux_init(struct oprofile_operations *ops) { }
4d015f79	285	static void mux_clone(int cpu) { }
d8471ad3 RR	286
	287	#endif
	288
1da177e4 LT	289	static void free_msrs(void)
	290	{
	291	int i;
c8912599	292	for_each_possible_cpu(i) {
d18d00f5 MT	293	kfree(per_cpu(cpu_msrs, i).counters);
	294	per_cpu(cpu_msrs, i).counters = NULL;
	295	kfree(per_cpu(cpu_msrs, i).controls);
	296	per_cpu(cpu_msrs, i).controls = NULL;
1da177e4 LT	297	}
	298	}
	299
1da177e4 LT	300	static int allocate_msrs(void)
1da177e4 LT	301	{
1da177e4 LT	302	size_t controls_size = sizeof(struct op_msr) * model->num_controls;
	303	size_t counters_size = sizeof(struct op_msr) * model->num_counters;
	304
4c168eaf	305	int i;
0939c17c	306	for_each_possible_cpu(i) {
d18d00f5	307	per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
6ab82f95 RR	308	GFP_KERNEL);
	309	if (!per_cpu(cpu_msrs, i).counters)
	310	return 0;
4c168eaf	311	per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
6ab82f95 RR	312	GFP_KERNEL);
	313	if (!per_cpu(cpu_msrs, i).controls)
	314	return 0;
1da177e4 LT	315	}
1da177e4 LT	316
6ab82f95	317	return 1;
1da177e4 LT	318	}
1da177e4 LT	319
b75f53db	320	static void nmi_cpu_setup(void *dummy)
1da177e4 LT	321	{
1da177e4 LT	322	int cpu = smp_processor_id();
d18d00f5	323	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
44ab9a6b	324	nmi_cpu_save_registers(msrs);
1da177e4	325	spin_lock(&oprofilefs_lock);
ef8828dd	326	model->setup_ctrs(model, msrs);
6bfccd09	327	nmi_cpu_setup_mux(cpu, msrs);
1da177e4	328	spin_unlock(&oprofilefs_lock);
d18d00f5	329	per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
1da177e4 LT	330	apic_write(APIC_LVTPC, APIC_DM_NMI);
	331	}
	332
2fbe7b25 DZ	333	static struct notifier_block profile_exceptions_nb = {
	334	.notifier_call = profile_exceptions_notify,
	335	.next = NULL,
5b75af0a	336	.priority = 2
2fbe7b25	337	};
1da177e4 LT	338
	339	static int nmi_setup(void)
	340	{
b75f53db	341	int err = 0;
6c977aad	342	int cpu;
2fbe7b25	343
1da177e4	344	if (!allocate_msrs())
6ab82f95 RR	345	err = -ENOMEM;
	346	else if (!nmi_setup_mux())
	347	err = -ENOMEM;
	348	else
	349	err = register_die_notifier(&profile_exceptions_nb);
1da177e4	350
b75f53db	351	if (err) {
1da177e4	352	free_msrs();
6ab82f95	353	nmi_shutdown_mux();
2fbe7b25	354	return err;
1da177e4	355	}
2fbe7b25	356
4c168eaf	357	/* We need to serialize save and setup for HT because the subset
1da177e4 LT	358	* of msrs are distinct for save and setup operations
1da177e4 LT	359	*/
6c977aad AK	360
6c977aad AK	361	/* Assume saved/restored counters are the same on all CPUs */
d18d00f5	362	model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
b75f53db	363	for_each_possible_cpu(cpu) {
4d015f79 RR	364	if (!cpu)
	365	continue;
	366
	367	memcpy(per_cpu(cpu_msrs, cpu).counters,
	368	per_cpu(cpu_msrs, 0).counters,
	369	sizeof(struct op_msr) * model->num_counters);
	370
	371	memcpy(per_cpu(cpu_msrs, cpu).controls,
	372	per_cpu(cpu_msrs, 0).controls,
	373	sizeof(struct op_msr) * model->num_controls);
	374
	375	mux_clone(cpu);
6c977aad	376	}
15c8b6c1	377	on_each_cpu(nmi_cpu_setup, NULL, 1);
1da177e4 LT	378	nmi_enabled = 1;
	379	return 0;
	380	}
	381
44ab9a6b	382	static void nmi_cpu_restore_registers(struct op_msrs *msrs)
1da177e4	383	{
b75f53db CM	384	struct op_msr *counters = msrs->counters;
b75f53db CM	385	struct op_msr *controls = msrs->controls;
1da177e4 LT	386	unsigned int i;
1da177e4 LT	387
1a245c45	388	for (i = 0; i < model->num_controls; ++i) {
95e74e62 RR	389	if (controls[i].addr)
95e74e62 RR	390	wrmsrl(controls[i].addr, controls[i].saved);
1da177e4	391	}
b75f53db	392
1a245c45	393	for (i = 0; i < model->num_counters; ++i) {
95e74e62 RR	394	if (counters[i].addr)
95e74e62 RR	395	wrmsrl(counters[i].addr, counters[i].saved);
1da177e4 LT	396	}
1da177e4 LT	397	}
1da177e4	398
b75f53db	399	static void nmi_cpu_shutdown(void *dummy)
1da177e4 LT	400	{
	401	unsigned int v;
	402	int cpu = smp_processor_id();
82a22528	403	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
b75f53db	404
1da177e4 LT	405	/* restoring APIC_LVTPC can trigger an apic error because the delivery
	406	* mode and vector nr combination can be illegal. That's by design: on
	407	* power on apic lvt contain a zero vector nr which are legal only for
	408	* NMI delivery mode. So inhibit apic err before restoring lvtpc
	409	*/
	410	v = apic_read(APIC_LVTERR);
	411	apic_write(APIC_LVTERR, v \| APIC_LVT_MASKED);
d18d00f5	412	apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
1da177e4	413	apic_write(APIC_LVTERR, v);
44ab9a6b	414	nmi_cpu_restore_registers(msrs);
1da177e4 LT	415	}
1da177e4 LT	416
1da177e4 LT	417	static void nmi_shutdown(void)
1da177e4 LT	418	{
b61e06f2 AR	419	struct op_msrs *msrs;
b61e06f2 AR	420
1da177e4	421	nmi_enabled = 0;
15c8b6c1	422	on_each_cpu(nmi_cpu_shutdown, NULL, 1);
2fbe7b25	423	unregister_die_notifier(&profile_exceptions_nb);
6ab82f95	424	nmi_shutdown_mux();
b61e06f2	425	msrs = &get_cpu_var(cpu_msrs);
d18d00f5	426	model->shutdown(msrs);
1da177e4	427	free_msrs();
93e1ade5	428	put_cpu_var(cpu_msrs);
1da177e4 LT	429	}
1da177e4 LT	430
b75f53db	431	static int nmi_create_files(struct super_block sb, struct dentry root)
1da177e4 LT	432	{
	433	unsigned int i;
	434
4d4036e0	435	for (i = 0; i < model->num_virt_counters; ++i) {
b75f53db	436	struct dentry *dir;
0c6856f7	437	char buf[4];
b75f53db	438
4d4036e0	439	#ifndef CONFIG_OPROFILE_EVENT_MULTIPLEX
b75f53db	440	/* quick little hack to _not_ expose a counter if it is not
cb9c448c DZ	441	* available for use. This should protect userspace app.
	442	* NOTE: assumes 1:1 mapping here (that counters are organized
	443	* sequentially in their struct assignment).
	444	*/
	445	if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
	446	continue;
4d4036e0	447	#endif /* CONFIG_OPROFILE_EVENT_MULTIPLEX */
cb9c448c	448
0c6856f7	449	snprintf(buf, sizeof(buf), "%d", i);
1da177e4	450	dir = oprofilefs_mkdir(sb, root, buf);
b75f53db CM	451	oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
	452	oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
	453	oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
	454	oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
	455	oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
	456	oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
1da177e4 LT	457	}
	458
	459	return 0;
	460	}
b75f53db	461
69046d43 RR	462	#ifdef CONFIG_SMP
	463	static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
	464	void *data)
	465	{
	466	int cpu = (unsigned long)data;
	467	switch (action) {
	468	case CPU_DOWN_FAILED:
	469	case CPU_ONLINE:
	470	smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
	471	break;
	472	case CPU_DOWN_PREPARE:
	473	smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
	474	break;
	475	}
	476	return NOTIFY_DONE;
	477	}
	478
	479	static struct notifier_block oprofile_cpu_nb = {
	480	.notifier_call = oprofile_cpu_notifier
	481	};
	482	#endif
	483
	484	#ifdef CONFIG_PM
	485
	486	static int nmi_suspend(struct sys_device *dev, pm_message_t state)
	487	{
	488	/* Only one CPU left, just stop that one */
	489	if (nmi_enabled == 1)
	490	nmi_cpu_stop(NULL);
	491	return 0;
	492	}
	493
	494	static int nmi_resume(struct sys_device *dev)
	495	{
	496	if (nmi_enabled == 1)
	497	nmi_cpu_start(NULL);
	498	return 0;
	499	}
	500
	501	static struct sysdev_class oprofile_sysclass = {
	502	.name = "oprofile",
	503	.resume = nmi_resume,
	504	.suspend = nmi_suspend,
	505	};
	506
	507	static struct sys_device device_oprofile = {
	508	.id = 0,
	509	.cls = &oprofile_sysclass,
	510	};
	511
	512	static int __init init_sysfs(void)
	513	{
	514	int error;
	515
	516	error = sysdev_class_register(&oprofile_sysclass);
	517	if (!error)
	518	error = sysdev_register(&device_oprofile);
	519	return error;
	520	}
	521
	522	static void exit_sysfs(void)
	523	{
	524	sysdev_unregister(&device_oprofile);
	525	sysdev_class_unregister(&oprofile_sysclass);
526	}
527
528	#else
529	#define init_sysfs() do { } while (0)
530	#define exit_sysfs() do { } while (0)
531	#endif /* CONFIG_PM */
532
b75f53db	533	static int __init p4_init(char **cpu_type)
1da177e4 LT	534	{
	535	__u8 cpu_model = boot_cpu_data.x86_model;
	536
1f3d7b60	537	if (cpu_model > 6 \|\| cpu_model == 5)
1da177e4 LT	538	return 0;
	539
	540	#ifndef CONFIG_SMP
	541	*cpu_type = "i386/p4";
	542	model = &op_p4_spec;
	543	return 1;
	544	#else
	545	switch (smp_num_siblings) {
b75f53db CM	546	case 1:
	547	*cpu_type = "i386/p4";
	548	model = &op_p4_spec;
	549	return 1;
	550
	551	case 2:
	552	*cpu_type = "i386/p4-ht";
	553	model = &op_p4_ht2_spec;
	554	return 1;
1da177e4 LT	555	}
	556	#endif
	557
	558	printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
	559	printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
	560	return 0;
	561	}
	562
7e4e0bd5 RR	563	static int force_arch_perfmon;
	564	static int force_cpu_type(const char str, struct kernel_param kp)
	565	{
8d7ff4f2	566	if (!strcmp(str, "arch_perfmon")) {
7e4e0bd5 RR	567	force_arch_perfmon = 1;
	568	printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
	569	}
	570
	571	return 0;
	572	}
	573	module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);
1dcdb5a9	574
b75f53db	575	static int __init ppro_init(char **cpu_type)
1da177e4 LT	576	{
1da177e4 LT	577	__u8 cpu_model = boot_cpu_data.x86_model;
259a83a8	578	struct op_x86_model_spec spec = &op_ppro_spec; / default */
1da177e4	579
1dcdb5a9 AK	580	if (force_arch_perfmon && cpu_has_arch_perfmon)
	581	return 0;
	582
4b9f12a3 LT	583	switch (cpu_model) {
	584	case 0 ... 2:
	585	*cpu_type = "i386/ppro";
	586	break;
	587	case 3 ... 5:
	588	*cpu_type = "i386/pii";
	589	break;
	590	case 6 ... 8:
3d337c65	591	case 10 ... 11:
4b9f12a3 LT	592	*cpu_type = "i386/piii";
	593	break;
	594	case 9:
3d337c65	595	case 13:
4b9f12a3 LT	596	*cpu_type = "i386/p6_mobile";
4b9f12a3 LT	597	break;
4b9f12a3	598	case 14:
64471ebe	599	*cpu_type = "i386/core";
4b9f12a3 LT	600	break;
	601	case 15: case 23:
	602	*cpu_type = "i386/core_2";
	603	break;
6adf406f	604	case 26:
802070f5	605	spec = &op_arch_perfmon_spec;
6adf406f AK	606	*cpu_type = "i386/core_i7";
	607	break;
	608	case 28:
	609	*cpu_type = "i386/atom";
	610	break;
4b9f12a3 LT	611	default:
4b9f12a3 LT	612	/* Unknown */
1da177e4	613	return 0;
1da177e4 LT	614	}
1da177e4 LT	615
802070f5	616	model = spec;
1da177e4 LT	617	return 1;
	618	}
	619
405ae7d3	620	/* in order to get sysfs right */
1da177e4 LT	621	static int using_nmi;
1da177e4 LT	622
96d0821c	623	int __init op_nmi_init(struct oprofile_operations *ops)
1da177e4 LT	624	{
	625	__u8 vendor = boot_cpu_data.x86_vendor;
	626	__u8 family = boot_cpu_data.x86;
b9917028	627	char *cpu_type = NULL;
adf5ec0b	628	int ret = 0;
1da177e4 LT	629
	630	if (!cpu_has_apic)
	631	return -ENODEV;
b75f53db	632
1da177e4	633	switch (vendor) {
b75f53db CM	634	case X86_VENDOR_AMD:
b75f53db CM	635	/* Needs to be at least an Athlon (or hammer in 32bit mode) */
1da177e4	636
b75f53db	637	switch (family) {
b75f53db	638	case 6:
b75f53db CM	639	cpu_type = "i386/athlon";
	640	break;
	641	case 0xf:
d20f24c6 RR	642	/*
	643	* Actually it could be i386/hammer too, but
	644	* give user space an consistent name.
	645	*/
b75f53db CM	646	cpu_type = "x86-64/hammer";
	647	break;
	648	case 0x10:
b75f53db CM	649	cpu_type = "x86-64/family10";
b75f53db CM	650	break;
12f2b261	651	case 0x11:
12f2b261 BK	652	cpu_type = "x86-64/family11h";
12f2b261 BK	653	break;
d20f24c6 RR	654	default:
d20f24c6 RR	655	return -ENODEV;
b75f53db	656	}
d20f24c6	657	model = &op_amd_spec;
b75f53db CM	658	break;
	659
	660	case X86_VENDOR_INTEL:
	661	switch (family) {
	662	/* Pentium IV */
	663	case 0xf:
b9917028	664	p4_init(&cpu_type);
1da177e4	665	break;
b75f53db CM	666
	667	/* A P6-class processor */
	668	case 6:
b9917028	669	ppro_init(&cpu_type);
1da177e4 LT	670	break;
	671
	672	default:
b9917028	673	break;
b75f53db	674	}
b9917028	675
e419294e RR	676	if (cpu_type)
	677	break;
	678
	679	if (!cpu_has_arch_perfmon)
b9917028	680	return -ENODEV;
e419294e RR	681
	682	/* use arch perfmon as fallback */
	683	cpu_type = "i386/arch_perfmon";
	684	model = &op_arch_perfmon_spec;
b75f53db CM	685	break;
	686
	687	default:
	688	return -ENODEV;
1da177e4 LT	689	}
1da177e4 LT	690
80a8c9ff AK	691	#ifdef CONFIG_SMP
	692	register_cpu_notifier(&oprofile_cpu_nb);
	693	#endif
270d3e1a	694	/* default values, can be overwritten by model */
6e63ea4b RR	695	ops->create_files = nmi_create_files;
	696	ops->setup = nmi_setup;
	697	ops->shutdown = nmi_shutdown;
	698	ops->start = nmi_start;
	699	ops->stop = nmi_stop;
	700	ops->cpu_type = cpu_type;
270d3e1a	701
adf5ec0b RR	702	if (model->init)
	703	ret = model->init(ops);
	704	if (ret)
	705	return ret;
	706
52471c67 RR	707	if (!model->num_virt_counters)
	708	model->num_virt_counters = model->num_counters;
	709
52805144 RR	710	mux_init(ops);
52805144 RR	711
405ae7d3	712	init_sysfs();
1da177e4	713	using_nmi = 1;
1da177e4 LT	714	printk(KERN_INFO "oprofile: using NMI interrupt.\n");
	715	return 0;
	716	}
	717
96d0821c	718	void op_nmi_exit(void)
1da177e4	719	{
80a8c9ff	720	if (using_nmi) {
405ae7d3	721	exit_sysfs();
80a8c9ff AK	722	#ifdef CONFIG_SMP
	723	unregister_cpu_notifier(&oprofile_cpu_nb);
	724	#endif
	725	}
adf5ec0b RR	726	if (model->exit)
adf5ec0b RR	727	model->exit();
1da177e4	728	}