[deliverable/linux.git] / arch / x86 / oprofile / nmi_int.c

/**
 * @file nmi_int.c
 *
 * @remark Copyright 2002 OProfile authors
 * @remark Read the file COPYING
 *
 * @author John Levon <levon@movementarian.org>
 */

#include <linux/init.h>
#include <linux/notifier.h>
#include <linux/smp.h>
#include <linux/oprofile.h>
#include <linux/sysdev.h>
#include <linux/slab.h>
#include <linux/moduleparam.h>
#include <linux/kdebug.h>
#include <asm/nmi.h>
#include <asm/msr.h>
#include <asm/apic.h>

#include "op_counter.h"
#include "op_x86_model.h"

static struct op_x86_model_spec const *model;
static struct op_msrs cpu_msrs[NR_CPUS];
static unsigned long saved_lvtpc[NR_CPUS];

static int nmi_start(void);
static void nmi_stop(void);

/* 0 == registered but off, 1 == registered and on */
static int nmi_enabled = 0;

#ifdef CONFIG_PM

static int nmi_suspend(struct sys_device *dev, pm_message_t state)
{
	if (nmi_enabled == 1)
		nmi_stop();
	return 0;
}

static int nmi_resume(struct sys_device *dev)
{
	if (nmi_enabled == 1)
		nmi_start();
	return 0;
}

static struct sysdev_class oprofile_sysclass = {
	.name		= "oprofile",
	.resume		= nmi_resume,
	.suspend	= nmi_suspend,
};

static struct sys_device device_oprofile = {
	.id	= 0,
	.cls	= &oprofile_sysclass,
};

static int __init init_sysfs(void)
{
	int error;

	error = sysdev_class_register(&oprofile_sysclass);
	if (!error)
		error = sysdev_register(&device_oprofile);
	return error;
}

static void exit_sysfs(void)
{
	sysdev_unregister(&device_oprofile);
	sysdev_class_unregister(&oprofile_sysclass);
}

#else
#define init_sysfs() do { } while (0)
#define exit_sysfs() do { } while (0)
#endif /* CONFIG_PM */

static int profile_exceptions_notify(struct notifier_block *self,
				     unsigned long val, void *data)
{
	struct die_args *args = (struct die_args *)data;
	int ret = NOTIFY_DONE;
	int cpu = smp_processor_id();

	switch (val) {
	case DIE_NMI:
		if (model->check_ctrs(args->regs, &cpu_msrs[cpu]))
			ret = NOTIFY_STOP;
		break;
	default:
		break;
	}
	return ret;
}

static void nmi_cpu_save_registers(struct op_msrs *msrs)
{
	unsigned int const nr_ctrs = model->num_counters;
	unsigned int const nr_ctrls = model->num_controls;
	struct op_msr *counters = msrs->counters;
	struct op_msr *controls = msrs->controls;
	unsigned int i;

	for (i = 0; i < nr_ctrs; ++i) {
		if (counters[i].addr) {
			rdmsr(counters[i].addr,
				counters[i].saved.low,
				counters[i].saved.high);
		}
	}

	for (i = 0; i < nr_ctrls; ++i) {
		if (controls[i].addr) {
			rdmsr(controls[i].addr,
				controls[i].saved.low,
				controls[i].saved.high);
		}
	}
}

static void nmi_save_registers(void *dummy)
{
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &cpu_msrs[cpu];
	nmi_cpu_save_registers(msrs);
}

static void free_msrs(void)
{
	int i;
	for_each_possible_cpu(i) {
		kfree(cpu_msrs[i].counters);
		cpu_msrs[i].counters = NULL;
		kfree(cpu_msrs[i].controls);
		cpu_msrs[i].controls = NULL;
	}
}

static int allocate_msrs(void)
{
	int success = 1;
	size_t controls_size = sizeof(struct op_msr) * model->num_controls;
	size_t counters_size = sizeof(struct op_msr) * model->num_counters;

	int i;
	for_each_possible_cpu(i) {
		cpu_msrs[i].counters = kmalloc(counters_size, GFP_KERNEL);
		if (!cpu_msrs[i].counters) {
			success = 0;
			break;
		}
		cpu_msrs[i].controls = kmalloc(controls_size, GFP_KERNEL);
		if (!cpu_msrs[i].controls) {
			success = 0;
			break;
		}
	}

	if (!success)
		free_msrs();

	return success;
}

static void nmi_cpu_setup(void *dummy)
{
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &cpu_msrs[cpu];
	spin_lock(&oprofilefs_lock);
	model->setup_ctrs(msrs);
	spin_unlock(&oprofilefs_lock);
	saved_lvtpc[cpu] = apic_read(APIC_LVTPC);
	apic_write(APIC_LVTPC, APIC_DM_NMI);
}

static struct notifier_block profile_exceptions_nb = {
	.notifier_call = profile_exceptions_notify,
	.next = NULL,
	.priority = 0
};

static int nmi_setup(void)
{
	int err = 0;
	int cpu;

	if (!allocate_msrs())
		return -ENOMEM;

	err = register_die_notifier(&profile_exceptions_nb);
	if (err) {
		free_msrs();
		return err;
	}

	/* We need to serialize save and setup for HT because the subset
	 * of msrs are distinct for save and setup operations
	 */

	/* Assume saved/restored counters are the same on all CPUs */
	model->fill_in_addresses(&cpu_msrs[0]);
	for_each_possible_cpu(cpu) {
		if (cpu != 0) {
			memcpy(cpu_msrs[cpu].counters, cpu_msrs[0].counters,
				sizeof(struct op_msr) * model->num_counters);

			memcpy(cpu_msrs[cpu].controls, cpu_msrs[0].controls,
				sizeof(struct op_msr) * model->num_controls);
		}

	}
	on_each_cpu(nmi_save_registers, NULL, 0, 1);
	on_each_cpu(nmi_cpu_setup, NULL, 0, 1);
	nmi_enabled = 1;
	return 0;
}

static void nmi_restore_registers(struct op_msrs *msrs)
{
	unsigned int const nr_ctrs = model->num_counters;
	unsigned int const nr_ctrls = model->num_controls;
	struct op_msr *counters = msrs->counters;
	struct op_msr *controls = msrs->controls;
	unsigned int i;

	for (i = 0; i < nr_ctrls; ++i) {
		if (controls[i].addr) {
			wrmsr(controls[i].addr,
				controls[i].saved.low,
				controls[i].saved.high);
		}
	}

	for (i = 0; i < nr_ctrs; ++i) {
		if (counters[i].addr) {
			wrmsr(counters[i].addr,
				counters[i].saved.low,
				counters[i].saved.high);
		}
	}
}

static void nmi_cpu_shutdown(void *dummy)
{
	unsigned int v;
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &cpu_msrs[cpu];

	/* restoring APIC_LVTPC can trigger an apic error because the delivery
	 * mode and vector nr combination can be illegal. That's by design: on
	 * power on apic lvt contain a zero vector nr which are legal only for
	 * NMI delivery mode. So inhibit apic err before restoring lvtpc
	 */
	v = apic_read(APIC_LVTERR);
	apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
	apic_write(APIC_LVTPC, saved_lvtpc[cpu]);
	apic_write(APIC_LVTERR, v);
	nmi_restore_registers(msrs);
}

static void nmi_shutdown(void)
{
	nmi_enabled = 0;
	on_each_cpu(nmi_cpu_shutdown, NULL, 0, 1);
	unregister_die_notifier(&profile_exceptions_nb);
	model->shutdown(cpu_msrs);
	free_msrs();
}

static void nmi_cpu_start(void *dummy)
{
	struct op_msrs const *msrs = &cpu_msrs[smp_processor_id()];
	model->start(msrs);
}

static int nmi_start(void)
{
	on_each_cpu(nmi_cpu_start, NULL, 0, 1);
	return 0;
}

static void nmi_cpu_stop(void *dummy)
{
	struct op_msrs const *msrs = &cpu_msrs[smp_processor_id()];
	model->stop(msrs);
}

static void nmi_stop(void)
{
	on_each_cpu(nmi_cpu_stop, NULL, 0, 1);
}

struct op_counter_config counter_config[OP_MAX_COUNTER];

static int nmi_create_files(struct super_block *sb, struct dentry *root)
{
	unsigned int i;

	for (i = 0; i < model->num_counters; ++i) {
		struct dentry *dir;
		char buf[4];

		/* quick little hack to _not_ expose a counter if it is not
		 * available for use.  This should protect userspace app.
		 * NOTE:  assumes 1:1 mapping here (that counters are organized
		 *        sequentially in their struct assignment).
		 */
		if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
			continue;

		snprintf(buf,  sizeof(buf), "%d", i);
		dir = oprofilefs_mkdir(sb, root, buf);
		oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
		oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
		oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
		oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
		oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
		oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
	}

	return 0;
}

static int p4force;
module_param(p4force, int, 0);

static int __init p4_init(char **cpu_type)
{
	__u8 cpu_model = boot_cpu_data.x86_model;

	if (!p4force && (cpu_model > 6 || cpu_model == 5))
		return 0;

#ifndef CONFIG_SMP
	*cpu_type = "i386/p4";
	model = &op_p4_spec;
	return 1;
#else
	switch (smp_num_siblings) {
	case 1:
		*cpu_type = "i386/p4";
		model = &op_p4_spec;
		return 1;

	case 2:
		*cpu_type = "i386/p4-ht";
		model = &op_p4_ht2_spec;
		return 1;
	}
#endif

	printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
	printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
	return 0;
}

static int __init ppro_init(char **cpu_type)
{
	__u8 cpu_model = boot_cpu_data.x86_model;

	if (cpu_model == 14)
		*cpu_type = "i386/core";
	else if (cpu_model == 15 || cpu_model == 23)
		*cpu_type = "i386/core_2";
	else if (cpu_model > 0xd)
		return 0;
	else if (cpu_model == 9) {
		*cpu_type = "i386/p6_mobile";
	} else if (cpu_model > 5) {
		*cpu_type = "i386/piii";
	} else if (cpu_model > 2) {
		*cpu_type = "i386/pii";
	} else {
		*cpu_type = "i386/ppro";
	}

	model = &op_ppro_spec;
	return 1;
}

/* in order to get sysfs right */
static int using_nmi;

int __init op_nmi_init(struct oprofile_operations *ops)
{
	__u8 vendor = boot_cpu_data.x86_vendor;
	__u8 family = boot_cpu_data.x86;
	char *cpu_type;

	if (!cpu_has_apic)
		return -ENODEV;

	switch (vendor) {
	case X86_VENDOR_AMD:
		/* Needs to be at least an Athlon (or hammer in 32bit mode) */

		switch (family) {
		default:
			return -ENODEV;
		case 6:
			model = &op_athlon_spec;
			cpu_type = "i386/athlon";
			break;
		case 0xf:
			model = &op_athlon_spec;
			/* Actually it could be i386/hammer too, but give
			 user space an consistent name. */
			cpu_type = "x86-64/hammer";
			break;
		case 0x10:
			model = &op_athlon_spec;
			cpu_type = "x86-64/family10";
			break;
		}
		break;

	case X86_VENDOR_INTEL:
		switch (family) {
			/* Pentium IV */
		case 0xf:
			if (!p4_init(&cpu_type))
				return -ENODEV;
			break;

			/* A P6-class processor */
		case 6:
			if (!ppro_init(&cpu_type))
				return -ENODEV;
			break;

		default:
			return -ENODEV;
		}
		break;

	default:
		return -ENODEV;
	}

	init_sysfs();
	using_nmi = 1;
	ops->create_files = nmi_create_files;
	ops->setup = nmi_setup;
	ops->shutdown = nmi_shutdown;
	ops->start = nmi_start;
	ops->stop = nmi_stop;
	ops->cpu_type = cpu_type;
	printk(KERN_INFO "oprofile: using NMI interrupt.\n");
	return 0;
}

void op_nmi_exit(void)
{
	if (using_nmi)
		exit_sysfs();
}
Commit	Line	Data
1da177e4 LT	1	/**
	2	* @file nmi_int.c
	3	*
	4	* @remark Copyright 2002 OProfile authors
	5	* @remark Read the file COPYING
	6	*
	7	* @author John Levon <levon@movementarian.org>
	8	*/
	9
	10	#include <linux/init.h>
	11	#include <linux/notifier.h>
	12	#include <linux/smp.h>
	13	#include <linux/oprofile.h>
	14	#include <linux/sysdev.h>
	15	#include <linux/slab.h>
1cfcea1b	16	#include <linux/moduleparam.h>
1eeb66a1	17	#include <linux/kdebug.h>
1da177e4 LT	18	#include <asm/nmi.h>
	19	#include <asm/msr.h>
	20	#include <asm/apic.h>
b75f53db	21
1da177e4 LT	22	#include "op_counter.h"
1da177e4 LT	23	#include "op_x86_model.h"
2fbe7b25	24
b75f53db	25	static struct op_x86_model_spec const *model;
1da177e4 LT	26	static struct op_msrs cpu_msrs[NR_CPUS];
1da177e4 LT	27	static unsigned long saved_lvtpc[NR_CPUS];
2fbe7b25	28
1da177e4 LT	29	static int nmi_start(void);
	30	static void nmi_stop(void);
	31
	32	/* 0 == registered but off, 1 == registered and on */
	33	static int nmi_enabled = 0;
	34
	35	#ifdef CONFIG_PM
	36
438510f6	37	static int nmi_suspend(struct sys_device *dev, pm_message_t state)
1da177e4 LT	38	{
	39	if (nmi_enabled == 1)
	40	nmi_stop();
	41	return 0;
	42	}
	43
1da177e4 LT	44	static int nmi_resume(struct sys_device *dev)
	45	{
	46	if (nmi_enabled == 1)
	47	nmi_start();
	48	return 0;
	49	}
	50
1da177e4	51	static struct sysdev_class oprofile_sysclass = {
af5ca3f4	52	.name = "oprofile",
1da177e4 LT	53	.resume = nmi_resume,
	54	.suspend = nmi_suspend,
	55	};
	56
1da177e4 LT	57	static struct sys_device device_oprofile = {
	58	.id = 0,
	59	.cls = &oprofile_sysclass,
	60	};
	61
405ae7d3	62	static int __init init_sysfs(void)
1da177e4 LT	63	{
1da177e4 LT	64	int error;
b75f53db CM	65
	66	error = sysdev_class_register(&oprofile_sysclass);
	67	if (!error)
1da177e4 LT	68	error = sysdev_register(&device_oprofile);
	69	return error;
	70	}
	71
405ae7d3	72	static void exit_sysfs(void)
1da177e4 LT	73	{
	74	sysdev_unregister(&device_oprofile);
	75	sysdev_class_unregister(&oprofile_sysclass);
	76	}
	77
	78	#else
405ae7d3 RD	79	#define init_sysfs() do { } while (0)
405ae7d3 RD	80	#define exit_sysfs() do { } while (0)
1da177e4 LT	81	#endif /* CONFIG_PM */
1da177e4 LT	82
c7c19f8e AB	83	static int profile_exceptions_notify(struct notifier_block *self,
c7c19f8e AB	84	unsigned long val, void *data)
1da177e4	85	{
2fbe7b25 DZ	86	struct die_args args = (struct die_args )data;
	87	int ret = NOTIFY_DONE;
	88	int cpu = smp_processor_id();
	89
b75f53db	90	switch (val) {
2fbe7b25 DZ	91	case DIE_NMI:
	92	if (model->check_ctrs(args->regs, &cpu_msrs[cpu]))
	93	ret = NOTIFY_STOP;
	94	break;
	95	default:
	96	break;
	97	}
	98	return ret;
1da177e4	99	}
2fbe7b25	100
b75f53db	101	static void nmi_cpu_save_registers(struct op_msrs *msrs)
1da177e4 LT	102	{
1da177e4 LT	103	unsigned int const nr_ctrs = model->num_counters;
b75f53db CM	104	unsigned int const nr_ctrls = model->num_controls;
	105	struct op_msr *counters = msrs->counters;
	106	struct op_msr *controls = msrs->controls;
1da177e4 LT	107	unsigned int i;
	108
	109	for (i = 0; i < nr_ctrs; ++i) {
b75f53db	110	if (counters[i].addr) {
cb9c448c DZ	111	rdmsr(counters[i].addr,
	112	counters[i].saved.low,
	113	counters[i].saved.high);
	114	}
1da177e4	115	}
b75f53db	116
1da177e4	117	for (i = 0; i < nr_ctrls; ++i) {
b75f53db	118	if (controls[i].addr) {
cb9c448c DZ	119	rdmsr(controls[i].addr,
	120	controls[i].saved.low,
	121	controls[i].saved.high);
	122	}
1da177e4 LT	123	}
	124	}
	125
b75f53db	126	static void nmi_save_registers(void *dummy)
1da177e4 LT	127	{
1da177e4 LT	128	int cpu = smp_processor_id();
b75f53db	129	struct op_msrs *msrs = &cpu_msrs[cpu];
1da177e4 LT	130	nmi_cpu_save_registers(msrs);
	131	}
	132
1da177e4 LT	133	static void free_msrs(void)
	134	{
	135	int i;
c8912599	136	for_each_possible_cpu(i) {
1da177e4 LT	137	kfree(cpu_msrs[i].counters);
	138	cpu_msrs[i].counters = NULL;
	139	kfree(cpu_msrs[i].controls);
	140	cpu_msrs[i].controls = NULL;
	141	}
	142	}
	143
1da177e4 LT	144	static int allocate_msrs(void)
	145	{
	146	int success = 1;
	147	size_t controls_size = sizeof(struct op_msr) * model->num_controls;
	148	size_t counters_size = sizeof(struct op_msr) * model->num_counters;
	149
	150	int i;
0939c17c	151	for_each_possible_cpu(i) {
1da177e4 LT	152	cpu_msrs[i].counters = kmalloc(counters_size, GFP_KERNEL);
	153	if (!cpu_msrs[i].counters) {
	154	success = 0;
	155	break;
	156	}
	157	cpu_msrs[i].controls = kmalloc(controls_size, GFP_KERNEL);
	158	if (!cpu_msrs[i].controls) {
	159	success = 0;
	160	break;
	161	}
	162	}
	163
	164	if (!success)
	165	free_msrs();
	166
	167	return success;
	168	}
	169
b75f53db	170	static void nmi_cpu_setup(void *dummy)
1da177e4 LT	171	{
1da177e4 LT	172	int cpu = smp_processor_id();
b75f53db	173	struct op_msrs *msrs = &cpu_msrs[cpu];
1da177e4 LT	174	spin_lock(&oprofilefs_lock);
	175	model->setup_ctrs(msrs);
	176	spin_unlock(&oprofilefs_lock);
	177	saved_lvtpc[cpu] = apic_read(APIC_LVTPC);
	178	apic_write(APIC_LVTPC, APIC_DM_NMI);
	179	}
	180
2fbe7b25 DZ	181	static struct notifier_block profile_exceptions_nb = {
	182	.notifier_call = profile_exceptions_notify,
	183	.next = NULL,
	184	.priority = 0
	185	};
1da177e4 LT	186
	187	static int nmi_setup(void)
	188	{
b75f53db	189	int err = 0;
6c977aad	190	int cpu;
2fbe7b25	191
1da177e4 LT	192	if (!allocate_msrs())
	193	return -ENOMEM;
	194
b75f53db CM	195	err = register_die_notifier(&profile_exceptions_nb);
b75f53db CM	196	if (err) {
1da177e4	197	free_msrs();
2fbe7b25	198	return err;
1da177e4	199	}
2fbe7b25	200
1da177e4 LT	201	/* We need to serialize save and setup for HT because the subset
	202	* of msrs are distinct for save and setup operations
	203	*/
6c977aad AK	204
	205	/* Assume saved/restored counters are the same on all CPUs */
	206	model->fill_in_addresses(&cpu_msrs[0]);
b75f53db	207	for_each_possible_cpu(cpu) {
0939c17c CW	208	if (cpu != 0) {
	209	memcpy(cpu_msrs[cpu].counters, cpu_msrs[0].counters,
	210	sizeof(struct op_msr) * model->num_counters);
	211
	212	memcpy(cpu_msrs[cpu].controls, cpu_msrs[0].controls,
	213	sizeof(struct op_msr) * model->num_controls);
	214	}
	215
6c977aad	216	}
1da177e4 LT	217	on_each_cpu(nmi_save_registers, NULL, 0, 1);
1da177e4 LT	218	on_each_cpu(nmi_cpu_setup, NULL, 0, 1);
1da177e4 LT	219	nmi_enabled = 1;
	220	return 0;
	221	}
	222
b75f53db	223	static void nmi_restore_registers(struct op_msrs *msrs)
1da177e4 LT	224	{
1da177e4 LT	225	unsigned int const nr_ctrs = model->num_counters;
b75f53db CM	226	unsigned int const nr_ctrls = model->num_controls;
	227	struct op_msr *counters = msrs->counters;
	228	struct op_msr *controls = msrs->controls;
1da177e4 LT	229	unsigned int i;
	230
	231	for (i = 0; i < nr_ctrls; ++i) {
b75f53db	232	if (controls[i].addr) {
cb9c448c DZ	233	wrmsr(controls[i].addr,
	234	controls[i].saved.low,
	235	controls[i].saved.high);
	236	}
1da177e4	237	}
b75f53db	238
1da177e4	239	for (i = 0; i < nr_ctrs; ++i) {
b75f53db	240	if (counters[i].addr) {
cb9c448c DZ	241	wrmsr(counters[i].addr,
	242	counters[i].saved.low,
	243	counters[i].saved.high);
	244	}
1da177e4 LT	245	}
1da177e4 LT	246	}
1da177e4	247
b75f53db	248	static void nmi_cpu_shutdown(void *dummy)
1da177e4 LT	249	{
	250	unsigned int v;
	251	int cpu = smp_processor_id();
b75f53db CM	252	struct op_msrs *msrs = &cpu_msrs[cpu];
b75f53db CM	253
1da177e4 LT	254	/* restoring APIC_LVTPC can trigger an apic error because the delivery
	255	* mode and vector nr combination can be illegal. That's by design: on
	256	* power on apic lvt contain a zero vector nr which are legal only for
	257	* NMI delivery mode. So inhibit apic err before restoring lvtpc
	258	*/
	259	v = apic_read(APIC_LVTERR);
	260	apic_write(APIC_LVTERR, v \| APIC_LVT_MASKED);
	261	apic_write(APIC_LVTPC, saved_lvtpc[cpu]);
	262	apic_write(APIC_LVTERR, v);
	263	nmi_restore_registers(msrs);
	264	}
	265
1da177e4 LT	266	static void nmi_shutdown(void)
	267	{
	268	nmi_enabled = 0;
	269	on_each_cpu(nmi_cpu_shutdown, NULL, 0, 1);
2fbe7b25	270	unregister_die_notifier(&profile_exceptions_nb);
0f8e45a2	271	model->shutdown(cpu_msrs);
1da177e4 LT	272	free_msrs();
	273	}
	274
b75f53db	275	static void nmi_cpu_start(void *dummy)
1da177e4	276	{
b75f53db	277	struct op_msrs const *msrs = &cpu_msrs[smp_processor_id()];
1da177e4 LT	278	model->start(msrs);
1da177e4 LT	279	}
1da177e4 LT	280
	281	static int nmi_start(void)
	282	{
	283	on_each_cpu(nmi_cpu_start, NULL, 0, 1);
	284	return 0;
	285	}
b75f53db CM	286
b75f53db CM	287	static void nmi_cpu_stop(void *dummy)
1da177e4	288	{
b75f53db	289	struct op_msrs const *msrs = &cpu_msrs[smp_processor_id()];
1da177e4 LT	290	model->stop(msrs);
1da177e4 LT	291	}
b75f53db	292
1da177e4 LT	293	static void nmi_stop(void)
	294	{
	295	on_each_cpu(nmi_cpu_stop, NULL, 0, 1);
	296	}
	297
1da177e4 LT	298	struct op_counter_config counter_config[OP_MAX_COUNTER];
1da177e4 LT	299
b75f53db	300	static int nmi_create_files(struct super_block sb, struct dentry root)
1da177e4 LT	301	{
	302	unsigned int i;
	303
	304	for (i = 0; i < model->num_counters; ++i) {
b75f53db	305	struct dentry *dir;
0c6856f7	306	char buf[4];
b75f53db CM	307
b75f53db CM	308	/* quick little hack to _not_ expose a counter if it is not
cb9c448c DZ	309	* available for use. This should protect userspace app.
	310	* NOTE: assumes 1:1 mapping here (that counters are organized
	311	* sequentially in their struct assignment).
	312	*/
	313	if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
	314	continue;
	315
0c6856f7	316	snprintf(buf, sizeof(buf), "%d", i);
1da177e4	317	dir = oprofilefs_mkdir(sb, root, buf);
b75f53db CM	318	oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
	319	oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
	320	oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
	321	oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
	322	oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
	323	oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
1da177e4 LT	324	}
	325
	326	return 0;
	327	}
b75f53db	328
1cfcea1b AK	329	static int p4force;
1cfcea1b AK	330	module_param(p4force, int, 0);
b75f53db CM	331
b75f53db CM	332	static int __init p4_init(char **cpu_type)
1da177e4 LT	333	{
	334	__u8 cpu_model = boot_cpu_data.x86_model;
	335
1cfcea1b	336	if (!p4force && (cpu_model > 6 \|\| cpu_model == 5))
1da177e4 LT	337	return 0;
	338
	339	#ifndef CONFIG_SMP
	340	*cpu_type = "i386/p4";
	341	model = &op_p4_spec;
	342	return 1;
	343	#else
	344	switch (smp_num_siblings) {
b75f53db CM	345	case 1:
	346	*cpu_type = "i386/p4";
	347	model = &op_p4_spec;
	348	return 1;
	349
	350	case 2:
	351	*cpu_type = "i386/p4-ht";
	352	model = &op_p4_ht2_spec;
	353	return 1;
1da177e4 LT	354	}
	355	#endif
	356
	357	printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
	358	printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
	359	return 0;
	360	}
	361
b75f53db	362	static int __init ppro_init(char **cpu_type)
1da177e4 LT	363	{
	364	__u8 cpu_model = boot_cpu_data.x86_model;
	365
64471ebe BL	366	if (cpu_model == 14)
64471ebe BL	367	*cpu_type = "i386/core";
e107ebe0	368	else if (cpu_model == 15 \|\| cpu_model == 23)
f04b92e9	369	*cpu_type = "i386/core_2";
64471ebe	370	else if (cpu_model > 0xd)
1da177e4	371	return 0;
64471ebe	372	else if (cpu_model == 9) {
1da177e4 LT	373	*cpu_type = "i386/p6_mobile";
	374	} else if (cpu_model > 5) {
	375	*cpu_type = "i386/piii";
	376	} else if (cpu_model > 2) {
	377	*cpu_type = "i386/pii";
	378	} else {
	379	*cpu_type = "i386/ppro";
	380	}
	381
	382	model = &op_ppro_spec;
	383	return 1;
	384	}
	385
405ae7d3	386	/* in order to get sysfs right */
1da177e4 LT	387	static int using_nmi;
1da177e4 LT	388
96d0821c	389	int __init op_nmi_init(struct oprofile_operations *ops)
1da177e4 LT	390	{
	391	__u8 vendor = boot_cpu_data.x86_vendor;
	392	__u8 family = boot_cpu_data.x86;
	393	char *cpu_type;
	394
	395	if (!cpu_has_apic)
	396	return -ENODEV;
b75f53db	397
1da177e4	398	switch (vendor) {
b75f53db CM	399	case X86_VENDOR_AMD:
b75f53db CM	400	/* Needs to be at least an Athlon (or hammer in 32bit mode) */
1da177e4	401
b75f53db CM	402	switch (family) {
	403	default:
	404	return -ENODEV;
	405	case 6:
	406	model = &op_athlon_spec;
	407	cpu_type = "i386/athlon";
	408	break;
	409	case 0xf:
	410	model = &op_athlon_spec;
	411	/* Actually it could be i386/hammer too, but give
	412	user space an consistent name. */
	413	cpu_type = "x86-64/hammer";
	414	break;
	415	case 0x10:
	416	model = &op_athlon_spec;
	417	cpu_type = "x86-64/family10";
	418	break;
	419	}
	420	break;
	421
	422	case X86_VENDOR_INTEL:
	423	switch (family) {
	424	/* Pentium IV */
	425	case 0xf:
	426	if (!p4_init(&cpu_type))
1da177e4	427	return -ENODEV;
1da177e4	428	break;
b75f53db CM	429
	430	/* A P6-class processor */
	431	case 6:
	432	if (!ppro_init(&cpu_type))
	433	return -ENODEV;
1da177e4 LT	434	break;
	435
	436	default:
	437	return -ENODEV;
b75f53db CM	438	}
	439	break;
	440
	441	default:
	442	return -ENODEV;
1da177e4 LT	443	}
1da177e4 LT	444
405ae7d3	445	init_sysfs();
1da177e4 LT	446	using_nmi = 1;
	447	ops->create_files = nmi_create_files;
	448	ops->setup = nmi_setup;
	449	ops->shutdown = nmi_shutdown;
	450	ops->start = nmi_start;
	451	ops->stop = nmi_stop;
	452	ops->cpu_type = cpu_type;
	453	printk(KERN_INFO "oprofile: using NMI interrupt.\n");
	454	return 0;
	455	}
	456
96d0821c	457	void op_nmi_exit(void)
1da177e4 LT	458	{
1da177e4 LT	459	if (using_nmi)
405ae7d3	460	exit_sysfs();
1da177e4	461	}