[deliverable/linux.git] / arch / x86 / oprofile / nmi_int.c

/**
 * @file nmi_int.c
 *
 * @remark Copyright 2002-2008 OProfile authors
 * @remark Read the file COPYING
 *
 * @author John Levon <levon@movementarian.org>
 * @author Robert Richter <robert.richter@amd.com>
 */

#include <linux/init.h>
#include <linux/notifier.h>
#include <linux/smp.h>
#include <linux/oprofile.h>
#include <linux/sysdev.h>
#include <linux/slab.h>
#include <linux/moduleparam.h>
#include <linux/kdebug.h>
#include <linux/cpu.h>
#include <asm/nmi.h>
#include <asm/msr.h>
#include <asm/apic.h>

#include "op_counter.h"
#include "op_x86_model.h"

static struct op_x86_model_spec const *model;
static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
static DEFINE_PER_CPU(unsigned long, saved_lvtpc);

/* 0 == registered but off, 1 == registered and on */
static int nmi_enabled = 0;

static int profile_exceptions_notify(struct notifier_block *self,
				     unsigned long val, void *data)
{
	struct die_args *args = (struct die_args *)data;
	int ret = NOTIFY_DONE;
	int cpu = smp_processor_id();

	switch (val) {
	case DIE_NMI:
	case DIE_NMI_IPI:
		model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu));
		ret = NOTIFY_STOP;
		break;
	default:
		break;
	}
	return ret;
}

static void nmi_cpu_save_registers(struct op_msrs *msrs)
{
	unsigned int const nr_ctrs = model->num_counters;
	unsigned int const nr_ctrls = model->num_controls;
	struct op_msr *counters = msrs->counters;
	struct op_msr *controls = msrs->controls;
	unsigned int i;

	for (i = 0; i < nr_ctrs; ++i) {
		if (counters[i].addr) {
			rdmsr(counters[i].addr,
				counters[i].saved.low,
				counters[i].saved.high);
		}
	}

	for (i = 0; i < nr_ctrls; ++i) {
		if (controls[i].addr) {
			rdmsr(controls[i].addr,
				controls[i].saved.low,
				controls[i].saved.high);
		}
	}
}

static void nmi_save_registers(void *dummy)
{
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
	nmi_cpu_save_registers(msrs);
}

static void free_msrs(void)
{
	int i;
	for_each_possible_cpu(i) {
		kfree(per_cpu(cpu_msrs, i).counters);
		per_cpu(cpu_msrs, i).counters = NULL;
		kfree(per_cpu(cpu_msrs, i).controls);
		per_cpu(cpu_msrs, i).controls = NULL;
	}
}

static int allocate_msrs(void)
{
	int success = 1;
	size_t controls_size = sizeof(struct op_msr) * model->num_controls;
	size_t counters_size = sizeof(struct op_msr) * model->num_counters;

	int i;
	for_each_possible_cpu(i) {
		per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
								GFP_KERNEL);
		if (!per_cpu(cpu_msrs, i).counters) {
			success = 0;
			break;
		}
		per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
								GFP_KERNEL);
		if (!per_cpu(cpu_msrs, i).controls) {
			success = 0;
			break;
		}
	}

	if (!success)
		free_msrs();

	return success;
}

static void nmi_cpu_setup(void *dummy)
{
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
	spin_lock(&oprofilefs_lock);
	model->setup_ctrs(msrs);
	spin_unlock(&oprofilefs_lock);
	per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
	apic_write(APIC_LVTPC, APIC_DM_NMI);
}

static struct notifier_block profile_exceptions_nb = {
	.notifier_call = profile_exceptions_notify,
	.next = NULL,
	.priority = 2
};

static int nmi_setup(void)
{
	int err = 0;
	int cpu;

	if (!allocate_msrs())
		return -ENOMEM;

	err = register_die_notifier(&profile_exceptions_nb);
	if (err) {
		free_msrs();
		return err;
	}

	/* We need to serialize save and setup for HT because the subset
	 * of msrs are distinct for save and setup operations
	 */

	/* Assume saved/restored counters are the same on all CPUs */
	model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
	for_each_possible_cpu(cpu) {
		if (cpu != 0) {
			memcpy(per_cpu(cpu_msrs, cpu).counters,
				per_cpu(cpu_msrs, 0).counters,
				sizeof(struct op_msr) * model->num_counters);

			memcpy(per_cpu(cpu_msrs, cpu).controls,
				per_cpu(cpu_msrs, 0).controls,
				sizeof(struct op_msr) * model->num_controls);
		}

	}
	on_each_cpu(nmi_save_registers, NULL, 1);
	on_each_cpu(nmi_cpu_setup, NULL, 1);
	nmi_enabled = 1;
	return 0;
}

static void nmi_restore_registers(struct op_msrs *msrs)
{
	unsigned int const nr_ctrs = model->num_counters;
	unsigned int const nr_ctrls = model->num_controls;
	struct op_msr *counters = msrs->counters;
	struct op_msr *controls = msrs->controls;
	unsigned int i;

	for (i = 0; i < nr_ctrls; ++i) {
		if (controls[i].addr) {
			wrmsr(controls[i].addr,
				controls[i].saved.low,
				controls[i].saved.high);
		}
	}

	for (i = 0; i < nr_ctrs; ++i) {
		if (counters[i].addr) {
			wrmsr(counters[i].addr,
				counters[i].saved.low,
				counters[i].saved.high);
		}
	}
}

static void nmi_cpu_shutdown(void *dummy)
{
	unsigned int v;
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);

	/* restoring APIC_LVTPC can trigger an apic error because the delivery
	 * mode and vector nr combination can be illegal. That's by design: on
	 * power on apic lvt contain a zero vector nr which are legal only for
	 * NMI delivery mode. So inhibit apic err before restoring lvtpc
	 */
	v = apic_read(APIC_LVTERR);
	apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
	apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
	apic_write(APIC_LVTERR, v);
	nmi_restore_registers(msrs);
}

static void nmi_shutdown(void)
{
	struct op_msrs *msrs;

	nmi_enabled = 0;
	on_each_cpu(nmi_cpu_shutdown, NULL, 1);
	unregister_die_notifier(&profile_exceptions_nb);
	msrs = &get_cpu_var(cpu_msrs);
	model->shutdown(msrs);
	free_msrs();
	put_cpu_var(cpu_msrs);
}

static void nmi_cpu_start(void *dummy)
{
	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
	model->start(msrs);
}

static int nmi_start(void)
{
	on_each_cpu(nmi_cpu_start, NULL, 1);
	return 0;
}

static void nmi_cpu_stop(void *dummy)
{
	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
	model->stop(msrs);
}

static void nmi_stop(void)
{
	on_each_cpu(nmi_cpu_stop, NULL, 1);
}

struct op_counter_config counter_config[OP_MAX_COUNTER];

static int nmi_create_files(struct super_block *sb, struct dentry *root)
{
	unsigned int i;

	for (i = 0; i < model->num_counters; ++i) {
		struct dentry *dir;
		char buf[4];

		/* quick little hack to _not_ expose a counter if it is not
		 * available for use.  This should protect userspace app.
		 * NOTE:  assumes 1:1 mapping here (that counters are organized
		 *        sequentially in their struct assignment).
		 */
		if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
			continue;

		snprintf(buf,  sizeof(buf), "%d", i);
		dir = oprofilefs_mkdir(sb, root, buf);
		oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
		oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
		oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
		oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
		oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
		oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
	}

	return 0;
}

#ifdef CONFIG_SMP
static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
				 void *data)
{
	int cpu = (unsigned long)data;
	switch (action) {
	case CPU_DOWN_FAILED:
	case CPU_ONLINE:
		smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
		break;
	case CPU_DOWN_PREPARE:
		smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
		break;
	}
	return NOTIFY_DONE;
}

static struct notifier_block oprofile_cpu_nb = {
	.notifier_call = oprofile_cpu_notifier
};
#endif

#ifdef CONFIG_PM

static int nmi_suspend(struct sys_device *dev, pm_message_t state)
{
	/* Only one CPU left, just stop that one */
	if (nmi_enabled == 1)
		nmi_cpu_stop(NULL);
	return 0;
}

static int nmi_resume(struct sys_device *dev)
{
	if (nmi_enabled == 1)
		nmi_cpu_start(NULL);
	return 0;
}

static struct sysdev_class oprofile_sysclass = {
	.name		= "oprofile",
	.resume		= nmi_resume,
	.suspend	= nmi_suspend,
};

static struct sys_device device_oprofile = {
	.id	= 0,
	.cls	= &oprofile_sysclass,
};

static int __init init_sysfs(void)
{
	int error;

	error = sysdev_class_register(&oprofile_sysclass);
	if (!error)
		error = sysdev_register(&device_oprofile);
	return error;
}

static void exit_sysfs(void)
{
	sysdev_unregister(&device_oprofile);
	sysdev_class_unregister(&oprofile_sysclass);
}

#else
#define init_sysfs() do { } while (0)
#define exit_sysfs() do { } while (0)
#endif /* CONFIG_PM */

static int __init p4_init(char **cpu_type)
{
	__u8 cpu_model = boot_cpu_data.x86_model;

	if (cpu_model > 6 || cpu_model == 5)
		return 0;

#ifndef CONFIG_SMP
	*cpu_type = "i386/p4";
	model = &op_p4_spec;
	return 1;
#else
	switch (smp_num_siblings) {
	case 1:
		*cpu_type = "i386/p4";
		model = &op_p4_spec;
		return 1;

	case 2:
		*cpu_type = "i386/p4-ht";
		model = &op_p4_ht2_spec;
		return 1;
	}
#endif

	printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
	printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
	return 0;
}

static int force_arch_perfmon;
static int force_cpu_type(const char *str, struct kernel_param *kp)
{
	if (!strcmp(str, "archperfmon")) {
		force_arch_perfmon = 1;
		printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
	}

	return 0;
}
module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);

static int __init ppro_init(char **cpu_type)
{
	__u8 cpu_model = boot_cpu_data.x86_model;

	if (force_arch_perfmon && cpu_has_arch_perfmon)
		return 0;

	switch (cpu_model) {
	case 0 ... 2:
		*cpu_type = "i386/ppro";
		break;
	case 3 ... 5:
		*cpu_type = "i386/pii";
		break;
	case 6 ... 8:
	case 10 ... 11:
		*cpu_type = "i386/piii";
		break;
	case 9:
	case 13:
		*cpu_type = "i386/p6_mobile";
		break;
	case 14:
		*cpu_type = "i386/core";
		break;
	case 15: case 23:
		*cpu_type = "i386/core_2";
		break;
	case 26:
		arch_perfmon_setup_counters();
		*cpu_type = "i386/core_i7";
		break;
	case 28:
		*cpu_type = "i386/atom";
		break;
	default:
		/* Unknown */
		return 0;
	}

	model = &op_ppro_spec;
	return 1;
}

static int __init arch_perfmon_init(char **cpu_type)
{
	if (!cpu_has_arch_perfmon)
		return 0;
	*cpu_type = "i386/arch_perfmon";
	model = &op_arch_perfmon_spec;
	arch_perfmon_setup_counters();
	return 1;
}

/* in order to get sysfs right */
static int using_nmi;

int __init op_nmi_init(struct oprofile_operations *ops)
{
	__u8 vendor = boot_cpu_data.x86_vendor;
	__u8 family = boot_cpu_data.x86;
	char *cpu_type = NULL;
	int ret = 0;

	if (!cpu_has_apic)
		return -ENODEV;

	switch (vendor) {
	case X86_VENDOR_AMD:
		/* Needs to be at least an Athlon (or hammer in 32bit mode) */

		switch (family) {
		default:
			return -ENODEV;
		case 6:
			model = &op_amd_spec;
			cpu_type = "i386/athlon";
			break;
		case 0xf:
			model = &op_amd_spec;
			/* Actually it could be i386/hammer too, but give
			 user space an consistent name. */
			cpu_type = "x86-64/hammer";
			break;
		case 0x10:
			model = &op_amd_spec;
			cpu_type = "x86-64/family10";
			break;
		case 0x11:
			model = &op_amd_spec;
			cpu_type = "x86-64/family11h";
			break;
		}
		break;

	case X86_VENDOR_INTEL:
		switch (family) {
			/* Pentium IV */
		case 0xf:
			p4_init(&cpu_type);
			break;

			/* A P6-class processor */
		case 6:
			ppro_init(&cpu_type);
			break;

		default:
			break;
		}

		if (!cpu_type && !arch_perfmon_init(&cpu_type))
			return -ENODEV;
		break;

	default:
		return -ENODEV;
	}

#ifdef CONFIG_SMP
	register_cpu_notifier(&oprofile_cpu_nb);
#endif
	/* default values, can be overwritten by model */
	ops->create_files = nmi_create_files;
	ops->setup = nmi_setup;
	ops->shutdown = nmi_shutdown;
	ops->start = nmi_start;
	ops->stop = nmi_stop;
	ops->cpu_type = cpu_type;

	if (model->init)
		ret = model->init(ops);
	if (ret)
		return ret;

	init_sysfs();
	using_nmi = 1;
	printk(KERN_INFO "oprofile: using NMI interrupt.\n");
	return 0;
}

void op_nmi_exit(void)
{
	if (using_nmi) {
		exit_sysfs();
#ifdef CONFIG_SMP
		unregister_cpu_notifier(&oprofile_cpu_nb);
#endif
	}
	if (model->exit)
		model->exit();
}
Commit	Line	Data
1da177e4 LT	1	/**
	2	* @file nmi_int.c
	3	*
adf5ec0b	4	* @remark Copyright 2002-2008 OProfile authors
1da177e4 LT	5	* @remark Read the file COPYING
	6	*
	7	* @author John Levon <levon@movementarian.org>
adf5ec0b	8	* @author Robert Richter <robert.richter@amd.com>
1da177e4 LT	9	*/
	10
	11	#include <linux/init.h>
	12	#include <linux/notifier.h>
	13	#include <linux/smp.h>
	14	#include <linux/oprofile.h>
	15	#include <linux/sysdev.h>
	16	#include <linux/slab.h>
1cfcea1b	17	#include <linux/moduleparam.h>
1eeb66a1	18	#include <linux/kdebug.h>
80a8c9ff	19	#include <linux/cpu.h>
1da177e4 LT	20	#include <asm/nmi.h>
	21	#include <asm/msr.h>
	22	#include <asm/apic.h>
b75f53db	23
1da177e4 LT	24	#include "op_counter.h"
1da177e4 LT	25	#include "op_x86_model.h"
2fbe7b25	26
b75f53db	27	static struct op_x86_model_spec const *model;
d18d00f5 MT	28	static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
d18d00f5 MT	29	static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
2fbe7b25	30
1da177e4 LT	31	/* 0 == registered but off, 1 == registered and on */
	32	static int nmi_enabled = 0;
	33
c7c19f8e AB	34	static int profile_exceptions_notify(struct notifier_block *self,
c7c19f8e AB	35	unsigned long val, void *data)
1da177e4	36	{
2fbe7b25 DZ	37	struct die_args args = (struct die_args )data;
	38	int ret = NOTIFY_DONE;
	39	int cpu = smp_processor_id();
	40
b75f53db	41	switch (val) {
2fbe7b25	42	case DIE_NMI:
5b75af0a MG	43	case DIE_NMI_IPI:
	44	model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu));
	45	ret = NOTIFY_STOP;
2fbe7b25 DZ	46	break;
	47	default:
	48	break;
	49	}
	50	return ret;
1da177e4	51	}
2fbe7b25	52
b75f53db	53	static void nmi_cpu_save_registers(struct op_msrs *msrs)
1da177e4 LT	54	{
1da177e4 LT	55	unsigned int const nr_ctrs = model->num_counters;
b75f53db CM	56	unsigned int const nr_ctrls = model->num_controls;
	57	struct op_msr *counters = msrs->counters;
	58	struct op_msr *controls = msrs->controls;
1da177e4 LT	59	unsigned int i;
	60
	61	for (i = 0; i < nr_ctrs; ++i) {
b75f53db	62	if (counters[i].addr) {
cb9c448c DZ	63	rdmsr(counters[i].addr,
	64	counters[i].saved.low,
	65	counters[i].saved.high);
	66	}
1da177e4	67	}
b75f53db	68
1da177e4	69	for (i = 0; i < nr_ctrls; ++i) {
b75f53db	70	if (controls[i].addr) {
cb9c448c DZ	71	rdmsr(controls[i].addr,
	72	controls[i].saved.low,
	73	controls[i].saved.high);
	74	}
1da177e4 LT	75	}
	76	}
	77
b75f53db	78	static void nmi_save_registers(void *dummy)
1da177e4 LT	79	{
1da177e4 LT	80	int cpu = smp_processor_id();
d18d00f5	81	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
1da177e4 LT	82	nmi_cpu_save_registers(msrs);
	83	}
	84
1da177e4 LT	85	static void free_msrs(void)
	86	{
	87	int i;
c8912599	88	for_each_possible_cpu(i) {
d18d00f5 MT	89	kfree(per_cpu(cpu_msrs, i).counters);
	90	per_cpu(cpu_msrs, i).counters = NULL;
	91	kfree(per_cpu(cpu_msrs, i).controls);
	92	per_cpu(cpu_msrs, i).controls = NULL;
1da177e4 LT	93	}
	94	}
	95
1da177e4 LT	96	static int allocate_msrs(void)
1da177e4 LT	97	{
4c168eaf	98	int success = 1;
1da177e4 LT	99	size_t controls_size = sizeof(struct op_msr) * model->num_controls;
	100	size_t counters_size = sizeof(struct op_msr) * model->num_counters;
	101
4c168eaf	102	int i;
0939c17c	103	for_each_possible_cpu(i) {
d18d00f5 MT	104	per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
	105	GFP_KERNEL);
	106	if (!per_cpu(cpu_msrs, i).counters) {
1da177e4 LT	107	success = 0;
	108	break;
	109	}
4c168eaf RR	110	per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
4c168eaf RR	111	GFP_KERNEL);
d18d00f5	112	if (!per_cpu(cpu_msrs, i).controls) {
1da177e4 LT	113	success = 0;
	114	break;
	115	}
	116	}
	117
	118	if (!success)
	119	free_msrs();
	120
	121	return success;
	122	}
	123
b75f53db	124	static void nmi_cpu_setup(void *dummy)
1da177e4 LT	125	{
1da177e4 LT	126	int cpu = smp_processor_id();
d18d00f5	127	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
1da177e4 LT	128	spin_lock(&oprofilefs_lock);
	129	model->setup_ctrs(msrs);
	130	spin_unlock(&oprofilefs_lock);
d18d00f5	131	per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
1da177e4 LT	132	apic_write(APIC_LVTPC, APIC_DM_NMI);
	133	}
	134
2fbe7b25 DZ	135	static struct notifier_block profile_exceptions_nb = {
	136	.notifier_call = profile_exceptions_notify,
	137	.next = NULL,
5b75af0a	138	.priority = 2
2fbe7b25	139	};
1da177e4 LT	140
	141	static int nmi_setup(void)
	142	{
b75f53db	143	int err = 0;
6c977aad	144	int cpu;
2fbe7b25	145
1da177e4 LT	146	if (!allocate_msrs())
	147	return -ENOMEM;
	148
b75f53db CM	149	err = register_die_notifier(&profile_exceptions_nb);
b75f53db CM	150	if (err) {
1da177e4	151	free_msrs();
2fbe7b25	152	return err;
1da177e4	153	}
2fbe7b25	154
4c168eaf	155	/* We need to serialize save and setup for HT because the subset
1da177e4 LT	156	* of msrs are distinct for save and setup operations
1da177e4 LT	157	*/
6c977aad AK	158
6c977aad AK	159	/* Assume saved/restored counters are the same on all CPUs */
d18d00f5	160	model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
b75f53db	161	for_each_possible_cpu(cpu) {
0939c17c	162	if (cpu != 0) {
d18d00f5 MT	163	memcpy(per_cpu(cpu_msrs, cpu).counters,
d18d00f5 MT	164	per_cpu(cpu_msrs, 0).counters,
0939c17c CW	165	sizeof(struct op_msr) * model->num_counters);
0939c17c CW	166
d18d00f5 MT	167	memcpy(per_cpu(cpu_msrs, cpu).controls,
d18d00f5 MT	168	per_cpu(cpu_msrs, 0).controls,
0939c17c CW	169	sizeof(struct op_msr) * model->num_controls);
0939c17c CW	170	}
4c168eaf	171
6c977aad	172	}
15c8b6c1 JA	173	on_each_cpu(nmi_save_registers, NULL, 1);
15c8b6c1 JA	174	on_each_cpu(nmi_cpu_setup, NULL, 1);
1da177e4 LT	175	nmi_enabled = 1;
	176	return 0;
	177	}
	178
4c168eaf	179	static void nmi_restore_registers(struct op_msrs *msrs)
1da177e4 LT	180	{
1da177e4 LT	181	unsigned int const nr_ctrs = model->num_counters;
b75f53db CM	182	unsigned int const nr_ctrls = model->num_controls;
	183	struct op_msr *counters = msrs->counters;
	184	struct op_msr *controls = msrs->controls;
1da177e4 LT	185	unsigned int i;
	186
	187	for (i = 0; i < nr_ctrls; ++i) {
b75f53db	188	if (controls[i].addr) {
cb9c448c DZ	189	wrmsr(controls[i].addr,
	190	controls[i].saved.low,
	191	controls[i].saved.high);
	192	}
1da177e4	193	}
b75f53db	194
1da177e4	195	for (i = 0; i < nr_ctrs; ++i) {
b75f53db	196	if (counters[i].addr) {
cb9c448c DZ	197	wrmsr(counters[i].addr,
	198	counters[i].saved.low,
	199	counters[i].saved.high);
	200	}
1da177e4 LT	201	}
1da177e4 LT	202	}
1da177e4	203
b75f53db	204	static void nmi_cpu_shutdown(void *dummy)
1da177e4 LT	205	{
	206	unsigned int v;
	207	int cpu = smp_processor_id();
d18d00f5	208	struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);
b75f53db	209
1da177e4 LT	210	/* restoring APIC_LVTPC can trigger an apic error because the delivery
	211	* mode and vector nr combination can be illegal. That's by design: on
	212	* power on apic lvt contain a zero vector nr which are legal only for
	213	* NMI delivery mode. So inhibit apic err before restoring lvtpc
	214	*/
	215	v = apic_read(APIC_LVTERR);
	216	apic_write(APIC_LVTERR, v \| APIC_LVT_MASKED);
d18d00f5	217	apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
1da177e4	218	apic_write(APIC_LVTERR, v);
4c168eaf	219	nmi_restore_registers(msrs);
1da177e4 LT	220	}
1da177e4 LT	221
1da177e4 LT	222	static void nmi_shutdown(void)
1da177e4 LT	223	{
b61e06f2 AR	224	struct op_msrs *msrs;
b61e06f2 AR	225
1da177e4	226	nmi_enabled = 0;
15c8b6c1	227	on_each_cpu(nmi_cpu_shutdown, NULL, 1);
2fbe7b25	228	unregister_die_notifier(&profile_exceptions_nb);
b61e06f2	229	msrs = &get_cpu_var(cpu_msrs);
d18d00f5	230	model->shutdown(msrs);
1da177e4	231	free_msrs();
93e1ade5	232	put_cpu_var(cpu_msrs);
1da177e4 LT	233	}
1da177e4 LT	234
b75f53db	235	static void nmi_cpu_start(void *dummy)
1da177e4	236	{
d18d00f5	237	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
1da177e4 LT	238	model->start(msrs);
1da177e4 LT	239	}
1da177e4 LT	240
	241	static int nmi_start(void)
	242	{
15c8b6c1	243	on_each_cpu(nmi_cpu_start, NULL, 1);
1da177e4 LT	244	return 0;
1da177e4 LT	245	}
b75f53db CM	246
b75f53db CM	247	static void nmi_cpu_stop(void *dummy)
1da177e4	248	{
d18d00f5	249	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
1da177e4 LT	250	model->stop(msrs);
1da177e4 LT	251	}
b75f53db	252
1da177e4 LT	253	static void nmi_stop(void)
1da177e4 LT	254	{
15c8b6c1	255	on_each_cpu(nmi_cpu_stop, NULL, 1);
1da177e4 LT	256	}
1da177e4 LT	257
1da177e4 LT	258	struct op_counter_config counter_config[OP_MAX_COUNTER];
1da177e4 LT	259
b75f53db	260	static int nmi_create_files(struct super_block sb, struct dentry root)
1da177e4 LT	261	{
	262	unsigned int i;
	263
	264	for (i = 0; i < model->num_counters; ++i) {
b75f53db	265	struct dentry *dir;
0c6856f7	266	char buf[4];
b75f53db CM	267
b75f53db CM	268	/* quick little hack to _not_ expose a counter if it is not
cb9c448c DZ	269	* available for use. This should protect userspace app.
	270	* NOTE: assumes 1:1 mapping here (that counters are organized
	271	* sequentially in their struct assignment).
	272	*/
	273	if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
	274	continue;
	275
0c6856f7	276	snprintf(buf, sizeof(buf), "%d", i);
1da177e4	277	dir = oprofilefs_mkdir(sb, root, buf);
b75f53db CM	278	oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
	279	oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
	280	oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
	281	oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
	282	oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
	283	oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
1da177e4 LT	284	}
	285
	286	return 0;
	287	}
b75f53db	288
69046d43 RR	289	#ifdef CONFIG_SMP
	290	static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
	291	void *data)
	292	{
	293	int cpu = (unsigned long)data;
	294	switch (action) {
	295	case CPU_DOWN_FAILED:
	296	case CPU_ONLINE:
	297	smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
	298	break;
	299	case CPU_DOWN_PREPARE:
	300	smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
	301	break;
	302	}
	303	return NOTIFY_DONE;
	304	}
	305
	306	static struct notifier_block oprofile_cpu_nb = {
	307	.notifier_call = oprofile_cpu_notifier
	308	};
	309	#endif
	310
	311	#ifdef CONFIG_PM
	312
	313	static int nmi_suspend(struct sys_device *dev, pm_message_t state)
	314	{
	315	/* Only one CPU left, just stop that one */
	316	if (nmi_enabled == 1)
	317	nmi_cpu_stop(NULL);
	318	return 0;
	319	}
	320
	321	static int nmi_resume(struct sys_device *dev)
	322	{
	323	if (nmi_enabled == 1)
	324	nmi_cpu_start(NULL);
	325	return 0;
	326	}
	327
	328	static struct sysdev_class oprofile_sysclass = {
	329	.name = "oprofile",
	330	.resume = nmi_resume,
	331	.suspend = nmi_suspend,
	332	};
	333
	334	static struct sys_device device_oprofile = {
	335	.id = 0,
	336	.cls = &oprofile_sysclass,
	337	};
	338
	339	static int __init init_sysfs(void)
	340	{
	341	int error;
	342
	343	error = sysdev_class_register(&oprofile_sysclass);
	344	if (!error)
	345	error = sysdev_register(&device_oprofile);
	346	return error;
	347	}
	348
	349	static void exit_sysfs(void)
	350	{
	351	sysdev_unregister(&device_oprofile);
	352	sysdev_class_unregister(&oprofile_sysclass);
353	}
354
355	#else
356	#define init_sysfs() do { } while (0)
357	#define exit_sysfs() do { } while (0)
358	#endif /* CONFIG_PM */
359
b75f53db	360	static int __init p4_init(char **cpu_type)
1da177e4 LT	361	{
	362	__u8 cpu_model = boot_cpu_data.x86_model;
	363
1f3d7b60	364	if (cpu_model > 6 \|\| cpu_model == 5)
1da177e4 LT	365	return 0;
	366
	367	#ifndef CONFIG_SMP
	368	*cpu_type = "i386/p4";
	369	model = &op_p4_spec;
	370	return 1;
	371	#else
	372	switch (smp_num_siblings) {
b75f53db CM	373	case 1:
	374	*cpu_type = "i386/p4";
	375	model = &op_p4_spec;
	376	return 1;
	377
	378	case 2:
	379	*cpu_type = "i386/p4-ht";
	380	model = &op_p4_ht2_spec;
	381	return 1;
1da177e4 LT	382	}
	383	#endif
	384
	385	printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
	386	printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
	387	return 0;
	388	}
	389
7e4e0bd5 RR	390	static int force_arch_perfmon;
	391	static int force_cpu_type(const char str, struct kernel_param kp)
	392	{
	393	if (!strcmp(str, "archperfmon")) {
	394	force_arch_perfmon = 1;
	395	printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
	396	}
	397
	398	return 0;
	399	}
	400	module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);
1dcdb5a9	401
b75f53db	402	static int __init ppro_init(char **cpu_type)
1da177e4 LT	403	{
	404	__u8 cpu_model = boot_cpu_data.x86_model;
	405
1dcdb5a9 AK	406	if (force_arch_perfmon && cpu_has_arch_perfmon)
	407	return 0;
	408
4b9f12a3 LT	409	switch (cpu_model) {
	410	case 0 ... 2:
	411	*cpu_type = "i386/ppro";
	412	break;
	413	case 3 ... 5:
	414	*cpu_type = "i386/pii";
	415	break;
	416	case 6 ... 8:
3d337c65	417	case 10 ... 11:
4b9f12a3 LT	418	*cpu_type = "i386/piii";
	419	break;
	420	case 9:
3d337c65	421	case 13:
4b9f12a3 LT	422	*cpu_type = "i386/p6_mobile";
4b9f12a3 LT	423	break;
4b9f12a3	424	case 14:
64471ebe	425	*cpu_type = "i386/core";
4b9f12a3 LT	426	break;
	427	case 15: case 23:
	428	*cpu_type = "i386/core_2";
	429	break;
6adf406f AK	430	case 26:
	431	arch_perfmon_setup_counters();
	432	*cpu_type = "i386/core_i7";
	433	break;
	434	case 28:
	435	*cpu_type = "i386/atom";
	436	break;
4b9f12a3 LT	437	default:
4b9f12a3 LT	438	/* Unknown */
1da177e4	439	return 0;
1da177e4 LT	440	}
	441
	442	model = &op_ppro_spec;
	443	return 1;
	444	}
	445
b9917028 AK	446	static int __init arch_perfmon_init(char **cpu_type)
	447	{
	448	if (!cpu_has_arch_perfmon)
	449	return 0;
	450	*cpu_type = "i386/arch_perfmon";
	451	model = &op_arch_perfmon_spec;
	452	arch_perfmon_setup_counters();
	453	return 1;
	454	}
	455
405ae7d3	456	/* in order to get sysfs right */
1da177e4 LT	457	static int using_nmi;
1da177e4 LT	458
96d0821c	459	int __init op_nmi_init(struct oprofile_operations *ops)
1da177e4 LT	460	{
	461	__u8 vendor = boot_cpu_data.x86_vendor;
	462	__u8 family = boot_cpu_data.x86;
b9917028	463	char *cpu_type = NULL;
adf5ec0b	464	int ret = 0;
1da177e4 LT	465
	466	if (!cpu_has_apic)
	467	return -ENODEV;
b75f53db	468
1da177e4	469	switch (vendor) {
b75f53db CM	470	case X86_VENDOR_AMD:
b75f53db CM	471	/* Needs to be at least an Athlon (or hammer in 32bit mode) */
1da177e4	472
b75f53db CM	473	switch (family) {
	474	default:
	475	return -ENODEV;
	476	case 6:
6657fe4f	477	model = &op_amd_spec;
b75f53db CM	478	cpu_type = "i386/athlon";
	479	break;
	480	case 0xf:
6657fe4f	481	model = &op_amd_spec;
b75f53db CM	482	/* Actually it could be i386/hammer too, but give
	483	user space an consistent name. */
	484	cpu_type = "x86-64/hammer";
	485	break;
	486	case 0x10:
6657fe4f	487	model = &op_amd_spec;
b75f53db CM	488	cpu_type = "x86-64/family10";
b75f53db CM	489	break;
12f2b261	490	case 0x11:
6657fe4f	491	model = &op_amd_spec;
12f2b261 BK	492	cpu_type = "x86-64/family11h";
12f2b261 BK	493	break;
b75f53db CM	494	}
	495	break;
	496
	497	case X86_VENDOR_INTEL:
	498	switch (family) {
	499	/* Pentium IV */
	500	case 0xf:
b9917028	501	p4_init(&cpu_type);
1da177e4	502	break;
b75f53db CM	503
	504	/* A P6-class processor */
	505	case 6:
b9917028	506	ppro_init(&cpu_type);
1da177e4 LT	507	break;
	508
	509	default:
b9917028	510	break;
b75f53db	511	}
b9917028 AK	512
	513	if (!cpu_type && !arch_perfmon_init(&cpu_type))
	514	return -ENODEV;
b75f53db CM	515	break;
	516
	517	default:
	518	return -ENODEV;
1da177e4 LT	519	}
1da177e4 LT	520
80a8c9ff AK	521	#ifdef CONFIG_SMP
	522	register_cpu_notifier(&oprofile_cpu_nb);
	523	#endif
270d3e1a RR	524	/* default values, can be overwritten by model */
	525	ops->create_files = nmi_create_files;
	526	ops->setup = nmi_setup;
	527	ops->shutdown = nmi_shutdown;
	528	ops->start = nmi_start;
	529	ops->stop = nmi_stop;
	530	ops->cpu_type = cpu_type;
	531
adf5ec0b RR	532	if (model->init)
	533	ret = model->init(ops);
	534	if (ret)
	535	return ret;
	536
405ae7d3	537	init_sysfs();
1da177e4	538	using_nmi = 1;
1da177e4 LT	539	printk(KERN_INFO "oprofile: using NMI interrupt.\n");
	540	return 0;
	541	}
	542
96d0821c	543	void op_nmi_exit(void)
1da177e4	544	{
80a8c9ff	545	if (using_nmi) {
405ae7d3	546	exit_sysfs();
80a8c9ff AK	547	#ifdef CONFIG_SMP
	548	unregister_cpu_notifier(&oprofile_cpu_nb);
	549	#endif
	550	}
adf5ec0b RR	551	if (model->exit)
adf5ec0b RR	552	model->exit();
1da177e4	553	}