Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /** |
2 | * @file nmi_int.c | |
3 | * | |
4d4036e0 | 4 | * @remark Copyright 2002-2009 OProfile authors |
1da177e4 LT |
5 | * @remark Read the file COPYING |
6 | * | |
7 | * @author John Levon <levon@movementarian.org> | |
adf5ec0b | 8 | * @author Robert Richter <robert.richter@amd.com> |
4d4036e0 JY |
9 | * @author Barry Kasindorf <barry.kasindorf@amd.com> |
10 | * @author Jason Yeh <jason.yeh@amd.com> | |
11 | * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | |
1da177e4 LT |
12 | */ |
13 | ||
14 | #include <linux/init.h> | |
15 | #include <linux/notifier.h> | |
16 | #include <linux/smp.h> | |
17 | #include <linux/oprofile.h> | |
18 | #include <linux/sysdev.h> | |
19 | #include <linux/slab.h> | |
1cfcea1b | 20 | #include <linux/moduleparam.h> |
1eeb66a1 | 21 | #include <linux/kdebug.h> |
80a8c9ff | 22 | #include <linux/cpu.h> |
1da177e4 LT |
23 | #include <asm/nmi.h> |
24 | #include <asm/msr.h> | |
25 | #include <asm/apic.h> | |
b75f53db | 26 | |
1da177e4 LT |
27 | #include "op_counter.h" |
28 | #include "op_x86_model.h" | |
2fbe7b25 | 29 | |
259a83a8 | 30 | static struct op_x86_model_spec *model; |
d18d00f5 MT |
31 | static DEFINE_PER_CPU(struct op_msrs, cpu_msrs); |
32 | static DEFINE_PER_CPU(unsigned long, saved_lvtpc); | |
2fbe7b25 | 33 | |
6ae56b55 RR |
34 | /* must be protected with get_online_cpus()/put_online_cpus(): */ |
35 | static int nmi_enabled; | |
36 | static int ctr_running; | |
1da177e4 | 37 | |
4d4036e0 JY |
38 | struct op_counter_config counter_config[OP_MAX_COUNTER]; |
39 | ||
3370d358 RR |
40 | /* common functions */ |
41 | ||
42 | u64 op_x86_get_ctrl(struct op_x86_model_spec const *model, | |
43 | struct op_counter_config *counter_config) | |
44 | { | |
45 | u64 val = 0; | |
46 | u16 event = (u16)counter_config->event; | |
47 | ||
48 | val |= ARCH_PERFMON_EVENTSEL_INT; | |
49 | val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0; | |
50 | val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0; | |
51 | val |= (counter_config->unit_mask & 0xFF) << 8; | |
52 | event &= model->event_mask ? model->event_mask : 0xFF; | |
53 | val |= event & 0xFF; | |
54 | val |= (event & 0x0F00) << 24; | |
55 | ||
56 | return val; | |
57 | } | |
58 | ||
59 | ||
c7c19f8e AB |
60 | static int profile_exceptions_notify(struct notifier_block *self, |
61 | unsigned long val, void *data) | |
1da177e4 | 62 | { |
2fbe7b25 DZ |
63 | struct die_args *args = (struct die_args *)data; |
64 | int ret = NOTIFY_DONE; | |
2fbe7b25 | 65 | |
b75f53db | 66 | switch (val) { |
2fbe7b25 | 67 | case DIE_NMI: |
5b75af0a | 68 | case DIE_NMI_IPI: |
de654649 RR |
69 | if (ctr_running) |
70 | model->check_ctrs(args->regs, &__get_cpu_var(cpu_msrs)); | |
71 | else if (!nmi_enabled) | |
72 | break; | |
73 | else | |
74 | model->stop(&__get_cpu_var(cpu_msrs)); | |
5b75af0a | 75 | ret = NOTIFY_STOP; |
2fbe7b25 DZ |
76 | break; |
77 | default: | |
78 | break; | |
79 | } | |
80 | return ret; | |
1da177e4 | 81 | } |
2fbe7b25 | 82 | |
b75f53db | 83 | static void nmi_cpu_save_registers(struct op_msrs *msrs) |
1da177e4 | 84 | { |
b75f53db CM |
85 | struct op_msr *counters = msrs->counters; |
86 | struct op_msr *controls = msrs->controls; | |
1da177e4 LT |
87 | unsigned int i; |
88 | ||
1a245c45 | 89 | for (i = 0; i < model->num_counters; ++i) { |
95e74e62 RR |
90 | if (counters[i].addr) |
91 | rdmsrl(counters[i].addr, counters[i].saved); | |
1da177e4 | 92 | } |
b75f53db | 93 | |
1a245c45 | 94 | for (i = 0; i < model->num_controls; ++i) { |
95e74e62 RR |
95 | if (controls[i].addr) |
96 | rdmsrl(controls[i].addr, controls[i].saved); | |
1da177e4 LT |
97 | } |
98 | } | |
99 | ||
b28d1b92 RR |
100 | static void nmi_cpu_start(void *dummy) |
101 | { | |
102 | struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs); | |
2623a1d5 RR |
103 | if (!msrs->controls) |
104 | WARN_ON_ONCE(1); | |
105 | else | |
106 | model->start(msrs); | |
b28d1b92 RR |
107 | } |
108 | ||
109 | static int nmi_start(void) | |
110 | { | |
6ae56b55 | 111 | get_online_cpus(); |
b28d1b92 | 112 | on_each_cpu(nmi_cpu_start, NULL, 1); |
6ae56b55 RR |
113 | ctr_running = 1; |
114 | put_online_cpus(); | |
b28d1b92 RR |
115 | return 0; |
116 | } | |
117 | ||
118 | static void nmi_cpu_stop(void *dummy) | |
119 | { | |
120 | struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs); | |
2623a1d5 RR |
121 | if (!msrs->controls) |
122 | WARN_ON_ONCE(1); | |
123 | else | |
124 | model->stop(msrs); | |
b28d1b92 RR |
125 | } |
126 | ||
127 | static void nmi_stop(void) | |
128 | { | |
6ae56b55 | 129 | get_online_cpus(); |
b28d1b92 | 130 | on_each_cpu(nmi_cpu_stop, NULL, 1); |
6ae56b55 RR |
131 | ctr_running = 0; |
132 | put_online_cpus(); | |
b28d1b92 RR |
133 | } |
134 | ||
d8471ad3 RR |
135 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX |
136 | ||
137 | static DEFINE_PER_CPU(int, switch_index); | |
138 | ||
39e97f40 RR |
139 | static inline int has_mux(void) |
140 | { | |
141 | return !!model->switch_ctrl; | |
142 | } | |
143 | ||
d8471ad3 RR |
144 | inline int op_x86_phys_to_virt(int phys) |
145 | { | |
146 | return __get_cpu_var(switch_index) + phys; | |
147 | } | |
148 | ||
61d149d5 RR |
149 | inline int op_x86_virt_to_phys(int virt) |
150 | { | |
151 | return virt % model->num_counters; | |
152 | } | |
153 | ||
6ab82f95 RR |
154 | static void nmi_shutdown_mux(void) |
155 | { | |
156 | int i; | |
39e97f40 RR |
157 | |
158 | if (!has_mux()) | |
159 | return; | |
160 | ||
6ab82f95 RR |
161 | for_each_possible_cpu(i) { |
162 | kfree(per_cpu(cpu_msrs, i).multiplex); | |
163 | per_cpu(cpu_msrs, i).multiplex = NULL; | |
164 | per_cpu(switch_index, i) = 0; | |
165 | } | |
166 | } | |
167 | ||
168 | static int nmi_setup_mux(void) | |
169 | { | |
170 | size_t multiplex_size = | |
171 | sizeof(struct op_msr) * model->num_virt_counters; | |
172 | int i; | |
39e97f40 RR |
173 | |
174 | if (!has_mux()) | |
175 | return 1; | |
176 | ||
6ab82f95 RR |
177 | for_each_possible_cpu(i) { |
178 | per_cpu(cpu_msrs, i).multiplex = | |
c17c8fbf | 179 | kzalloc(multiplex_size, GFP_KERNEL); |
6ab82f95 RR |
180 | if (!per_cpu(cpu_msrs, i).multiplex) |
181 | return 0; | |
182 | } | |
39e97f40 | 183 | |
6ab82f95 RR |
184 | return 1; |
185 | } | |
186 | ||
48fb4b46 RR |
187 | static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) |
188 | { | |
189 | int i; | |
190 | struct op_msr *multiplex = msrs->multiplex; | |
191 | ||
39e97f40 RR |
192 | if (!has_mux()) |
193 | return; | |
194 | ||
48fb4b46 RR |
195 | for (i = 0; i < model->num_virt_counters; ++i) { |
196 | if (counter_config[i].enabled) { | |
197 | multiplex[i].saved = -(u64)counter_config[i].count; | |
198 | } else { | |
48fb4b46 RR |
199 | multiplex[i].saved = 0; |
200 | } | |
201 | } | |
202 | ||
203 | per_cpu(switch_index, cpu) = 0; | |
204 | } | |
205 | ||
d0f585dd RR |
206 | static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs) |
207 | { | |
68dc819c | 208 | struct op_msr *counters = msrs->counters; |
d0f585dd RR |
209 | struct op_msr *multiplex = msrs->multiplex; |
210 | int i; | |
211 | ||
212 | for (i = 0; i < model->num_counters; ++i) { | |
213 | int virt = op_x86_phys_to_virt(i); | |
68dc819c RR |
214 | if (counters[i].addr) |
215 | rdmsrl(counters[i].addr, multiplex[virt].saved); | |
d0f585dd RR |
216 | } |
217 | } | |
218 | ||
219 | static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs) | |
220 | { | |
68dc819c | 221 | struct op_msr *counters = msrs->counters; |
d0f585dd RR |
222 | struct op_msr *multiplex = msrs->multiplex; |
223 | int i; | |
224 | ||
225 | for (i = 0; i < model->num_counters; ++i) { | |
226 | int virt = op_x86_phys_to_virt(i); | |
68dc819c RR |
227 | if (counters[i].addr) |
228 | wrmsrl(counters[i].addr, multiplex[virt].saved); | |
d0f585dd RR |
229 | } |
230 | } | |
231 | ||
b28d1b92 RR |
232 | static void nmi_cpu_switch(void *dummy) |
233 | { | |
234 | int cpu = smp_processor_id(); | |
235 | int si = per_cpu(switch_index, cpu); | |
236 | struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu); | |
237 | ||
238 | nmi_cpu_stop(NULL); | |
239 | nmi_cpu_save_mpx_registers(msrs); | |
240 | ||
241 | /* move to next set */ | |
242 | si += model->num_counters; | |
d8cc108f | 243 | if ((si >= model->num_virt_counters) || (counter_config[si].count == 0)) |
b28d1b92 RR |
244 | per_cpu(switch_index, cpu) = 0; |
245 | else | |
246 | per_cpu(switch_index, cpu) = si; | |
247 | ||
248 | model->switch_ctrl(model, msrs); | |
249 | nmi_cpu_restore_mpx_registers(msrs); | |
250 | ||
251 | nmi_cpu_start(NULL); | |
252 | } | |
253 | ||
254 | ||
255 | /* | |
256 | * Quick check to see if multiplexing is necessary. | |
257 | * The check should be sufficient since counters are used | |
258 | * in ordre. | |
259 | */ | |
260 | static int nmi_multiplex_on(void) | |
261 | { | |
262 | return counter_config[model->num_counters].count ? 0 : -EINVAL; | |
263 | } | |
264 | ||
265 | static int nmi_switch_event(void) | |
266 | { | |
39e97f40 | 267 | if (!has_mux()) |
b28d1b92 RR |
268 | return -ENOSYS; /* not implemented */ |
269 | if (nmi_multiplex_on() < 0) | |
270 | return -EINVAL; /* not necessary */ | |
271 | ||
6ae56b55 RR |
272 | get_online_cpus(); |
273 | if (ctr_running) | |
274 | on_each_cpu(nmi_cpu_switch, NULL, 1); | |
275 | put_online_cpus(); | |
b28d1b92 | 276 | |
b28d1b92 RR |
277 | return 0; |
278 | } | |
279 | ||
52805144 RR |
280 | static inline void mux_init(struct oprofile_operations *ops) |
281 | { | |
282 | if (has_mux()) | |
283 | ops->switch_events = nmi_switch_event; | |
284 | } | |
285 | ||
4d015f79 RR |
286 | static void mux_clone(int cpu) |
287 | { | |
288 | if (!has_mux()) | |
289 | return; | |
290 | ||
291 | memcpy(per_cpu(cpu_msrs, cpu).multiplex, | |
292 | per_cpu(cpu_msrs, 0).multiplex, | |
293 | sizeof(struct op_msr) * model->num_virt_counters); | |
294 | } | |
295 | ||
d8471ad3 RR |
296 | #else |
297 | ||
298 | inline int op_x86_phys_to_virt(int phys) { return phys; } | |
61d149d5 | 299 | inline int op_x86_virt_to_phys(int virt) { return virt; } |
6ab82f95 RR |
300 | static inline void nmi_shutdown_mux(void) { } |
301 | static inline int nmi_setup_mux(void) { return 1; } | |
48fb4b46 RR |
302 | static inline void |
303 | nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { } | |
52805144 | 304 | static inline void mux_init(struct oprofile_operations *ops) { } |
4d015f79 | 305 | static void mux_clone(int cpu) { } |
d8471ad3 RR |
306 | |
307 | #endif | |
308 | ||
1da177e4 LT |
309 | static void free_msrs(void) |
310 | { | |
311 | int i; | |
c8912599 | 312 | for_each_possible_cpu(i) { |
d18d00f5 MT |
313 | kfree(per_cpu(cpu_msrs, i).counters); |
314 | per_cpu(cpu_msrs, i).counters = NULL; | |
315 | kfree(per_cpu(cpu_msrs, i).controls); | |
316 | per_cpu(cpu_msrs, i).controls = NULL; | |
1da177e4 | 317 | } |
8f5a2dd8 | 318 | nmi_shutdown_mux(); |
1da177e4 LT |
319 | } |
320 | ||
1da177e4 LT |
321 | static int allocate_msrs(void) |
322 | { | |
1da177e4 LT |
323 | size_t controls_size = sizeof(struct op_msr) * model->num_controls; |
324 | size_t counters_size = sizeof(struct op_msr) * model->num_counters; | |
325 | ||
4c168eaf | 326 | int i; |
0939c17c | 327 | for_each_possible_cpu(i) { |
c17c8fbf | 328 | per_cpu(cpu_msrs, i).counters = kzalloc(counters_size, |
6ab82f95 RR |
329 | GFP_KERNEL); |
330 | if (!per_cpu(cpu_msrs, i).counters) | |
8f5a2dd8 | 331 | goto fail; |
c17c8fbf | 332 | per_cpu(cpu_msrs, i).controls = kzalloc(controls_size, |
6ab82f95 RR |
333 | GFP_KERNEL); |
334 | if (!per_cpu(cpu_msrs, i).controls) | |
8f5a2dd8 | 335 | goto fail; |
1da177e4 LT |
336 | } |
337 | ||
8f5a2dd8 RR |
338 | if (!nmi_setup_mux()) |
339 | goto fail; | |
340 | ||
6ab82f95 | 341 | return 1; |
8f5a2dd8 RR |
342 | |
343 | fail: | |
344 | free_msrs(); | |
345 | return 0; | |
1da177e4 LT |
346 | } |
347 | ||
b75f53db | 348 | static void nmi_cpu_setup(void *dummy) |
1da177e4 LT |
349 | { |
350 | int cpu = smp_processor_id(); | |
d18d00f5 | 351 | struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu); |
44ab9a6b | 352 | nmi_cpu_save_registers(msrs); |
1da177e4 | 353 | spin_lock(&oprofilefs_lock); |
ef8828dd | 354 | model->setup_ctrs(model, msrs); |
6bfccd09 | 355 | nmi_cpu_setup_mux(cpu, msrs); |
1da177e4 | 356 | spin_unlock(&oprofilefs_lock); |
d18d00f5 | 357 | per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC); |
1da177e4 LT |
358 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
359 | } | |
360 | ||
2fbe7b25 DZ |
361 | static struct notifier_block profile_exceptions_nb = { |
362 | .notifier_call = profile_exceptions_notify, | |
363 | .next = NULL, | |
5b75af0a | 364 | .priority = 2 |
2fbe7b25 | 365 | }; |
1da177e4 | 366 | |
44ab9a6b | 367 | static void nmi_cpu_restore_registers(struct op_msrs *msrs) |
1da177e4 | 368 | { |
b75f53db CM |
369 | struct op_msr *counters = msrs->counters; |
370 | struct op_msr *controls = msrs->controls; | |
1da177e4 LT |
371 | unsigned int i; |
372 | ||
1a245c45 | 373 | for (i = 0; i < model->num_controls; ++i) { |
95e74e62 RR |
374 | if (controls[i].addr) |
375 | wrmsrl(controls[i].addr, controls[i].saved); | |
1da177e4 | 376 | } |
b75f53db | 377 | |
1a245c45 | 378 | for (i = 0; i < model->num_counters; ++i) { |
95e74e62 RR |
379 | if (counters[i].addr) |
380 | wrmsrl(counters[i].addr, counters[i].saved); | |
1da177e4 LT |
381 | } |
382 | } | |
1da177e4 | 383 | |
b75f53db | 384 | static void nmi_cpu_shutdown(void *dummy) |
1da177e4 LT |
385 | { |
386 | unsigned int v; | |
387 | int cpu = smp_processor_id(); | |
82a22528 | 388 | struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu); |
b75f53db | 389 | |
1da177e4 LT |
390 | /* restoring APIC_LVTPC can trigger an apic error because the delivery |
391 | * mode and vector nr combination can be illegal. That's by design: on | |
392 | * power on apic lvt contain a zero vector nr which are legal only for | |
393 | * NMI delivery mode. So inhibit apic err before restoring lvtpc | |
394 | */ | |
395 | v = apic_read(APIC_LVTERR); | |
396 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
d18d00f5 | 397 | apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu)); |
1da177e4 | 398 | apic_write(APIC_LVTERR, v); |
44ab9a6b | 399 | nmi_cpu_restore_registers(msrs); |
bae663bc RR |
400 | if (model->cpu_down) |
401 | model->cpu_down(); | |
1da177e4 LT |
402 | } |
403 | ||
6ae56b55 RR |
404 | static void nmi_cpu_up(void *dummy) |
405 | { | |
406 | if (nmi_enabled) | |
407 | nmi_cpu_setup(dummy); | |
408 | if (ctr_running) | |
409 | nmi_cpu_start(dummy); | |
410 | } | |
411 | ||
412 | static void nmi_cpu_down(void *dummy) | |
413 | { | |
414 | if (ctr_running) | |
415 | nmi_cpu_stop(dummy); | |
416 | if (nmi_enabled) | |
417 | nmi_cpu_shutdown(dummy); | |
418 | } | |
419 | ||
b75f53db | 420 | static int nmi_create_files(struct super_block *sb, struct dentry *root) |
1da177e4 LT |
421 | { |
422 | unsigned int i; | |
423 | ||
4d4036e0 | 424 | for (i = 0; i < model->num_virt_counters; ++i) { |
b75f53db | 425 | struct dentry *dir; |
0c6856f7 | 426 | char buf[4]; |
b75f53db CM |
427 | |
428 | /* quick little hack to _not_ expose a counter if it is not | |
cb9c448c DZ |
429 | * available for use. This should protect userspace app. |
430 | * NOTE: assumes 1:1 mapping here (that counters are organized | |
431 | * sequentially in their struct assignment). | |
432 | */ | |
11be1a7b | 433 | if (!avail_to_resrv_perfctr_nmi_bit(op_x86_virt_to_phys(i))) |
cb9c448c DZ |
434 | continue; |
435 | ||
0c6856f7 | 436 | snprintf(buf, sizeof(buf), "%d", i); |
1da177e4 | 437 | dir = oprofilefs_mkdir(sb, root, buf); |
b75f53db CM |
438 | oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled); |
439 | oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event); | |
440 | oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count); | |
441 | oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask); | |
442 | oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel); | |
443 | oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user); | |
1da177e4 LT |
444 | } |
445 | ||
446 | return 0; | |
447 | } | |
b75f53db | 448 | |
69046d43 RR |
449 | static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action, |
450 | void *data) | |
451 | { | |
452 | int cpu = (unsigned long)data; | |
453 | switch (action) { | |
454 | case CPU_DOWN_FAILED: | |
455 | case CPU_ONLINE: | |
6ae56b55 | 456 | smp_call_function_single(cpu, nmi_cpu_up, NULL, 0); |
69046d43 RR |
457 | break; |
458 | case CPU_DOWN_PREPARE: | |
6ae56b55 | 459 | smp_call_function_single(cpu, nmi_cpu_down, NULL, 1); |
69046d43 RR |
460 | break; |
461 | } | |
462 | return NOTIFY_DONE; | |
463 | } | |
464 | ||
465 | static struct notifier_block oprofile_cpu_nb = { | |
466 | .notifier_call = oprofile_cpu_notifier | |
467 | }; | |
69046d43 | 468 | |
d30d64c6 RR |
469 | static int nmi_setup(void) |
470 | { | |
471 | int err = 0; | |
472 | int cpu; | |
473 | ||
474 | if (!allocate_msrs()) | |
475 | return -ENOMEM; | |
476 | ||
477 | /* We need to serialize save and setup for HT because the subset | |
478 | * of msrs are distinct for save and setup operations | |
479 | */ | |
480 | ||
481 | /* Assume saved/restored counters are the same on all CPUs */ | |
482 | err = model->fill_in_addresses(&per_cpu(cpu_msrs, 0)); | |
483 | if (err) | |
484 | goto fail; | |
485 | ||
486 | for_each_possible_cpu(cpu) { | |
487 | if (!cpu) | |
488 | continue; | |
489 | ||
490 | memcpy(per_cpu(cpu_msrs, cpu).counters, | |
491 | per_cpu(cpu_msrs, 0).counters, | |
492 | sizeof(struct op_msr) * model->num_counters); | |
493 | ||
494 | memcpy(per_cpu(cpu_msrs, cpu).controls, | |
495 | per_cpu(cpu_msrs, 0).controls, | |
496 | sizeof(struct op_msr) * model->num_controls); | |
497 | ||
498 | mux_clone(cpu); | |
499 | } | |
500 | ||
501 | nmi_enabled = 0; | |
502 | ctr_running = 0; | |
503 | barrier(); | |
504 | err = register_die_notifier(&profile_exceptions_nb); | |
505 | if (err) | |
506 | goto fail; | |
507 | ||
508 | get_online_cpus(); | |
3de668ee | 509 | register_cpu_notifier(&oprofile_cpu_nb); |
d30d64c6 RR |
510 | on_each_cpu(nmi_cpu_setup, NULL, 1); |
511 | nmi_enabled = 1; | |
512 | put_online_cpus(); | |
513 | ||
514 | return 0; | |
515 | fail: | |
516 | free_msrs(); | |
517 | return err; | |
518 | } | |
519 | ||
520 | static void nmi_shutdown(void) | |
521 | { | |
522 | struct op_msrs *msrs; | |
523 | ||
524 | get_online_cpus(); | |
3de668ee | 525 | unregister_cpu_notifier(&oprofile_cpu_nb); |
d30d64c6 RR |
526 | on_each_cpu(nmi_cpu_shutdown, NULL, 1); |
527 | nmi_enabled = 0; | |
528 | ctr_running = 0; | |
529 | put_online_cpus(); | |
530 | barrier(); | |
531 | unregister_die_notifier(&profile_exceptions_nb); | |
532 | msrs = &get_cpu_var(cpu_msrs); | |
533 | model->shutdown(msrs); | |
534 | free_msrs(); | |
535 | put_cpu_var(cpu_msrs); | |
536 | } | |
537 | ||
69046d43 RR |
538 | #ifdef CONFIG_PM |
539 | ||
540 | static int nmi_suspend(struct sys_device *dev, pm_message_t state) | |
541 | { | |
542 | /* Only one CPU left, just stop that one */ | |
543 | if (nmi_enabled == 1) | |
544 | nmi_cpu_stop(NULL); | |
545 | return 0; | |
546 | } | |
547 | ||
548 | static int nmi_resume(struct sys_device *dev) | |
549 | { | |
550 | if (nmi_enabled == 1) | |
551 | nmi_cpu_start(NULL); | |
552 | return 0; | |
553 | } | |
554 | ||
555 | static struct sysdev_class oprofile_sysclass = { | |
556 | .name = "oprofile", | |
557 | .resume = nmi_resume, | |
558 | .suspend = nmi_suspend, | |
559 | }; | |
560 | ||
561 | static struct sys_device device_oprofile = { | |
562 | .id = 0, | |
563 | .cls = &oprofile_sysclass, | |
564 | }; | |
565 | ||
566 | static int __init init_sysfs(void) | |
567 | { | |
568 | int error; | |
569 | ||
570 | error = sysdev_class_register(&oprofile_sysclass); | |
10f0412f RR |
571 | if (error) |
572 | return error; | |
573 | ||
574 | error = sysdev_register(&device_oprofile); | |
575 | if (error) | |
576 | sysdev_class_unregister(&oprofile_sysclass); | |
577 | ||
69046d43 RR |
578 | return error; |
579 | } | |
580 | ||
581 | static void exit_sysfs(void) | |
582 | { | |
583 | sysdev_unregister(&device_oprofile); | |
584 | sysdev_class_unregister(&oprofile_sysclass); | |
585 | } | |
586 | ||
587 | #else | |
269f45c2 RR |
588 | |
589 | static inline int init_sysfs(void) { return 0; } | |
590 | static inline void exit_sysfs(void) { } | |
591 | ||
69046d43 RR |
592 | #endif /* CONFIG_PM */ |
593 | ||
b75f53db | 594 | static int __init p4_init(char **cpu_type) |
1da177e4 LT |
595 | { |
596 | __u8 cpu_model = boot_cpu_data.x86_model; | |
597 | ||
1f3d7b60 | 598 | if (cpu_model > 6 || cpu_model == 5) |
1da177e4 LT |
599 | return 0; |
600 | ||
601 | #ifndef CONFIG_SMP | |
602 | *cpu_type = "i386/p4"; | |
603 | model = &op_p4_spec; | |
604 | return 1; | |
605 | #else | |
606 | switch (smp_num_siblings) { | |
b75f53db CM |
607 | case 1: |
608 | *cpu_type = "i386/p4"; | |
609 | model = &op_p4_spec; | |
610 | return 1; | |
611 | ||
612 | case 2: | |
613 | *cpu_type = "i386/p4-ht"; | |
614 | model = &op_p4_ht2_spec; | |
615 | return 1; | |
1da177e4 LT |
616 | } |
617 | #endif | |
618 | ||
619 | printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n"); | |
620 | printk(KERN_INFO "oprofile: Reverting to timer mode.\n"); | |
621 | return 0; | |
622 | } | |
623 | ||
7e4e0bd5 RR |
624 | static int force_arch_perfmon; |
625 | static int force_cpu_type(const char *str, struct kernel_param *kp) | |
626 | { | |
8d7ff4f2 | 627 | if (!strcmp(str, "arch_perfmon")) { |
7e4e0bd5 RR |
628 | force_arch_perfmon = 1; |
629 | printk(KERN_INFO "oprofile: forcing architectural perfmon\n"); | |
630 | } | |
631 | ||
632 | return 0; | |
633 | } | |
634 | module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0); | |
1dcdb5a9 | 635 | |
b75f53db | 636 | static int __init ppro_init(char **cpu_type) |
1da177e4 LT |
637 | { |
638 | __u8 cpu_model = boot_cpu_data.x86_model; | |
259a83a8 | 639 | struct op_x86_model_spec *spec = &op_ppro_spec; /* default */ |
1da177e4 | 640 | |
1dcdb5a9 AK |
641 | if (force_arch_perfmon && cpu_has_arch_perfmon) |
642 | return 0; | |
643 | ||
45c34e05 JV |
644 | /* |
645 | * Documentation on identifying Intel processors by CPU family | |
646 | * and model can be found in the Intel Software Developer's | |
647 | * Manuals (SDM): | |
648 | * | |
649 | * http://www.intel.com/products/processor/manuals/ | |
650 | * | |
651 | * As of May 2010 the documentation for this was in the: | |
652 | * "Intel 64 and IA-32 Architectures Software Developer's | |
653 | * Manual Volume 3B: System Programming Guide", "Table B-1 | |
654 | * CPUID Signature Values of DisplayFamily_DisplayModel". | |
655 | */ | |
4b9f12a3 LT |
656 | switch (cpu_model) { |
657 | case 0 ... 2: | |
658 | *cpu_type = "i386/ppro"; | |
659 | break; | |
660 | case 3 ... 5: | |
661 | *cpu_type = "i386/pii"; | |
662 | break; | |
663 | case 6 ... 8: | |
3d337c65 | 664 | case 10 ... 11: |
4b9f12a3 LT |
665 | *cpu_type = "i386/piii"; |
666 | break; | |
667 | case 9: | |
3d337c65 | 668 | case 13: |
4b9f12a3 LT |
669 | *cpu_type = "i386/p6_mobile"; |
670 | break; | |
4b9f12a3 | 671 | case 14: |
64471ebe | 672 | *cpu_type = "i386/core"; |
4b9f12a3 | 673 | break; |
c33f543d PS |
674 | case 0x0f: |
675 | case 0x16: | |
676 | case 0x17: | |
bb7ab785 | 677 | case 0x1d: |
4b9f12a3 LT |
678 | *cpu_type = "i386/core_2"; |
679 | break; | |
45c34e05 | 680 | case 0x1a: |
a7c55cbe | 681 | case 0x1e: |
e83e452b | 682 | case 0x2e: |
802070f5 | 683 | spec = &op_arch_perfmon_spec; |
6adf406f AK |
684 | *cpu_type = "i386/core_i7"; |
685 | break; | |
45c34e05 | 686 | case 0x1c: |
6adf406f AK |
687 | *cpu_type = "i386/atom"; |
688 | break; | |
4b9f12a3 LT |
689 | default: |
690 | /* Unknown */ | |
1da177e4 | 691 | return 0; |
1da177e4 LT |
692 | } |
693 | ||
802070f5 | 694 | model = spec; |
1da177e4 LT |
695 | return 1; |
696 | } | |
697 | ||
96d0821c | 698 | int __init op_nmi_init(struct oprofile_operations *ops) |
1da177e4 LT |
699 | { |
700 | __u8 vendor = boot_cpu_data.x86_vendor; | |
701 | __u8 family = boot_cpu_data.x86; | |
b9917028 | 702 | char *cpu_type = NULL; |
adf5ec0b | 703 | int ret = 0; |
1da177e4 LT |
704 | |
705 | if (!cpu_has_apic) | |
706 | return -ENODEV; | |
b75f53db | 707 | |
1da177e4 | 708 | switch (vendor) { |
b75f53db CM |
709 | case X86_VENDOR_AMD: |
710 | /* Needs to be at least an Athlon (or hammer in 32bit mode) */ | |
1da177e4 | 711 | |
b75f53db | 712 | switch (family) { |
b75f53db | 713 | case 6: |
b75f53db CM |
714 | cpu_type = "i386/athlon"; |
715 | break; | |
716 | case 0xf: | |
d20f24c6 RR |
717 | /* |
718 | * Actually it could be i386/hammer too, but | |
719 | * give user space an consistent name. | |
720 | */ | |
b75f53db CM |
721 | cpu_type = "x86-64/hammer"; |
722 | break; | |
723 | case 0x10: | |
b75f53db CM |
724 | cpu_type = "x86-64/family10"; |
725 | break; | |
12f2b261 | 726 | case 0x11: |
12f2b261 BK |
727 | cpu_type = "x86-64/family11h"; |
728 | break; | |
3acbf084 RR |
729 | case 0x12: |
730 | cpu_type = "x86-64/family12h"; | |
731 | break; | |
e6341474 RR |
732 | case 0x14: |
733 | cpu_type = "x86-64/family14h"; | |
734 | break; | |
d20f24c6 RR |
735 | default: |
736 | return -ENODEV; | |
b75f53db | 737 | } |
d20f24c6 | 738 | model = &op_amd_spec; |
b75f53db CM |
739 | break; |
740 | ||
741 | case X86_VENDOR_INTEL: | |
742 | switch (family) { | |
743 | /* Pentium IV */ | |
744 | case 0xf: | |
b9917028 | 745 | p4_init(&cpu_type); |
1da177e4 | 746 | break; |
b75f53db CM |
747 | |
748 | /* A P6-class processor */ | |
749 | case 6: | |
b9917028 | 750 | ppro_init(&cpu_type); |
1da177e4 LT |
751 | break; |
752 | ||
753 | default: | |
b9917028 | 754 | break; |
b75f53db | 755 | } |
b9917028 | 756 | |
e419294e RR |
757 | if (cpu_type) |
758 | break; | |
759 | ||
760 | if (!cpu_has_arch_perfmon) | |
b9917028 | 761 | return -ENODEV; |
e419294e RR |
762 | |
763 | /* use arch perfmon as fallback */ | |
764 | cpu_type = "i386/arch_perfmon"; | |
765 | model = &op_arch_perfmon_spec; | |
b75f53db CM |
766 | break; |
767 | ||
768 | default: | |
769 | return -ENODEV; | |
1da177e4 LT |
770 | } |
771 | ||
270d3e1a | 772 | /* default values, can be overwritten by model */ |
6e63ea4b RR |
773 | ops->create_files = nmi_create_files; |
774 | ops->setup = nmi_setup; | |
775 | ops->shutdown = nmi_shutdown; | |
776 | ops->start = nmi_start; | |
777 | ops->stop = nmi_stop; | |
778 | ops->cpu_type = cpu_type; | |
270d3e1a | 779 | |
adf5ec0b RR |
780 | if (model->init) |
781 | ret = model->init(ops); | |
782 | if (ret) | |
783 | return ret; | |
784 | ||
52471c67 RR |
785 | if (!model->num_virt_counters) |
786 | model->num_virt_counters = model->num_counters; | |
787 | ||
52805144 RR |
788 | mux_init(ops); |
789 | ||
10f0412f RR |
790 | ret = init_sysfs(); |
791 | if (ret) | |
792 | return ret; | |
793 | ||
1da177e4 LT |
794 | printk(KERN_INFO "oprofile: using NMI interrupt.\n"); |
795 | return 0; | |
796 | } | |
797 | ||
96d0821c | 798 | void op_nmi_exit(void) |
1da177e4 | 799 | { |
5140434d | 800 | exit_sysfs(); |
1da177e4 | 801 | } |