[deliverable/linux.git] / arch / x86 / oprofile / nmi_int.c

/**
 * @file nmi_int.c
 *
 * @remark Copyright 2002 OProfile authors
 * @remark Read the file COPYING
 *
 * @author John Levon <levon@movementarian.org>
 */

#include <linux/init.h>
#include <linux/notifier.h>
#include <linux/smp.h>
#include <linux/oprofile.h>
#include <linux/sysdev.h>
#include <linux/slab.h>
#include <linux/moduleparam.h>
#include <linux/kdebug.h>
#include <linux/cpu.h>
#include <asm/nmi.h>
#include <asm/msr.h>
#include <asm/apic.h>

#include "op_counter.h"
#include "op_x86_model.h"

static struct op_x86_model_spec const *model;
static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
static DEFINE_PER_CPU(unsigned long, saved_lvtpc);

static int nmi_start(void);
static void nmi_stop(void);
static void nmi_cpu_start(void *dummy);
static void nmi_cpu_stop(void *dummy);

/* 0 == registered but off, 1 == registered and on */
static int nmi_enabled = 0;

#ifdef CONFIG_SMP
static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
				 void *data)
{
	int cpu = (unsigned long)data;
	switch (action) {
	case CPU_DOWN_FAILED:
	case CPU_ONLINE:
		smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
		break;
	case CPU_DOWN_PREPARE:
		smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
		break;
	}
	return NOTIFY_DONE;
}

static struct notifier_block oprofile_cpu_nb = {
	.notifier_call = oprofile_cpu_notifier
};
#endif

#ifdef CONFIG_PM

static int nmi_suspend(struct sys_device *dev, pm_message_t state)
{
	/* Only one CPU left, just stop that one */
	if (nmi_enabled == 1)
		nmi_cpu_stop(NULL);
	return 0;
}

static int nmi_resume(struct sys_device *dev)
{
	if (nmi_enabled == 1)
		nmi_cpu_start(NULL);
	return 0;
}

static struct sysdev_class oprofile_sysclass = {
	.name		= "oprofile",
	.resume		= nmi_resume,
	.suspend	= nmi_suspend,
};

static struct sys_device device_oprofile = {
	.id	= 0,
	.cls	= &oprofile_sysclass,
};

static int __init init_sysfs(void)
{
	int error;

	error = sysdev_class_register(&oprofile_sysclass);
	if (!error)
		error = sysdev_register(&device_oprofile);
	return error;
}

static void exit_sysfs(void)
{
	sysdev_unregister(&device_oprofile);
	sysdev_class_unregister(&oprofile_sysclass);
}

#else
#define init_sysfs() do { } while (0)
#define exit_sysfs() do { } while (0)
#endif /* CONFIG_PM */

static int profile_exceptions_notify(struct notifier_block *self,
				     unsigned long val, void *data)
{
	struct die_args *args = (struct die_args *)data;
	int ret = NOTIFY_DONE;
	int cpu = smp_processor_id();

	switch (val) {
	case DIE_NMI:
		if (model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu)))
			ret = NOTIFY_STOP;
		break;
	default:
		break;
	}
	return ret;
}

static void nmi_cpu_save_registers(struct op_msrs *msrs)
{
	unsigned int const nr_ctrs = model->num_counters;
	unsigned int const nr_ctrls = model->num_controls;
	struct op_msr *counters = msrs->counters;
	struct op_msr *controls = msrs->controls;
	unsigned int i;

	for (i = 0; i < nr_ctrs; ++i) {
		if (counters[i].addr) {
			rdmsr(counters[i].addr,
				counters[i].saved.low,
				counters[i].saved.high);
		}
	}

	for (i = 0; i < nr_ctrls; ++i) {
		if (controls[i].addr) {
			rdmsr(controls[i].addr,
				controls[i].saved.low,
				controls[i].saved.high);
		}
	}
}

static void nmi_save_registers(void *dummy)
{
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
	nmi_cpu_save_registers(msrs);
}

static void free_msrs(void)
{
	int i;
	for_each_possible_cpu(i) {
		kfree(per_cpu(cpu_msrs, i).counters);
		per_cpu(cpu_msrs, i).counters = NULL;
		kfree(per_cpu(cpu_msrs, i).controls);
		per_cpu(cpu_msrs, i).controls = NULL;
	}
}

static int allocate_msrs(void)
{
	int success = 1;
	size_t controls_size = sizeof(struct op_msr) * model->num_controls;
	size_t counters_size = sizeof(struct op_msr) * model->num_counters;

	int i;
	for_each_possible_cpu(i) {
		per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
								GFP_KERNEL);
		if (!per_cpu(cpu_msrs, i).counters) {
			success = 0;
			break;
		}
		per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
								GFP_KERNEL);
		if (!per_cpu(cpu_msrs, i).controls) {
			success = 0;
			break;
		}
	}

	if (!success)
		free_msrs();

	return success;
}

static void nmi_cpu_setup(void *dummy)
{
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
	spin_lock(&oprofilefs_lock);
	model->setup_ctrs(msrs);
	spin_unlock(&oprofilefs_lock);
	per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
	apic_write(APIC_LVTPC, APIC_DM_NMI);
}

static struct notifier_block profile_exceptions_nb = {
	.notifier_call = profile_exceptions_notify,
	.next = NULL,
	.priority = 0
};

static int nmi_setup(void)
{
	int err = 0;
	int cpu;

	if (!allocate_msrs())
		return -ENOMEM;

	err = register_die_notifier(&profile_exceptions_nb);
	if (err) {
		free_msrs();
		return err;
	}

	/* We need to serialize save and setup for HT because the subset
	 * of msrs are distinct for save and setup operations
	 */

	/* Assume saved/restored counters are the same on all CPUs */
	model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
	for_each_possible_cpu(cpu) {
		if (cpu != 0) {
			memcpy(per_cpu(cpu_msrs, cpu).counters,
				per_cpu(cpu_msrs, 0).counters,
				sizeof(struct op_msr) * model->num_counters);

			memcpy(per_cpu(cpu_msrs, cpu).controls,
				per_cpu(cpu_msrs, 0).controls,
				sizeof(struct op_msr) * model->num_controls);
		}

	}
	on_each_cpu(nmi_save_registers, NULL, 1);
	on_each_cpu(nmi_cpu_setup, NULL, 1);
	nmi_enabled = 1;
	return 0;
}

static void nmi_restore_registers(struct op_msrs *msrs)
{
	unsigned int const nr_ctrs = model->num_counters;
	unsigned int const nr_ctrls = model->num_controls;
	struct op_msr *counters = msrs->counters;
	struct op_msr *controls = msrs->controls;
	unsigned int i;

	for (i = 0; i < nr_ctrls; ++i) {
		if (controls[i].addr) {
			wrmsr(controls[i].addr,
				controls[i].saved.low,
				controls[i].saved.high);
		}
	}

	for (i = 0; i < nr_ctrs; ++i) {
		if (counters[i].addr) {
			wrmsr(counters[i].addr,
				counters[i].saved.low,
				counters[i].saved.high);
		}
	}
}

static void nmi_cpu_shutdown(void *dummy)
{
	unsigned int v;
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);

	/* restoring APIC_LVTPC can trigger an apic error because the delivery
	 * mode and vector nr combination can be illegal. That's by design: on
	 * power on apic lvt contain a zero vector nr which are legal only for
	 * NMI delivery mode. So inhibit apic err before restoring lvtpc
	 */
	v = apic_read(APIC_LVTERR);
	apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
	apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
	apic_write(APIC_LVTERR, v);
	nmi_restore_registers(msrs);
}

static void nmi_shutdown(void)
{
	struct op_msrs *msrs = &get_cpu_var(cpu_msrs);
	nmi_enabled = 0;
	on_each_cpu(nmi_cpu_shutdown, NULL, 1);
	unregister_die_notifier(&profile_exceptions_nb);
	model->shutdown(msrs);
	free_msrs();
	put_cpu_var(cpu_msrs);
}

static void nmi_cpu_start(void *dummy)
{
	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
	model->start(msrs);
}

static int nmi_start(void)
{
	on_each_cpu(nmi_cpu_start, NULL, 1);
	return 0;
}

static void nmi_cpu_stop(void *dummy)
{
	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
	model->stop(msrs);
}

static void nmi_stop(void)
{
	on_each_cpu(nmi_cpu_stop, NULL, 1);
}

struct op_counter_config counter_config[OP_MAX_COUNTER];

static int nmi_create_files(struct super_block *sb, struct dentry *root)
{
	unsigned int i;

	for (i = 0; i < model->num_counters; ++i) {
		struct dentry *dir;
		char buf[4];

		/* quick little hack to _not_ expose a counter if it is not
		 * available for use.  This should protect userspace app.
		 * NOTE:  assumes 1:1 mapping here (that counters are organized
		 *        sequentially in their struct assignment).
		 */
		if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
			continue;

		snprintf(buf,  sizeof(buf), "%d", i);
		dir = oprofilefs_mkdir(sb, root, buf);
		oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
		oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
		oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
		oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
		oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
		oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
	}

	return 0;
}

static int p4force;
module_param(p4force, int, 0);

static int __init p4_init(char **cpu_type)
{
	__u8 cpu_model = boot_cpu_data.x86_model;

	if (!p4force && (cpu_model > 6 || cpu_model == 5))
		return 0;

#ifndef CONFIG_SMP
	*cpu_type = "i386/p4";
	model = &op_p4_spec;
	return 1;
#else
	switch (smp_num_siblings) {
	case 1:
		*cpu_type = "i386/p4";
		model = &op_p4_spec;
		return 1;

	case 2:
		*cpu_type = "i386/p4-ht";
		model = &op_p4_ht2_spec;
		return 1;
	}
#endif

	printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
	printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
	return 0;
}

static int __init ppro_init(char **cpu_type)
{
	__u8 cpu_model = boot_cpu_data.x86_model;

	switch (cpu_model) {
	case 0 ... 2:
		*cpu_type = "i386/ppro";
		break;
	case 3 ... 5:
		*cpu_type = "i386/pii";
		break;
	case 6 ... 8:
		*cpu_type = "i386/piii";
		break;
	case 9:
		*cpu_type = "i386/p6_mobile";
		break;
	case 10 ... 13:
		*cpu_type = "i386/p6";
		break;
	case 14:
		*cpu_type = "i386/core";
		break;
	case 15: case 23:
		*cpu_type = "i386/core_2";
		break;
	case 26:
		*cpu_type = "i386/core_2";
		break;
	default:
		/* Unknown */
		return 0;
	}

	model = &op_ppro_spec;
	return 1;
}

/* in order to get sysfs right */
static int using_nmi;

int __init op_nmi_init(struct oprofile_operations *ops)
{
	__u8 vendor = boot_cpu_data.x86_vendor;
	__u8 family = boot_cpu_data.x86;
	char *cpu_type;

	if (!cpu_has_apic)
		return -ENODEV;

	switch (vendor) {
	case X86_VENDOR_AMD:
		/* Needs to be at least an Athlon (or hammer in 32bit mode) */

		switch (family) {
		default:
			return -ENODEV;
		case 6:
			model = &op_athlon_spec;
			cpu_type = "i386/athlon";
			break;
		case 0xf:
			model = &op_athlon_spec;
			/* Actually it could be i386/hammer too, but give
			 user space an consistent name. */
			cpu_type = "x86-64/hammer";
			break;
		case 0x10:
			model = &op_athlon_spec;
			cpu_type = "x86-64/family10";
			break;
		}
		break;

	case X86_VENDOR_INTEL:
		switch (family) {
			/* Pentium IV */
		case 0xf:
			if (!p4_init(&cpu_type))
				return -ENODEV;
			break;

			/* A P6-class processor */
		case 6:
			if (!ppro_init(&cpu_type))
				return -ENODEV;
			break;

		default:
			return -ENODEV;
		}
		break;

	default:
		return -ENODEV;
	}

	init_sysfs();
#ifdef CONFIG_SMP
	register_cpu_notifier(&oprofile_cpu_nb);
#endif
	using_nmi = 1;
	ops->create_files = nmi_create_files;
	ops->setup = nmi_setup;
	ops->shutdown = nmi_shutdown;
	ops->start = nmi_start;
	ops->stop = nmi_stop;
	ops->cpu_type = cpu_type;
	printk(KERN_INFO "oprofile: using NMI interrupt.\n");
	return 0;
}

void op_nmi_exit(void)
{
	if (using_nmi) {
		exit_sysfs();
#ifdef CONFIG_SMP
		unregister_cpu_notifier(&oprofile_cpu_nb);
#endif
	}
}
Commit	Line	Data
1da177e4 LT	1	/**
	2	* @file nmi_int.c
	3	*
	4	* @remark Copyright 2002 OProfile authors
	5	* @remark Read the file COPYING
	6	*
	7	* @author John Levon <levon@movementarian.org>
	8	*/
	9
	10	#include <linux/init.h>
	11	#include <linux/notifier.h>
	12	#include <linux/smp.h>
	13	#include <linux/oprofile.h>
	14	#include <linux/sysdev.h>
	15	#include <linux/slab.h>
1cfcea1b	16	#include <linux/moduleparam.h>
1eeb66a1	17	#include <linux/kdebug.h>
80a8c9ff	18	#include <linux/cpu.h>
1da177e4 LT	19	#include <asm/nmi.h>
	20	#include <asm/msr.h>
	21	#include <asm/apic.h>
b75f53db	22
1da177e4 LT	23	#include "op_counter.h"
1da177e4 LT	24	#include "op_x86_model.h"
2fbe7b25	25
b75f53db	26	static struct op_x86_model_spec const *model;
d18d00f5 MT	27	static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
d18d00f5 MT	28	static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
2fbe7b25	29
1da177e4 LT	30	static int nmi_start(void);
1da177e4 LT	31	static void nmi_stop(void);
80a8c9ff AK	32	static void nmi_cpu_start(void *dummy);
80a8c9ff AK	33	static void nmi_cpu_stop(void *dummy);
1da177e4 LT	34
	35	/* 0 == registered but off, 1 == registered and on */
	36	static int nmi_enabled = 0;
	37
80a8c9ff AK	38	#ifdef CONFIG_SMP
	39	static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
	40	void *data)
	41	{
	42	int cpu = (unsigned long)data;
	43	switch (action) {
	44	case CPU_DOWN_FAILED:
	45	case CPU_ONLINE:
	46	smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
	47	break;
	48	case CPU_DOWN_PREPARE:
	49	smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
	50	break;
	51	}
	52	return NOTIFY_DONE;
	53	}
	54
	55	static struct notifier_block oprofile_cpu_nb = {
	56	.notifier_call = oprofile_cpu_notifier
	57	};
	58	#endif
	59
1da177e4 LT	60	#ifdef CONFIG_PM
1da177e4 LT	61
438510f6	62	static int nmi_suspend(struct sys_device *dev, pm_message_t state)
1da177e4	63	{
80a8c9ff	64	/* Only one CPU left, just stop that one */
1da177e4	65	if (nmi_enabled == 1)
80a8c9ff	66	nmi_cpu_stop(NULL);
1da177e4 LT	67	return 0;
	68	}
	69
1da177e4 LT	70	static int nmi_resume(struct sys_device *dev)
	71	{
	72	if (nmi_enabled == 1)
80a8c9ff	73	nmi_cpu_start(NULL);
1da177e4 LT	74	return 0;
	75	}
	76
1da177e4	77	static struct sysdev_class oprofile_sysclass = {
af5ca3f4	78	.name = "oprofile",
1da177e4 LT	79	.resume = nmi_resume,
	80	.suspend = nmi_suspend,
	81	};
	82
1da177e4 LT	83	static struct sys_device device_oprofile = {
	84	.id = 0,
	85	.cls = &oprofile_sysclass,
	86	};
	87
405ae7d3	88	static int __init init_sysfs(void)
1da177e4 LT	89	{
1da177e4 LT	90	int error;
b75f53db CM	91
	92	error = sysdev_class_register(&oprofile_sysclass);
	93	if (!error)
1da177e4 LT	94	error = sysdev_register(&device_oprofile);
	95	return error;
	96	}
	97
405ae7d3	98	static void exit_sysfs(void)
1da177e4 LT	99	{
	100	sysdev_unregister(&device_oprofile);
	101	sysdev_class_unregister(&oprofile_sysclass);
	102	}
	103
	104	#else
405ae7d3 RD	105	#define init_sysfs() do { } while (0)
405ae7d3 RD	106	#define exit_sysfs() do { } while (0)
1da177e4 LT	107	#endif /* CONFIG_PM */
1da177e4 LT	108
c7c19f8e AB	109	static int profile_exceptions_notify(struct notifier_block *self,
c7c19f8e AB	110	unsigned long val, void *data)
1da177e4	111	{
2fbe7b25 DZ	112	struct die_args args = (struct die_args )data;
	113	int ret = NOTIFY_DONE;
	114	int cpu = smp_processor_id();
	115
b75f53db	116	switch (val) {
2fbe7b25	117	case DIE_NMI:
d18d00f5	118	if (model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu)))
2fbe7b25 DZ	119	ret = NOTIFY_STOP;
	120	break;
	121	default:
	122	break;
	123	}
	124	return ret;
1da177e4	125	}
2fbe7b25	126
b75f53db	127	static void nmi_cpu_save_registers(struct op_msrs *msrs)
1da177e4 LT	128	{
1da177e4 LT	129	unsigned int const nr_ctrs = model->num_counters;
b75f53db CM	130	unsigned int const nr_ctrls = model->num_controls;
	131	struct op_msr *counters = msrs->counters;
	132	struct op_msr *controls = msrs->controls;
1da177e4 LT	133	unsigned int i;
	134
	135	for (i = 0; i < nr_ctrs; ++i) {
b75f53db	136	if (counters[i].addr) {
cb9c448c DZ	137	rdmsr(counters[i].addr,
	138	counters[i].saved.low,
	139	counters[i].saved.high);
	140	}
1da177e4	141	}
b75f53db	142
1da177e4	143	for (i = 0; i < nr_ctrls; ++i) {
b75f53db	144	if (controls[i].addr) {
cb9c448c DZ	145	rdmsr(controls[i].addr,
	146	controls[i].saved.low,
	147	controls[i].saved.high);
	148	}
1da177e4 LT	149	}
	150	}
	151
b75f53db	152	static void nmi_save_registers(void *dummy)
1da177e4 LT	153	{
1da177e4 LT	154	int cpu = smp_processor_id();
d18d00f5	155	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
1da177e4 LT	156	nmi_cpu_save_registers(msrs);
	157	}
	158
1da177e4 LT	159	static void free_msrs(void)
	160	{
	161	int i;
c8912599	162	for_each_possible_cpu(i) {
d18d00f5 MT	163	kfree(per_cpu(cpu_msrs, i).counters);
	164	per_cpu(cpu_msrs, i).counters = NULL;
	165	kfree(per_cpu(cpu_msrs, i).controls);
	166	per_cpu(cpu_msrs, i).controls = NULL;
1da177e4 LT	167	}
	168	}
	169
1da177e4 LT	170	static int allocate_msrs(void)
	171	{
	172	int success = 1;
	173	size_t controls_size = sizeof(struct op_msr) * model->num_controls;
	174	size_t counters_size = sizeof(struct op_msr) * model->num_counters;
	175
	176	int i;
0939c17c	177	for_each_possible_cpu(i) {
d18d00f5 MT	178	per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
	179	GFP_KERNEL);
	180	if (!per_cpu(cpu_msrs, i).counters) {
1da177e4 LT	181	success = 0;
	182	break;
	183	}
d18d00f5 MT	184	per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
	185	GFP_KERNEL);
	186	if (!per_cpu(cpu_msrs, i).controls) {
1da177e4 LT	187	success = 0;
	188	break;
	189	}
	190	}
	191
	192	if (!success)
	193	free_msrs();
	194
	195	return success;
	196	}
	197
b75f53db	198	static void nmi_cpu_setup(void *dummy)
1da177e4 LT	199	{
1da177e4 LT	200	int cpu = smp_processor_id();
d18d00f5	201	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
1da177e4 LT	202	spin_lock(&oprofilefs_lock);
	203	model->setup_ctrs(msrs);
	204	spin_unlock(&oprofilefs_lock);
d18d00f5	205	per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
1da177e4 LT	206	apic_write(APIC_LVTPC, APIC_DM_NMI);
	207	}
	208
2fbe7b25 DZ	209	static struct notifier_block profile_exceptions_nb = {
	210	.notifier_call = profile_exceptions_notify,
	211	.next = NULL,
	212	.priority = 0
	213	};
1da177e4 LT	214
	215	static int nmi_setup(void)
	216	{
b75f53db	217	int err = 0;
6c977aad	218	int cpu;
2fbe7b25	219
1da177e4 LT	220	if (!allocate_msrs())
	221	return -ENOMEM;
	222
b75f53db CM	223	err = register_die_notifier(&profile_exceptions_nb);
b75f53db CM	224	if (err) {
1da177e4	225	free_msrs();
2fbe7b25	226	return err;
1da177e4	227	}
2fbe7b25	228
1da177e4 LT	229	/* We need to serialize save and setup for HT because the subset
	230	* of msrs are distinct for save and setup operations
	231	*/
6c977aad AK	232
6c977aad AK	233	/* Assume saved/restored counters are the same on all CPUs */
d18d00f5	234	model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
b75f53db	235	for_each_possible_cpu(cpu) {
0939c17c	236	if (cpu != 0) {
d18d00f5 MT	237	memcpy(per_cpu(cpu_msrs, cpu).counters,
d18d00f5 MT	238	per_cpu(cpu_msrs, 0).counters,
0939c17c CW	239	sizeof(struct op_msr) * model->num_counters);
0939c17c CW	240
d18d00f5 MT	241	memcpy(per_cpu(cpu_msrs, cpu).controls,
d18d00f5 MT	242	per_cpu(cpu_msrs, 0).controls,
0939c17c CW	243	sizeof(struct op_msr) * model->num_controls);
	244	}
	245
6c977aad	246	}
15c8b6c1 JA	247	on_each_cpu(nmi_save_registers, NULL, 1);
15c8b6c1 JA	248	on_each_cpu(nmi_cpu_setup, NULL, 1);
1da177e4 LT	249	nmi_enabled = 1;
	250	return 0;
	251	}
	252
b75f53db	253	static void nmi_restore_registers(struct op_msrs *msrs)
1da177e4 LT	254	{
1da177e4 LT	255	unsigned int const nr_ctrs = model->num_counters;
b75f53db CM	256	unsigned int const nr_ctrls = model->num_controls;
	257	struct op_msr *counters = msrs->counters;
	258	struct op_msr *controls = msrs->controls;
1da177e4 LT	259	unsigned int i;
	260
	261	for (i = 0; i < nr_ctrls; ++i) {
b75f53db	262	if (controls[i].addr) {
cb9c448c DZ	263	wrmsr(controls[i].addr,
	264	controls[i].saved.low,
	265	controls[i].saved.high);
	266	}
1da177e4	267	}
b75f53db	268
1da177e4	269	for (i = 0; i < nr_ctrs; ++i) {
b75f53db	270	if (counters[i].addr) {
cb9c448c DZ	271	wrmsr(counters[i].addr,
	272	counters[i].saved.low,
	273	counters[i].saved.high);
	274	}
1da177e4 LT	275	}
1da177e4 LT	276	}
1da177e4	277
b75f53db	278	static void nmi_cpu_shutdown(void *dummy)
1da177e4 LT	279	{
	280	unsigned int v;
	281	int cpu = smp_processor_id();
d18d00f5	282	struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);
b75f53db	283
1da177e4 LT	284	/* restoring APIC_LVTPC can trigger an apic error because the delivery
	285	* mode and vector nr combination can be illegal. That's by design: on
	286	* power on apic lvt contain a zero vector nr which are legal only for
	287	* NMI delivery mode. So inhibit apic err before restoring lvtpc
	288	*/
	289	v = apic_read(APIC_LVTERR);
	290	apic_write(APIC_LVTERR, v \| APIC_LVT_MASKED);
d18d00f5	291	apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
1da177e4 LT	292	apic_write(APIC_LVTERR, v);
	293	nmi_restore_registers(msrs);
	294	}
	295
1da177e4 LT	296	static void nmi_shutdown(void)
1da177e4 LT	297	{
93e1ade5	298	struct op_msrs *msrs = &get_cpu_var(cpu_msrs);
1da177e4	299	nmi_enabled = 0;
15c8b6c1	300	on_each_cpu(nmi_cpu_shutdown, NULL, 1);
2fbe7b25	301	unregister_die_notifier(&profile_exceptions_nb);
d18d00f5	302	model->shutdown(msrs);
1da177e4	303	free_msrs();
93e1ade5	304	put_cpu_var(cpu_msrs);
1da177e4 LT	305	}
1da177e4 LT	306
b75f53db	307	static void nmi_cpu_start(void *dummy)
1da177e4	308	{
d18d00f5	309	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
1da177e4 LT	310	model->start(msrs);
1da177e4 LT	311	}
1da177e4 LT	312
	313	static int nmi_start(void)
	314	{
15c8b6c1	315	on_each_cpu(nmi_cpu_start, NULL, 1);
1da177e4 LT	316	return 0;
1da177e4 LT	317	}
b75f53db CM	318
b75f53db CM	319	static void nmi_cpu_stop(void *dummy)
1da177e4	320	{
d18d00f5	321	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
1da177e4 LT	322	model->stop(msrs);
1da177e4 LT	323	}
b75f53db	324
1da177e4 LT	325	static void nmi_stop(void)
1da177e4 LT	326	{
15c8b6c1	327	on_each_cpu(nmi_cpu_stop, NULL, 1);
1da177e4 LT	328	}
1da177e4 LT	329
1da177e4 LT	330	struct op_counter_config counter_config[OP_MAX_COUNTER];
1da177e4 LT	331
b75f53db	332	static int nmi_create_files(struct super_block sb, struct dentry root)
1da177e4 LT	333	{
	334	unsigned int i;
	335
	336	for (i = 0; i < model->num_counters; ++i) {
b75f53db	337	struct dentry *dir;
0c6856f7	338	char buf[4];
b75f53db CM	339
b75f53db CM	340	/* quick little hack to _not_ expose a counter if it is not
cb9c448c DZ	341	* available for use. This should protect userspace app.
	342	* NOTE: assumes 1:1 mapping here (that counters are organized
	343	* sequentially in their struct assignment).
	344	*/
	345	if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
	346	continue;
	347
0c6856f7	348	snprintf(buf, sizeof(buf), "%d", i);
1da177e4	349	dir = oprofilefs_mkdir(sb, root, buf);
b75f53db CM	350	oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
	351	oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
	352	oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
	353	oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
	354	oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
	355	oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
1da177e4 LT	356	}
	357
	358	return 0;
	359	}
b75f53db	360
1cfcea1b AK	361	static int p4force;
1cfcea1b AK	362	module_param(p4force, int, 0);
b75f53db CM	363
b75f53db CM	364	static int __init p4_init(char **cpu_type)
1da177e4 LT	365	{
	366	__u8 cpu_model = boot_cpu_data.x86_model;
	367
1cfcea1b	368	if (!p4force && (cpu_model > 6 \|\| cpu_model == 5))
1da177e4 LT	369	return 0;
	370
	371	#ifndef CONFIG_SMP
	372	*cpu_type = "i386/p4";
	373	model = &op_p4_spec;
	374	return 1;
	375	#else
	376	switch (smp_num_siblings) {
b75f53db CM	377	case 1:
	378	*cpu_type = "i386/p4";
	379	model = &op_p4_spec;
	380	return 1;
	381
	382	case 2:
	383	*cpu_type = "i386/p4-ht";
	384	model = &op_p4_ht2_spec;
	385	return 1;
1da177e4 LT	386	}
	387	#endif
	388
	389	printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
	390	printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
	391	return 0;
	392	}
	393
b75f53db	394	static int __init ppro_init(char **cpu_type)
1da177e4 LT	395	{
	396	__u8 cpu_model = boot_cpu_data.x86_model;
	397
4b9f12a3 LT	398	switch (cpu_model) {
	399	case 0 ... 2:
	400	*cpu_type = "i386/ppro";
	401	break;
	402	case 3 ... 5:
	403	*cpu_type = "i386/pii";
	404	break;
	405	case 6 ... 8:
	406	*cpu_type = "i386/piii";
	407	break;
	408	case 9:
	409	*cpu_type = "i386/p6_mobile";
	410	break;
	411	case 10 ... 13:
	412	*cpu_type = "i386/p6";
	413	break;
	414	case 14:
64471ebe	415	*cpu_type = "i386/core";
4b9f12a3 LT	416	break;
	417	case 15: case 23:
	418	*cpu_type = "i386/core_2";
	419	break;
	420	case 26:
f04b92e9	421	*cpu_type = "i386/core_2";
4b9f12a3 LT	422	break;
	423	default:
	424	/* Unknown */
1da177e4	425	return 0;
1da177e4 LT	426	}
	427
	428	model = &op_ppro_spec;
	429	return 1;
	430	}
	431
405ae7d3	432	/* in order to get sysfs right */
1da177e4 LT	433	static int using_nmi;
1da177e4 LT	434
96d0821c	435	int __init op_nmi_init(struct oprofile_operations *ops)
1da177e4 LT	436	{
	437	__u8 vendor = boot_cpu_data.x86_vendor;
	438	__u8 family = boot_cpu_data.x86;
	439	char *cpu_type;
	440
	441	if (!cpu_has_apic)
	442	return -ENODEV;
b75f53db	443
1da177e4	444	switch (vendor) {
b75f53db CM	445	case X86_VENDOR_AMD:
b75f53db CM	446	/* Needs to be at least an Athlon (or hammer in 32bit mode) */
1da177e4	447
b75f53db CM	448	switch (family) {
	449	default:
	450	return -ENODEV;
	451	case 6:
	452	model = &op_athlon_spec;
	453	cpu_type = "i386/athlon";
	454	break;
	455	case 0xf:
	456	model = &op_athlon_spec;
	457	/* Actually it could be i386/hammer too, but give
	458	user space an consistent name. */
	459	cpu_type = "x86-64/hammer";
	460	break;
	461	case 0x10:
	462	model = &op_athlon_spec;
	463	cpu_type = "x86-64/family10";
	464	break;
	465	}
	466	break;
	467
	468	case X86_VENDOR_INTEL:
	469	switch (family) {
	470	/* Pentium IV */
	471	case 0xf:
	472	if (!p4_init(&cpu_type))
1da177e4	473	return -ENODEV;
1da177e4	474	break;
b75f53db CM	475
	476	/* A P6-class processor */
	477	case 6:
	478	if (!ppro_init(&cpu_type))
	479	return -ENODEV;
1da177e4 LT	480	break;
	481
	482	default:
	483	return -ENODEV;
b75f53db CM	484	}
	485	break;
	486
	487	default:
	488	return -ENODEV;
1da177e4 LT	489	}
1da177e4 LT	490
405ae7d3	491	init_sysfs();
80a8c9ff AK	492	#ifdef CONFIG_SMP
	493	register_cpu_notifier(&oprofile_cpu_nb);
	494	#endif
1da177e4 LT	495	using_nmi = 1;
	496	ops->create_files = nmi_create_files;
	497	ops->setup = nmi_setup;
	498	ops->shutdown = nmi_shutdown;
	499	ops->start = nmi_start;
	500	ops->stop = nmi_stop;
	501	ops->cpu_type = cpu_type;
	502	printk(KERN_INFO "oprofile: using NMI interrupt.\n");
	503	return 0;
	504	}
	505
96d0821c	506	void op_nmi_exit(void)
1da177e4	507	{
80a8c9ff	508	if (using_nmi) {
405ae7d3	509	exit_sysfs();
80a8c9ff AK	510	#ifdef CONFIG_SMP
	511	unregister_cpu_notifier(&oprofile_cpu_nb);
	512	#endif
	513	}
1da177e4	514	}