Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /** |
2 | * @file nmi_int.c | |
3 | * | |
4d4036e0 | 4 | * @remark Copyright 2002-2009 OProfile authors |
1da177e4 LT |
5 | * @remark Read the file COPYING |
6 | * | |
7 | * @author John Levon <levon@movementarian.org> | |
adf5ec0b | 8 | * @author Robert Richter <robert.richter@amd.com> |
4d4036e0 JY |
9 | * @author Barry Kasindorf <barry.kasindorf@amd.com> |
10 | * @author Jason Yeh <jason.yeh@amd.com> | |
11 | * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | |
1da177e4 LT |
12 | */ |
13 | ||
14 | #include <linux/init.h> | |
15 | #include <linux/notifier.h> | |
16 | #include <linux/smp.h> | |
17 | #include <linux/oprofile.h> | |
18 | #include <linux/sysdev.h> | |
19 | #include <linux/slab.h> | |
1cfcea1b | 20 | #include <linux/moduleparam.h> |
1eeb66a1 | 21 | #include <linux/kdebug.h> |
80a8c9ff | 22 | #include <linux/cpu.h> |
1da177e4 LT |
23 | #include <asm/nmi.h> |
24 | #include <asm/msr.h> | |
25 | #include <asm/apic.h> | |
b75f53db | 26 | |
1da177e4 LT |
27 | #include "op_counter.h" |
28 | #include "op_x86_model.h" | |
2fbe7b25 | 29 | |
259a83a8 | 30 | static struct op_x86_model_spec *model; |
d18d00f5 MT |
31 | static DEFINE_PER_CPU(struct op_msrs, cpu_msrs); |
32 | static DEFINE_PER_CPU(unsigned long, saved_lvtpc); | |
2fbe7b25 | 33 | |
6ae56b55 RR |
34 | /* must be protected with get_online_cpus()/put_online_cpus(): */ |
35 | static int nmi_enabled; | |
36 | static int ctr_running; | |
1da177e4 | 37 | |
4d4036e0 JY |
38 | struct op_counter_config counter_config[OP_MAX_COUNTER]; |
39 | ||
3370d358 RR |
40 | /* common functions */ |
41 | ||
42 | u64 op_x86_get_ctrl(struct op_x86_model_spec const *model, | |
43 | struct op_counter_config *counter_config) | |
44 | { | |
45 | u64 val = 0; | |
46 | u16 event = (u16)counter_config->event; | |
47 | ||
48 | val |= ARCH_PERFMON_EVENTSEL_INT; | |
49 | val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0; | |
50 | val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0; | |
51 | val |= (counter_config->unit_mask & 0xFF) << 8; | |
914a76ca AK |
52 | counter_config->extra &= (ARCH_PERFMON_EVENTSEL_INV | |
53 | ARCH_PERFMON_EVENTSEL_EDGE | | |
54 | ARCH_PERFMON_EVENTSEL_CMASK); | |
55 | val |= counter_config->extra; | |
3370d358 RR |
56 | event &= model->event_mask ? model->event_mask : 0xFF; |
57 | val |= event & 0xFF; | |
58 | val |= (event & 0x0F00) << 24; | |
59 | ||
60 | return val; | |
61 | } | |
62 | ||
63 | ||
c7c19f8e AB |
64 | static int profile_exceptions_notify(struct notifier_block *self, |
65 | unsigned long val, void *data) | |
1da177e4 | 66 | { |
2fbe7b25 DZ |
67 | struct die_args *args = (struct die_args *)data; |
68 | int ret = NOTIFY_DONE; | |
2fbe7b25 | 69 | |
b75f53db | 70 | switch (val) { |
2fbe7b25 | 71 | case DIE_NMI: |
de654649 RR |
72 | if (ctr_running) |
73 | model->check_ctrs(args->regs, &__get_cpu_var(cpu_msrs)); | |
74 | else if (!nmi_enabled) | |
75 | break; | |
76 | else | |
77 | model->stop(&__get_cpu_var(cpu_msrs)); | |
5b75af0a | 78 | ret = NOTIFY_STOP; |
2fbe7b25 DZ |
79 | break; |
80 | default: | |
81 | break; | |
82 | } | |
83 | return ret; | |
1da177e4 | 84 | } |
2fbe7b25 | 85 | |
b75f53db | 86 | static void nmi_cpu_save_registers(struct op_msrs *msrs) |
1da177e4 | 87 | { |
b75f53db CM |
88 | struct op_msr *counters = msrs->counters; |
89 | struct op_msr *controls = msrs->controls; | |
1da177e4 LT |
90 | unsigned int i; |
91 | ||
1a245c45 | 92 | for (i = 0; i < model->num_counters; ++i) { |
95e74e62 RR |
93 | if (counters[i].addr) |
94 | rdmsrl(counters[i].addr, counters[i].saved); | |
1da177e4 | 95 | } |
b75f53db | 96 | |
1a245c45 | 97 | for (i = 0; i < model->num_controls; ++i) { |
95e74e62 RR |
98 | if (controls[i].addr) |
99 | rdmsrl(controls[i].addr, controls[i].saved); | |
1da177e4 LT |
100 | } |
101 | } | |
102 | ||
b28d1b92 RR |
103 | static void nmi_cpu_start(void *dummy) |
104 | { | |
105 | struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs); | |
2623a1d5 RR |
106 | if (!msrs->controls) |
107 | WARN_ON_ONCE(1); | |
108 | else | |
109 | model->start(msrs); | |
b28d1b92 RR |
110 | } |
111 | ||
112 | static int nmi_start(void) | |
113 | { | |
6ae56b55 | 114 | get_online_cpus(); |
b28d1b92 | 115 | on_each_cpu(nmi_cpu_start, NULL, 1); |
6ae56b55 RR |
116 | ctr_running = 1; |
117 | put_online_cpus(); | |
b28d1b92 RR |
118 | return 0; |
119 | } | |
120 | ||
121 | static void nmi_cpu_stop(void *dummy) | |
122 | { | |
123 | struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs); | |
2623a1d5 RR |
124 | if (!msrs->controls) |
125 | WARN_ON_ONCE(1); | |
126 | else | |
127 | model->stop(msrs); | |
b28d1b92 RR |
128 | } |
129 | ||
130 | static void nmi_stop(void) | |
131 | { | |
6ae56b55 | 132 | get_online_cpus(); |
b28d1b92 | 133 | on_each_cpu(nmi_cpu_stop, NULL, 1); |
6ae56b55 RR |
134 | ctr_running = 0; |
135 | put_online_cpus(); | |
b28d1b92 RR |
136 | } |
137 | ||
d8471ad3 RR |
138 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX |
139 | ||
140 | static DEFINE_PER_CPU(int, switch_index); | |
141 | ||
39e97f40 RR |
142 | static inline int has_mux(void) |
143 | { | |
144 | return !!model->switch_ctrl; | |
145 | } | |
146 | ||
d8471ad3 RR |
147 | inline int op_x86_phys_to_virt(int phys) |
148 | { | |
0a3aee0d | 149 | return __this_cpu_read(switch_index) + phys; |
d8471ad3 RR |
150 | } |
151 | ||
61d149d5 RR |
152 | inline int op_x86_virt_to_phys(int virt) |
153 | { | |
154 | return virt % model->num_counters; | |
155 | } | |
156 | ||
6ab82f95 RR |
157 | static void nmi_shutdown_mux(void) |
158 | { | |
159 | int i; | |
39e97f40 RR |
160 | |
161 | if (!has_mux()) | |
162 | return; | |
163 | ||
6ab82f95 RR |
164 | for_each_possible_cpu(i) { |
165 | kfree(per_cpu(cpu_msrs, i).multiplex); | |
166 | per_cpu(cpu_msrs, i).multiplex = NULL; | |
167 | per_cpu(switch_index, i) = 0; | |
168 | } | |
169 | } | |
170 | ||
171 | static int nmi_setup_mux(void) | |
172 | { | |
173 | size_t multiplex_size = | |
174 | sizeof(struct op_msr) * model->num_virt_counters; | |
175 | int i; | |
39e97f40 RR |
176 | |
177 | if (!has_mux()) | |
178 | return 1; | |
179 | ||
6ab82f95 RR |
180 | for_each_possible_cpu(i) { |
181 | per_cpu(cpu_msrs, i).multiplex = | |
c17c8fbf | 182 | kzalloc(multiplex_size, GFP_KERNEL); |
6ab82f95 RR |
183 | if (!per_cpu(cpu_msrs, i).multiplex) |
184 | return 0; | |
185 | } | |
39e97f40 | 186 | |
6ab82f95 RR |
187 | return 1; |
188 | } | |
189 | ||
48fb4b46 RR |
190 | static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) |
191 | { | |
192 | int i; | |
193 | struct op_msr *multiplex = msrs->multiplex; | |
194 | ||
39e97f40 RR |
195 | if (!has_mux()) |
196 | return; | |
197 | ||
48fb4b46 RR |
198 | for (i = 0; i < model->num_virt_counters; ++i) { |
199 | if (counter_config[i].enabled) { | |
200 | multiplex[i].saved = -(u64)counter_config[i].count; | |
201 | } else { | |
48fb4b46 RR |
202 | multiplex[i].saved = 0; |
203 | } | |
204 | } | |
205 | ||
206 | per_cpu(switch_index, cpu) = 0; | |
207 | } | |
208 | ||
d0f585dd RR |
209 | static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs) |
210 | { | |
68dc819c | 211 | struct op_msr *counters = msrs->counters; |
d0f585dd RR |
212 | struct op_msr *multiplex = msrs->multiplex; |
213 | int i; | |
214 | ||
215 | for (i = 0; i < model->num_counters; ++i) { | |
216 | int virt = op_x86_phys_to_virt(i); | |
68dc819c RR |
217 | if (counters[i].addr) |
218 | rdmsrl(counters[i].addr, multiplex[virt].saved); | |
d0f585dd RR |
219 | } |
220 | } | |
221 | ||
222 | static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs) | |
223 | { | |
68dc819c | 224 | struct op_msr *counters = msrs->counters; |
d0f585dd RR |
225 | struct op_msr *multiplex = msrs->multiplex; |
226 | int i; | |
227 | ||
228 | for (i = 0; i < model->num_counters; ++i) { | |
229 | int virt = op_x86_phys_to_virt(i); | |
68dc819c RR |
230 | if (counters[i].addr) |
231 | wrmsrl(counters[i].addr, multiplex[virt].saved); | |
d0f585dd RR |
232 | } |
233 | } | |
234 | ||
b28d1b92 RR |
235 | static void nmi_cpu_switch(void *dummy) |
236 | { | |
237 | int cpu = smp_processor_id(); | |
238 | int si = per_cpu(switch_index, cpu); | |
239 | struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu); | |
240 | ||
241 | nmi_cpu_stop(NULL); | |
242 | nmi_cpu_save_mpx_registers(msrs); | |
243 | ||
244 | /* move to next set */ | |
245 | si += model->num_counters; | |
d8cc108f | 246 | if ((si >= model->num_virt_counters) || (counter_config[si].count == 0)) |
b28d1b92 RR |
247 | per_cpu(switch_index, cpu) = 0; |
248 | else | |
249 | per_cpu(switch_index, cpu) = si; | |
250 | ||
251 | model->switch_ctrl(model, msrs); | |
252 | nmi_cpu_restore_mpx_registers(msrs); | |
253 | ||
254 | nmi_cpu_start(NULL); | |
255 | } | |
256 | ||
257 | ||
258 | /* | |
259 | * Quick check to see if multiplexing is necessary. | |
260 | * The check should be sufficient since counters are used | |
261 | * in ordre. | |
262 | */ | |
263 | static int nmi_multiplex_on(void) | |
264 | { | |
265 | return counter_config[model->num_counters].count ? 0 : -EINVAL; | |
266 | } | |
267 | ||
268 | static int nmi_switch_event(void) | |
269 | { | |
39e97f40 | 270 | if (!has_mux()) |
b28d1b92 RR |
271 | return -ENOSYS; /* not implemented */ |
272 | if (nmi_multiplex_on() < 0) | |
273 | return -EINVAL; /* not necessary */ | |
274 | ||
6ae56b55 RR |
275 | get_online_cpus(); |
276 | if (ctr_running) | |
277 | on_each_cpu(nmi_cpu_switch, NULL, 1); | |
278 | put_online_cpus(); | |
b28d1b92 | 279 | |
b28d1b92 RR |
280 | return 0; |
281 | } | |
282 | ||
52805144 RR |
283 | static inline void mux_init(struct oprofile_operations *ops) |
284 | { | |
285 | if (has_mux()) | |
286 | ops->switch_events = nmi_switch_event; | |
287 | } | |
288 | ||
4d015f79 RR |
289 | static void mux_clone(int cpu) |
290 | { | |
291 | if (!has_mux()) | |
292 | return; | |
293 | ||
294 | memcpy(per_cpu(cpu_msrs, cpu).multiplex, | |
295 | per_cpu(cpu_msrs, 0).multiplex, | |
296 | sizeof(struct op_msr) * model->num_virt_counters); | |
297 | } | |
298 | ||
d8471ad3 RR |
299 | #else |
300 | ||
301 | inline int op_x86_phys_to_virt(int phys) { return phys; } | |
61d149d5 | 302 | inline int op_x86_virt_to_phys(int virt) { return virt; } |
6ab82f95 RR |
303 | static inline void nmi_shutdown_mux(void) { } |
304 | static inline int nmi_setup_mux(void) { return 1; } | |
48fb4b46 RR |
305 | static inline void |
306 | nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { } | |
52805144 | 307 | static inline void mux_init(struct oprofile_operations *ops) { } |
4d015f79 | 308 | static void mux_clone(int cpu) { } |
d8471ad3 RR |
309 | |
310 | #endif | |
311 | ||
1da177e4 LT |
312 | static void free_msrs(void) |
313 | { | |
314 | int i; | |
c8912599 | 315 | for_each_possible_cpu(i) { |
d18d00f5 MT |
316 | kfree(per_cpu(cpu_msrs, i).counters); |
317 | per_cpu(cpu_msrs, i).counters = NULL; | |
318 | kfree(per_cpu(cpu_msrs, i).controls); | |
319 | per_cpu(cpu_msrs, i).controls = NULL; | |
1da177e4 | 320 | } |
8f5a2dd8 | 321 | nmi_shutdown_mux(); |
1da177e4 LT |
322 | } |
323 | ||
1da177e4 LT |
324 | static int allocate_msrs(void) |
325 | { | |
1da177e4 LT |
326 | size_t controls_size = sizeof(struct op_msr) * model->num_controls; |
327 | size_t counters_size = sizeof(struct op_msr) * model->num_counters; | |
328 | ||
4c168eaf | 329 | int i; |
0939c17c | 330 | for_each_possible_cpu(i) { |
c17c8fbf | 331 | per_cpu(cpu_msrs, i).counters = kzalloc(counters_size, |
6ab82f95 RR |
332 | GFP_KERNEL); |
333 | if (!per_cpu(cpu_msrs, i).counters) | |
8f5a2dd8 | 334 | goto fail; |
c17c8fbf | 335 | per_cpu(cpu_msrs, i).controls = kzalloc(controls_size, |
6ab82f95 RR |
336 | GFP_KERNEL); |
337 | if (!per_cpu(cpu_msrs, i).controls) | |
8f5a2dd8 | 338 | goto fail; |
1da177e4 LT |
339 | } |
340 | ||
8f5a2dd8 RR |
341 | if (!nmi_setup_mux()) |
342 | goto fail; | |
343 | ||
6ab82f95 | 344 | return 1; |
8f5a2dd8 RR |
345 | |
346 | fail: | |
347 | free_msrs(); | |
348 | return 0; | |
1da177e4 LT |
349 | } |
350 | ||
b75f53db | 351 | static void nmi_cpu_setup(void *dummy) |
1da177e4 LT |
352 | { |
353 | int cpu = smp_processor_id(); | |
d18d00f5 | 354 | struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu); |
44ab9a6b | 355 | nmi_cpu_save_registers(msrs); |
1da177e4 | 356 | spin_lock(&oprofilefs_lock); |
ef8828dd | 357 | model->setup_ctrs(model, msrs); |
6bfccd09 | 358 | nmi_cpu_setup_mux(cpu, msrs); |
1da177e4 | 359 | spin_unlock(&oprofilefs_lock); |
d18d00f5 | 360 | per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC); |
1da177e4 LT |
361 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
362 | } | |
363 | ||
2fbe7b25 DZ |
364 | static struct notifier_block profile_exceptions_nb = { |
365 | .notifier_call = profile_exceptions_notify, | |
366 | .next = NULL, | |
166d7514 | 367 | .priority = NMI_LOCAL_LOW_PRIOR, |
2fbe7b25 | 368 | }; |
1da177e4 | 369 | |
44ab9a6b | 370 | static void nmi_cpu_restore_registers(struct op_msrs *msrs) |
1da177e4 | 371 | { |
b75f53db CM |
372 | struct op_msr *counters = msrs->counters; |
373 | struct op_msr *controls = msrs->controls; | |
1da177e4 LT |
374 | unsigned int i; |
375 | ||
1a245c45 | 376 | for (i = 0; i < model->num_controls; ++i) { |
95e74e62 RR |
377 | if (controls[i].addr) |
378 | wrmsrl(controls[i].addr, controls[i].saved); | |
1da177e4 | 379 | } |
b75f53db | 380 | |
1a245c45 | 381 | for (i = 0; i < model->num_counters; ++i) { |
95e74e62 RR |
382 | if (counters[i].addr) |
383 | wrmsrl(counters[i].addr, counters[i].saved); | |
1da177e4 LT |
384 | } |
385 | } | |
1da177e4 | 386 | |
b75f53db | 387 | static void nmi_cpu_shutdown(void *dummy) |
1da177e4 LT |
388 | { |
389 | unsigned int v; | |
390 | int cpu = smp_processor_id(); | |
82a22528 | 391 | struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu); |
b75f53db | 392 | |
1da177e4 LT |
393 | /* restoring APIC_LVTPC can trigger an apic error because the delivery |
394 | * mode and vector nr combination can be illegal. That's by design: on | |
395 | * power on apic lvt contain a zero vector nr which are legal only for | |
396 | * NMI delivery mode. So inhibit apic err before restoring lvtpc | |
397 | */ | |
398 | v = apic_read(APIC_LVTERR); | |
399 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
d18d00f5 | 400 | apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu)); |
1da177e4 | 401 | apic_write(APIC_LVTERR, v); |
44ab9a6b | 402 | nmi_cpu_restore_registers(msrs); |
bae663bc RR |
403 | if (model->cpu_down) |
404 | model->cpu_down(); | |
1da177e4 LT |
405 | } |
406 | ||
6ae56b55 RR |
407 | static void nmi_cpu_up(void *dummy) |
408 | { | |
409 | if (nmi_enabled) | |
410 | nmi_cpu_setup(dummy); | |
411 | if (ctr_running) | |
412 | nmi_cpu_start(dummy); | |
413 | } | |
414 | ||
415 | static void nmi_cpu_down(void *dummy) | |
416 | { | |
417 | if (ctr_running) | |
418 | nmi_cpu_stop(dummy); | |
419 | if (nmi_enabled) | |
420 | nmi_cpu_shutdown(dummy); | |
421 | } | |
422 | ||
b75f53db | 423 | static int nmi_create_files(struct super_block *sb, struct dentry *root) |
1da177e4 LT |
424 | { |
425 | unsigned int i; | |
426 | ||
4d4036e0 | 427 | for (i = 0; i < model->num_virt_counters; ++i) { |
b75f53db | 428 | struct dentry *dir; |
0c6856f7 | 429 | char buf[4]; |
b75f53db CM |
430 | |
431 | /* quick little hack to _not_ expose a counter if it is not | |
cb9c448c DZ |
432 | * available for use. This should protect userspace app. |
433 | * NOTE: assumes 1:1 mapping here (that counters are organized | |
434 | * sequentially in their struct assignment). | |
435 | */ | |
11be1a7b | 436 | if (!avail_to_resrv_perfctr_nmi_bit(op_x86_virt_to_phys(i))) |
cb9c448c DZ |
437 | continue; |
438 | ||
0c6856f7 | 439 | snprintf(buf, sizeof(buf), "%d", i); |
1da177e4 | 440 | dir = oprofilefs_mkdir(sb, root, buf); |
b75f53db CM |
441 | oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled); |
442 | oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event); | |
443 | oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count); | |
444 | oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask); | |
445 | oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel); | |
446 | oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user); | |
914a76ca | 447 | oprofilefs_create_ulong(sb, dir, "extra", &counter_config[i].extra); |
1da177e4 LT |
448 | } |
449 | ||
450 | return 0; | |
451 | } | |
b75f53db | 452 | |
69046d43 RR |
453 | static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action, |
454 | void *data) | |
455 | { | |
456 | int cpu = (unsigned long)data; | |
457 | switch (action) { | |
458 | case CPU_DOWN_FAILED: | |
459 | case CPU_ONLINE: | |
6ae56b55 | 460 | smp_call_function_single(cpu, nmi_cpu_up, NULL, 0); |
69046d43 RR |
461 | break; |
462 | case CPU_DOWN_PREPARE: | |
6ae56b55 | 463 | smp_call_function_single(cpu, nmi_cpu_down, NULL, 1); |
69046d43 RR |
464 | break; |
465 | } | |
466 | return NOTIFY_DONE; | |
467 | } | |
468 | ||
469 | static struct notifier_block oprofile_cpu_nb = { | |
470 | .notifier_call = oprofile_cpu_notifier | |
471 | }; | |
69046d43 | 472 | |
d30d64c6 RR |
473 | static int nmi_setup(void) |
474 | { | |
475 | int err = 0; | |
476 | int cpu; | |
477 | ||
478 | if (!allocate_msrs()) | |
479 | return -ENOMEM; | |
480 | ||
481 | /* We need to serialize save and setup for HT because the subset | |
482 | * of msrs are distinct for save and setup operations | |
483 | */ | |
484 | ||
485 | /* Assume saved/restored counters are the same on all CPUs */ | |
486 | err = model->fill_in_addresses(&per_cpu(cpu_msrs, 0)); | |
487 | if (err) | |
488 | goto fail; | |
489 | ||
490 | for_each_possible_cpu(cpu) { | |
491 | if (!cpu) | |
492 | continue; | |
493 | ||
494 | memcpy(per_cpu(cpu_msrs, cpu).counters, | |
495 | per_cpu(cpu_msrs, 0).counters, | |
496 | sizeof(struct op_msr) * model->num_counters); | |
497 | ||
498 | memcpy(per_cpu(cpu_msrs, cpu).controls, | |
499 | per_cpu(cpu_msrs, 0).controls, | |
500 | sizeof(struct op_msr) * model->num_controls); | |
501 | ||
502 | mux_clone(cpu); | |
503 | } | |
504 | ||
505 | nmi_enabled = 0; | |
506 | ctr_running = 0; | |
507 | barrier(); | |
508 | err = register_die_notifier(&profile_exceptions_nb); | |
509 | if (err) | |
510 | goto fail; | |
511 | ||
512 | get_online_cpus(); | |
3de668ee | 513 | register_cpu_notifier(&oprofile_cpu_nb); |
d30d64c6 RR |
514 | on_each_cpu(nmi_cpu_setup, NULL, 1); |
515 | nmi_enabled = 1; | |
516 | put_online_cpus(); | |
517 | ||
518 | return 0; | |
519 | fail: | |
520 | free_msrs(); | |
521 | return err; | |
522 | } | |
523 | ||
524 | static void nmi_shutdown(void) | |
525 | { | |
526 | struct op_msrs *msrs; | |
527 | ||
528 | get_online_cpus(); | |
3de668ee | 529 | unregister_cpu_notifier(&oprofile_cpu_nb); |
d30d64c6 RR |
530 | on_each_cpu(nmi_cpu_shutdown, NULL, 1); |
531 | nmi_enabled = 0; | |
532 | ctr_running = 0; | |
533 | put_online_cpus(); | |
534 | barrier(); | |
535 | unregister_die_notifier(&profile_exceptions_nb); | |
536 | msrs = &get_cpu_var(cpu_msrs); | |
537 | model->shutdown(msrs); | |
538 | free_msrs(); | |
539 | put_cpu_var(cpu_msrs); | |
540 | } | |
541 | ||
69046d43 RR |
542 | #ifdef CONFIG_PM |
543 | ||
544 | static int nmi_suspend(struct sys_device *dev, pm_message_t state) | |
545 | { | |
546 | /* Only one CPU left, just stop that one */ | |
547 | if (nmi_enabled == 1) | |
548 | nmi_cpu_stop(NULL); | |
549 | return 0; | |
550 | } | |
551 | ||
552 | static int nmi_resume(struct sys_device *dev) | |
553 | { | |
554 | if (nmi_enabled == 1) | |
555 | nmi_cpu_start(NULL); | |
556 | return 0; | |
557 | } | |
558 | ||
559 | static struct sysdev_class oprofile_sysclass = { | |
560 | .name = "oprofile", | |
561 | .resume = nmi_resume, | |
562 | .suspend = nmi_suspend, | |
563 | }; | |
564 | ||
565 | static struct sys_device device_oprofile = { | |
566 | .id = 0, | |
567 | .cls = &oprofile_sysclass, | |
568 | }; | |
569 | ||
570 | static int __init init_sysfs(void) | |
571 | { | |
572 | int error; | |
573 | ||
574 | error = sysdev_class_register(&oprofile_sysclass); | |
10f0412f RR |
575 | if (error) |
576 | return error; | |
577 | ||
578 | error = sysdev_register(&device_oprofile); | |
579 | if (error) | |
580 | sysdev_class_unregister(&oprofile_sysclass); | |
581 | ||
69046d43 RR |
582 | return error; |
583 | } | |
584 | ||
585 | static void exit_sysfs(void) | |
586 | { | |
587 | sysdev_unregister(&device_oprofile); | |
588 | sysdev_class_unregister(&oprofile_sysclass); | |
589 | } | |
590 | ||
591 | #else | |
269f45c2 RR |
592 | |
593 | static inline int init_sysfs(void) { return 0; } | |
594 | static inline void exit_sysfs(void) { } | |
595 | ||
69046d43 RR |
596 | #endif /* CONFIG_PM */ |
597 | ||
b75f53db | 598 | static int __init p4_init(char **cpu_type) |
1da177e4 LT |
599 | { |
600 | __u8 cpu_model = boot_cpu_data.x86_model; | |
601 | ||
1f3d7b60 | 602 | if (cpu_model > 6 || cpu_model == 5) |
1da177e4 LT |
603 | return 0; |
604 | ||
605 | #ifndef CONFIG_SMP | |
606 | *cpu_type = "i386/p4"; | |
607 | model = &op_p4_spec; | |
608 | return 1; | |
609 | #else | |
610 | switch (smp_num_siblings) { | |
b75f53db CM |
611 | case 1: |
612 | *cpu_type = "i386/p4"; | |
613 | model = &op_p4_spec; | |
614 | return 1; | |
615 | ||
616 | case 2: | |
617 | *cpu_type = "i386/p4-ht"; | |
618 | model = &op_p4_ht2_spec; | |
619 | return 1; | |
1da177e4 LT |
620 | } |
621 | #endif | |
622 | ||
623 | printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n"); | |
624 | printk(KERN_INFO "oprofile: Reverting to timer mode.\n"); | |
625 | return 0; | |
626 | } | |
627 | ||
7e4e0bd5 RR |
628 | static int force_arch_perfmon; |
629 | static int force_cpu_type(const char *str, struct kernel_param *kp) | |
630 | { | |
8d7ff4f2 | 631 | if (!strcmp(str, "arch_perfmon")) { |
7e4e0bd5 RR |
632 | force_arch_perfmon = 1; |
633 | printk(KERN_INFO "oprofile: forcing architectural perfmon\n"); | |
634 | } | |
635 | ||
636 | return 0; | |
637 | } | |
638 | module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0); | |
1dcdb5a9 | 639 | |
b75f53db | 640 | static int __init ppro_init(char **cpu_type) |
1da177e4 LT |
641 | { |
642 | __u8 cpu_model = boot_cpu_data.x86_model; | |
259a83a8 | 643 | struct op_x86_model_spec *spec = &op_ppro_spec; /* default */ |
1da177e4 | 644 | |
1dcdb5a9 AK |
645 | if (force_arch_perfmon && cpu_has_arch_perfmon) |
646 | return 0; | |
647 | ||
45c34e05 JV |
648 | /* |
649 | * Documentation on identifying Intel processors by CPU family | |
650 | * and model can be found in the Intel Software Developer's | |
651 | * Manuals (SDM): | |
652 | * | |
653 | * http://www.intel.com/products/processor/manuals/ | |
654 | * | |
655 | * As of May 2010 the documentation for this was in the: | |
656 | * "Intel 64 and IA-32 Architectures Software Developer's | |
657 | * Manual Volume 3B: System Programming Guide", "Table B-1 | |
658 | * CPUID Signature Values of DisplayFamily_DisplayModel". | |
659 | */ | |
4b9f12a3 LT |
660 | switch (cpu_model) { |
661 | case 0 ... 2: | |
662 | *cpu_type = "i386/ppro"; | |
663 | break; | |
664 | case 3 ... 5: | |
665 | *cpu_type = "i386/pii"; | |
666 | break; | |
667 | case 6 ... 8: | |
3d337c65 | 668 | case 10 ... 11: |
4b9f12a3 LT |
669 | *cpu_type = "i386/piii"; |
670 | break; | |
671 | case 9: | |
3d337c65 | 672 | case 13: |
4b9f12a3 LT |
673 | *cpu_type = "i386/p6_mobile"; |
674 | break; | |
4b9f12a3 | 675 | case 14: |
64471ebe | 676 | *cpu_type = "i386/core"; |
4b9f12a3 | 677 | break; |
c33f543d PS |
678 | case 0x0f: |
679 | case 0x16: | |
680 | case 0x17: | |
bb7ab785 | 681 | case 0x1d: |
4b9f12a3 LT |
682 | *cpu_type = "i386/core_2"; |
683 | break; | |
45c34e05 | 684 | case 0x1a: |
a7c55cbe | 685 | case 0x1e: |
e83e452b | 686 | case 0x2e: |
802070f5 | 687 | spec = &op_arch_perfmon_spec; |
6adf406f AK |
688 | *cpu_type = "i386/core_i7"; |
689 | break; | |
45c34e05 | 690 | case 0x1c: |
6adf406f AK |
691 | *cpu_type = "i386/atom"; |
692 | break; | |
4b9f12a3 LT |
693 | default: |
694 | /* Unknown */ | |
1da177e4 | 695 | return 0; |
1da177e4 LT |
696 | } |
697 | ||
802070f5 | 698 | model = spec; |
1da177e4 LT |
699 | return 1; |
700 | } | |
701 | ||
96d0821c | 702 | int __init op_nmi_init(struct oprofile_operations *ops) |
1da177e4 LT |
703 | { |
704 | __u8 vendor = boot_cpu_data.x86_vendor; | |
705 | __u8 family = boot_cpu_data.x86; | |
b9917028 | 706 | char *cpu_type = NULL; |
adf5ec0b | 707 | int ret = 0; |
1da177e4 LT |
708 | |
709 | if (!cpu_has_apic) | |
710 | return -ENODEV; | |
b75f53db | 711 | |
1da177e4 | 712 | switch (vendor) { |
b75f53db CM |
713 | case X86_VENDOR_AMD: |
714 | /* Needs to be at least an Athlon (or hammer in 32bit mode) */ | |
1da177e4 | 715 | |
b75f53db | 716 | switch (family) { |
b75f53db | 717 | case 6: |
b75f53db CM |
718 | cpu_type = "i386/athlon"; |
719 | break; | |
720 | case 0xf: | |
d20f24c6 RR |
721 | /* |
722 | * Actually it could be i386/hammer too, but | |
723 | * give user space an consistent name. | |
724 | */ | |
b75f53db CM |
725 | cpu_type = "x86-64/hammer"; |
726 | break; | |
727 | case 0x10: | |
b75f53db CM |
728 | cpu_type = "x86-64/family10"; |
729 | break; | |
12f2b261 | 730 | case 0x11: |
12f2b261 BK |
731 | cpu_type = "x86-64/family11h"; |
732 | break; | |
3acbf084 RR |
733 | case 0x12: |
734 | cpu_type = "x86-64/family12h"; | |
735 | break; | |
e6341474 RR |
736 | case 0x14: |
737 | cpu_type = "x86-64/family14h"; | |
738 | break; | |
30570bce RR |
739 | case 0x15: |
740 | cpu_type = "x86-64/family15h"; | |
741 | break; | |
d20f24c6 RR |
742 | default: |
743 | return -ENODEV; | |
b75f53db | 744 | } |
d20f24c6 | 745 | model = &op_amd_spec; |
b75f53db CM |
746 | break; |
747 | ||
748 | case X86_VENDOR_INTEL: | |
749 | switch (family) { | |
750 | /* Pentium IV */ | |
751 | case 0xf: | |
b9917028 | 752 | p4_init(&cpu_type); |
1da177e4 | 753 | break; |
b75f53db CM |
754 | |
755 | /* A P6-class processor */ | |
756 | case 6: | |
b9917028 | 757 | ppro_init(&cpu_type); |
1da177e4 LT |
758 | break; |
759 | ||
760 | default: | |
b9917028 | 761 | break; |
b75f53db | 762 | } |
b9917028 | 763 | |
e419294e RR |
764 | if (cpu_type) |
765 | break; | |
766 | ||
767 | if (!cpu_has_arch_perfmon) | |
b9917028 | 768 | return -ENODEV; |
e419294e RR |
769 | |
770 | /* use arch perfmon as fallback */ | |
771 | cpu_type = "i386/arch_perfmon"; | |
772 | model = &op_arch_perfmon_spec; | |
b75f53db CM |
773 | break; |
774 | ||
775 | default: | |
776 | return -ENODEV; | |
1da177e4 LT |
777 | } |
778 | ||
270d3e1a | 779 | /* default values, can be overwritten by model */ |
6e63ea4b RR |
780 | ops->create_files = nmi_create_files; |
781 | ops->setup = nmi_setup; | |
782 | ops->shutdown = nmi_shutdown; | |
783 | ops->start = nmi_start; | |
784 | ops->stop = nmi_stop; | |
785 | ops->cpu_type = cpu_type; | |
270d3e1a | 786 | |
adf5ec0b RR |
787 | if (model->init) |
788 | ret = model->init(ops); | |
789 | if (ret) | |
790 | return ret; | |
791 | ||
52471c67 RR |
792 | if (!model->num_virt_counters) |
793 | model->num_virt_counters = model->num_counters; | |
794 | ||
52805144 RR |
795 | mux_init(ops); |
796 | ||
10f0412f RR |
797 | ret = init_sysfs(); |
798 | if (ret) | |
799 | return ret; | |
800 | ||
1da177e4 LT |
801 | printk(KERN_INFO "oprofile: using NMI interrupt.\n"); |
802 | return 0; | |
803 | } | |
804 | ||
96d0821c | 805 | void op_nmi_exit(void) |
1da177e4 | 806 | { |
5140434d | 807 | exit_sysfs(); |
1da177e4 | 808 | } |