Commit | Line | Data |
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1da177e4 LT |
1 | /** |
2 | * @file nmi_int.c | |
3 | * | |
4d4036e0 | 4 | * @remark Copyright 2002-2009 OProfile authors |
1da177e4 LT |
5 | * @remark Read the file COPYING |
6 | * | |
7 | * @author John Levon <levon@movementarian.org> | |
adf5ec0b | 8 | * @author Robert Richter <robert.richter@amd.com> |
4d4036e0 JY |
9 | * @author Barry Kasindorf <barry.kasindorf@amd.com> |
10 | * @author Jason Yeh <jason.yeh@amd.com> | |
11 | * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | |
1da177e4 LT |
12 | */ |
13 | ||
14 | #include <linux/init.h> | |
15 | #include <linux/notifier.h> | |
16 | #include <linux/smp.h> | |
17 | #include <linux/oprofile.h> | |
18 | #include <linux/sysdev.h> | |
19 | #include <linux/slab.h> | |
1cfcea1b | 20 | #include <linux/moduleparam.h> |
1eeb66a1 | 21 | #include <linux/kdebug.h> |
80a8c9ff | 22 | #include <linux/cpu.h> |
1da177e4 LT |
23 | #include <asm/nmi.h> |
24 | #include <asm/msr.h> | |
25 | #include <asm/apic.h> | |
b75f53db | 26 | |
1da177e4 LT |
27 | #include "op_counter.h" |
28 | #include "op_x86_model.h" | |
2fbe7b25 | 29 | |
4d4036e0 JY |
30 | |
31 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX | |
32 | DEFINE_PER_CPU(int, switch_index); | |
33 | #endif | |
34 | ||
35 | ||
b75f53db | 36 | static struct op_x86_model_spec const *model; |
d18d00f5 MT |
37 | static DEFINE_PER_CPU(struct op_msrs, cpu_msrs); |
38 | static DEFINE_PER_CPU(unsigned long, saved_lvtpc); | |
2fbe7b25 | 39 | |
1da177e4 LT |
40 | /* 0 == registered but off, 1 == registered and on */ |
41 | static int nmi_enabled = 0; | |
42 | ||
4d4036e0 JY |
43 | |
44 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX | |
45 | extern atomic_t multiplex_counter; | |
46 | #endif | |
47 | ||
48 | struct op_counter_config counter_config[OP_MAX_COUNTER]; | |
49 | ||
3370d358 RR |
50 | /* common functions */ |
51 | ||
52 | u64 op_x86_get_ctrl(struct op_x86_model_spec const *model, | |
53 | struct op_counter_config *counter_config) | |
54 | { | |
55 | u64 val = 0; | |
56 | u16 event = (u16)counter_config->event; | |
57 | ||
58 | val |= ARCH_PERFMON_EVENTSEL_INT; | |
59 | val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0; | |
60 | val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0; | |
61 | val |= (counter_config->unit_mask & 0xFF) << 8; | |
62 | event &= model->event_mask ? model->event_mask : 0xFF; | |
63 | val |= event & 0xFF; | |
64 | val |= (event & 0x0F00) << 24; | |
65 | ||
66 | return val; | |
67 | } | |
68 | ||
69 | ||
c7c19f8e AB |
70 | static int profile_exceptions_notify(struct notifier_block *self, |
71 | unsigned long val, void *data) | |
1da177e4 | 72 | { |
2fbe7b25 DZ |
73 | struct die_args *args = (struct die_args *)data; |
74 | int ret = NOTIFY_DONE; | |
75 | int cpu = smp_processor_id(); | |
76 | ||
b75f53db | 77 | switch (val) { |
2fbe7b25 | 78 | case DIE_NMI: |
5b75af0a MG |
79 | case DIE_NMI_IPI: |
80 | model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu)); | |
81 | ret = NOTIFY_STOP; | |
2fbe7b25 DZ |
82 | break; |
83 | default: | |
84 | break; | |
85 | } | |
86 | return ret; | |
1da177e4 | 87 | } |
2fbe7b25 | 88 | |
b75f53db | 89 | static void nmi_cpu_save_registers(struct op_msrs *msrs) |
1da177e4 | 90 | { |
b75f53db CM |
91 | struct op_msr *counters = msrs->counters; |
92 | struct op_msr *controls = msrs->controls; | |
1da177e4 LT |
93 | unsigned int i; |
94 | ||
1a245c45 | 95 | for (i = 0; i < model->num_counters; ++i) { |
95e74e62 RR |
96 | if (counters[i].addr) |
97 | rdmsrl(counters[i].addr, counters[i].saved); | |
1da177e4 | 98 | } |
b75f53db | 99 | |
1a245c45 | 100 | for (i = 0; i < model->num_controls; ++i) { |
95e74e62 RR |
101 | if (controls[i].addr) |
102 | rdmsrl(controls[i].addr, controls[i].saved); | |
1da177e4 LT |
103 | } |
104 | } | |
105 | ||
1da177e4 LT |
106 | static void free_msrs(void) |
107 | { | |
108 | int i; | |
c8912599 | 109 | for_each_possible_cpu(i) { |
d18d00f5 MT |
110 | kfree(per_cpu(cpu_msrs, i).counters); |
111 | per_cpu(cpu_msrs, i).counters = NULL; | |
112 | kfree(per_cpu(cpu_msrs, i).controls); | |
113 | per_cpu(cpu_msrs, i).controls = NULL; | |
4d4036e0 JY |
114 | |
115 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX | |
116 | kfree(per_cpu(cpu_msrs, i).multiplex); | |
117 | per_cpu(cpu_msrs, i).multiplex = NULL; | |
118 | #endif | |
1da177e4 LT |
119 | } |
120 | } | |
121 | ||
1da177e4 LT |
122 | static int allocate_msrs(void) |
123 | { | |
4c168eaf | 124 | int success = 1; |
1da177e4 LT |
125 | size_t controls_size = sizeof(struct op_msr) * model->num_controls; |
126 | size_t counters_size = sizeof(struct op_msr) * model->num_counters; | |
4d4036e0 JY |
127 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX |
128 | size_t multiplex_size = sizeof(struct op_msr) * model->num_virt_counters; | |
129 | #endif | |
1da177e4 | 130 | |
4c168eaf | 131 | int i; |
0939c17c | 132 | for_each_possible_cpu(i) { |
d18d00f5 MT |
133 | per_cpu(cpu_msrs, i).counters = kmalloc(counters_size, |
134 | GFP_KERNEL); | |
135 | if (!per_cpu(cpu_msrs, i).counters) { | |
1da177e4 LT |
136 | success = 0; |
137 | break; | |
138 | } | |
4c168eaf RR |
139 | per_cpu(cpu_msrs, i).controls = kmalloc(controls_size, |
140 | GFP_KERNEL); | |
d18d00f5 | 141 | if (!per_cpu(cpu_msrs, i).controls) { |
1da177e4 LT |
142 | success = 0; |
143 | break; | |
144 | } | |
4d4036e0 JY |
145 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX |
146 | per_cpu(cpu_msrs, i).multiplex = | |
147 | kmalloc(multiplex_size, GFP_KERNEL); | |
148 | if (!per_cpu(cpu_msrs, i).multiplex) { | |
149 | success = 0; | |
150 | break; | |
151 | } | |
152 | #endif | |
1da177e4 LT |
153 | } |
154 | ||
155 | if (!success) | |
156 | free_msrs(); | |
157 | ||
158 | return success; | |
159 | } | |
160 | ||
4d4036e0 JY |
161 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX |
162 | ||
6bfccd09 | 163 | static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) |
4d4036e0 JY |
164 | { |
165 | int i; | |
166 | struct op_msr *multiplex = msrs->multiplex; | |
167 | ||
168 | for (i = 0; i < model->num_virt_counters; ++i) { | |
169 | if (counter_config[i].enabled) { | |
170 | multiplex[i].saved = -(u64)counter_config[i].count; | |
171 | } else { | |
172 | multiplex[i].addr = 0; | |
173 | multiplex[i].saved = 0; | |
174 | } | |
175 | } | |
6bfccd09 RR |
176 | |
177 | per_cpu(switch_index, cpu) = 0; | |
4d4036e0 JY |
178 | } |
179 | ||
6bfccd09 RR |
180 | #else |
181 | ||
182 | static inline void | |
183 | nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { } | |
184 | ||
4d4036e0 JY |
185 | #endif |
186 | ||
b75f53db | 187 | static void nmi_cpu_setup(void *dummy) |
1da177e4 LT |
188 | { |
189 | int cpu = smp_processor_id(); | |
d18d00f5 | 190 | struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu); |
44ab9a6b | 191 | nmi_cpu_save_registers(msrs); |
1da177e4 | 192 | spin_lock(&oprofilefs_lock); |
ef8828dd | 193 | model->setup_ctrs(model, msrs); |
6bfccd09 | 194 | nmi_cpu_setup_mux(cpu, msrs); |
1da177e4 | 195 | spin_unlock(&oprofilefs_lock); |
d18d00f5 | 196 | per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC); |
1da177e4 LT |
197 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
198 | } | |
199 | ||
2fbe7b25 DZ |
200 | static struct notifier_block profile_exceptions_nb = { |
201 | .notifier_call = profile_exceptions_notify, | |
202 | .next = NULL, | |
5b75af0a | 203 | .priority = 2 |
2fbe7b25 | 204 | }; |
1da177e4 LT |
205 | |
206 | static int nmi_setup(void) | |
207 | { | |
b75f53db | 208 | int err = 0; |
6c977aad | 209 | int cpu; |
2fbe7b25 | 210 | |
1da177e4 LT |
211 | if (!allocate_msrs()) |
212 | return -ENOMEM; | |
213 | ||
b75f53db CM |
214 | err = register_die_notifier(&profile_exceptions_nb); |
215 | if (err) { | |
1da177e4 | 216 | free_msrs(); |
2fbe7b25 | 217 | return err; |
1da177e4 | 218 | } |
2fbe7b25 | 219 | |
4c168eaf | 220 | /* We need to serialize save and setup for HT because the subset |
1da177e4 LT |
221 | * of msrs are distinct for save and setup operations |
222 | */ | |
6c977aad AK |
223 | |
224 | /* Assume saved/restored counters are the same on all CPUs */ | |
d18d00f5 | 225 | model->fill_in_addresses(&per_cpu(cpu_msrs, 0)); |
b75f53db | 226 | for_each_possible_cpu(cpu) { |
0939c17c | 227 | if (cpu != 0) { |
d18d00f5 MT |
228 | memcpy(per_cpu(cpu_msrs, cpu).counters, |
229 | per_cpu(cpu_msrs, 0).counters, | |
0939c17c CW |
230 | sizeof(struct op_msr) * model->num_counters); |
231 | ||
d18d00f5 MT |
232 | memcpy(per_cpu(cpu_msrs, cpu).controls, |
233 | per_cpu(cpu_msrs, 0).controls, | |
0939c17c | 234 | sizeof(struct op_msr) * model->num_controls); |
4d4036e0 JY |
235 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX |
236 | memcpy(per_cpu(cpu_msrs, cpu).multiplex, | |
237 | per_cpu(cpu_msrs, 0).multiplex, | |
238 | sizeof(struct op_msr) * model->num_virt_counters); | |
239 | #endif | |
0939c17c | 240 | } |
6c977aad | 241 | } |
15c8b6c1 | 242 | on_each_cpu(nmi_cpu_setup, NULL, 1); |
1da177e4 LT |
243 | nmi_enabled = 1; |
244 | return 0; | |
245 | } | |
246 | ||
4d4036e0 JY |
247 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX |
248 | ||
249 | static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs) | |
250 | { | |
251 | unsigned int si = __get_cpu_var(switch_index); | |
252 | struct op_msr *multiplex = msrs->multiplex; | |
253 | unsigned int i; | |
254 | ||
255 | for (i = 0; i < model->num_counters; ++i) { | |
256 | int offset = i + si; | |
257 | if (multiplex[offset].addr) { | |
258 | rdmsrl(multiplex[offset].addr, | |
259 | multiplex[offset].saved); | |
260 | } | |
261 | } | |
262 | } | |
263 | ||
264 | static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs) | |
265 | { | |
266 | unsigned int si = __get_cpu_var(switch_index); | |
267 | struct op_msr *multiplex = msrs->multiplex; | |
268 | unsigned int i; | |
269 | ||
270 | for (i = 0; i < model->num_counters; ++i) { | |
271 | int offset = i + si; | |
272 | if (multiplex[offset].addr) { | |
273 | wrmsrl(multiplex[offset].addr, | |
274 | multiplex[offset].saved); | |
275 | } | |
276 | } | |
277 | } | |
278 | ||
279 | #endif | |
280 | ||
44ab9a6b | 281 | static void nmi_cpu_restore_registers(struct op_msrs *msrs) |
1da177e4 | 282 | { |
b75f53db CM |
283 | struct op_msr *counters = msrs->counters; |
284 | struct op_msr *controls = msrs->controls; | |
1da177e4 LT |
285 | unsigned int i; |
286 | ||
1a245c45 | 287 | for (i = 0; i < model->num_controls; ++i) { |
95e74e62 RR |
288 | if (controls[i].addr) |
289 | wrmsrl(controls[i].addr, controls[i].saved); | |
1da177e4 | 290 | } |
b75f53db | 291 | |
1a245c45 | 292 | for (i = 0; i < model->num_counters; ++i) { |
95e74e62 RR |
293 | if (counters[i].addr) |
294 | wrmsrl(counters[i].addr, counters[i].saved); | |
1da177e4 LT |
295 | } |
296 | } | |
1da177e4 | 297 | |
b75f53db | 298 | static void nmi_cpu_shutdown(void *dummy) |
1da177e4 LT |
299 | { |
300 | unsigned int v; | |
301 | int cpu = smp_processor_id(); | |
82a22528 | 302 | struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu); |
b75f53db | 303 | |
1da177e4 LT |
304 | /* restoring APIC_LVTPC can trigger an apic error because the delivery |
305 | * mode and vector nr combination can be illegal. That's by design: on | |
306 | * power on apic lvt contain a zero vector nr which are legal only for | |
307 | * NMI delivery mode. So inhibit apic err before restoring lvtpc | |
308 | */ | |
309 | v = apic_read(APIC_LVTERR); | |
310 | apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); | |
d18d00f5 | 311 | apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu)); |
1da177e4 | 312 | apic_write(APIC_LVTERR, v); |
44ab9a6b | 313 | nmi_cpu_restore_registers(msrs); |
4d4036e0 | 314 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX |
82a22528 | 315 | per_cpu(switch_index, cpu) = 0; |
4d4036e0 | 316 | #endif |
1da177e4 LT |
317 | } |
318 | ||
1da177e4 LT |
319 | static void nmi_shutdown(void) |
320 | { | |
b61e06f2 AR |
321 | struct op_msrs *msrs; |
322 | ||
1da177e4 | 323 | nmi_enabled = 0; |
15c8b6c1 | 324 | on_each_cpu(nmi_cpu_shutdown, NULL, 1); |
2fbe7b25 | 325 | unregister_die_notifier(&profile_exceptions_nb); |
b61e06f2 | 326 | msrs = &get_cpu_var(cpu_msrs); |
d18d00f5 | 327 | model->shutdown(msrs); |
1da177e4 | 328 | free_msrs(); |
93e1ade5 | 329 | put_cpu_var(cpu_msrs); |
1da177e4 LT |
330 | } |
331 | ||
b75f53db | 332 | static void nmi_cpu_start(void *dummy) |
1da177e4 | 333 | { |
d18d00f5 | 334 | struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs); |
1da177e4 LT |
335 | model->start(msrs); |
336 | } | |
1da177e4 LT |
337 | |
338 | static int nmi_start(void) | |
339 | { | |
15c8b6c1 | 340 | on_each_cpu(nmi_cpu_start, NULL, 1); |
1da177e4 LT |
341 | return 0; |
342 | } | |
b75f53db CM |
343 | |
344 | static void nmi_cpu_stop(void *dummy) | |
1da177e4 | 345 | { |
d18d00f5 | 346 | struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs); |
1da177e4 LT |
347 | model->stop(msrs); |
348 | } | |
b75f53db | 349 | |
1da177e4 LT |
350 | static void nmi_stop(void) |
351 | { | |
15c8b6c1 | 352 | on_each_cpu(nmi_cpu_stop, NULL, 1); |
1da177e4 LT |
353 | } |
354 | ||
b75f53db | 355 | static int nmi_create_files(struct super_block *sb, struct dentry *root) |
1da177e4 LT |
356 | { |
357 | unsigned int i; | |
358 | ||
4d4036e0 | 359 | for (i = 0; i < model->num_virt_counters; ++i) { |
b75f53db | 360 | struct dentry *dir; |
0c6856f7 | 361 | char buf[4]; |
b75f53db | 362 | |
4d4036e0 | 363 | #ifndef CONFIG_OPROFILE_EVENT_MULTIPLEX |
b75f53db | 364 | /* quick little hack to _not_ expose a counter if it is not |
cb9c448c DZ |
365 | * available for use. This should protect userspace app. |
366 | * NOTE: assumes 1:1 mapping here (that counters are organized | |
367 | * sequentially in their struct assignment). | |
368 | */ | |
369 | if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i))) | |
370 | continue; | |
4d4036e0 | 371 | #endif /* CONFIG_OPROFILE_EVENT_MULTIPLEX */ |
cb9c448c | 372 | |
0c6856f7 | 373 | snprintf(buf, sizeof(buf), "%d", i); |
1da177e4 | 374 | dir = oprofilefs_mkdir(sb, root, buf); |
b75f53db CM |
375 | oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled); |
376 | oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event); | |
377 | oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count); | |
378 | oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask); | |
379 | oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel); | |
380 | oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user); | |
1da177e4 LT |
381 | } |
382 | ||
383 | return 0; | |
384 | } | |
b75f53db | 385 | |
4d4036e0 JY |
386 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX |
387 | ||
388 | static void nmi_cpu_switch(void *dummy) | |
389 | { | |
390 | int cpu = smp_processor_id(); | |
391 | int si = per_cpu(switch_index, cpu); | |
392 | struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu); | |
393 | ||
394 | nmi_cpu_stop(NULL); | |
395 | nmi_cpu_save_mpx_registers(msrs); | |
396 | ||
397 | /* move to next set */ | |
398 | si += model->num_counters; | |
399 | if ((si > model->num_virt_counters) || (counter_config[si].count == 0)) | |
400 | per_cpu(switch_index, cpu) = 0; | |
401 | else | |
402 | per_cpu(switch_index, cpu) = si; | |
403 | ||
404 | model->switch_ctrl(model, msrs); | |
405 | nmi_cpu_restore_mpx_registers(msrs); | |
406 | ||
407 | nmi_cpu_start(NULL); | |
408 | } | |
409 | ||
410 | ||
411 | /* | |
412 | * Quick check to see if multiplexing is necessary. | |
413 | * The check should be sufficient since counters are used | |
414 | * in ordre. | |
415 | */ | |
416 | static int nmi_multiplex_on(void) | |
417 | { | |
418 | return counter_config[model->num_counters].count ? 0 : -EINVAL; | |
419 | } | |
420 | ||
421 | static int nmi_switch_event(void) | |
422 | { | |
423 | if (!model->switch_ctrl) | |
424 | return -ENOSYS; /* not implemented */ | |
425 | if (nmi_multiplex_on() < 0) | |
426 | return -EINVAL; /* not necessary */ | |
427 | ||
428 | on_each_cpu(nmi_cpu_switch, NULL, 1); | |
429 | ||
430 | atomic_inc(&multiplex_counter); | |
431 | ||
432 | return 0; | |
433 | } | |
434 | ||
435 | #endif | |
436 | ||
69046d43 RR |
437 | #ifdef CONFIG_SMP |
438 | static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action, | |
439 | void *data) | |
440 | { | |
441 | int cpu = (unsigned long)data; | |
442 | switch (action) { | |
443 | case CPU_DOWN_FAILED: | |
444 | case CPU_ONLINE: | |
445 | smp_call_function_single(cpu, nmi_cpu_start, NULL, 0); | |
446 | break; | |
447 | case CPU_DOWN_PREPARE: | |
448 | smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1); | |
449 | break; | |
450 | } | |
451 | return NOTIFY_DONE; | |
452 | } | |
453 | ||
454 | static struct notifier_block oprofile_cpu_nb = { | |
455 | .notifier_call = oprofile_cpu_notifier | |
456 | }; | |
457 | #endif | |
458 | ||
459 | #ifdef CONFIG_PM | |
460 | ||
461 | static int nmi_suspend(struct sys_device *dev, pm_message_t state) | |
462 | { | |
463 | /* Only one CPU left, just stop that one */ | |
464 | if (nmi_enabled == 1) | |
465 | nmi_cpu_stop(NULL); | |
466 | return 0; | |
467 | } | |
468 | ||
469 | static int nmi_resume(struct sys_device *dev) | |
470 | { | |
471 | if (nmi_enabled == 1) | |
472 | nmi_cpu_start(NULL); | |
473 | return 0; | |
474 | } | |
475 | ||
476 | static struct sysdev_class oprofile_sysclass = { | |
477 | .name = "oprofile", | |
478 | .resume = nmi_resume, | |
479 | .suspend = nmi_suspend, | |
480 | }; | |
481 | ||
482 | static struct sys_device device_oprofile = { | |
483 | .id = 0, | |
484 | .cls = &oprofile_sysclass, | |
485 | }; | |
486 | ||
487 | static int __init init_sysfs(void) | |
488 | { | |
489 | int error; | |
490 | ||
491 | error = sysdev_class_register(&oprofile_sysclass); | |
492 | if (!error) | |
493 | error = sysdev_register(&device_oprofile); | |
494 | return error; | |
495 | } | |
496 | ||
497 | static void exit_sysfs(void) | |
498 | { | |
499 | sysdev_unregister(&device_oprofile); | |
500 | sysdev_class_unregister(&oprofile_sysclass); | |
501 | } | |
502 | ||
503 | #else | |
504 | #define init_sysfs() do { } while (0) | |
505 | #define exit_sysfs() do { } while (0) | |
506 | #endif /* CONFIG_PM */ | |
507 | ||
b75f53db | 508 | static int __init p4_init(char **cpu_type) |
1da177e4 LT |
509 | { |
510 | __u8 cpu_model = boot_cpu_data.x86_model; | |
511 | ||
1f3d7b60 | 512 | if (cpu_model > 6 || cpu_model == 5) |
1da177e4 LT |
513 | return 0; |
514 | ||
515 | #ifndef CONFIG_SMP | |
516 | *cpu_type = "i386/p4"; | |
517 | model = &op_p4_spec; | |
518 | return 1; | |
519 | #else | |
520 | switch (smp_num_siblings) { | |
b75f53db CM |
521 | case 1: |
522 | *cpu_type = "i386/p4"; | |
523 | model = &op_p4_spec; | |
524 | return 1; | |
525 | ||
526 | case 2: | |
527 | *cpu_type = "i386/p4-ht"; | |
528 | model = &op_p4_ht2_spec; | |
529 | return 1; | |
1da177e4 LT |
530 | } |
531 | #endif | |
532 | ||
533 | printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n"); | |
534 | printk(KERN_INFO "oprofile: Reverting to timer mode.\n"); | |
535 | return 0; | |
536 | } | |
537 | ||
7e4e0bd5 RR |
538 | static int force_arch_perfmon; |
539 | static int force_cpu_type(const char *str, struct kernel_param *kp) | |
540 | { | |
8d7ff4f2 | 541 | if (!strcmp(str, "arch_perfmon")) { |
7e4e0bd5 RR |
542 | force_arch_perfmon = 1; |
543 | printk(KERN_INFO "oprofile: forcing architectural perfmon\n"); | |
544 | } | |
545 | ||
546 | return 0; | |
547 | } | |
548 | module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0); | |
1dcdb5a9 | 549 | |
b75f53db | 550 | static int __init ppro_init(char **cpu_type) |
1da177e4 LT |
551 | { |
552 | __u8 cpu_model = boot_cpu_data.x86_model; | |
802070f5 | 553 | struct op_x86_model_spec const *spec = &op_ppro_spec; /* default */ |
1da177e4 | 554 | |
1dcdb5a9 AK |
555 | if (force_arch_perfmon && cpu_has_arch_perfmon) |
556 | return 0; | |
557 | ||
4b9f12a3 LT |
558 | switch (cpu_model) { |
559 | case 0 ... 2: | |
560 | *cpu_type = "i386/ppro"; | |
561 | break; | |
562 | case 3 ... 5: | |
563 | *cpu_type = "i386/pii"; | |
564 | break; | |
565 | case 6 ... 8: | |
3d337c65 | 566 | case 10 ... 11: |
4b9f12a3 LT |
567 | *cpu_type = "i386/piii"; |
568 | break; | |
569 | case 9: | |
3d337c65 | 570 | case 13: |
4b9f12a3 LT |
571 | *cpu_type = "i386/p6_mobile"; |
572 | break; | |
4b9f12a3 | 573 | case 14: |
64471ebe | 574 | *cpu_type = "i386/core"; |
4b9f12a3 LT |
575 | break; |
576 | case 15: case 23: | |
577 | *cpu_type = "i386/core_2"; | |
578 | break; | |
6adf406f | 579 | case 26: |
802070f5 | 580 | spec = &op_arch_perfmon_spec; |
6adf406f AK |
581 | *cpu_type = "i386/core_i7"; |
582 | break; | |
583 | case 28: | |
584 | *cpu_type = "i386/atom"; | |
585 | break; | |
4b9f12a3 LT |
586 | default: |
587 | /* Unknown */ | |
1da177e4 | 588 | return 0; |
1da177e4 LT |
589 | } |
590 | ||
802070f5 | 591 | model = spec; |
1da177e4 LT |
592 | return 1; |
593 | } | |
594 | ||
405ae7d3 | 595 | /* in order to get sysfs right */ |
1da177e4 LT |
596 | static int using_nmi; |
597 | ||
96d0821c | 598 | int __init op_nmi_init(struct oprofile_operations *ops) |
1da177e4 LT |
599 | { |
600 | __u8 vendor = boot_cpu_data.x86_vendor; | |
601 | __u8 family = boot_cpu_data.x86; | |
b9917028 | 602 | char *cpu_type = NULL; |
adf5ec0b | 603 | int ret = 0; |
1da177e4 LT |
604 | |
605 | if (!cpu_has_apic) | |
606 | return -ENODEV; | |
b75f53db | 607 | |
1da177e4 | 608 | switch (vendor) { |
b75f53db CM |
609 | case X86_VENDOR_AMD: |
610 | /* Needs to be at least an Athlon (or hammer in 32bit mode) */ | |
1da177e4 | 611 | |
b75f53db | 612 | switch (family) { |
b75f53db | 613 | case 6: |
b75f53db CM |
614 | cpu_type = "i386/athlon"; |
615 | break; | |
616 | case 0xf: | |
d20f24c6 RR |
617 | /* |
618 | * Actually it could be i386/hammer too, but | |
619 | * give user space an consistent name. | |
620 | */ | |
b75f53db CM |
621 | cpu_type = "x86-64/hammer"; |
622 | break; | |
623 | case 0x10: | |
b75f53db CM |
624 | cpu_type = "x86-64/family10"; |
625 | break; | |
12f2b261 | 626 | case 0x11: |
12f2b261 BK |
627 | cpu_type = "x86-64/family11h"; |
628 | break; | |
d20f24c6 RR |
629 | default: |
630 | return -ENODEV; | |
b75f53db | 631 | } |
d20f24c6 | 632 | model = &op_amd_spec; |
b75f53db CM |
633 | break; |
634 | ||
635 | case X86_VENDOR_INTEL: | |
636 | switch (family) { | |
637 | /* Pentium IV */ | |
638 | case 0xf: | |
b9917028 | 639 | p4_init(&cpu_type); |
1da177e4 | 640 | break; |
b75f53db CM |
641 | |
642 | /* A P6-class processor */ | |
643 | case 6: | |
b9917028 | 644 | ppro_init(&cpu_type); |
1da177e4 LT |
645 | break; |
646 | ||
647 | default: | |
b9917028 | 648 | break; |
b75f53db | 649 | } |
b9917028 | 650 | |
e419294e RR |
651 | if (cpu_type) |
652 | break; | |
653 | ||
654 | if (!cpu_has_arch_perfmon) | |
b9917028 | 655 | return -ENODEV; |
e419294e RR |
656 | |
657 | /* use arch perfmon as fallback */ | |
658 | cpu_type = "i386/arch_perfmon"; | |
659 | model = &op_arch_perfmon_spec; | |
b75f53db CM |
660 | break; |
661 | ||
662 | default: | |
663 | return -ENODEV; | |
1da177e4 LT |
664 | } |
665 | ||
80a8c9ff AK |
666 | #ifdef CONFIG_SMP |
667 | register_cpu_notifier(&oprofile_cpu_nb); | |
668 | #endif | |
270d3e1a | 669 | /* default values, can be overwritten by model */ |
6e63ea4b RR |
670 | ops->create_files = nmi_create_files; |
671 | ops->setup = nmi_setup; | |
672 | ops->shutdown = nmi_shutdown; | |
673 | ops->start = nmi_start; | |
674 | ops->stop = nmi_stop; | |
675 | ops->cpu_type = cpu_type; | |
4d4036e0 JY |
676 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX |
677 | ops->switch_events = nmi_switch_event; | |
678 | #endif | |
270d3e1a | 679 | |
adf5ec0b RR |
680 | if (model->init) |
681 | ret = model->init(ops); | |
682 | if (ret) | |
683 | return ret; | |
684 | ||
405ae7d3 | 685 | init_sysfs(); |
1da177e4 | 686 | using_nmi = 1; |
1da177e4 LT |
687 | printk(KERN_INFO "oprofile: using NMI interrupt.\n"); |
688 | return 0; | |
689 | } | |
690 | ||
96d0821c | 691 | void op_nmi_exit(void) |
1da177e4 | 692 | { |
80a8c9ff | 693 | if (using_nmi) { |
405ae7d3 | 694 | exit_sysfs(); |
80a8c9ff AK |
695 | #ifdef CONFIG_SMP |
696 | unregister_cpu_notifier(&oprofile_cpu_nb); | |
697 | #endif | |
698 | } | |
adf5ec0b RR |
699 | if (model->exit) |
700 | model->exit(); | |
1da177e4 | 701 | } |