[deliverable/linux.git] / arch / x86 / oprofile / nmi_int.c

/**
 * @file nmi_int.c
 *
 * @remark Copyright 2002-2008 OProfile authors
 * @remark Read the file COPYING
 *
 * @author John Levon <levon@movementarian.org>
 * @author Robert Richter <robert.richter@amd.com>
 */

#include <linux/init.h>
#include <linux/notifier.h>
#include <linux/smp.h>
#include <linux/oprofile.h>
#include <linux/sysdev.h>
#include <linux/slab.h>
#include <linux/moduleparam.h>
#include <linux/kdebug.h>
#include <asm/nmi.h>
#include <asm/msr.h>
#include <asm/apic.h>

#include "op_counter.h"
#include "op_x86_model.h"

static struct op_x86_model_spec const *model;
static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
static DEFINE_PER_CPU(unsigned long, saved_lvtpc);

static int nmi_start(void);
static void nmi_stop(void);

/* 0 == registered but off, 1 == registered and on */
static int nmi_enabled = 0;

#ifdef CONFIG_PM

static int nmi_suspend(struct sys_device *dev, pm_message_t state)
{
	if (nmi_enabled == 1)
		nmi_stop();
	return 0;
}

static int nmi_resume(struct sys_device *dev)
{
	if (nmi_enabled == 1)
		nmi_start();
	return 0;
}

static struct sysdev_class oprofile_sysclass = {
	.name		= "oprofile",
	.resume		= nmi_resume,
	.suspend	= nmi_suspend,
};

static struct sys_device device_oprofile = {
	.id	= 0,
	.cls	= &oprofile_sysclass,
};

static int __init init_sysfs(void)
{
	int error;

	error = sysdev_class_register(&oprofile_sysclass);
	if (!error)
		error = sysdev_register(&device_oprofile);
	return error;
}

static void exit_sysfs(void)
{
	sysdev_unregister(&device_oprofile);
	sysdev_class_unregister(&oprofile_sysclass);
}

#else
#define init_sysfs() do { } while (0)
#define exit_sysfs() do { } while (0)
#endif /* CONFIG_PM */

static int profile_exceptions_notify(struct notifier_block *self,
				     unsigned long val, void *data)
{
	struct die_args *args = (struct die_args *)data;
	int ret = NOTIFY_DONE;
	int cpu = smp_processor_id();

	switch (val) {
	case DIE_NMI:
		if (model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu)))
			ret = NOTIFY_STOP;
		break;
	default:
		break;
	}
	return ret;
}

static void nmi_cpu_save_registers(struct op_msrs *msrs)
{
	unsigned int const nr_ctrs = model->num_counters;
	unsigned int const nr_ctrls = model->num_controls;
	struct op_msr *counters = msrs->counters;
	struct op_msr *controls = msrs->controls;
	unsigned int i;

	for (i = 0; i < nr_ctrs; ++i) {
		if (counters[i].addr) {
			rdmsr(counters[i].addr,
				counters[i].saved.low,
				counters[i].saved.high);
		}
	}

	for (i = 0; i < nr_ctrls; ++i) {
		if (controls[i].addr) {
			rdmsr(controls[i].addr,
				controls[i].saved.low,
				controls[i].saved.high);
		}
	}
}

static void nmi_save_registers(void *dummy)
{
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
	nmi_cpu_save_registers(msrs);
}

static void free_msrs(void)
{
	int i;
	for_each_possible_cpu(i) {
		kfree(per_cpu(cpu_msrs, i).counters);
		per_cpu(cpu_msrs, i).counters = NULL;
		kfree(per_cpu(cpu_msrs, i).controls);
		per_cpu(cpu_msrs, i).controls = NULL;
	}
}

static int allocate_msrs(void)
{
	int success = 1;
	size_t controls_size = sizeof(struct op_msr) * model->num_controls;
	size_t counters_size = sizeof(struct op_msr) * model->num_counters;

	int i;
	for_each_possible_cpu(i) {
		per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
								GFP_KERNEL);
		if (!per_cpu(cpu_msrs, i).counters) {
			success = 0;
			break;
		}
		per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
								GFP_KERNEL);
		if (!per_cpu(cpu_msrs, i).controls) {
			success = 0;
			break;
		}
	}

	if (!success)
		free_msrs();

	return success;
}

static void nmi_cpu_setup(void *dummy)
{
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
	spin_lock(&oprofilefs_lock);
	model->setup_ctrs(msrs);
	spin_unlock(&oprofilefs_lock);
	per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
	apic_write(APIC_LVTPC, APIC_DM_NMI);
}

static struct notifier_block profile_exceptions_nb = {
	.notifier_call = profile_exceptions_notify,
	.next = NULL,
	.priority = 0
};

static int nmi_setup(void)
{
	int err = 0;
	int cpu;

	if (!allocate_msrs())
		return -ENOMEM;

	err = register_die_notifier(&profile_exceptions_nb);
	if (err) {
		free_msrs();
		return err;
	}

	/* We need to serialize save and setup for HT because the subset
	 * of msrs are distinct for save and setup operations
	 */

	/* Assume saved/restored counters are the same on all CPUs */
	model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
	for_each_possible_cpu(cpu) {
		if (cpu != 0) {
			memcpy(per_cpu(cpu_msrs, cpu).counters,
				per_cpu(cpu_msrs, 0).counters,
				sizeof(struct op_msr) * model->num_counters);

			memcpy(per_cpu(cpu_msrs, cpu).controls,
				per_cpu(cpu_msrs, 0).controls,
				sizeof(struct op_msr) * model->num_controls);
		}

	}
	on_each_cpu(nmi_save_registers, NULL, 1);
	on_each_cpu(nmi_cpu_setup, NULL, 1);
	nmi_enabled = 1;
	return 0;
}

static void nmi_restore_registers(struct op_msrs *msrs)
{
	unsigned int const nr_ctrs = model->num_counters;
	unsigned int const nr_ctrls = model->num_controls;
	struct op_msr *counters = msrs->counters;
	struct op_msr *controls = msrs->controls;
	unsigned int i;

	for (i = 0; i < nr_ctrls; ++i) {
		if (controls[i].addr) {
			wrmsr(controls[i].addr,
				controls[i].saved.low,
				controls[i].saved.high);
		}
	}

	for (i = 0; i < nr_ctrs; ++i) {
		if (counters[i].addr) {
			wrmsr(counters[i].addr,
				counters[i].saved.low,
				counters[i].saved.high);
		}
	}
}

static void nmi_cpu_shutdown(void *dummy)
{
	unsigned int v;
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);

	/* restoring APIC_LVTPC can trigger an apic error because the delivery
	 * mode and vector nr combination can be illegal. That's by design: on
	 * power on apic lvt contain a zero vector nr which are legal only for
	 * NMI delivery mode. So inhibit apic err before restoring lvtpc
	 */
	v = apic_read(APIC_LVTERR);
	apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
	apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
	apic_write(APIC_LVTERR, v);
	nmi_restore_registers(msrs);
}

static void nmi_shutdown(void)
{
	struct op_msrs *msrs = &get_cpu_var(cpu_msrs);
	nmi_enabled = 0;
	on_each_cpu(nmi_cpu_shutdown, NULL, 1);
	unregister_die_notifier(&profile_exceptions_nb);
	model->shutdown(msrs);
	free_msrs();
	put_cpu_var(cpu_msrs);
}

static void nmi_cpu_start(void *dummy)
{
	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
	model->start(msrs);
}

static int nmi_start(void)
{
	on_each_cpu(nmi_cpu_start, NULL, 1);
	return 0;
}

static void nmi_cpu_stop(void *dummy)
{
	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
	model->stop(msrs);
}

static void nmi_stop(void)
{
	on_each_cpu(nmi_cpu_stop, NULL, 1);
}

struct op_counter_config counter_config[OP_MAX_COUNTER];

static int nmi_create_files(struct super_block *sb, struct dentry *root)
{
	unsigned int i;

	for (i = 0; i < model->num_counters; ++i) {
		struct dentry *dir;
		char buf[4];

		/* quick little hack to _not_ expose a counter if it is not
		 * available for use.  This should protect userspace app.
		 * NOTE:  assumes 1:1 mapping here (that counters are organized
		 *        sequentially in their struct assignment).
		 */
		if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
			continue;

		snprintf(buf,  sizeof(buf), "%d", i);
		dir = oprofilefs_mkdir(sb, root, buf);
		oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
		oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
		oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
		oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
		oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
		oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
	}

	return 0;
}

static int p4force;
module_param(p4force, int, 0);

static int __init p4_init(char **cpu_type)
{
	__u8 cpu_model = boot_cpu_data.x86_model;

	if (!p4force && (cpu_model > 6 || cpu_model == 5))
		return 0;

#ifndef CONFIG_SMP
	*cpu_type = "i386/p4";
	model = &op_p4_spec;
	return 1;
#else
	switch (smp_num_siblings) {
	case 1:
		*cpu_type = "i386/p4";
		model = &op_p4_spec;
		return 1;

	case 2:
		*cpu_type = "i386/p4-ht";
		model = &op_p4_ht2_spec;
		return 1;
	}
#endif

	printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
	printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
	return 0;
}

static int __init ppro_init(char **cpu_type)
{
	__u8 cpu_model = boot_cpu_data.x86_model;

	switch (cpu_model) {
	case 0 ... 2:
		*cpu_type = "i386/ppro";
		break;
	case 3 ... 5:
		*cpu_type = "i386/pii";
		break;
	case 6 ... 8:
		*cpu_type = "i386/piii";
		break;
	case 9:
		*cpu_type = "i386/p6_mobile";
		break;
	case 10 ... 13:
		*cpu_type = "i386/p6";
		break;
	case 14:
		*cpu_type = "i386/core";
		break;
	case 15: case 23:
		*cpu_type = "i386/core_2";
		break;
	case 26:
		*cpu_type = "i386/core_2";
		break;
	default:
		/* Unknown */
		return 0;
	}

	model = &op_ppro_spec;
	return 1;
}

/* in order to get sysfs right */
static int using_nmi;

int __init op_nmi_init(struct oprofile_operations *ops)
{
	__u8 vendor = boot_cpu_data.x86_vendor;
	__u8 family = boot_cpu_data.x86;
	char *cpu_type;
	int ret = 0;

	if (!cpu_has_apic)
		return -ENODEV;

	switch (vendor) {
	case X86_VENDOR_AMD:
		/* Needs to be at least an Athlon (or hammer in 32bit mode) */

		switch (family) {
		default:
			return -ENODEV;
		case 6:
			model = &op_athlon_spec;
			cpu_type = "i386/athlon";
			break;
		case 0xf:
			model = &op_athlon_spec;
			/* Actually it could be i386/hammer too, but give
			 user space an consistent name. */
			cpu_type = "x86-64/hammer";
			break;
		case 0x10:
			model = &op_athlon_spec;
			cpu_type = "x86-64/family10";
			break;
		case 0x11:
			model = &op_athlon_spec;
			cpu_type = "x86-64/family11h";
			break;
		}
		break;

	case X86_VENDOR_INTEL:
		switch (family) {
			/* Pentium IV */
		case 0xf:
			if (!p4_init(&cpu_type))
				return -ENODEV;
			break;

			/* A P6-class processor */
		case 6:
			if (!ppro_init(&cpu_type))
				return -ENODEV;
			break;

		default:
			return -ENODEV;
		}
		break;

	default:
		return -ENODEV;
	}

	if (model->init)
		ret = model->init(ops);
	if (ret)
		return ret;

	init_sysfs();
	using_nmi = 1;
	ops->create_files = nmi_create_files;
	ops->setup = nmi_setup;
	ops->shutdown = nmi_shutdown;
	ops->start = nmi_start;
	ops->stop = nmi_stop;
	ops->cpu_type = cpu_type;
	printk(KERN_INFO "oprofile: using NMI interrupt.\n");
	return 0;
}

void op_nmi_exit(void)
{
	if (using_nmi)
		exit_sysfs();
	if (model->exit)
		model->exit();
}
Commit	Line	Data
1da177e4 LT	1	/**
	2	* @file nmi_int.c
	3	*
adf5ec0b	4	* @remark Copyright 2002-2008 OProfile authors
1da177e4 LT	5	* @remark Read the file COPYING
	6	*
	7	* @author John Levon <levon@movementarian.org>
adf5ec0b	8	* @author Robert Richter <robert.richter@amd.com>
1da177e4 LT	9	*/
	10
	11	#include <linux/init.h>
	12	#include <linux/notifier.h>
	13	#include <linux/smp.h>
	14	#include <linux/oprofile.h>
	15	#include <linux/sysdev.h>
	16	#include <linux/slab.h>
1cfcea1b	17	#include <linux/moduleparam.h>
1eeb66a1	18	#include <linux/kdebug.h>
1da177e4 LT	19	#include <asm/nmi.h>
	20	#include <asm/msr.h>
	21	#include <asm/apic.h>
b75f53db	22
1da177e4 LT	23	#include "op_counter.h"
1da177e4 LT	24	#include "op_x86_model.h"
2fbe7b25	25
b75f53db	26	static struct op_x86_model_spec const *model;
d18d00f5 MT	27	static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
d18d00f5 MT	28	static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
2fbe7b25	29
1da177e4 LT	30	static int nmi_start(void);
	31	static void nmi_stop(void);
	32
	33	/* 0 == registered but off, 1 == registered and on */
	34	static int nmi_enabled = 0;
	35
	36	#ifdef CONFIG_PM
	37
438510f6	38	static int nmi_suspend(struct sys_device *dev, pm_message_t state)
1da177e4 LT	39	{
	40	if (nmi_enabled == 1)
	41	nmi_stop();
	42	return 0;
	43	}
	44
1da177e4 LT	45	static int nmi_resume(struct sys_device *dev)
	46	{
	47	if (nmi_enabled == 1)
	48	nmi_start();
	49	return 0;
	50	}
	51
1da177e4	52	static struct sysdev_class oprofile_sysclass = {
af5ca3f4	53	.name = "oprofile",
1da177e4 LT	54	.resume = nmi_resume,
	55	.suspend = nmi_suspend,
	56	};
	57
1da177e4 LT	58	static struct sys_device device_oprofile = {
	59	.id = 0,
	60	.cls = &oprofile_sysclass,
	61	};
	62
405ae7d3	63	static int __init init_sysfs(void)
1da177e4 LT	64	{
1da177e4 LT	65	int error;
b75f53db CM	66
	67	error = sysdev_class_register(&oprofile_sysclass);
	68	if (!error)
1da177e4 LT	69	error = sysdev_register(&device_oprofile);
	70	return error;
	71	}
	72
405ae7d3	73	static void exit_sysfs(void)
1da177e4 LT	74	{
	75	sysdev_unregister(&device_oprofile);
	76	sysdev_class_unregister(&oprofile_sysclass);
	77	}
	78
	79	#else
405ae7d3 RD	80	#define init_sysfs() do { } while (0)
405ae7d3 RD	81	#define exit_sysfs() do { } while (0)
1da177e4 LT	82	#endif /* CONFIG_PM */
1da177e4 LT	83
c7c19f8e AB	84	static int profile_exceptions_notify(struct notifier_block *self,
c7c19f8e AB	85	unsigned long val, void *data)
1da177e4	86	{
2fbe7b25 DZ	87	struct die_args args = (struct die_args )data;
	88	int ret = NOTIFY_DONE;
	89	int cpu = smp_processor_id();
	90
b75f53db	91	switch (val) {
2fbe7b25	92	case DIE_NMI:
d18d00f5	93	if (model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu)))
2fbe7b25 DZ	94	ret = NOTIFY_STOP;
	95	break;
	96	default:
	97	break;
	98	}
	99	return ret;
1da177e4	100	}
2fbe7b25	101
b75f53db	102	static void nmi_cpu_save_registers(struct op_msrs *msrs)
1da177e4 LT	103	{
1da177e4 LT	104	unsigned int const nr_ctrs = model->num_counters;
b75f53db CM	105	unsigned int const nr_ctrls = model->num_controls;
	106	struct op_msr *counters = msrs->counters;
	107	struct op_msr *controls = msrs->controls;
1da177e4 LT	108	unsigned int i;
	109
	110	for (i = 0; i < nr_ctrs; ++i) {
b75f53db	111	if (counters[i].addr) {
cb9c448c DZ	112	rdmsr(counters[i].addr,
	113	counters[i].saved.low,
	114	counters[i].saved.high);
	115	}
1da177e4	116	}
b75f53db	117
1da177e4	118	for (i = 0; i < nr_ctrls; ++i) {
b75f53db	119	if (controls[i].addr) {
cb9c448c DZ	120	rdmsr(controls[i].addr,
	121	controls[i].saved.low,
	122	controls[i].saved.high);
	123	}
1da177e4 LT	124	}
	125	}
	126
b75f53db	127	static void nmi_save_registers(void *dummy)
1da177e4 LT	128	{
1da177e4 LT	129	int cpu = smp_processor_id();
d18d00f5	130	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
1da177e4 LT	131	nmi_cpu_save_registers(msrs);
	132	}
	133
1da177e4 LT	134	static void free_msrs(void)
	135	{
	136	int i;
c8912599	137	for_each_possible_cpu(i) {
d18d00f5 MT	138	kfree(per_cpu(cpu_msrs, i).counters);
	139	per_cpu(cpu_msrs, i).counters = NULL;
	140	kfree(per_cpu(cpu_msrs, i).controls);
	141	per_cpu(cpu_msrs, i).controls = NULL;
1da177e4 LT	142	}
	143	}
	144
1da177e4 LT	145	static int allocate_msrs(void)
	146	{
	147	int success = 1;
	148	size_t controls_size = sizeof(struct op_msr) * model->num_controls;
	149	size_t counters_size = sizeof(struct op_msr) * model->num_counters;
	150
	151	int i;
0939c17c	152	for_each_possible_cpu(i) {
d18d00f5 MT	153	per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
	154	GFP_KERNEL);
	155	if (!per_cpu(cpu_msrs, i).counters) {
1da177e4 LT	156	success = 0;
	157	break;
	158	}
d18d00f5 MT	159	per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
	160	GFP_KERNEL);
	161	if (!per_cpu(cpu_msrs, i).controls) {
1da177e4 LT	162	success = 0;
	163	break;
	164	}
	165	}
	166
	167	if (!success)
	168	free_msrs();
	169
	170	return success;
	171	}
	172
b75f53db	173	static void nmi_cpu_setup(void *dummy)
1da177e4 LT	174	{
1da177e4 LT	175	int cpu = smp_processor_id();
d18d00f5	176	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
1da177e4 LT	177	spin_lock(&oprofilefs_lock);
	178	model->setup_ctrs(msrs);
	179	spin_unlock(&oprofilefs_lock);
d18d00f5	180	per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
1da177e4 LT	181	apic_write(APIC_LVTPC, APIC_DM_NMI);
	182	}
	183
2fbe7b25 DZ	184	static struct notifier_block profile_exceptions_nb = {
	185	.notifier_call = profile_exceptions_notify,
	186	.next = NULL,
	187	.priority = 0
	188	};
1da177e4 LT	189
	190	static int nmi_setup(void)
	191	{
b75f53db	192	int err = 0;
6c977aad	193	int cpu;
2fbe7b25	194
1da177e4 LT	195	if (!allocate_msrs())
	196	return -ENOMEM;
	197
b75f53db CM	198	err = register_die_notifier(&profile_exceptions_nb);
b75f53db CM	199	if (err) {
1da177e4	200	free_msrs();
2fbe7b25	201	return err;
1da177e4	202	}
2fbe7b25	203
1da177e4 LT	204	/* We need to serialize save and setup for HT because the subset
	205	* of msrs are distinct for save and setup operations
	206	*/
6c977aad AK	207
6c977aad AK	208	/* Assume saved/restored counters are the same on all CPUs */
d18d00f5	209	model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
b75f53db	210	for_each_possible_cpu(cpu) {
0939c17c	211	if (cpu != 0) {
d18d00f5 MT	212	memcpy(per_cpu(cpu_msrs, cpu).counters,
d18d00f5 MT	213	per_cpu(cpu_msrs, 0).counters,
0939c17c CW	214	sizeof(struct op_msr) * model->num_counters);
0939c17c CW	215
d18d00f5 MT	216	memcpy(per_cpu(cpu_msrs, cpu).controls,
d18d00f5 MT	217	per_cpu(cpu_msrs, 0).controls,
0939c17c CW	218	sizeof(struct op_msr) * model->num_controls);
	219	}
	220
6c977aad	221	}
15c8b6c1 JA	222	on_each_cpu(nmi_save_registers, NULL, 1);
15c8b6c1 JA	223	on_each_cpu(nmi_cpu_setup, NULL, 1);
1da177e4 LT	224	nmi_enabled = 1;
	225	return 0;
	226	}
	227
b75f53db	228	static void nmi_restore_registers(struct op_msrs *msrs)
1da177e4 LT	229	{
1da177e4 LT	230	unsigned int const nr_ctrs = model->num_counters;
b75f53db CM	231	unsigned int const nr_ctrls = model->num_controls;
	232	struct op_msr *counters = msrs->counters;
	233	struct op_msr *controls = msrs->controls;
1da177e4 LT	234	unsigned int i;
	235
	236	for (i = 0; i < nr_ctrls; ++i) {
b75f53db	237	if (controls[i].addr) {
cb9c448c DZ	238	wrmsr(controls[i].addr,
	239	controls[i].saved.low,
	240	controls[i].saved.high);
	241	}
1da177e4	242	}
b75f53db	243
1da177e4	244	for (i = 0; i < nr_ctrs; ++i) {
b75f53db	245	if (counters[i].addr) {
cb9c448c DZ	246	wrmsr(counters[i].addr,
	247	counters[i].saved.low,
	248	counters[i].saved.high);
	249	}
1da177e4 LT	250	}
1da177e4 LT	251	}
1da177e4	252
b75f53db	253	static void nmi_cpu_shutdown(void *dummy)
1da177e4 LT	254	{
	255	unsigned int v;
	256	int cpu = smp_processor_id();
d18d00f5	257	struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);
b75f53db	258
1da177e4 LT	259	/* restoring APIC_LVTPC can trigger an apic error because the delivery
	260	* mode and vector nr combination can be illegal. That's by design: on
	261	* power on apic lvt contain a zero vector nr which are legal only for
	262	* NMI delivery mode. So inhibit apic err before restoring lvtpc
	263	*/
	264	v = apic_read(APIC_LVTERR);
	265	apic_write(APIC_LVTERR, v \| APIC_LVT_MASKED);
d18d00f5	266	apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
1da177e4 LT	267	apic_write(APIC_LVTERR, v);
	268	nmi_restore_registers(msrs);
	269	}
	270
1da177e4 LT	271	static void nmi_shutdown(void)
1da177e4 LT	272	{
93e1ade5	273	struct op_msrs *msrs = &get_cpu_var(cpu_msrs);
1da177e4	274	nmi_enabled = 0;
15c8b6c1	275	on_each_cpu(nmi_cpu_shutdown, NULL, 1);
2fbe7b25	276	unregister_die_notifier(&profile_exceptions_nb);
d18d00f5	277	model->shutdown(msrs);
1da177e4	278	free_msrs();
93e1ade5	279	put_cpu_var(cpu_msrs);
1da177e4 LT	280	}
1da177e4 LT	281
b75f53db	282	static void nmi_cpu_start(void *dummy)
1da177e4	283	{
d18d00f5	284	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
1da177e4 LT	285	model->start(msrs);
1da177e4 LT	286	}
1da177e4 LT	287
	288	static int nmi_start(void)
	289	{
15c8b6c1	290	on_each_cpu(nmi_cpu_start, NULL, 1);
1da177e4 LT	291	return 0;
1da177e4 LT	292	}
b75f53db CM	293
b75f53db CM	294	static void nmi_cpu_stop(void *dummy)
1da177e4	295	{
d18d00f5	296	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
1da177e4 LT	297	model->stop(msrs);
1da177e4 LT	298	}
b75f53db	299
1da177e4 LT	300	static void nmi_stop(void)
1da177e4 LT	301	{
15c8b6c1	302	on_each_cpu(nmi_cpu_stop, NULL, 1);
1da177e4 LT	303	}
1da177e4 LT	304
1da177e4 LT	305	struct op_counter_config counter_config[OP_MAX_COUNTER];
1da177e4 LT	306
b75f53db	307	static int nmi_create_files(struct super_block sb, struct dentry root)
1da177e4 LT	308	{
	309	unsigned int i;
	310
	311	for (i = 0; i < model->num_counters; ++i) {
b75f53db	312	struct dentry *dir;
0c6856f7	313	char buf[4];
b75f53db CM	314
b75f53db CM	315	/* quick little hack to _not_ expose a counter if it is not
cb9c448c DZ	316	* available for use. This should protect userspace app.
	317	* NOTE: assumes 1:1 mapping here (that counters are organized
	318	* sequentially in their struct assignment).
	319	*/
	320	if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
	321	continue;
	322
0c6856f7	323	snprintf(buf, sizeof(buf), "%d", i);
1da177e4	324	dir = oprofilefs_mkdir(sb, root, buf);
b75f53db CM	325	oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
	326	oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
	327	oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
	328	oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
	329	oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
	330	oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
1da177e4 LT	331	}
	332
	333	return 0;
	334	}
b75f53db	335
1cfcea1b AK	336	static int p4force;
1cfcea1b AK	337	module_param(p4force, int, 0);
b75f53db CM	338
b75f53db CM	339	static int __init p4_init(char **cpu_type)
1da177e4 LT	340	{
	341	__u8 cpu_model = boot_cpu_data.x86_model;
	342
1cfcea1b	343	if (!p4force && (cpu_model > 6 \|\| cpu_model == 5))
1da177e4 LT	344	return 0;
	345
	346	#ifndef CONFIG_SMP
	347	*cpu_type = "i386/p4";
	348	model = &op_p4_spec;
	349	return 1;
	350	#else
	351	switch (smp_num_siblings) {
b75f53db CM	352	case 1:
	353	*cpu_type = "i386/p4";
	354	model = &op_p4_spec;
	355	return 1;
	356
	357	case 2:
	358	*cpu_type = "i386/p4-ht";
	359	model = &op_p4_ht2_spec;
	360	return 1;
1da177e4 LT	361	}
	362	#endif
	363
	364	printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
	365	printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
	366	return 0;
	367	}
	368
b75f53db	369	static int __init ppro_init(char **cpu_type)
1da177e4 LT	370	{
	371	__u8 cpu_model = boot_cpu_data.x86_model;
	372
4b9f12a3 LT	373	switch (cpu_model) {
	374	case 0 ... 2:
	375	*cpu_type = "i386/ppro";
	376	break;
	377	case 3 ... 5:
	378	*cpu_type = "i386/pii";
	379	break;
	380	case 6 ... 8:
	381	*cpu_type = "i386/piii";
	382	break;
	383	case 9:
	384	*cpu_type = "i386/p6_mobile";
	385	break;
	386	case 10 ... 13:
	387	*cpu_type = "i386/p6";
	388	break;
	389	case 14:
64471ebe	390	*cpu_type = "i386/core";
4b9f12a3 LT	391	break;
	392	case 15: case 23:
	393	*cpu_type = "i386/core_2";
	394	break;
	395	case 26:
f04b92e9	396	*cpu_type = "i386/core_2";
4b9f12a3 LT	397	break;
	398	default:
	399	/* Unknown */
1da177e4	400	return 0;
1da177e4 LT	401	}
	402
	403	model = &op_ppro_spec;
	404	return 1;
	405	}
	406
405ae7d3	407	/* in order to get sysfs right */
1da177e4 LT	408	static int using_nmi;
1da177e4 LT	409
96d0821c	410	int __init op_nmi_init(struct oprofile_operations *ops)
1da177e4 LT	411	{
	412	__u8 vendor = boot_cpu_data.x86_vendor;
	413	__u8 family = boot_cpu_data.x86;
	414	char *cpu_type;
adf5ec0b	415	int ret = 0;
1da177e4 LT	416
	417	if (!cpu_has_apic)
	418	return -ENODEV;
b75f53db	419
1da177e4	420	switch (vendor) {
b75f53db CM	421	case X86_VENDOR_AMD:
b75f53db CM	422	/* Needs to be at least an Athlon (or hammer in 32bit mode) */
1da177e4	423
b75f53db CM	424	switch (family) {
	425	default:
	426	return -ENODEV;
	427	case 6:
	428	model = &op_athlon_spec;
	429	cpu_type = "i386/athlon";
	430	break;
	431	case 0xf:
	432	model = &op_athlon_spec;
	433	/* Actually it could be i386/hammer too, but give
	434	user space an consistent name. */
	435	cpu_type = "x86-64/hammer";
	436	break;
	437	case 0x10:
	438	model = &op_athlon_spec;
	439	cpu_type = "x86-64/family10";
	440	break;
12f2b261 BK	441	case 0x11:
	442	model = &op_athlon_spec;
	443	cpu_type = "x86-64/family11h";
	444	break;
b75f53db CM	445	}
	446	break;
	447
	448	case X86_VENDOR_INTEL:
	449	switch (family) {
	450	/* Pentium IV */
	451	case 0xf:
	452	if (!p4_init(&cpu_type))
1da177e4	453	return -ENODEV;
1da177e4	454	break;
b75f53db CM	455
	456	/* A P6-class processor */
	457	case 6:
	458	if (!ppro_init(&cpu_type))
	459	return -ENODEV;
1da177e4 LT	460	break;
	461
	462	default:
	463	return -ENODEV;
b75f53db CM	464	}
	465	break;
	466
	467	default:
	468	return -ENODEV;
1da177e4 LT	469	}
1da177e4 LT	470
adf5ec0b RR	471	if (model->init)
	472	ret = model->init(ops);
	473	if (ret)
	474	return ret;
	475
405ae7d3	476	init_sysfs();
1da177e4 LT	477	using_nmi = 1;
	478	ops->create_files = nmi_create_files;
	479	ops->setup = nmi_setup;
	480	ops->shutdown = nmi_shutdown;
	481	ops->start = nmi_start;
	482	ops->stop = nmi_stop;
	483	ops->cpu_type = cpu_type;
	484	printk(KERN_INFO "oprofile: using NMI interrupt.\n");
	485	return 0;
	486	}
	487
96d0821c	488	void op_nmi_exit(void)
1da177e4 LT	489	{
1da177e4 LT	490	if (using_nmi)
405ae7d3	491	exit_sysfs();
adf5ec0b RR	492	if (model->exit)
adf5ec0b RR	493	model->exit();
1da177e4	494	}