[deliverable/linux.git] / arch / x86 / oprofile / nmi_int.c

/**
 * @file nmi_int.c
 *
 * @remark Copyright 2002-2008 OProfile authors
 * @remark Read the file COPYING
 *
 * @author John Levon <levon@movementarian.org>
 * @author Robert Richter <robert.richter@amd.com>
 */

#include <linux/init.h>
#include <linux/notifier.h>
#include <linux/smp.h>
#include <linux/oprofile.h>
#include <linux/sysdev.h>
#include <linux/slab.h>
#include <linux/moduleparam.h>
#include <linux/kdebug.h>
#include <linux/cpu.h>
#include <asm/nmi.h>
#include <asm/msr.h>
#include <asm/apic.h>

#include "op_counter.h"
#include "op_x86_model.h"

static struct op_x86_model_spec const *model;
static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
static DEFINE_PER_CPU(unsigned long, saved_lvtpc);

static int nmi_start(void);
static void nmi_stop(void);
static void nmi_cpu_start(void *dummy);
static void nmi_cpu_stop(void *dummy);

/* 0 == registered but off, 1 == registered and on */
static int nmi_enabled = 0;

#ifdef CONFIG_SMP
static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
				 void *data)
{
	int cpu = (unsigned long)data;
	switch (action) {
	case CPU_DOWN_FAILED:
	case CPU_ONLINE:
		smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
		break;
	case CPU_DOWN_PREPARE:
		smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
		break;
	}
	return NOTIFY_DONE;
}

static struct notifier_block oprofile_cpu_nb = {
	.notifier_call = oprofile_cpu_notifier
};
#endif

#ifdef CONFIG_PM

static int nmi_suspend(struct sys_device *dev, pm_message_t state)
{
	/* Only one CPU left, just stop that one */
	if (nmi_enabled == 1)
		nmi_cpu_stop(NULL);
	return 0;
}

static int nmi_resume(struct sys_device *dev)
{
	if (nmi_enabled == 1)
		nmi_cpu_start(NULL);
	return 0;
}

static struct sysdev_class oprofile_sysclass = {
	.name		= "oprofile",
	.resume		= nmi_resume,
	.suspend	= nmi_suspend,
};

static struct sys_device device_oprofile = {
	.id	= 0,
	.cls	= &oprofile_sysclass,
};

static int __init init_sysfs(void)
{
	int error;

	error = sysdev_class_register(&oprofile_sysclass);
	if (!error)
		error = sysdev_register(&device_oprofile);
	return error;
}

static void exit_sysfs(void)
{
	sysdev_unregister(&device_oprofile);
	sysdev_class_unregister(&oprofile_sysclass);
}

#else
#define init_sysfs() do { } while (0)
#define exit_sysfs() do { } while (0)
#endif /* CONFIG_PM */

static int profile_exceptions_notify(struct notifier_block *self,
				     unsigned long val, void *data)
{
	struct die_args *args = (struct die_args *)data;
	int ret = NOTIFY_DONE;
	int cpu = smp_processor_id();

	switch (val) {
	case DIE_NMI:
		if (model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu)))
			ret = NOTIFY_STOP;
		break;
	default:
		break;
	}
	return ret;
}

static void nmi_cpu_save_registers(struct op_msrs *msrs)
{
	unsigned int const nr_ctrs = model->num_counters;
	unsigned int const nr_ctrls = model->num_controls;
	struct op_msr *counters = msrs->counters;
	struct op_msr *controls = msrs->controls;
	unsigned int i;

	for (i = 0; i < nr_ctrs; ++i) {
		if (counters[i].addr) {
			rdmsr(counters[i].addr,
				counters[i].saved.low,
				counters[i].saved.high);
		}
	}

	for (i = 0; i < nr_ctrls; ++i) {
		if (controls[i].addr) {
			rdmsr(controls[i].addr,
				controls[i].saved.low,
				controls[i].saved.high);
		}
	}
}

static void nmi_save_registers(void *dummy)
{
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
	nmi_cpu_save_registers(msrs);
}

static void free_msrs(void)
{
	int i;
	for_each_possible_cpu(i) {
		kfree(per_cpu(cpu_msrs, i).counters);
		per_cpu(cpu_msrs, i).counters = NULL;
		kfree(per_cpu(cpu_msrs, i).controls);
		per_cpu(cpu_msrs, i).controls = NULL;
	}
}

static int allocate_msrs(void)
{
	int success = 1;
	size_t controls_size = sizeof(struct op_msr) * model->num_controls;
	size_t counters_size = sizeof(struct op_msr) * model->num_counters;

	int i;
	for_each_possible_cpu(i) {
		per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
								GFP_KERNEL);
		if (!per_cpu(cpu_msrs, i).counters) {
			success = 0;
			break;
		}
		per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
								GFP_KERNEL);
		if (!per_cpu(cpu_msrs, i).controls) {
			success = 0;
			break;
		}
	}

	if (!success)
		free_msrs();

	return success;
}

static void nmi_cpu_setup(void *dummy)
{
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
	spin_lock(&oprofilefs_lock);
	model->setup_ctrs(msrs);
	spin_unlock(&oprofilefs_lock);
	per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
	apic_write(APIC_LVTPC, APIC_DM_NMI);
}

static struct notifier_block profile_exceptions_nb = {
	.notifier_call = profile_exceptions_notify,
	.next = NULL,
	.priority = 0
};

static int nmi_setup(void)
{
	int err = 0;
	int cpu;

	if (!allocate_msrs())
		return -ENOMEM;

	err = register_die_notifier(&profile_exceptions_nb);
	if (err) {
		free_msrs();
		return err;
	}

	/* We need to serialize save and setup for HT because the subset
	 * of msrs are distinct for save and setup operations
	 */

	/* Assume saved/restored counters are the same on all CPUs */
	model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
	for_each_possible_cpu(cpu) {
		if (cpu != 0) {
			memcpy(per_cpu(cpu_msrs, cpu).counters,
				per_cpu(cpu_msrs, 0).counters,
				sizeof(struct op_msr) * model->num_counters);

			memcpy(per_cpu(cpu_msrs, cpu).controls,
				per_cpu(cpu_msrs, 0).controls,
				sizeof(struct op_msr) * model->num_controls);
		}

	}
	on_each_cpu(nmi_save_registers, NULL, 1);
	on_each_cpu(nmi_cpu_setup, NULL, 1);
	nmi_enabled = 1;
	return 0;
}

static void nmi_restore_registers(struct op_msrs *msrs)
{
	unsigned int const nr_ctrs = model->num_counters;
	unsigned int const nr_ctrls = model->num_controls;
	struct op_msr *counters = msrs->counters;
	struct op_msr *controls = msrs->controls;
	unsigned int i;

	for (i = 0; i < nr_ctrls; ++i) {
		if (controls[i].addr) {
			wrmsr(controls[i].addr,
				controls[i].saved.low,
				controls[i].saved.high);
		}
	}

	for (i = 0; i < nr_ctrs; ++i) {
		if (counters[i].addr) {
			wrmsr(counters[i].addr,
				counters[i].saved.low,
				counters[i].saved.high);
		}
	}
}

static void nmi_cpu_shutdown(void *dummy)
{
	unsigned int v;
	int cpu = smp_processor_id();
	struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);

	/* restoring APIC_LVTPC can trigger an apic error because the delivery
	 * mode and vector nr combination can be illegal. That's by design: on
	 * power on apic lvt contain a zero vector nr which are legal only for
	 * NMI delivery mode. So inhibit apic err before restoring lvtpc
	 */
	v = apic_read(APIC_LVTERR);
	apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
	apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
	apic_write(APIC_LVTERR, v);
	nmi_restore_registers(msrs);
}

static void nmi_shutdown(void)
{
	struct op_msrs *msrs;

	nmi_enabled = 0;
	on_each_cpu(nmi_cpu_shutdown, NULL, 1);
	unregister_die_notifier(&profile_exceptions_nb);
	msrs = &get_cpu_var(cpu_msrs);
	model->shutdown(msrs);
	free_msrs();
	put_cpu_var(cpu_msrs);
}

static void nmi_cpu_start(void *dummy)
{
	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
	model->start(msrs);
}

static int nmi_start(void)
{
	on_each_cpu(nmi_cpu_start, NULL, 1);
	return 0;
}

static void nmi_cpu_stop(void *dummy)
{
	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
	model->stop(msrs);
}

static void nmi_stop(void)
{
	on_each_cpu(nmi_cpu_stop, NULL, 1);
}

struct op_counter_config counter_config[OP_MAX_COUNTER];

static int nmi_create_files(struct super_block *sb, struct dentry *root)
{
	unsigned int i;

	for (i = 0; i < model->num_counters; ++i) {
		struct dentry *dir;
		char buf[4];

		/* quick little hack to _not_ expose a counter if it is not
		 * available for use.  This should protect userspace app.
		 * NOTE:  assumes 1:1 mapping here (that counters are organized
		 *        sequentially in their struct assignment).
		 */
		if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
			continue;

		snprintf(buf,  sizeof(buf), "%d", i);
		dir = oprofilefs_mkdir(sb, root, buf);
		oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
		oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
		oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
		oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
		oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
		oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
	}

	return 0;
}

static int p4force;
module_param(p4force, int, 0);

static int __init p4_init(char **cpu_type)
{
	__u8 cpu_model = boot_cpu_data.x86_model;

	if (!p4force && (cpu_model > 6 || cpu_model == 5))
		return 0;

#ifndef CONFIG_SMP
	*cpu_type = "i386/p4";
	model = &op_p4_spec;
	return 1;
#else
	switch (smp_num_siblings) {
	case 1:
		*cpu_type = "i386/p4";
		model = &op_p4_spec;
		return 1;

	case 2:
		*cpu_type = "i386/p4-ht";
		model = &op_p4_ht2_spec;
		return 1;
	}
#endif

	printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
	printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
	return 0;
}

static int __init ppro_init(char **cpu_type)
{
	__u8 cpu_model = boot_cpu_data.x86_model;

	switch (cpu_model) {
	case 0 ... 2:
		*cpu_type = "i386/ppro";
		break;
	case 3 ... 5:
		*cpu_type = "i386/pii";
		break;
	case 6 ... 8:
		*cpu_type = "i386/piii";
		break;
	case 9:
		*cpu_type = "i386/p6_mobile";
		break;
	case 10 ... 13:
		*cpu_type = "i386/p6";
		break;
	case 14:
		*cpu_type = "i386/core";
		break;
	case 15: case 23:
		*cpu_type = "i386/core_2";
		break;
	default:
		/* Unknown */
		return 0;
	}

	model = &op_ppro_spec;
	return 1;
}

/* in order to get sysfs right */
static int using_nmi;

int __init op_nmi_init(struct oprofile_operations *ops)
{
	__u8 vendor = boot_cpu_data.x86_vendor;
	__u8 family = boot_cpu_data.x86;
	char *cpu_type;
	int ret = 0;

	if (!cpu_has_apic)
		return -ENODEV;

	switch (vendor) {
	case X86_VENDOR_AMD:
		/* Needs to be at least an Athlon (or hammer in 32bit mode) */

		switch (family) {
		default:
			return -ENODEV;
		case 6:
			model = &op_amd_spec;
			cpu_type = "i386/athlon";
			break;
		case 0xf:
			model = &op_amd_spec;
			/* Actually it could be i386/hammer too, but give
			 user space an consistent name. */
			cpu_type = "x86-64/hammer";
			break;
		case 0x10:
			model = &op_amd_spec;
			cpu_type = "x86-64/family10";
			break;
		case 0x11:
			model = &op_amd_spec;
			cpu_type = "x86-64/family11h";
			break;
		}
		break;

	case X86_VENDOR_INTEL:
		switch (family) {
			/* Pentium IV */
		case 0xf:
			if (!p4_init(&cpu_type))
				return -ENODEV;
			break;

			/* A P6-class processor */
		case 6:
			if (!ppro_init(&cpu_type))
				return -ENODEV;
			break;

		default:
			return -ENODEV;
		}
		break;

	default:
		return -ENODEV;
	}

#ifdef CONFIG_SMP
	register_cpu_notifier(&oprofile_cpu_nb);
#endif
	/* default values, can be overwritten by model */
	ops->create_files = nmi_create_files;
	ops->setup = nmi_setup;
	ops->shutdown = nmi_shutdown;
	ops->start = nmi_start;
	ops->stop = nmi_stop;
	ops->cpu_type = cpu_type;

	if (model->init)
		ret = model->init(ops);
	if (ret)
		return ret;

	init_sysfs();
	using_nmi = 1;
	printk(KERN_INFO "oprofile: using NMI interrupt.\n");
	return 0;
}

void op_nmi_exit(void)
{
	if (using_nmi) {
		exit_sysfs();
#ifdef CONFIG_SMP
		unregister_cpu_notifier(&oprofile_cpu_nb);
#endif
	}
	if (model->exit)
		model->exit();
}
Commit	Line	Data
1da177e4 LT	1	/**
	2	* @file nmi_int.c
	3	*
adf5ec0b	4	* @remark Copyright 2002-2008 OProfile authors
1da177e4 LT	5	* @remark Read the file COPYING
	6	*
	7	* @author John Levon <levon@movementarian.org>
adf5ec0b	8	* @author Robert Richter <robert.richter@amd.com>
1da177e4 LT	9	*/
	10
	11	#include <linux/init.h>
	12	#include <linux/notifier.h>
	13	#include <linux/smp.h>
	14	#include <linux/oprofile.h>
	15	#include <linux/sysdev.h>
	16	#include <linux/slab.h>
1cfcea1b	17	#include <linux/moduleparam.h>
1eeb66a1	18	#include <linux/kdebug.h>
80a8c9ff	19	#include <linux/cpu.h>
1da177e4 LT	20	#include <asm/nmi.h>
	21	#include <asm/msr.h>
	22	#include <asm/apic.h>
b75f53db	23
1da177e4 LT	24	#include "op_counter.h"
1da177e4 LT	25	#include "op_x86_model.h"
2fbe7b25	26
b75f53db	27	static struct op_x86_model_spec const *model;
d18d00f5 MT	28	static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
d18d00f5 MT	29	static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
2fbe7b25	30
1da177e4 LT	31	static int nmi_start(void);
1da177e4 LT	32	static void nmi_stop(void);
80a8c9ff AK	33	static void nmi_cpu_start(void *dummy);
80a8c9ff AK	34	static void nmi_cpu_stop(void *dummy);
1da177e4 LT	35
	36	/* 0 == registered but off, 1 == registered and on */
	37	static int nmi_enabled = 0;
	38
80a8c9ff AK	39	#ifdef CONFIG_SMP
	40	static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
	41	void *data)
	42	{
	43	int cpu = (unsigned long)data;
	44	switch (action) {
	45	case CPU_DOWN_FAILED:
	46	case CPU_ONLINE:
	47	smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
	48	break;
	49	case CPU_DOWN_PREPARE:
	50	smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
	51	break;
	52	}
	53	return NOTIFY_DONE;
	54	}
	55
	56	static struct notifier_block oprofile_cpu_nb = {
	57	.notifier_call = oprofile_cpu_notifier
	58	};
	59	#endif
	60
1da177e4 LT	61	#ifdef CONFIG_PM
1da177e4 LT	62
438510f6	63	static int nmi_suspend(struct sys_device *dev, pm_message_t state)
1da177e4	64	{
80a8c9ff	65	/* Only one CPU left, just stop that one */
1da177e4	66	if (nmi_enabled == 1)
80a8c9ff	67	nmi_cpu_stop(NULL);
1da177e4 LT	68	return 0;
	69	}
	70
1da177e4 LT	71	static int nmi_resume(struct sys_device *dev)
	72	{
	73	if (nmi_enabled == 1)
80a8c9ff	74	nmi_cpu_start(NULL);
1da177e4 LT	75	return 0;
	76	}
	77
1da177e4	78	static struct sysdev_class oprofile_sysclass = {
af5ca3f4	79	.name = "oprofile",
1da177e4 LT	80	.resume = nmi_resume,
	81	.suspend = nmi_suspend,
	82	};
	83
1da177e4 LT	84	static struct sys_device device_oprofile = {
	85	.id = 0,
	86	.cls = &oprofile_sysclass,
	87	};
	88
405ae7d3	89	static int __init init_sysfs(void)
1da177e4 LT	90	{
1da177e4 LT	91	int error;
b75f53db CM	92
	93	error = sysdev_class_register(&oprofile_sysclass);
	94	if (!error)
1da177e4 LT	95	error = sysdev_register(&device_oprofile);
	96	return error;
	97	}
	98
405ae7d3	99	static void exit_sysfs(void)
1da177e4 LT	100	{
	101	sysdev_unregister(&device_oprofile);
	102	sysdev_class_unregister(&oprofile_sysclass);
	103	}
	104
	105	#else
405ae7d3 RD	106	#define init_sysfs() do { } while (0)
405ae7d3 RD	107	#define exit_sysfs() do { } while (0)
1da177e4 LT	108	#endif /* CONFIG_PM */
1da177e4 LT	109
c7c19f8e AB	110	static int profile_exceptions_notify(struct notifier_block *self,
c7c19f8e AB	111	unsigned long val, void *data)
1da177e4	112	{
2fbe7b25 DZ	113	struct die_args args = (struct die_args )data;
	114	int ret = NOTIFY_DONE;
	115	int cpu = smp_processor_id();
	116
b75f53db	117	switch (val) {
2fbe7b25	118	case DIE_NMI:
d18d00f5	119	if (model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu)))
2fbe7b25 DZ	120	ret = NOTIFY_STOP;
	121	break;
	122	default:
	123	break;
	124	}
	125	return ret;
1da177e4	126	}
2fbe7b25	127
b75f53db	128	static void nmi_cpu_save_registers(struct op_msrs *msrs)
1da177e4 LT	129	{
1da177e4 LT	130	unsigned int const nr_ctrs = model->num_counters;
b75f53db CM	131	unsigned int const nr_ctrls = model->num_controls;
	132	struct op_msr *counters = msrs->counters;
	133	struct op_msr *controls = msrs->controls;
1da177e4 LT	134	unsigned int i;
	135
	136	for (i = 0; i < nr_ctrs; ++i) {
b75f53db	137	if (counters[i].addr) {
cb9c448c DZ	138	rdmsr(counters[i].addr,
	139	counters[i].saved.low,
	140	counters[i].saved.high);
	141	}
1da177e4	142	}
b75f53db	143
1da177e4	144	for (i = 0; i < nr_ctrls; ++i) {
b75f53db	145	if (controls[i].addr) {
cb9c448c DZ	146	rdmsr(controls[i].addr,
	147	controls[i].saved.low,
	148	controls[i].saved.high);
	149	}
1da177e4 LT	150	}
	151	}
	152
b75f53db	153	static void nmi_save_registers(void *dummy)
1da177e4 LT	154	{
1da177e4 LT	155	int cpu = smp_processor_id();
d18d00f5	156	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
1da177e4 LT	157	nmi_cpu_save_registers(msrs);
	158	}
	159
1da177e4 LT	160	static void free_msrs(void)
	161	{
	162	int i;
c8912599	163	for_each_possible_cpu(i) {
d18d00f5 MT	164	kfree(per_cpu(cpu_msrs, i).counters);
	165	per_cpu(cpu_msrs, i).counters = NULL;
	166	kfree(per_cpu(cpu_msrs, i).controls);
	167	per_cpu(cpu_msrs, i).controls = NULL;
1da177e4 LT	168	}
	169	}
	170
1da177e4 LT	171	static int allocate_msrs(void)
1da177e4 LT	172	{
4c168eaf	173	int success = 1;
1da177e4 LT	174	size_t controls_size = sizeof(struct op_msr) * model->num_controls;
	175	size_t counters_size = sizeof(struct op_msr) * model->num_counters;
	176
4c168eaf	177	int i;
0939c17c	178	for_each_possible_cpu(i) {
d18d00f5 MT	179	per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
	180	GFP_KERNEL);
	181	if (!per_cpu(cpu_msrs, i).counters) {
1da177e4 LT	182	success = 0;
	183	break;
	184	}
4c168eaf RR	185	per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
4c168eaf RR	186	GFP_KERNEL);
d18d00f5	187	if (!per_cpu(cpu_msrs, i).controls) {
1da177e4 LT	188	success = 0;
	189	break;
	190	}
	191	}
	192
	193	if (!success)
	194	free_msrs();
	195
	196	return success;
	197	}
	198
b75f53db	199	static void nmi_cpu_setup(void *dummy)
1da177e4 LT	200	{
1da177e4 LT	201	int cpu = smp_processor_id();
d18d00f5	202	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
1da177e4 LT	203	spin_lock(&oprofilefs_lock);
	204	model->setup_ctrs(msrs);
	205	spin_unlock(&oprofilefs_lock);
d18d00f5	206	per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
1da177e4 LT	207	apic_write(APIC_LVTPC, APIC_DM_NMI);
	208	}
	209
2fbe7b25 DZ	210	static struct notifier_block profile_exceptions_nb = {
	211	.notifier_call = profile_exceptions_notify,
	212	.next = NULL,
	213	.priority = 0
	214	};
1da177e4 LT	215
	216	static int nmi_setup(void)
	217	{
b75f53db	218	int err = 0;
6c977aad	219	int cpu;
2fbe7b25	220
1da177e4 LT	221	if (!allocate_msrs())
	222	return -ENOMEM;
	223
b75f53db CM	224	err = register_die_notifier(&profile_exceptions_nb);
b75f53db CM	225	if (err) {
1da177e4	226	free_msrs();
2fbe7b25	227	return err;
1da177e4	228	}
2fbe7b25	229
4c168eaf	230	/* We need to serialize save and setup for HT because the subset
1da177e4 LT	231	* of msrs are distinct for save and setup operations
1da177e4 LT	232	*/
6c977aad AK	233
6c977aad AK	234	/* Assume saved/restored counters are the same on all CPUs */
d18d00f5	235	model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
b75f53db	236	for_each_possible_cpu(cpu) {
0939c17c	237	if (cpu != 0) {
d18d00f5 MT	238	memcpy(per_cpu(cpu_msrs, cpu).counters,
d18d00f5 MT	239	per_cpu(cpu_msrs, 0).counters,
0939c17c CW	240	sizeof(struct op_msr) * model->num_counters);
0939c17c CW	241
d18d00f5 MT	242	memcpy(per_cpu(cpu_msrs, cpu).controls,
d18d00f5 MT	243	per_cpu(cpu_msrs, 0).controls,
0939c17c CW	244	sizeof(struct op_msr) * model->num_controls);
0939c17c CW	245	}
4c168eaf	246
6c977aad	247	}
15c8b6c1 JA	248	on_each_cpu(nmi_save_registers, NULL, 1);
15c8b6c1 JA	249	on_each_cpu(nmi_cpu_setup, NULL, 1);
1da177e4 LT	250	nmi_enabled = 1;
	251	return 0;
	252	}
	253
4c168eaf	254	static void nmi_restore_registers(struct op_msrs *msrs)
1da177e4 LT	255	{
1da177e4 LT	256	unsigned int const nr_ctrs = model->num_counters;
b75f53db CM	257	unsigned int const nr_ctrls = model->num_controls;
	258	struct op_msr *counters = msrs->counters;
	259	struct op_msr *controls = msrs->controls;
1da177e4 LT	260	unsigned int i;
	261
	262	for (i = 0; i < nr_ctrls; ++i) {
b75f53db	263	if (controls[i].addr) {
cb9c448c DZ	264	wrmsr(controls[i].addr,
	265	controls[i].saved.low,
	266	controls[i].saved.high);
	267	}
1da177e4	268	}
b75f53db	269
1da177e4	270	for (i = 0; i < nr_ctrs; ++i) {
b75f53db	271	if (counters[i].addr) {
cb9c448c DZ	272	wrmsr(counters[i].addr,
	273	counters[i].saved.low,
	274	counters[i].saved.high);
	275	}
1da177e4 LT	276	}
1da177e4 LT	277	}
1da177e4	278
b75f53db	279	static void nmi_cpu_shutdown(void *dummy)
1da177e4 LT	280	{
	281	unsigned int v;
	282	int cpu = smp_processor_id();
d18d00f5	283	struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);
b75f53db	284
1da177e4 LT	285	/* restoring APIC_LVTPC can trigger an apic error because the delivery
	286	* mode and vector nr combination can be illegal. That's by design: on
	287	* power on apic lvt contain a zero vector nr which are legal only for
	288	* NMI delivery mode. So inhibit apic err before restoring lvtpc
	289	*/
	290	v = apic_read(APIC_LVTERR);
	291	apic_write(APIC_LVTERR, v \| APIC_LVT_MASKED);
d18d00f5	292	apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
1da177e4	293	apic_write(APIC_LVTERR, v);
4c168eaf	294	nmi_restore_registers(msrs);
1da177e4 LT	295	}
1da177e4 LT	296
1da177e4 LT	297	static void nmi_shutdown(void)
1da177e4 LT	298	{
b61e06f2 AR	299	struct op_msrs *msrs;
b61e06f2 AR	300
1da177e4	301	nmi_enabled = 0;
15c8b6c1	302	on_each_cpu(nmi_cpu_shutdown, NULL, 1);
2fbe7b25	303	unregister_die_notifier(&profile_exceptions_nb);
b61e06f2	304	msrs = &get_cpu_var(cpu_msrs);
d18d00f5	305	model->shutdown(msrs);
1da177e4	306	free_msrs();
93e1ade5	307	put_cpu_var(cpu_msrs);
1da177e4 LT	308	}
1da177e4 LT	309
b75f53db	310	static void nmi_cpu_start(void *dummy)
1da177e4	311	{
d18d00f5	312	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
1da177e4 LT	313	model->start(msrs);
1da177e4 LT	314	}
1da177e4 LT	315
	316	static int nmi_start(void)
	317	{
15c8b6c1	318	on_each_cpu(nmi_cpu_start, NULL, 1);
1da177e4 LT	319	return 0;
1da177e4 LT	320	}
b75f53db CM	321
b75f53db CM	322	static void nmi_cpu_stop(void *dummy)
1da177e4	323	{
d18d00f5	324	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
1da177e4 LT	325	model->stop(msrs);
1da177e4 LT	326	}
b75f53db	327
1da177e4 LT	328	static void nmi_stop(void)
1da177e4 LT	329	{
15c8b6c1	330	on_each_cpu(nmi_cpu_stop, NULL, 1);
1da177e4 LT	331	}
1da177e4 LT	332
1da177e4 LT	333	struct op_counter_config counter_config[OP_MAX_COUNTER];
1da177e4 LT	334
b75f53db	335	static int nmi_create_files(struct super_block sb, struct dentry root)
1da177e4 LT	336	{
	337	unsigned int i;
	338
	339	for (i = 0; i < model->num_counters; ++i) {
b75f53db	340	struct dentry *dir;
0c6856f7	341	char buf[4];
b75f53db CM	342
b75f53db CM	343	/* quick little hack to _not_ expose a counter if it is not
cb9c448c DZ	344	* available for use. This should protect userspace app.
	345	* NOTE: assumes 1:1 mapping here (that counters are organized
	346	* sequentially in their struct assignment).
	347	*/
	348	if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
	349	continue;
	350
0c6856f7	351	snprintf(buf, sizeof(buf), "%d", i);
1da177e4	352	dir = oprofilefs_mkdir(sb, root, buf);
b75f53db CM	353	oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
	354	oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
	355	oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
	356	oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
	357	oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
	358	oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
1da177e4 LT	359	}
	360
	361	return 0;
	362	}
b75f53db	363
1cfcea1b AK	364	static int p4force;
1cfcea1b AK	365	module_param(p4force, int, 0);
b75f53db CM	366
b75f53db CM	367	static int __init p4_init(char **cpu_type)
1da177e4 LT	368	{
	369	__u8 cpu_model = boot_cpu_data.x86_model;
	370
1cfcea1b	371	if (!p4force && (cpu_model > 6 \|\| cpu_model == 5))
1da177e4 LT	372	return 0;
	373
	374	#ifndef CONFIG_SMP
	375	*cpu_type = "i386/p4";
	376	model = &op_p4_spec;
	377	return 1;
	378	#else
	379	switch (smp_num_siblings) {
b75f53db CM	380	case 1:
	381	*cpu_type = "i386/p4";
	382	model = &op_p4_spec;
	383	return 1;
	384
	385	case 2:
	386	*cpu_type = "i386/p4-ht";
	387	model = &op_p4_ht2_spec;
	388	return 1;
1da177e4 LT	389	}
	390	#endif
	391
	392	printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
	393	printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
	394	return 0;
	395	}
	396
b75f53db	397	static int __init ppro_init(char **cpu_type)
1da177e4 LT	398	{
	399	__u8 cpu_model = boot_cpu_data.x86_model;
	400
4b9f12a3 LT	401	switch (cpu_model) {
	402	case 0 ... 2:
	403	*cpu_type = "i386/ppro";
	404	break;
	405	case 3 ... 5:
	406	*cpu_type = "i386/pii";
	407	break;
	408	case 6 ... 8:
	409	*cpu_type = "i386/piii";
	410	break;
	411	case 9:
	412	*cpu_type = "i386/p6_mobile";
	413	break;
	414	case 10 ... 13:
	415	*cpu_type = "i386/p6";
	416	break;
	417	case 14:
64471ebe	418	*cpu_type = "i386/core";
4b9f12a3 LT	419	break;
	420	case 15: case 23:
	421	*cpu_type = "i386/core_2";
	422	break;
4b9f12a3 LT	423	default:
4b9f12a3 LT	424	/* Unknown */
1da177e4	425	return 0;
1da177e4 LT	426	}
	427
	428	model = &op_ppro_spec;
	429	return 1;
	430	}
	431
405ae7d3	432	/* in order to get sysfs right */
1da177e4 LT	433	static int using_nmi;
1da177e4 LT	434
96d0821c	435	int __init op_nmi_init(struct oprofile_operations *ops)
1da177e4 LT	436	{
	437	__u8 vendor = boot_cpu_data.x86_vendor;
	438	__u8 family = boot_cpu_data.x86;
	439	char *cpu_type;
adf5ec0b	440	int ret = 0;
1da177e4 LT	441
	442	if (!cpu_has_apic)
	443	return -ENODEV;
b75f53db	444
1da177e4	445	switch (vendor) {
b75f53db CM	446	case X86_VENDOR_AMD:
b75f53db CM	447	/* Needs to be at least an Athlon (or hammer in 32bit mode) */
1da177e4	448
b75f53db CM	449	switch (family) {
	450	default:
	451	return -ENODEV;
	452	case 6:
6657fe4f	453	model = &op_amd_spec;
b75f53db CM	454	cpu_type = "i386/athlon";
	455	break;
	456	case 0xf:
6657fe4f	457	model = &op_amd_spec;
b75f53db CM	458	/* Actually it could be i386/hammer too, but give
	459	user space an consistent name. */
	460	cpu_type = "x86-64/hammer";
	461	break;
	462	case 0x10:
6657fe4f	463	model = &op_amd_spec;
b75f53db CM	464	cpu_type = "x86-64/family10";
b75f53db CM	465	break;
12f2b261	466	case 0x11:
6657fe4f	467	model = &op_amd_spec;
12f2b261 BK	468	cpu_type = "x86-64/family11h";
12f2b261 BK	469	break;
b75f53db CM	470	}
	471	break;
	472
	473	case X86_VENDOR_INTEL:
	474	switch (family) {
	475	/* Pentium IV */
	476	case 0xf:
	477	if (!p4_init(&cpu_type))
1da177e4	478	return -ENODEV;
1da177e4	479	break;
b75f53db CM	480
	481	/* A P6-class processor */
	482	case 6:
	483	if (!ppro_init(&cpu_type))
	484	return -ENODEV;
1da177e4 LT	485	break;
	486
	487	default:
	488	return -ENODEV;
b75f53db CM	489	}
	490	break;
	491
	492	default:
	493	return -ENODEV;
1da177e4 LT	494	}
1da177e4 LT	495
80a8c9ff AK	496	#ifdef CONFIG_SMP
	497	register_cpu_notifier(&oprofile_cpu_nb);
	498	#endif
270d3e1a RR	499	/* default values, can be overwritten by model */
	500	ops->create_files = nmi_create_files;
	501	ops->setup = nmi_setup;
	502	ops->shutdown = nmi_shutdown;
	503	ops->start = nmi_start;
	504	ops->stop = nmi_stop;
	505	ops->cpu_type = cpu_type;
	506
adf5ec0b RR	507	if (model->init)
	508	ret = model->init(ops);
	509	if (ret)
	510	return ret;
	511
405ae7d3	512	init_sysfs();
1da177e4	513	using_nmi = 1;
1da177e4 LT	514	printk(KERN_INFO "oprofile: using NMI interrupt.\n");
	515	return 0;
	516	}
	517
96d0821c	518	void op_nmi_exit(void)
1da177e4	519	{
80a8c9ff	520	if (using_nmi) {
405ae7d3	521	exit_sysfs();
80a8c9ff AK	522	#ifdef CONFIG_SMP
	523	unregister_cpu_notifier(&oprofile_cpu_nb);
	524	#endif
	525	}
adf5ec0b RR	526	if (model->exit)
adf5ec0b RR	527	model->exit();
1da177e4	528	}