Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | #include <linux/init.h> |
2 | #include <linux/pci.h> | |
d199a048 | 3 | #include <linux/topology.h> |
91ede005 | 4 | #include <linux/cpu.h> |
27811d8c YL |
5 | #include <linux/range.h> |
6 | ||
24d9b70b | 7 | #include <asm/amd_nb.h> |
82487711 | 8 | #include <asm/pci_x86.h> |
3a27dd1c | 9 | |
871d5f8d | 10 | #include <asm/pci-direct.h> |
1da177e4 | 11 | |
99935a7a YL |
12 | #include "bus_numa.h" |
13 | ||
9e7f7231 SS |
14 | #define AMD_NB_F0_NODE_ID 0x60 |
15 | #define AMD_NB_F0_UNIT_ID 0x64 | |
16 | #define AMD_NB_F1_CONFIG_MAP_REG 0xe0 | |
17 | ||
18 | #define RANGE_NUM 16 | |
19 | #define AMD_NB_F1_CONFIG_MAP_RANGES 4 | |
1da177e4 | 20 | |
9e7f7231 | 21 | struct amd_hostbridge { |
30a18d6c YL |
22 | u32 bus; |
23 | u32 slot; | |
30a18d6c YL |
24 | u32 device; |
25 | }; | |
26 | ||
9e7f7231 SS |
27 | /* |
28 | * IMPORTANT NOTE: | |
29 | * hb_probes[] and early_root_info_init() is in maintenance mode. | |
30 | * It only supports K8, Fam10h, Fam11h, and Fam15h_00h-0fh . | |
31 | * Future processor will rely on information in ACPI. | |
32 | */ | |
33 | static struct amd_hostbridge hb_probes[] __initdata = { | |
34 | { 0, 0x18, 0x1100 }, /* K8 */ | |
35 | { 0, 0x18, 0x1200 }, /* Family10h */ | |
36 | { 0xff, 0, 0x1200 }, /* Family10h */ | |
37 | { 0, 0x18, 0x1300 }, /* Family11h */ | |
38 | { 0, 0x18, 0x1600 }, /* Family15h */ | |
30a18d6c YL |
39 | }; |
40 | ||
d28e5ac2 YL |
41 | static struct pci_root_info __init *find_pci_root_info(int node, int link) |
42 | { | |
43 | struct pci_root_info *info; | |
44 | ||
45 | /* find the position */ | |
46 | list_for_each_entry(info, &pci_root_infos, list) | |
47 | if (info->node == node && info->link == link) | |
48 | return info; | |
49 | ||
50 | return NULL; | |
51 | } | |
52 | ||
1da177e4 | 53 | /** |
9e7f7231 | 54 | * early_root_info_init() |
871d5f8d | 55 | * called before pcibios_scan_root and pci_scan_bus |
9e7f7231 SS |
56 | * fills the mp_bus_to_cpumask array based according |
57 | * to the LDT Bus Number Registers found in the northbridge. | |
1da177e4 | 58 | */ |
9e7f7231 | 59 | static int __init early_root_info_init(void) |
1da177e4 | 60 | { |
30a18d6c | 61 | int i; |
30a18d6c | 62 | unsigned bus; |
871d5f8d | 63 | unsigned slot; |
35ddd068 | 64 | int node; |
30a18d6c YL |
65 | int link; |
66 | int def_node; | |
67 | int def_link; | |
68 | struct pci_root_info *info; | |
69 | u32 reg; | |
97445c3b YL |
70 | u64 start; |
71 | u64 end; | |
27811d8c | 72 | struct range range[RANGE_NUM]; |
30a18d6c YL |
73 | u64 val; |
74 | u32 address; | |
3e3da00c | 75 | bool found; |
24d25dbf BH |
76 | struct resource fam10h_mmconf_res, *fam10h_mmconf; |
77 | u64 fam10h_mmconf_start; | |
78 | u64 fam10h_mmconf_end; | |
1da177e4 | 79 | |
871d5f8d YL |
80 | if (!early_pci_allowed()) |
81 | return -1; | |
82 | ||
3e3da00c | 83 | found = false; |
9e7f7231 | 84 | for (i = 0; i < ARRAY_SIZE(hb_probes); i++) { |
30a18d6c YL |
85 | u32 id; |
86 | u16 device; | |
87 | u16 vendor; | |
35ddd068 | 88 | |
9e7f7231 SS |
89 | bus = hb_probes[i].bus; |
90 | slot = hb_probes[i].slot; | |
30a18d6c | 91 | id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID); |
30a18d6c YL |
92 | vendor = id & 0xffff; |
93 | device = (id>>16) & 0xffff; | |
9e7f7231 SS |
94 | |
95 | if (vendor != PCI_VENDOR_ID_AMD) | |
96 | continue; | |
97 | ||
98 | if (hb_probes[i].device == device) { | |
3e3da00c | 99 | found = true; |
30a18d6c YL |
100 | break; |
101 | } | |
102 | } | |
103 | ||
3e3da00c | 104 | if (!found) |
30a18d6c | 105 | return 0; |
35ddd068 | 106 | |
94d4bb5b SS |
107 | /* |
108 | * We should learn topology and routing information from _PXM and | |
109 | * _CRS methods in the ACPI namespace. We extract node numbers | |
110 | * here to work around BIOSes that don't supply _PXM. | |
111 | */ | |
9e7f7231 | 112 | for (i = 0; i < AMD_NB_F1_CONFIG_MAP_RANGES; i++) { |
30a18d6c YL |
113 | int min_bus; |
114 | int max_bus; | |
9e7f7231 SS |
115 | reg = read_pci_config(bus, slot, 1, |
116 | AMD_NB_F1_CONFIG_MAP_REG + (i << 2)); | |
35ddd068 YL |
117 | |
118 | /* Check if that register is enabled for bus range */ | |
30a18d6c | 119 | if ((reg & 7) != 3) |
35ddd068 YL |
120 | continue; |
121 | ||
30a18d6c YL |
122 | min_bus = (reg >> 16) & 0xff; |
123 | max_bus = (reg >> 24) & 0xff; | |
124 | node = (reg >> 4) & 0x07; | |
30a18d6c YL |
125 | link = (reg >> 8) & 0x03; |
126 | ||
d28e5ac2 | 127 | info = alloc_pci_root_info(min_bus, max_bus, node, link); |
1da177e4 LT |
128 | } |
129 | ||
94d4bb5b SS |
130 | /* |
131 | * The following code extracts routing information for use on old | |
132 | * systems where Linux doesn't automatically use host bridge _CRS | |
133 | * methods (or when the user specifies "pci=nocrs"). | |
134 | * | |
135 | * We only do this through Fam11h, because _CRS should be enough on | |
136 | * newer systems. | |
137 | */ | |
138 | if (boot_cpu_data.x86 > 0x11) | |
139 | return 0; | |
140 | ||
30a18d6c | 141 | /* get the default node and link for left over res */ |
9e7f7231 | 142 | reg = read_pci_config(bus, slot, 0, AMD_NB_F0_NODE_ID); |
30a18d6c | 143 | def_node = (reg >> 8) & 0x07; |
9e7f7231 | 144 | reg = read_pci_config(bus, slot, 0, AMD_NB_F0_UNIT_ID); |
30a18d6c YL |
145 | def_link = (reg >> 8) & 0x03; |
146 | ||
147 | memset(range, 0, sizeof(range)); | |
e9a0064a | 148 | add_range(range, RANGE_NUM, 0, 0, 0xffff + 1); |
30a18d6c YL |
149 | /* io port resource */ |
150 | for (i = 0; i < 4; i++) { | |
151 | reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3)); | |
152 | if (!(reg & 3)) | |
153 | continue; | |
154 | ||
155 | start = reg & 0xfff000; | |
156 | reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3)); | |
157 | node = reg & 0x07; | |
158 | link = (reg >> 4) & 0x03; | |
159 | end = (reg & 0xfff000) | 0xfff; | |
160 | ||
d28e5ac2 YL |
161 | info = find_pci_root_info(node, link); |
162 | if (!info) | |
30a18d6c YL |
163 | continue; /* not found */ |
164 | ||
6e184f29 | 165 | printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n", |
97445c3b | 166 | node, link, start, end); |
e8ee6f0a YL |
167 | |
168 | /* kernel only handle 16 bit only */ | |
169 | if (end > 0xffff) | |
170 | end = 0xffff; | |
171 | update_res(info, start, end, IORESOURCE_IO, 1); | |
e9a0064a | 172 | subtract_range(range, RANGE_NUM, start, end + 1); |
30a18d6c YL |
173 | } |
174 | /* add left over io port range to def node/link, [0, 0xffff] */ | |
175 | /* find the position */ | |
d28e5ac2 YL |
176 | info = find_pci_root_info(def_node, def_link); |
177 | if (info) { | |
30a18d6c YL |
178 | for (i = 0; i < RANGE_NUM; i++) { |
179 | if (!range[i].end) | |
180 | continue; | |
181 | ||
e9a0064a | 182 | update_res(info, range[i].start, range[i].end - 1, |
30a18d6c YL |
183 | IORESOURCE_IO, 1); |
184 | } | |
185 | } | |
186 | ||
187 | memset(range, 0, sizeof(range)); | |
188 | /* 0xfd00000000-0xffffffffff for HT */ | |
e9a0064a YL |
189 | end = cap_resource((0xfdULL<<32) - 1); |
190 | end++; | |
191 | add_range(range, RANGE_NUM, 0, 0, end); | |
30a18d6c YL |
192 | |
193 | /* need to take out [0, TOM) for RAM*/ | |
194 | address = MSR_K8_TOP_MEM1; | |
195 | rdmsrl(address, val); | |
8004dd96 | 196 | end = (val & 0xffffff800000ULL); |
97445c3b | 197 | printk(KERN_INFO "TOM: %016llx aka %lldM\n", end, end>>20); |
30a18d6c | 198 | if (end < (1ULL<<32)) |
e9a0064a | 199 | subtract_range(range, RANGE_NUM, 0, end); |
30a18d6c | 200 | |
6e184f29 | 201 | /* get mmconfig */ |
24d25dbf | 202 | fam10h_mmconf = amd_get_mmconfig_range(&fam10h_mmconf_res); |
6e184f29 | 203 | /* need to take out mmconf range */ |
24d25dbf BH |
204 | if (fam10h_mmconf) { |
205 | printk(KERN_DEBUG "Fam 10h mmconf %pR\n", fam10h_mmconf); | |
206 | fam10h_mmconf_start = fam10h_mmconf->start; | |
207 | fam10h_mmconf_end = fam10h_mmconf->end; | |
e9a0064a YL |
208 | subtract_range(range, RANGE_NUM, fam10h_mmconf_start, |
209 | fam10h_mmconf_end + 1); | |
24d25dbf BH |
210 | } else { |
211 | fam10h_mmconf_start = 0; | |
212 | fam10h_mmconf_end = 0; | |
6e184f29 YL |
213 | } |
214 | ||
30a18d6c YL |
215 | /* mmio resource */ |
216 | for (i = 0; i < 8; i++) { | |
217 | reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3)); | |
218 | if (!(reg & 3)) | |
219 | continue; | |
220 | ||
221 | start = reg & 0xffffff00; /* 39:16 on 31:8*/ | |
222 | start <<= 8; | |
223 | reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3)); | |
224 | node = reg & 0x07; | |
225 | link = (reg >> 4) & 0x03; | |
226 | end = (reg & 0xffffff00); | |
227 | end <<= 8; | |
228 | end |= 0xffff; | |
229 | ||
d28e5ac2 | 230 | info = find_pci_root_info(node, link); |
30a18d6c | 231 | |
d28e5ac2 YL |
232 | if (!info) |
233 | continue; | |
6e184f29 YL |
234 | |
235 | printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]", | |
97445c3b | 236 | node, link, start, end); |
6e184f29 YL |
237 | /* |
238 | * some sick allocation would have range overlap with fam10h | |
239 | * mmconf range, so need to update start and end. | |
240 | */ | |
241 | if (fam10h_mmconf_end) { | |
242 | int changed = 0; | |
243 | u64 endx = 0; | |
244 | if (start >= fam10h_mmconf_start && | |
245 | start <= fam10h_mmconf_end) { | |
246 | start = fam10h_mmconf_end + 1; | |
247 | changed = 1; | |
248 | } | |
249 | ||
250 | if (end >= fam10h_mmconf_start && | |
251 | end <= fam10h_mmconf_end) { | |
252 | end = fam10h_mmconf_start - 1; | |
253 | changed = 1; | |
254 | } | |
255 | ||
256 | if (start < fam10h_mmconf_start && | |
257 | end > fam10h_mmconf_end) { | |
258 | /* we got a hole */ | |
259 | endx = fam10h_mmconf_start - 1; | |
260 | update_res(info, start, endx, IORESOURCE_MEM, 0); | |
e9a0064a YL |
261 | subtract_range(range, RANGE_NUM, start, |
262 | endx + 1); | |
97445c3b | 263 | printk(KERN_CONT " ==> [%llx, %llx]", start, endx); |
6e184f29 YL |
264 | start = fam10h_mmconf_end + 1; |
265 | changed = 1; | |
266 | } | |
267 | if (changed) { | |
268 | if (start <= end) { | |
97445c3b | 269 | printk(KERN_CONT " %s [%llx, %llx]", endx ? "and" : "==>", start, end); |
6e184f29 YL |
270 | } else { |
271 | printk(KERN_CONT "%s\n", endx?"":" ==> none"); | |
272 | continue; | |
273 | } | |
274 | } | |
275 | } | |
276 | ||
9ad3f2c7 YL |
277 | update_res(info, cap_resource(start), cap_resource(end), |
278 | IORESOURCE_MEM, 1); | |
e9a0064a | 279 | subtract_range(range, RANGE_NUM, start, end + 1); |
6e184f29 | 280 | printk(KERN_CONT "\n"); |
30a18d6c YL |
281 | } |
282 | ||
283 | /* need to take out [4G, TOM2) for RAM*/ | |
284 | /* SYS_CFG */ | |
285 | address = MSR_K8_SYSCFG; | |
286 | rdmsrl(address, val); | |
287 | /* TOP_MEM2 is enabled? */ | |
288 | if (val & (1<<21)) { | |
289 | /* TOP_MEM2 */ | |
290 | address = MSR_K8_TOP_MEM2; | |
291 | rdmsrl(address, val); | |
8004dd96 | 292 | end = (val & 0xffffff800000ULL); |
97445c3b | 293 | printk(KERN_INFO "TOM2: %016llx aka %lldM\n", end, end>>20); |
e9a0064a | 294 | subtract_range(range, RANGE_NUM, 1ULL<<32, end); |
30a18d6c YL |
295 | } |
296 | ||
297 | /* | |
298 | * add left over mmio range to def node/link ? | |
299 | * that is tricky, just record range in from start_min to 4G | |
300 | */ | |
d28e5ac2 YL |
301 | info = find_pci_root_info(def_node, def_link); |
302 | if (info) { | |
30a18d6c YL |
303 | for (i = 0; i < RANGE_NUM; i++) { |
304 | if (!range[i].end) | |
305 | continue; | |
306 | ||
9ad3f2c7 | 307 | update_res(info, cap_resource(range[i].start), |
e9a0064a | 308 | cap_resource(range[i].end - 1), |
30a18d6c YL |
309 | IORESOURCE_MEM, 1); |
310 | } | |
311 | } | |
312 | ||
d28e5ac2 | 313 | list_for_each_entry(info, &pci_root_infos, list) { |
30a18d6c | 314 | int busnum; |
d28e5ac2 | 315 | struct pci_root_res *root_res; |
30a18d6c | 316 | |
a10bb128 YL |
317 | busnum = info->busn.start; |
318 | printk(KERN_DEBUG "bus: %pR on node %x link %x\n", | |
319 | &info->busn, info->node, info->link); | |
d28e5ac2 YL |
320 | list_for_each_entry(root_res, &info->resources, list) |
321 | printk(KERN_DEBUG "bus: %02x %pR\n", | |
322 | busnum, &root_res->res); | |
30a18d6c YL |
323 | } |
324 | ||
1da177e4 LT |
325 | return 0; |
326 | } | |
327 | ||
3a27dd1c RR |
328 | #define ENABLE_CF8_EXT_CFG (1ULL << 46) |
329 | ||
148f9bb8 | 330 | static void enable_pci_io_ecs(void *unused) |
3a27dd1c RR |
331 | { |
332 | u64 reg; | |
333 | rdmsrl(MSR_AMD64_NB_CFG, reg); | |
334 | if (!(reg & ENABLE_CF8_EXT_CFG)) { | |
335 | reg |= ENABLE_CF8_EXT_CFG; | |
336 | wrmsrl(MSR_AMD64_NB_CFG, reg); | |
337 | } | |
338 | } | |
339 | ||
148f9bb8 PG |
340 | static int amd_cpu_notify(struct notifier_block *self, unsigned long action, |
341 | void *hcpu) | |
3a27dd1c | 342 | { |
91ede005 | 343 | int cpu = (long)hcpu; |
ed21763e | 344 | switch (action) { |
91ede005 RR |
345 | case CPU_ONLINE: |
346 | case CPU_ONLINE_FROZEN: | |
347 | smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0); | |
348 | break; | |
349 | default: | |
350 | break; | |
351 | } | |
352 | return NOTIFY_OK; | |
353 | } | |
354 | ||
148f9bb8 | 355 | static struct notifier_block amd_cpu_notifier = { |
91ede005 RR |
356 | .notifier_call = amd_cpu_notify, |
357 | }; | |
358 | ||
24d9b70b JB |
359 | static void __init pci_enable_pci_io_ecs(void) |
360 | { | |
361 | #ifdef CONFIG_AMD_NB | |
362 | unsigned int i, n; | |
363 | ||
364 | for (n = i = 0; !n && amd_nb_bus_dev_ranges[i].dev_limit; ++i) { | |
365 | u8 bus = amd_nb_bus_dev_ranges[i].bus; | |
366 | u8 slot = amd_nb_bus_dev_ranges[i].dev_base; | |
367 | u8 limit = amd_nb_bus_dev_ranges[i].dev_limit; | |
368 | ||
369 | for (; slot < limit; ++slot) { | |
370 | u32 val = read_pci_config(bus, slot, 3, 0); | |
371 | ||
372 | if (!early_is_amd_nb(val)) | |
373 | continue; | |
374 | ||
375 | val = read_pci_config(bus, slot, 3, 0x8c); | |
376 | if (!(val & (ENABLE_CF8_EXT_CFG >> 32))) { | |
377 | val |= ENABLE_CF8_EXT_CFG >> 32; | |
378 | write_pci_config(bus, slot, 3, 0x8c, val); | |
379 | } | |
380 | ++n; | |
381 | } | |
382 | } | |
24d9b70b JB |
383 | #endif |
384 | } | |
385 | ||
91ede005 RR |
386 | static int __init pci_io_ecs_init(void) |
387 | { | |
388 | int cpu; | |
389 | ||
3a27dd1c | 390 | /* assume all cpus from fam10h have IO ECS */ |
9e7f7231 | 391 | if (boot_cpu_data.x86 < 0x10) |
3a27dd1c | 392 | return 0; |
91ede005 | 393 | |
24d9b70b JB |
394 | /* Try the PCI method first. */ |
395 | if (early_pci_allowed()) | |
396 | pci_enable_pci_io_ecs(); | |
397 | ||
9f668f66 | 398 | cpu_notifier_register_begin(); |
91ede005 RR |
399 | for_each_online_cpu(cpu) |
400 | amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE, | |
401 | (void *)(long)cpu); | |
9f668f66 SB |
402 | __register_cpu_notifier(&amd_cpu_notifier); |
403 | cpu_notifier_register_done(); | |
404 | ||
3a27dd1c | 405 | pci_probe |= PCI_HAS_IO_ECS; |
91ede005 | 406 | |
3a27dd1c RR |
407 | return 0; |
408 | } | |
409 | ||
9b4e27b5 RR |
410 | static int __init amd_postcore_init(void) |
411 | { | |
412 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) | |
413 | return 0; | |
414 | ||
9e7f7231 | 415 | early_root_info_init(); |
91ede005 | 416 | pci_io_ecs_init(); |
9b4e27b5 RR |
417 | |
418 | return 0; | |
419 | } | |
420 | ||
421 | postcore_initcall(amd_postcore_init); |