[deliverable/linux.git] / arch / x86 / pci / common.c

/*
 *	Low-Level PCI Support for PC
 *
 *	(c) 1999--2000 Martin Mares <mj@ucw.cz>
 */

#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/pci-acpi.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/dmi.h>
#include <linux/slab.h>

#include <asm-generic/pci-bridge.h>
#include <asm/acpi.h>
#include <asm/segment.h>
#include <asm/io.h>
#include <asm/smp.h>
#include <asm/pci_x86.h>
#include <asm/setup.h>

unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2 |
				PCI_PROBE_MMCONF;

unsigned int pci_early_dump_regs;
static int pci_bf_sort;
static int smbios_type_b1_flag;
int pci_routeirq;
int noioapicquirk;
#ifdef CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS
int noioapicreroute = 0;
#else
int noioapicreroute = 1;
#endif
int pcibios_last_bus = -1;
unsigned long pirq_table_addr;
const struct pci_raw_ops *__read_mostly raw_pci_ops;
const struct pci_raw_ops *__read_mostly raw_pci_ext_ops;

int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
						int reg, int len, u32 *val)
{
	if (domain == 0 && reg < 256 && raw_pci_ops)
		return raw_pci_ops->read(domain, bus, devfn, reg, len, val);
	if (raw_pci_ext_ops)
		return raw_pci_ext_ops->read(domain, bus, devfn, reg, len, val);
	return -EINVAL;
}

int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
						int reg, int len, u32 val)
{
	if (domain == 0 && reg < 256 && raw_pci_ops)
		return raw_pci_ops->write(domain, bus, devfn, reg, len, val);
	if (raw_pci_ext_ops)
		return raw_pci_ext_ops->write(domain, bus, devfn, reg, len, val);
	return -EINVAL;
}

static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
{
	return raw_pci_read(pci_domain_nr(bus), bus->number,
				 devfn, where, size, value);
}

static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
{
	return raw_pci_write(pci_domain_nr(bus), bus->number,
				  devfn, where, size, value);
}

struct pci_ops pci_root_ops = {
	.read = pci_read,
	.write = pci_write,
};

/*
 * This interrupt-safe spinlock protects all accesses to PCI
 * configuration space.
 */
DEFINE_RAW_SPINLOCK(pci_config_lock);

static int __init can_skip_ioresource_align(const struct dmi_system_id *d)
{
	pci_probe |= PCI_CAN_SKIP_ISA_ALIGN;
	printk(KERN_INFO "PCI: %s detected, can skip ISA alignment\n", d->ident);
	return 0;
}

static const struct dmi_system_id can_skip_pciprobe_dmi_table[] __initconst = {
/*
 * Systems where PCI IO resource ISA alignment can be skipped
 * when the ISA enable bit in the bridge control is not set
 */
	{
		.callback = can_skip_ioresource_align,
		.ident = "IBM System x3800",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "x3800"),
		},
	},
	{
		.callback = can_skip_ioresource_align,
		.ident = "IBM System x3850",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "x3850"),
		},
	},
	{
		.callback = can_skip_ioresource_align,
		.ident = "IBM System x3950",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "x3950"),
		},
	},
	{}
};

void __init dmi_check_skip_isa_align(void)
{
	dmi_check_system(can_skip_pciprobe_dmi_table);
}

static void pcibios_fixup_device_resources(struct pci_dev *dev)
{
	struct resource *rom_r = &dev->resource[PCI_ROM_RESOURCE];
	struct resource *bar_r;
	int bar;

	if (pci_probe & PCI_NOASSIGN_BARS) {
		/*
		* If the BIOS did not assign the BAR, zero out the
		* resource so the kernel doesn't attmept to assign
		* it later on in pci_assign_unassigned_resources
		*/
		for (bar = 0; bar <= PCI_STD_RESOURCE_END; bar++) {
			bar_r = &dev->resource[bar];
			if (bar_r->start == 0 && bar_r->end != 0) {
				bar_r->flags = 0;
				bar_r->end = 0;
			}
		}
	}

	if (pci_probe & PCI_NOASSIGN_ROMS) {
		if (rom_r->parent)
			return;
		if (rom_r->start) {
			/* we deal with BIOS assigned ROM later */
			return;
		}
		rom_r->start = rom_r->end = rom_r->flags = 0;
	}
}

/*
 *  Called after each bus is probed, but before its children
 *  are examined.
 */

void pcibios_fixup_bus(struct pci_bus *b)
{
	struct pci_dev *dev;

	pci_read_bridge_bases(b);
	list_for_each_entry(dev, &b->devices, bus_list)
		pcibios_fixup_device_resources(dev);
}

void pcibios_add_bus(struct pci_bus *bus)
{
	acpi_pci_add_bus(bus);
}

void pcibios_remove_bus(struct pci_bus *bus)
{
	acpi_pci_remove_bus(bus);
}

/*
 * Only use DMI information to set this if nothing was passed
 * on the kernel command line (which was parsed earlier).
 */

static int __init set_bf_sort(const struct dmi_system_id *d)
{
	if (pci_bf_sort == pci_bf_sort_default) {
		pci_bf_sort = pci_dmi_bf;
		printk(KERN_INFO "PCI: %s detected, enabling pci=bfsort.\n", d->ident);
	}
	return 0;
}

static void __init read_dmi_type_b1(const struct dmi_header *dm,
				    void *private_data)
{
	u8 *d = (u8 *)dm + 4;

	if (dm->type != 0xB1)
		return;
	switch (((*(u32 *)d) >> 9) & 0x03) {
	case 0x00:
		printk(KERN_INFO "dmi type 0xB1 record - unknown flag\n");
		break;
	case 0x01: /* set pci=bfsort */
		smbios_type_b1_flag = 1;
		break;
	case 0x02: /* do not set pci=bfsort */
		smbios_type_b1_flag = 2;
		break;
	default:
		break;
	}
}

static int __init find_sort_method(const struct dmi_system_id *d)
{
	dmi_walk(read_dmi_type_b1, NULL);

	if (smbios_type_b1_flag == 1) {
		set_bf_sort(d);
		return 0;
	}
	return -1;
}

/*
 * Enable renumbering of PCI bus# ranges to reach all PCI busses (Cardbus)
 */
#ifdef __i386__
static int __init assign_all_busses(const struct dmi_system_id *d)
{
	pci_probe |= PCI_ASSIGN_ALL_BUSSES;
	printk(KERN_INFO "%s detected: enabling PCI bus# renumbering"
			" (pci=assign-busses)\n", d->ident);
	return 0;
}
#endif

static int __init set_scan_all(const struct dmi_system_id *d)
{
	printk(KERN_INFO "PCI: %s detected, enabling pci=pcie_scan_all\n",
	       d->ident);
	pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
	return 0;
}

static const struct dmi_system_id pciprobe_dmi_table[] __initconst = {
#ifdef __i386__
/*
 * Laptops which need pci=assign-busses to see Cardbus cards
 */
	{
		.callback = assign_all_busses,
		.ident = "Samsung X20 Laptop",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Samsung Electronics"),
			DMI_MATCH(DMI_PRODUCT_NAME, "SX20S"),
		},
	},
#endif		/* __i386__ */
	{
		.callback = set_bf_sort,
		.ident = "Dell PowerEdge 1950",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1950"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "Dell PowerEdge 1955",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1955"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "Dell PowerEdge 2900",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2900"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "Dell PowerEdge 2950",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2950"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "Dell PowerEdge R900",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge R900"),
		},
	},
	{
		.callback = find_sort_method,
		.ident = "Dell System",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL20p G3",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G3"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL20p G4",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G4"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL30p G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL30p G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL25p G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL25p G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL35p G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL35p G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL45p G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL45p G2",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G2"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL460c G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL460c G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL465c G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL465c G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL480c G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL480c G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL685c G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL685c G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant DL360",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL360"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant DL380",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL380"),
		},
	},
#ifdef __i386__
	{
		.callback = assign_all_busses,
		.ident = "Compaq EVO N800c",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Compaq"),
			DMI_MATCH(DMI_PRODUCT_NAME, "EVO N800c"),
		},
	},
#endif
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant DL385 G2",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL385 G2"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant DL585 G2",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL585 G2"),
		},
	},
	{
		.callback = set_scan_all,
		.ident = "Stratus/NEC ftServer",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Stratus"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ftServer"),
		},
	},
	{}
};

void __init dmi_check_pciprobe(void)
{
	dmi_check_system(pciprobe_dmi_table);
}

void pcibios_scan_root(int busnum)
{
	struct pci_bus *bus;
	struct pci_sysdata *sd;
	LIST_HEAD(resources);

	sd = kzalloc(sizeof(*sd), GFP_KERNEL);
	if (!sd) {
		printk(KERN_ERR "PCI: OOM, skipping PCI bus %02x\n", busnum);
		return;
	}
	sd->node = x86_pci_root_bus_node(busnum);
	x86_pci_root_bus_resources(busnum, &resources);
	printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busnum);
	bus = pci_scan_root_bus(NULL, busnum, &pci_root_ops, sd, &resources);
	if (!bus) {
		pci_free_resource_list(&resources);
		kfree(sd);
	}
}

void __init pcibios_set_cache_line_size(void)
{
	struct cpuinfo_x86 *c = &boot_cpu_data;

	/*
	 * Set PCI cacheline size to that of the CPU if the CPU has reported it.
	 * (For older CPUs that don't support cpuid, we se it to 32 bytes
	 * It's also good for 386/486s (which actually have 16)
	 * as quite a few PCI devices do not support smaller values.
	 */
	if (c->x86_clflush_size > 0) {
		pci_dfl_cache_line_size = c->x86_clflush_size >> 2;
		printk(KERN_DEBUG "PCI: pci_cache_line_size set to %d bytes\n",
			pci_dfl_cache_line_size << 2);
	} else {
 		pci_dfl_cache_line_size = 32 >> 2;
		printk(KERN_DEBUG "PCI: Unknown cacheline size. Setting to 32 bytes\n");
	}
}

int __init pcibios_init(void)
{
	if (!raw_pci_ops) {
		printk(KERN_WARNING "PCI: System does not support PCI\n");
		return 0;
	}

	pcibios_set_cache_line_size();
	pcibios_resource_survey();

	if (pci_bf_sort >= pci_force_bf)
		pci_sort_breadthfirst();
	return 0;
}

char *__init pcibios_setup(char *str)
{
	if (!strcmp(str, "off")) {
		pci_probe = 0;
		return NULL;
	} else if (!strcmp(str, "bfsort")) {
		pci_bf_sort = pci_force_bf;
		return NULL;
	} else if (!strcmp(str, "nobfsort")) {
		pci_bf_sort = pci_force_nobf;
		return NULL;
	}
#ifdef CONFIG_PCI_BIOS
	else if (!strcmp(str, "bios")) {
		pci_probe = PCI_PROBE_BIOS;
		return NULL;
	} else if (!strcmp(str, "nobios")) {
		pci_probe &= ~PCI_PROBE_BIOS;
		return NULL;
	} else if (!strcmp(str, "biosirq")) {
		pci_probe |= PCI_BIOS_IRQ_SCAN;
		return NULL;
	} else if (!strncmp(str, "pirqaddr=", 9)) {
		pirq_table_addr = simple_strtoul(str+9, NULL, 0);
		return NULL;
	}
#endif
#ifdef CONFIG_PCI_DIRECT
	else if (!strcmp(str, "conf1")) {
		pci_probe = PCI_PROBE_CONF1 | PCI_NO_CHECKS;
		return NULL;
	}
	else if (!strcmp(str, "conf2")) {
		pci_probe = PCI_PROBE_CONF2 | PCI_NO_CHECKS;
		return NULL;
	}
#endif
#ifdef CONFIG_PCI_MMCONFIG
	else if (!strcmp(str, "nommconf")) {
		pci_probe &= ~PCI_PROBE_MMCONF;
		return NULL;
	}
	else if (!strcmp(str, "check_enable_amd_mmconf")) {
		pci_probe |= PCI_CHECK_ENABLE_AMD_MMCONF;
		return NULL;
	}
#endif
	else if (!strcmp(str, "noacpi")) {
		acpi_noirq_set();
		return NULL;
	}
	else if (!strcmp(str, "noearly")) {
		pci_probe |= PCI_PROBE_NOEARLY;
		return NULL;
	}
	else if (!strcmp(str, "usepirqmask")) {
		pci_probe |= PCI_USE_PIRQ_MASK;
		return NULL;
	} else if (!strncmp(str, "irqmask=", 8)) {
		pcibios_irq_mask = simple_strtol(str+8, NULL, 0);
		return NULL;
	} else if (!strncmp(str, "lastbus=", 8)) {
		pcibios_last_bus = simple_strtol(str+8, NULL, 0);
		return NULL;
	} else if (!strcmp(str, "rom")) {
		pci_probe |= PCI_ASSIGN_ROMS;
		return NULL;
	} else if (!strcmp(str, "norom")) {
		pci_probe |= PCI_NOASSIGN_ROMS;
		return NULL;
	} else if (!strcmp(str, "nobar")) {
		pci_probe |= PCI_NOASSIGN_BARS;
		return NULL;
	} else if (!strcmp(str, "assign-busses")) {
		pci_probe |= PCI_ASSIGN_ALL_BUSSES;
		return NULL;
	} else if (!strcmp(str, "use_crs")) {
		pci_probe |= PCI_USE__CRS;
		return NULL;
	} else if (!strcmp(str, "nocrs")) {
		pci_probe |= PCI_ROOT_NO_CRS;
		return NULL;
	} else if (!strcmp(str, "earlydump")) {
		pci_early_dump_regs = 1;
		return NULL;
	} else if (!strcmp(str, "routeirq")) {
		pci_routeirq = 1;
		return NULL;
	} else if (!strcmp(str, "skip_isa_align")) {
		pci_probe |= PCI_CAN_SKIP_ISA_ALIGN;
		return NULL;
	} else if (!strcmp(str, "noioapicquirk")) {
		noioapicquirk = 1;
		return NULL;
	} else if (!strcmp(str, "ioapicreroute")) {
		if (noioapicreroute != -1)
			noioapicreroute = 0;
		return NULL;
	} else if (!strcmp(str, "noioapicreroute")) {
		if (noioapicreroute != -1)
			noioapicreroute = 1;
		return NULL;
	}
	return str;
}

unsigned int pcibios_assign_all_busses(void)
{
	return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
}

int pcibios_add_device(struct pci_dev *dev)
{
	struct setup_data *data;
	struct pci_setup_rom *rom;
	u64 pa_data;

	pa_data = boot_params.hdr.setup_data;
	while (pa_data) {
		data = ioremap(pa_data, sizeof(*rom));
		if (!data)
			return -ENOMEM;

		if (data->type == SETUP_PCI) {
			rom = (struct pci_setup_rom *)data;

			if ((pci_domain_nr(dev->bus) == rom->segment) &&
			    (dev->bus->number == rom->bus) &&
			    (PCI_SLOT(dev->devfn) == rom->device) &&
			    (PCI_FUNC(dev->devfn) == rom->function) &&
			    (dev->vendor == rom->vendor) &&
			    (dev->device == rom->devid)) {
				dev->rom = pa_data +
				      offsetof(struct pci_setup_rom, romdata);
				dev->romlen = rom->pcilen;
			}
		}
		pa_data = data->next;
		iounmap(data);
	}
	return 0;
}

int pcibios_enable_device(struct pci_dev *dev, int mask)
{
	int err;

	if ((err = pci_enable_resources(dev, mask)) < 0)
		return err;

	if (!pci_dev_msi_enabled(dev))
		return pcibios_enable_irq(dev);
	return 0;
}

void pcibios_disable_device (struct pci_dev *dev)
{
	if (!pci_dev_msi_enabled(dev) && pcibios_disable_irq)
		pcibios_disable_irq(dev);
}

int pci_ext_cfg_avail(void)
{
	if (raw_pci_ext_ops)
		return 1;
	else
		return 0;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Low-Level PCI Support for PC
	3	*
	4	* (c) 1999--2000 Martin Mares <mj@ucw.cz>
	5	*/
	6
	7	#include <linux/sched.h>
	8	#include <linux/pci.h>
89016506	9	#include <linux/pci-acpi.h>
1da177e4 LT	10	#include <linux/ioport.h>
1da177e4 LT	11	#include <linux/init.h>
8c4b2cf9	12	#include <linux/dmi.h>
5a0e3ad6	13	#include <linux/slab.h>
1da177e4	14
284f5f9d	15	#include <asm-generic/pci-bridge.h>
1da177e4 LT	16	#include <asm/acpi.h>
	17	#include <asm/segment.h>
	18	#include <asm/io.h>
	19	#include <asm/smp.h>
82487711	20	#include <asm/pci_x86.h>
f9a37be0	21	#include <asm/setup.h>
1da177e4	22
1da177e4 LT	23	unsigned int pci_probe = PCI_PROBE_BIOS \| PCI_PROBE_CONF1 \| PCI_PROBE_CONF2 \|
	24	PCI_PROBE_MMCONF;
	25
e3f2baeb	26	unsigned int pci_early_dump_regs;
2b290da0	27	static int pci_bf_sort;
6e8af08d	28	static int smbios_type_b1_flag;
1da177e4	29	int pci_routeirq;
a9322f64	30	int noioapicquirk;
41b9eb26 SA	31	#ifdef CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS
	32	int noioapicreroute = 0;
	33	#else
9197979b	34	int noioapicreroute = 1;
41b9eb26	35	#endif
1da177e4	36	int pcibios_last_bus = -1;
120bb424	37	unsigned long pirq_table_addr;
72da0b07 JB	38	const struct pci_raw_ops *__read_mostly raw_pci_ops;
72da0b07 JB	39	const struct pci_raw_ops *__read_mostly raw_pci_ext_ops;
b6ce068a MW	40
	41	int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
	42	int reg, int len, u32 *val)
	43	{
beef3129	44	if (domain == 0 && reg < 256 && raw_pci_ops)
b6ce068a MW	45	return raw_pci_ops->read(domain, bus, devfn, reg, len, val);
	46	if (raw_pci_ext_ops)
	47	return raw_pci_ext_ops->read(domain, bus, devfn, reg, len, val);
	48	return -EINVAL;
	49	}
	50
	51	int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
	52	int reg, int len, u32 val)
	53	{
beef3129	54	if (domain == 0 && reg < 256 && raw_pci_ops)
b6ce068a MW	55	return raw_pci_ops->write(domain, bus, devfn, reg, len, val);
	56	if (raw_pci_ext_ops)
	57	return raw_pci_ext_ops->write(domain, bus, devfn, reg, len, val);
	58	return -EINVAL;
	59	}
1da177e4 LT	60
	61	static int pci_read(struct pci_bus bus, unsigned int devfn, int where, int size, u32 value)
	62	{
b6ce068a	63	return raw_pci_read(pci_domain_nr(bus), bus->number,
a79e4198	64	devfn, where, size, value);
1da177e4 LT	65	}
	66
	67	static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
	68	{
b6ce068a	69	return raw_pci_write(pci_domain_nr(bus), bus->number,
a79e4198	70	devfn, where, size, value);
1da177e4 LT	71	}
	72
	73	struct pci_ops pci_root_ops = {
	74	.read = pci_read,
	75	.write = pci_write,
	76	};
	77
1da177e4 LT	78	/*
	79	* This interrupt-safe spinlock protects all accesses to PCI
	80	* configuration space.
	81	*/
d19f61f0	82	DEFINE_RAW_SPINLOCK(pci_config_lock);
1da177e4	83
4ac9cbfa	84	static int __init can_skip_ioresource_align(const struct dmi_system_id *d)
13a6ddb0 YL	85	{
	86	pci_probe \|= PCI_CAN_SKIP_ISA_ALIGN;
	87	printk(KERN_INFO "PCI: %s detected, can skip ISA alignment\n", d->ident);
	88	return 0;
	89	}
	90
4ac9cbfa	91	static const struct dmi_system_id can_skip_pciprobe_dmi_table[] __initconst = {
13a6ddb0 YL	92	/*
	93	* Systems where PCI IO resource ISA alignment can be skipped
	94	* when the ISA enable bit in the bridge control is not set
	95	*/
	96	{
	97	.callback = can_skip_ioresource_align,
	98	.ident = "IBM System x3800",
	99	.matches = {
	100	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
	101	DMI_MATCH(DMI_PRODUCT_NAME, "x3800"),
	102	},
	103	},
	104	{
	105	.callback = can_skip_ioresource_align,
	106	.ident = "IBM System x3850",
	107	.matches = {
	108	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
	109	DMI_MATCH(DMI_PRODUCT_NAME, "x3850"),
	110	},
	111	},
	112	{
	113	.callback = can_skip_ioresource_align,
	114	.ident = "IBM System x3950",
	115	.matches = {
	116	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
	117	DMI_MATCH(DMI_PRODUCT_NAME, "x3950"),
	118	},
	119	},
	120	{}
	121	};
	122
	123	void __init dmi_check_skip_isa_align(void)
	124	{
	125	dmi_check_system(can_skip_pciprobe_dmi_table);
	126	}
	127
a18e3690	128	static void pcibios_fixup_device_resources(struct pci_dev *dev)
bb71ad88 GH	129	{
bb71ad88 GH	130	struct resource *rom_r = &dev->resource[PCI_ROM_RESOURCE];
7bd1c365 MH	131	struct resource *bar_r;
	132	int bar;
	133
	134	if (pci_probe & PCI_NOASSIGN_BARS) {
	135	/*
	136	* If the BIOS did not assign the BAR, zero out the
	137	* resource so the kernel doesn't attmept to assign
	138	* it later on in pci_assign_unassigned_resources
	139	*/
	140	for (bar = 0; bar <= PCI_STD_RESOURCE_END; bar++) {
	141	bar_r = &dev->resource[bar];
	142	if (bar_r->start == 0 && bar_r->end != 0) {
	143	bar_r->flags = 0;
	144	bar_r->end = 0;
	145	}
	146	}
	147	}
bb71ad88 GH	148
	149	if (pci_probe & PCI_NOASSIGN_ROMS) {
	150	if (rom_r->parent)
	151	return;
	152	if (rom_r->start) {
	153	/* we deal with BIOS assigned ROM later */
	154	return;
	155	}
	156	rom_r->start = rom_r->end = rom_r->flags = 0;
	157	}
	158	}
	159
1da177e4 LT	160	/*
	161	* Called after each bus is probed, but before its children
	162	* are examined.
	163	*/
	164
a18e3690	165	void pcibios_fixup_bus(struct pci_bus *b)
1da177e4	166	{
bb71ad88 GH	167	struct pci_dev *dev;
bb71ad88 GH	168
1da177e4	169	pci_read_bridge_bases(b);
bb71ad88 GH	170	list_for_each_entry(dev, &b->devices, bus_list)
bb71ad88 GH	171	pcibios_fixup_device_resources(dev);
1da177e4 LT	172	}
1da177e4 LT	173
89016506 JL	174	void pcibios_add_bus(struct pci_bus *bus)
	175	{
	176	acpi_pci_add_bus(bus);
	177	}
	178
	179	void pcibios_remove_bus(struct pci_bus *bus)
	180	{
	181	acpi_pci_remove_bus(bus);
	182	}
	183
6b4b78fe MD	184	/*
	185	* Only use DMI information to set this if nothing was passed
	186	* on the kernel command line (which was parsed earlier).
	187	*/
	188
4ac9cbfa	189	static int __init set_bf_sort(const struct dmi_system_id *d)
6b4b78fe MD	190	{
	191	if (pci_bf_sort == pci_bf_sort_default) {
	192	pci_bf_sort = pci_dmi_bf;
	193	printk(KERN_INFO "PCI: %s detected, enabling pci=bfsort.\n", d->ident);
	194	}
	195	return 0;
	196	}
	197
4ac9cbfa MK	198	static void __init read_dmi_type_b1(const struct dmi_header *dm,
4ac9cbfa MK	199	void *private_data)
6e8af08d ND	200	{
	201	u8 d = (u8 )dm + 4;
	202
	203	if (dm->type != 0xB1)
	204	return;
	205	switch ((((u32 )d) >> 9) & 0x03) {
	206	case 0x00:
	207	printk(KERN_INFO "dmi type 0xB1 record - unknown flag\n");
	208	break;
	209	case 0x01: /* set pci=bfsort */
	210	smbios_type_b1_flag = 1;
	211	break;
	212	case 0x02: /* do not set pci=bfsort */
	213	smbios_type_b1_flag = 2;
	214	break;
	215	default:
	216	break;
	217	}
	218	}
	219
4ac9cbfa	220	static int __init find_sort_method(const struct dmi_system_id *d)
6e8af08d ND	221	{
	222	dmi_walk(read_dmi_type_b1, NULL);
	223
	224	if (smbios_type_b1_flag == 1) {
	225	set_bf_sort(d);
	226	return 0;
	227	}
	228	return -1;
	229	}
	230
8c4b2cf9 BK	231	/*
	232	* Enable renumbering of PCI bus# ranges to reach all PCI busses (Cardbus)
	233	*/
	234	#ifdef __i386__
4ac9cbfa	235	static int __init assign_all_busses(const struct dmi_system_id *d)
8c4b2cf9 BK	236	{
	237	pci_probe \|= PCI_ASSIGN_ALL_BUSSES;
	238	printk(KERN_INFO "%s detected: enabling PCI bus# renumbering"
	239	" (pci=assign-busses)\n", d->ident);
	240	return 0;
	241	}
	242	#endif
	243
4ac9cbfa	244	static int __init set_scan_all(const struct dmi_system_id *d)
284f5f9d BH	245	{
	246	printk(KERN_INFO "PCI: %s detected, enabling pci=pcie_scan_all\n",
	247	d->ident);
	248	pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
	249	return 0;
	250	}
	251
4ac9cbfa	252	static const struct dmi_system_id pciprobe_dmi_table[] __initconst = {
6b4b78fe	253	#ifdef __i386__
8c4b2cf9 BK	254	/*
	255	* Laptops which need pci=assign-busses to see Cardbus cards
	256	*/
8c4b2cf9 BK	257	{
	258	.callback = assign_all_busses,
	259	.ident = "Samsung X20 Laptop",
	260	.matches = {
	261	DMI_MATCH(DMI_SYS_VENDOR, "Samsung Electronics"),
	262	DMI_MATCH(DMI_PRODUCT_NAME, "SX20S"),
	263	},
	264	},
	265	#endif /* __i386__ */
6b4b78fe MD	266	{
	267	.callback = set_bf_sort,
	268	.ident = "Dell PowerEdge 1950",
	269	.matches = {
	270	DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
	271	DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1950"),
	272	},
	273	},
	274	{
	275	.callback = set_bf_sort,
	276	.ident = "Dell PowerEdge 1955",
	277	.matches = {
	278	DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
	279	DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1955"),
	280	},
	281	},
	282	{
	283	.callback = set_bf_sort,
	284	.ident = "Dell PowerEdge 2900",
	285	.matches = {
	286	DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
	287	DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2900"),
	288	},
	289	},
	290	{
	291	.callback = set_bf_sort,
	292	.ident = "Dell PowerEdge 2950",
	293	.matches = {
	294	DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
	295	DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2950"),
	296	},
	297	},
f7a9dae7 MD	298	{
	299	.callback = set_bf_sort,
	300	.ident = "Dell PowerEdge R900",
	301	.matches = {
	302	DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
	303	DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge R900"),
	304	},
	305	},
9b373ed1 ND	306	{
	307	.callback = find_sort_method,
	308	.ident = "Dell System",
	309	.matches = {
	310	DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
	311	},
	312	},
f52383d3 AG	313	{
	314	.callback = set_bf_sort,
	315	.ident = "HP ProLiant BL20p G3",
	316	.matches = {
	317	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	318	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G3"),
	319	},
	320	},
	321	{
	322	.callback = set_bf_sort,
	323	.ident = "HP ProLiant BL20p G4",
	324	.matches = {
	325	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	326	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G4"),
	327	},
	328	},
	329	{
	330	.callback = set_bf_sort,
	331	.ident = "HP ProLiant BL30p G1",
	332	.matches = {
	333	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	334	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL30p G1"),
	335	},
	336	},
	337	{
	338	.callback = set_bf_sort,
	339	.ident = "HP ProLiant BL25p G1",
	340	.matches = {
	341	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	342	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL25p G1"),
	343	},
	344	},
	345	{
	346	.callback = set_bf_sort,
	347	.ident = "HP ProLiant BL35p G1",
	348	.matches = {
	349	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	350	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL35p G1"),
	351	},
	352	},
	353	{
	354	.callback = set_bf_sort,
	355	.ident = "HP ProLiant BL45p G1",
	356	.matches = {
	357	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	358	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G1"),
	359	},
	360	},
	361	{
	362	.callback = set_bf_sort,
	363	.ident = "HP ProLiant BL45p G2",
	364	.matches = {
	365	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	366	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G2"),
	367	},
	368	},
	369	{
	370	.callback = set_bf_sort,
	371	.ident = "HP ProLiant BL460c G1",
	372	.matches = {
	373	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	374	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL460c G1"),
	375	},
	376	},
377	{
378	.callback = set_bf_sort,
379	.ident = "HP ProLiant BL465c G1",
380	.matches = {
381	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
382	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL465c G1"),
383	},
384	},
385	{
386	.callback = set_bf_sort,
387	.ident = "HP ProLiant BL480c G1",
388	.matches = {
389	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
390	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL480c G1"),
391	},
392	},
393	{
394	.callback = set_bf_sort,
395	.ident = "HP ProLiant BL685c G1",
396	.matches = {
397	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
398	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL685c G1"),
399	},
400	},
8f8ae1a7 MS	401	{
8f8ae1a7 MS	402	.callback = set_bf_sort,
8d64c781	403	.ident = "HP ProLiant DL360",
8f8ae1a7 MS	404	.matches = {
8f8ae1a7 MS	405	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
8d64c781	406	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL360"),
8f8ae1a7 MS	407	},
	408	},
	409	{
	410	.callback = set_bf_sort,
8d64c781	411	.ident = "HP ProLiant DL380",
8f8ae1a7 MS	412	.matches = {
8f8ae1a7 MS	413	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
8d64c781	414	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL380"),
8f8ae1a7 MS	415	},
8f8ae1a7 MS	416	},
5b1ea82f JL	417	#ifdef __i386__
	418	{
	419	.callback = assign_all_busses,
	420	.ident = "Compaq EVO N800c",
	421	.matches = {
	422	DMI_MATCH(DMI_SYS_VENDOR, "Compaq"),
	423	DMI_MATCH(DMI_PRODUCT_NAME, "EVO N800c"),
	424	},
	425	},
	426	#endif
c82bc5ad MS	427	{
c82bc5ad MS	428	.callback = set_bf_sort,
739db07f	429	.ident = "HP ProLiant DL385 G2",
c82bc5ad MS	430	.matches = {
c82bc5ad MS	431	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
739db07f	432	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL385 G2"),
c82bc5ad MS	433	},
	434	},
	435	{
	436	.callback = set_bf_sort,
739db07f	437	.ident = "HP ProLiant DL585 G2",
c82bc5ad MS	438	.matches = {
c82bc5ad MS	439	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
739db07f	440	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL585 G2"),
c82bc5ad MS	441	},
c82bc5ad MS	442	},
284f5f9d BH	443	{
	444	.callback = set_scan_all,
	445	.ident = "Stratus/NEC ftServer",
	446	.matches = {
1278998f MS	447	DMI_MATCH(DMI_SYS_VENDOR, "Stratus"),
1278998f MS	448	DMI_MATCH(DMI_PRODUCT_NAME, "ftServer"),
284f5f9d BH	449	},
284f5f9d BH	450	},
8c4b2cf9 BK	451	{}
8c4b2cf9 BK	452	};
1da177e4	453
0df18ff3 YL	454	void __init dmi_check_pciprobe(void)
	455	{
	456	dmi_check_system(pciprobe_dmi_table);
	457	}
	458
49886cf4	459	void pcibios_scan_root(int busnum)
1da177e4	460	{
289a24a6 BH	461	struct pci_bus *bus;
	462	struct pci_sysdata *sd;
	463	LIST_HEAD(resources);
	464
	465	sd = kzalloc(sizeof(*sd), GFP_KERNEL);
	466	if (!sd) {
	467	printk(KERN_ERR "PCI: OOM, skipping PCI bus %02x\n", busnum);
49886cf4	468	return;
289a24a6	469	}
6616dbdf	470	sd->node = x86_pci_root_bus_node(busnum);
289a24a6 BH	471	x86_pci_root_bus_resources(busnum, &resources);
	472	printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busnum);
	473	bus = pci_scan_root_bus(NULL, busnum, &pci_root_ops, sd, &resources);
	474	if (!bus) {
	475	pci_free_resource_list(&resources);
	476	kfree(sd);
	477	}
1da177e4	478	}
c57ca65a	479
44de3395	480	void __init pcibios_set_cache_line_size(void)
1da177e4 LT	481	{
	482	struct cpuinfo_x86 *c = &boot_cpu_data;
	483
1da177e4	484	/*
76b1a87b DJ	485	* Set PCI cacheline size to that of the CPU if the CPU has reported it.
	486	* (For older CPUs that don't support cpuid, we se it to 32 bytes
	487	* It's also good for 386/486s (which actually have 16)
1da177e4 LT	488	* as quite a few PCI devices do not support smaller values.
1da177e4 LT	489	*/
76b1a87b DJ	490	if (c->x86_clflush_size > 0) {
	491	pci_dfl_cache_line_size = c->x86_clflush_size >> 2;
	492	printk(KERN_DEBUG "PCI: pci_cache_line_size set to %d bytes\n",
	493	pci_dfl_cache_line_size << 2);
	494	} else {
	495	pci_dfl_cache_line_size = 32 >> 2;
	496	printk(KERN_DEBUG "PCI: Unknown cacheline size. Setting to 32 bytes\n");
	497	}
44de3395 AN	498	}
	499
	500	int __init pcibios_init(void)
	501	{
	502	if (!raw_pci_ops) {
	503	printk(KERN_WARNING "PCI: System does not support PCI\n");
	504	return 0;
	505	}
1da177e4	506
44de3395	507	pcibios_set_cache_line_size();
1da177e4 LT	508	pcibios_resource_survey();
1da177e4 LT	509
6b4b78fe MD	510	if (pci_bf_sort >= pci_force_bf)
6b4b78fe MD	511	pci_sort_breadthfirst();
1da177e4 LT	512	return 0;
	513	}
	514
4ac9cbfa	515	char __init pcibios_setup(char str)
1da177e4 LT	516	{
	517	if (!strcmp(str, "off")) {
	518	pci_probe = 0;
	519	return NULL;
6b4b78fe MD	520	} else if (!strcmp(str, "bfsort")) {
	521	pci_bf_sort = pci_force_bf;
	522	return NULL;
	523	} else if (!strcmp(str, "nobfsort")) {
	524	pci_bf_sort = pci_force_nobf;
	525	return NULL;
1da177e4 LT	526	}
	527	#ifdef CONFIG_PCI_BIOS
	528	else if (!strcmp(str, "bios")) {
	529	pci_probe = PCI_PROBE_BIOS;
	530	return NULL;
	531	} else if (!strcmp(str, "nobios")) {
	532	pci_probe &= ~PCI_PROBE_BIOS;
	533	return NULL;
1da177e4 LT	534	} else if (!strcmp(str, "biosirq")) {
	535	pci_probe \|= PCI_BIOS_IRQ_SCAN;
	536	return NULL;
120bb424	537	} else if (!strncmp(str, "pirqaddr=", 9)) {
	538	pirq_table_addr = simple_strtoul(str+9, NULL, 0);
	539	return NULL;
1da177e4 LT	540	}
	541	#endif
	542	#ifdef CONFIG_PCI_DIRECT
	543	else if (!strcmp(str, "conf1")) {
	544	pci_probe = PCI_PROBE_CONF1 \| PCI_NO_CHECKS;
	545	return NULL;
	546	}
	547	else if (!strcmp(str, "conf2")) {
	548	pci_probe = PCI_PROBE_CONF2 \| PCI_NO_CHECKS;
	549	return NULL;
	550	}
	551	#endif
	552	#ifdef CONFIG_PCI_MMCONFIG
	553	else if (!strcmp(str, "nommconf")) {
	554	pci_probe &= ~PCI_PROBE_MMCONF;
	555	return NULL;
	556	}
5f0b2976 YL	557	else if (!strcmp(str, "check_enable_amd_mmconf")) {
	558	pci_probe \|= PCI_CHECK_ENABLE_AMD_MMCONF;
	559	return NULL;
	560	}
1da177e4 LT	561	#endif
	562	else if (!strcmp(str, "noacpi")) {
	563	acpi_noirq_set();
	564	return NULL;
	565	}
0637a70a AK	566	else if (!strcmp(str, "noearly")) {
	567	pci_probe \|= PCI_PROBE_NOEARLY;
	568	return NULL;
	569	}
1da177e4 LT	570	else if (!strcmp(str, "usepirqmask")) {
	571	pci_probe \|= PCI_USE_PIRQ_MASK;
	572	return NULL;
	573	} else if (!strncmp(str, "irqmask=", 8)) {
	574	pcibios_irq_mask = simple_strtol(str+8, NULL, 0);
	575	return NULL;
	576	} else if (!strncmp(str, "lastbus=", 8)) {
	577	pcibios_last_bus = simple_strtol(str+8, NULL, 0);
	578	return NULL;
c5f9ee3d	579	} else if (!strcmp(str, "rom")) {
1da177e4 LT	580	pci_probe \|= PCI_ASSIGN_ROMS;
1da177e4 LT	581	return NULL;
bb71ad88 GH	582	} else if (!strcmp(str, "norom")) {
	583	pci_probe \|= PCI_NOASSIGN_ROMS;
	584	return NULL;
7bd1c365 MH	585	} else if (!strcmp(str, "nobar")) {
	586	pci_probe \|= PCI_NOASSIGN_BARS;
	587	return NULL;
1da177e4 LT	588	} else if (!strcmp(str, "assign-busses")) {
	589	pci_probe \|= PCI_ASSIGN_ALL_BUSSES;
	590	return NULL;
236e946b LT	591	} else if (!strcmp(str, "use_crs")) {
236e946b LT	592	pci_probe \|= PCI_USE__CRS;
62f420f8	593	return NULL;
7bc5e3f2 BH	594	} else if (!strcmp(str, "nocrs")) {
	595	pci_probe \|= PCI_ROOT_NO_CRS;
	596	return NULL;
e3f2baeb YL	597	} else if (!strcmp(str, "earlydump")) {
	598	pci_early_dump_regs = 1;
	599	return NULL;
1da177e4 LT	600	} else if (!strcmp(str, "routeirq")) {
	601	pci_routeirq = 1;
	602	return NULL;
13a6ddb0 YL	603	} else if (!strcmp(str, "skip_isa_align")) {
	604	pci_probe \|= PCI_CAN_SKIP_ISA_ALIGN;
	605	return NULL;
a9322f64 SA	606	} else if (!strcmp(str, "noioapicquirk")) {
	607	noioapicquirk = 1;
	608	return NULL;
9197979b SA	609	} else if (!strcmp(str, "ioapicreroute")) {
	610	if (noioapicreroute != -1)
	611	noioapicreroute = 0;
	612	return NULL;
41b9eb26 SA	613	} else if (!strcmp(str, "noioapicreroute")) {
	614	if (noioapicreroute != -1)
	615	noioapicreroute = 1;
	616	return NULL;
1da177e4 LT	617	}
	618	return str;
	619	}
	620
	621	unsigned int pcibios_assign_all_busses(void)
	622	{
	623	return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
	624	}
	625
f9a37be0 MG	626	int pcibios_add_device(struct pci_dev *dev)
	627	{
	628	struct setup_data *data;
	629	struct pci_setup_rom *rom;
	630	u64 pa_data;
	631
	632	pa_data = boot_params.hdr.setup_data;
	633	while (pa_data) {
65694c5a MF	634	data = ioremap(pa_data, sizeof(*rom));
	635	if (!data)
	636	return -ENOMEM;
f9a37be0 MG	637
	638	if (data->type == SETUP_PCI) {
	639	rom = (struct pci_setup_rom *)data;
	640
	641	if ((pci_domain_nr(dev->bus) == rom->segment) &&
	642	(dev->bus->number == rom->bus) &&
	643	(PCI_SLOT(dev->devfn) == rom->device) &&
	644	(PCI_FUNC(dev->devfn) == rom->function) &&
	645	(dev->vendor == rom->vendor) &&
	646	(dev->device == rom->devid)) {
dbd3fc33 BH	647	dev->rom = pa_data +
dbd3fc33 BH	648	offsetof(struct pci_setup_rom, romdata);
f9a37be0 MG	649	dev->romlen = rom->pcilen;
	650	}
	651	}
	652	pa_data = data->next;
65694c5a	653	iounmap(data);
f9a37be0 MG	654	}
	655	return 0;
	656	}
	657
1da177e4 LT	658	int pcibios_enable_device(struct pci_dev *dev, int mask)
	659	{
	660	int err;
	661
b81d988c	662	if ((err = pci_enable_resources(dev, mask)) < 0)
1da177e4 LT	663	return err;
1da177e4 LT	664
16cf0ebc	665	if (!pci_dev_msi_enabled(dev))
bba6f6fc EB	666	return pcibios_enable_irq(dev);
bba6f6fc EB	667	return 0;
1da177e4	668	}
87bec66b DSL	669
	670	void pcibios_disable_device (struct pci_dev *dev)
	671	{
16cf0ebc	672	if (!pci_dev_msi_enabled(dev) && pcibios_disable_irq)
87bec66b DSL	673	pcibios_disable_irq(dev);
87bec66b DSL	674	}
73c59afc	675
642c92da	676	int pci_ext_cfg_avail(void)
0ef5f8f6 AP	677	{
	678	if (raw_pci_ext_ops)
	679	return 1;
	680	else
	681	return 0;
	682	}