[deliverable/linux.git] / arch / x86 / pci / common.c

/*
 *	Low-Level PCI Support for PC
 *
 *	(c) 1999--2000 Martin Mares <mj@ucw.cz>
 */

#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/pci-acpi.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/dmi.h>
#include <linux/slab.h>

#include <asm-generic/pci-bridge.h>
#include <asm/acpi.h>
#include <asm/segment.h>
#include <asm/io.h>
#include <asm/smp.h>
#include <asm/pci_x86.h>
#include <asm/setup.h>

unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2 |
				PCI_PROBE_MMCONF;

unsigned int pci_early_dump_regs;
static int pci_bf_sort;
static int smbios_type_b1_flag;
int pci_routeirq;
int noioapicquirk;
#ifdef CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS
int noioapicreroute = 0;
#else
int noioapicreroute = 1;
#endif
int pcibios_last_bus = -1;
unsigned long pirq_table_addr;
const struct pci_raw_ops *__read_mostly raw_pci_ops;
const struct pci_raw_ops *__read_mostly raw_pci_ext_ops;

int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
						int reg, int len, u32 *val)
{
	if (domain == 0 && reg < 256 && raw_pci_ops)
		return raw_pci_ops->read(domain, bus, devfn, reg, len, val);
	if (raw_pci_ext_ops)
		return raw_pci_ext_ops->read(domain, bus, devfn, reg, len, val);
	return -EINVAL;
}

int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
						int reg, int len, u32 val)
{
	if (domain == 0 && reg < 256 && raw_pci_ops)
		return raw_pci_ops->write(domain, bus, devfn, reg, len, val);
	if (raw_pci_ext_ops)
		return raw_pci_ext_ops->write(domain, bus, devfn, reg, len, val);
	return -EINVAL;
}

static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
{
	return raw_pci_read(pci_domain_nr(bus), bus->number,
				 devfn, where, size, value);
}

static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
{
	return raw_pci_write(pci_domain_nr(bus), bus->number,
				  devfn, where, size, value);
}

struct pci_ops pci_root_ops = {
	.read = pci_read,
	.write = pci_write,
};

/*
 * This interrupt-safe spinlock protects all accesses to PCI
 * configuration space.
 */
DEFINE_RAW_SPINLOCK(pci_config_lock);

static int __init can_skip_ioresource_align(const struct dmi_system_id *d)
{
	pci_probe |= PCI_CAN_SKIP_ISA_ALIGN;
	printk(KERN_INFO "PCI: %s detected, can skip ISA alignment\n", d->ident);
	return 0;
}

static const struct dmi_system_id can_skip_pciprobe_dmi_table[] __initconst = {
/*
 * Systems where PCI IO resource ISA alignment can be skipped
 * when the ISA enable bit in the bridge control is not set
 */
	{
		.callback = can_skip_ioresource_align,
		.ident = "IBM System x3800",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "x3800"),
		},
	},
	{
		.callback = can_skip_ioresource_align,
		.ident = "IBM System x3850",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "x3850"),
		},
	},
	{
		.callback = can_skip_ioresource_align,
		.ident = "IBM System x3950",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "x3950"),
		},
	},
	{}
};

void __init dmi_check_skip_isa_align(void)
{
	dmi_check_system(can_skip_pciprobe_dmi_table);
}

static void pcibios_fixup_device_resources(struct pci_dev *dev)
{
	struct resource *rom_r = &dev->resource[PCI_ROM_RESOURCE];
	struct resource *bar_r;
	int bar;

	if (pci_probe & PCI_NOASSIGN_BARS) {
		/*
		* If the BIOS did not assign the BAR, zero out the
		* resource so the kernel doesn't attmept to assign
		* it later on in pci_assign_unassigned_resources
		*/
		for (bar = 0; bar <= PCI_STD_RESOURCE_END; bar++) {
			bar_r = &dev->resource[bar];
			if (bar_r->start == 0 && bar_r->end != 0) {
				bar_r->flags = 0;
				bar_r->end = 0;
			}
		}
	}

	if (pci_probe & PCI_NOASSIGN_ROMS) {
		if (rom_r->parent)
			return;
		if (rom_r->start) {
			/* we deal with BIOS assigned ROM later */
			return;
		}
		rom_r->start = rom_r->end = rom_r->flags = 0;
	}
}

/*
 *  Called after each bus is probed, but before its children
 *  are examined.
 */

void pcibios_fixup_bus(struct pci_bus *b)
{
	struct pci_dev *dev;

	list_for_each_entry(dev, &b->devices, bus_list)
		pcibios_fixup_device_resources(dev);
}

void pcibios_add_bus(struct pci_bus *bus)
{
	acpi_pci_add_bus(bus);
}

void pcibios_remove_bus(struct pci_bus *bus)
{
	acpi_pci_remove_bus(bus);
}

/*
 * Only use DMI information to set this if nothing was passed
 * on the kernel command line (which was parsed earlier).
 */

static int __init set_bf_sort(const struct dmi_system_id *d)
{
	if (pci_bf_sort == pci_bf_sort_default) {
		pci_bf_sort = pci_dmi_bf;
		printk(KERN_INFO "PCI: %s detected, enabling pci=bfsort.\n", d->ident);
	}
	return 0;
}

static void __init read_dmi_type_b1(const struct dmi_header *dm,
				    void *private_data)
{
	u8 *d = (u8 *)dm + 4;

	if (dm->type != 0xB1)
		return;
	switch (((*(u32 *)d) >> 9) & 0x03) {
	case 0x00:
		printk(KERN_INFO "dmi type 0xB1 record - unknown flag\n");
		break;
	case 0x01: /* set pci=bfsort */
		smbios_type_b1_flag = 1;
		break;
	case 0x02: /* do not set pci=bfsort */
		smbios_type_b1_flag = 2;
		break;
	default:
		break;
	}
}

static int __init find_sort_method(const struct dmi_system_id *d)
{
	dmi_walk(read_dmi_type_b1, NULL);

	if (smbios_type_b1_flag == 1) {
		set_bf_sort(d);
		return 0;
	}
	return -1;
}

/*
 * Enable renumbering of PCI bus# ranges to reach all PCI busses (Cardbus)
 */
#ifdef __i386__
static int __init assign_all_busses(const struct dmi_system_id *d)
{
	pci_probe |= PCI_ASSIGN_ALL_BUSSES;
	printk(KERN_INFO "%s detected: enabling PCI bus# renumbering"
			" (pci=assign-busses)\n", d->ident);
	return 0;
}
#endif

static int __init set_scan_all(const struct dmi_system_id *d)
{
	printk(KERN_INFO "PCI: %s detected, enabling pci=pcie_scan_all\n",
	       d->ident);
	pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
	return 0;
}

static const struct dmi_system_id pciprobe_dmi_table[] __initconst = {
#ifdef __i386__
/*
 * Laptops which need pci=assign-busses to see Cardbus cards
 */
	{
		.callback = assign_all_busses,
		.ident = "Samsung X20 Laptop",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Samsung Electronics"),
			DMI_MATCH(DMI_PRODUCT_NAME, "SX20S"),
		},
	},
#endif		/* __i386__ */
	{
		.callback = set_bf_sort,
		.ident = "Dell PowerEdge 1950",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1950"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "Dell PowerEdge 1955",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1955"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "Dell PowerEdge 2900",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2900"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "Dell PowerEdge 2950",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2950"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "Dell PowerEdge R900",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge R900"),
		},
	},
	{
		.callback = find_sort_method,
		.ident = "Dell System",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL20p G3",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G3"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL20p G4",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G4"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL30p G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL30p G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL25p G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL25p G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL35p G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL35p G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL45p G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL45p G2",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G2"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL460c G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL460c G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL465c G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL465c G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL480c G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL480c G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL685c G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL685c G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant DL360",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL360"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant DL380",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL380"),
		},
	},
#ifdef __i386__
	{
		.callback = assign_all_busses,
		.ident = "Compaq EVO N800c",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Compaq"),
			DMI_MATCH(DMI_PRODUCT_NAME, "EVO N800c"),
		},
	},
#endif
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant DL385 G2",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL385 G2"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant DL585 G2",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL585 G2"),
		},
	},
	{
		.callback = set_scan_all,
		.ident = "Stratus/NEC ftServer",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Stratus"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ftServer"),
		},
	},
        {
                .callback = set_scan_all,
                .ident = "Stratus/NEC ftServer",
                .matches = {
                        DMI_MATCH(DMI_SYS_VENDOR, "NEC"),
                        DMI_MATCH(DMI_PRODUCT_NAME, "Express5800/R32"),
                },
        },
        {
                .callback = set_scan_all,
                .ident = "Stratus/NEC ftServer",
                .matches = {
                        DMI_MATCH(DMI_SYS_VENDOR, "NEC"),
                        DMI_MATCH(DMI_PRODUCT_NAME, "Express5800/R31"),
                },
        },
	{}
};

void __init dmi_check_pciprobe(void)
{
	dmi_check_system(pciprobe_dmi_table);
}

void pcibios_scan_root(int busnum)
{
	struct pci_bus *bus;
	struct pci_sysdata *sd;
	LIST_HEAD(resources);

	sd = kzalloc(sizeof(*sd), GFP_KERNEL);
	if (!sd) {
		printk(KERN_ERR "PCI: OOM, skipping PCI bus %02x\n", busnum);
		return;
	}
	sd->node = x86_pci_root_bus_node(busnum);
	x86_pci_root_bus_resources(busnum, &resources);
	printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busnum);
	bus = pci_scan_root_bus(NULL, busnum, &pci_root_ops, sd, &resources);
	if (!bus) {
		pci_free_resource_list(&resources);
		kfree(sd);
		return;
	}
	pci_bus_add_devices(bus);
}

void __init pcibios_set_cache_line_size(void)
{
	struct cpuinfo_x86 *c = &boot_cpu_data;

	/*
	 * Set PCI cacheline size to that of the CPU if the CPU has reported it.
	 * (For older CPUs that don't support cpuid, we se it to 32 bytes
	 * It's also good for 386/486s (which actually have 16)
	 * as quite a few PCI devices do not support smaller values.
	 */
	if (c->x86_clflush_size > 0) {
		pci_dfl_cache_line_size = c->x86_clflush_size >> 2;
		printk(KERN_DEBUG "PCI: pci_cache_line_size set to %d bytes\n",
			pci_dfl_cache_line_size << 2);
	} else {
 		pci_dfl_cache_line_size = 32 >> 2;
		printk(KERN_DEBUG "PCI: Unknown cacheline size. Setting to 32 bytes\n");
	}
}

int __init pcibios_init(void)
{
	if (!raw_pci_ops) {
		printk(KERN_WARNING "PCI: System does not support PCI\n");
		return 0;
	}

	pcibios_set_cache_line_size();
	pcibios_resource_survey();

	if (pci_bf_sort >= pci_force_bf)
		pci_sort_breadthfirst();
	return 0;
}

char *__init pcibios_setup(char *str)
{
	if (!strcmp(str, "off")) {
		pci_probe = 0;
		return NULL;
	} else if (!strcmp(str, "bfsort")) {
		pci_bf_sort = pci_force_bf;
		return NULL;
	} else if (!strcmp(str, "nobfsort")) {
		pci_bf_sort = pci_force_nobf;
		return NULL;
	}
#ifdef CONFIG_PCI_BIOS
	else if (!strcmp(str, "bios")) {
		pci_probe = PCI_PROBE_BIOS;
		return NULL;
	} else if (!strcmp(str, "nobios")) {
		pci_probe &= ~PCI_PROBE_BIOS;
		return NULL;
	} else if (!strcmp(str, "biosirq")) {
		pci_probe |= PCI_BIOS_IRQ_SCAN;
		return NULL;
	} else if (!strncmp(str, "pirqaddr=", 9)) {
		pirq_table_addr = simple_strtoul(str+9, NULL, 0);
		return NULL;
	}
#endif
#ifdef CONFIG_PCI_DIRECT
	else if (!strcmp(str, "conf1")) {
		pci_probe = PCI_PROBE_CONF1 | PCI_NO_CHECKS;
		return NULL;
	}
	else if (!strcmp(str, "conf2")) {
		pci_probe = PCI_PROBE_CONF2 | PCI_NO_CHECKS;
		return NULL;
	}
#endif
#ifdef CONFIG_PCI_MMCONFIG
	else if (!strcmp(str, "nommconf")) {
		pci_probe &= ~PCI_PROBE_MMCONF;
		return NULL;
	}
	else if (!strcmp(str, "check_enable_amd_mmconf")) {
		pci_probe |= PCI_CHECK_ENABLE_AMD_MMCONF;
		return NULL;
	}
#endif
	else if (!strcmp(str, "noacpi")) {
		acpi_noirq_set();
		return NULL;
	}
	else if (!strcmp(str, "noearly")) {
		pci_probe |= PCI_PROBE_NOEARLY;
		return NULL;
	}
	else if (!strcmp(str, "usepirqmask")) {
		pci_probe |= PCI_USE_PIRQ_MASK;
		return NULL;
	} else if (!strncmp(str, "irqmask=", 8)) {
		pcibios_irq_mask = simple_strtol(str+8, NULL, 0);
		return NULL;
	} else if (!strncmp(str, "lastbus=", 8)) {
		pcibios_last_bus = simple_strtol(str+8, NULL, 0);
		return NULL;
	} else if (!strcmp(str, "rom")) {
		pci_probe |= PCI_ASSIGN_ROMS;
		return NULL;
	} else if (!strcmp(str, "norom")) {
		pci_probe |= PCI_NOASSIGN_ROMS;
		return NULL;
	} else if (!strcmp(str, "nobar")) {
		pci_probe |= PCI_NOASSIGN_BARS;
		return NULL;
	} else if (!strcmp(str, "assign-busses")) {
		pci_probe |= PCI_ASSIGN_ALL_BUSSES;
		return NULL;
	} else if (!strcmp(str, "use_crs")) {
		pci_probe |= PCI_USE__CRS;
		return NULL;
	} else if (!strcmp(str, "nocrs")) {
		pci_probe |= PCI_ROOT_NO_CRS;
		return NULL;
	} else if (!strcmp(str, "earlydump")) {
		pci_early_dump_regs = 1;
		return NULL;
	} else if (!strcmp(str, "routeirq")) {
		pci_routeirq = 1;
		return NULL;
	} else if (!strcmp(str, "skip_isa_align")) {
		pci_probe |= PCI_CAN_SKIP_ISA_ALIGN;
		return NULL;
	} else if (!strcmp(str, "noioapicquirk")) {
		noioapicquirk = 1;
		return NULL;
	} else if (!strcmp(str, "ioapicreroute")) {
		if (noioapicreroute != -1)
			noioapicreroute = 0;
		return NULL;
	} else if (!strcmp(str, "noioapicreroute")) {
		if (noioapicreroute != -1)
			noioapicreroute = 1;
		return NULL;
	}
	return str;
}

unsigned int pcibios_assign_all_busses(void)
{
	return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
}

int pcibios_add_device(struct pci_dev *dev)
{
	struct setup_data *data;
	struct pci_setup_rom *rom;
	u64 pa_data;

	pa_data = boot_params.hdr.setup_data;
	while (pa_data) {
		data = ioremap(pa_data, sizeof(*rom));
		if (!data)
			return -ENOMEM;

		if (data->type == SETUP_PCI) {
			rom = (struct pci_setup_rom *)data;

			if ((pci_domain_nr(dev->bus) == rom->segment) &&
			    (dev->bus->number == rom->bus) &&
			    (PCI_SLOT(dev->devfn) == rom->device) &&
			    (PCI_FUNC(dev->devfn) == rom->function) &&
			    (dev->vendor == rom->vendor) &&
			    (dev->device == rom->devid)) {
				dev->rom = pa_data +
				      offsetof(struct pci_setup_rom, romdata);
				dev->romlen = rom->pcilen;
			}
		}
		pa_data = data->next;
		iounmap(data);
	}
	return 0;
}

int pcibios_alloc_irq(struct pci_dev *dev)
{
	return pcibios_enable_irq(dev);
}

void pcibios_free_irq(struct pci_dev *dev)
{
	if (pcibios_disable_irq)
		pcibios_disable_irq(dev);
}

int pcibios_enable_device(struct pci_dev *dev, int mask)
{
	return pci_enable_resources(dev, mask);
}

int pci_ext_cfg_avail(void)
{
	if (raw_pci_ext_ops)
		return 1;
	else
		return 0;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Low-Level PCI Support for PC
	3	*
	4	* (c) 1999--2000 Martin Mares <mj@ucw.cz>
	5	*/
	6
	7	#include <linux/sched.h>
	8	#include <linux/pci.h>
89016506	9	#include <linux/pci-acpi.h>
1da177e4 LT	10	#include <linux/ioport.h>
1da177e4 LT	11	#include <linux/init.h>
8c4b2cf9	12	#include <linux/dmi.h>
5a0e3ad6	13	#include <linux/slab.h>
1da177e4	14
284f5f9d	15	#include <asm-generic/pci-bridge.h>
1da177e4 LT	16	#include <asm/acpi.h>
	17	#include <asm/segment.h>
	18	#include <asm/io.h>
	19	#include <asm/smp.h>
82487711	20	#include <asm/pci_x86.h>
f9a37be0	21	#include <asm/setup.h>
1da177e4	22
1da177e4 LT	23	unsigned int pci_probe = PCI_PROBE_BIOS \| PCI_PROBE_CONF1 \| PCI_PROBE_CONF2 \|
	24	PCI_PROBE_MMCONF;
	25
e3f2baeb	26	unsigned int pci_early_dump_regs;
2b290da0	27	static int pci_bf_sort;
6e8af08d	28	static int smbios_type_b1_flag;
1da177e4	29	int pci_routeirq;
a9322f64	30	int noioapicquirk;
41b9eb26 SA	31	#ifdef CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS
	32	int noioapicreroute = 0;
	33	#else
9197979b	34	int noioapicreroute = 1;
41b9eb26	35	#endif
1da177e4	36	int pcibios_last_bus = -1;
120bb424	37	unsigned long pirq_table_addr;
72da0b07 JB	38	const struct pci_raw_ops *__read_mostly raw_pci_ops;
72da0b07 JB	39	const struct pci_raw_ops *__read_mostly raw_pci_ext_ops;
b6ce068a MW	40
	41	int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
	42	int reg, int len, u32 *val)
	43	{
beef3129	44	if (domain == 0 && reg < 256 && raw_pci_ops)
b6ce068a MW	45	return raw_pci_ops->read(domain, bus, devfn, reg, len, val);
	46	if (raw_pci_ext_ops)
	47	return raw_pci_ext_ops->read(domain, bus, devfn, reg, len, val);
	48	return -EINVAL;
	49	}
	50
	51	int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
	52	int reg, int len, u32 val)
	53	{
beef3129	54	if (domain == 0 && reg < 256 && raw_pci_ops)
b6ce068a MW	55	return raw_pci_ops->write(domain, bus, devfn, reg, len, val);
	56	if (raw_pci_ext_ops)
	57	return raw_pci_ext_ops->write(domain, bus, devfn, reg, len, val);
	58	return -EINVAL;
	59	}
1da177e4 LT	60
	61	static int pci_read(struct pci_bus bus, unsigned int devfn, int where, int size, u32 value)
	62	{
b6ce068a	63	return raw_pci_read(pci_domain_nr(bus), bus->number,
a79e4198	64	devfn, where, size, value);
1da177e4 LT	65	}
	66
	67	static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
	68	{
b6ce068a	69	return raw_pci_write(pci_domain_nr(bus), bus->number,
a79e4198	70	devfn, where, size, value);
1da177e4 LT	71	}
	72
	73	struct pci_ops pci_root_ops = {
	74	.read = pci_read,
	75	.write = pci_write,
	76	};
	77
1da177e4 LT	78	/*
	79	* This interrupt-safe spinlock protects all accesses to PCI
	80	* configuration space.
	81	*/
d19f61f0	82	DEFINE_RAW_SPINLOCK(pci_config_lock);
1da177e4	83
4ac9cbfa	84	static int __init can_skip_ioresource_align(const struct dmi_system_id *d)
13a6ddb0 YL	85	{
	86	pci_probe \|= PCI_CAN_SKIP_ISA_ALIGN;
	87	printk(KERN_INFO "PCI: %s detected, can skip ISA alignment\n", d->ident);
	88	return 0;
	89	}
	90
4ac9cbfa	91	static const struct dmi_system_id can_skip_pciprobe_dmi_table[] __initconst = {
13a6ddb0 YL	92	/*
	93	* Systems where PCI IO resource ISA alignment can be skipped
	94	* when the ISA enable bit in the bridge control is not set
	95	*/
	96	{
	97	.callback = can_skip_ioresource_align,
	98	.ident = "IBM System x3800",
	99	.matches = {
	100	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
	101	DMI_MATCH(DMI_PRODUCT_NAME, "x3800"),
	102	},
	103	},
	104	{
	105	.callback = can_skip_ioresource_align,
	106	.ident = "IBM System x3850",
	107	.matches = {
	108	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
	109	DMI_MATCH(DMI_PRODUCT_NAME, "x3850"),
	110	},
	111	},
	112	{
	113	.callback = can_skip_ioresource_align,
	114	.ident = "IBM System x3950",
	115	.matches = {
	116	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
	117	DMI_MATCH(DMI_PRODUCT_NAME, "x3950"),
	118	},
	119	},
	120	{}
	121	};
	122
	123	void __init dmi_check_skip_isa_align(void)
	124	{
	125	dmi_check_system(can_skip_pciprobe_dmi_table);
	126	}
	127
a18e3690	128	static void pcibios_fixup_device_resources(struct pci_dev *dev)
bb71ad88 GH	129	{
bb71ad88 GH	130	struct resource *rom_r = &dev->resource[PCI_ROM_RESOURCE];
7bd1c365 MH	131	struct resource *bar_r;
	132	int bar;
	133
	134	if (pci_probe & PCI_NOASSIGN_BARS) {
	135	/*
	136	* If the BIOS did not assign the BAR, zero out the
	137	* resource so the kernel doesn't attmept to assign
	138	* it later on in pci_assign_unassigned_resources
	139	*/
	140	for (bar = 0; bar <= PCI_STD_RESOURCE_END; bar++) {
	141	bar_r = &dev->resource[bar];
	142	if (bar_r->start == 0 && bar_r->end != 0) {
	143	bar_r->flags = 0;
	144	bar_r->end = 0;
	145	}
	146	}
	147	}
bb71ad88 GH	148
	149	if (pci_probe & PCI_NOASSIGN_ROMS) {
	150	if (rom_r->parent)
	151	return;
	152	if (rom_r->start) {
	153	/* we deal with BIOS assigned ROM later */
	154	return;
	155	}
	156	rom_r->start = rom_r->end = rom_r->flags = 0;
	157	}
	158	}
	159
1da177e4 LT	160	/*
	161	* Called after each bus is probed, but before its children
	162	* are examined.
	163	*/
	164
a18e3690	165	void pcibios_fixup_bus(struct pci_bus *b)
1da177e4	166	{
bb71ad88 GH	167	struct pci_dev *dev;
bb71ad88 GH	168
bb71ad88 GH	169	list_for_each_entry(dev, &b->devices, bus_list)
bb71ad88 GH	170	pcibios_fixup_device_resources(dev);
1da177e4 LT	171	}
1da177e4 LT	172
89016506 JL	173	void pcibios_add_bus(struct pci_bus *bus)
	174	{
	175	acpi_pci_add_bus(bus);
	176	}
	177
	178	void pcibios_remove_bus(struct pci_bus *bus)
	179	{
	180	acpi_pci_remove_bus(bus);
	181	}
	182
6b4b78fe MD	183	/*
	184	* Only use DMI information to set this if nothing was passed
	185	* on the kernel command line (which was parsed earlier).
	186	*/
	187
4ac9cbfa	188	static int __init set_bf_sort(const struct dmi_system_id *d)
6b4b78fe MD	189	{
	190	if (pci_bf_sort == pci_bf_sort_default) {
	191	pci_bf_sort = pci_dmi_bf;
	192	printk(KERN_INFO "PCI: %s detected, enabling pci=bfsort.\n", d->ident);
	193	}
	194	return 0;
	195	}
	196
4ac9cbfa MK	197	static void __init read_dmi_type_b1(const struct dmi_header *dm,
4ac9cbfa MK	198	void *private_data)
6e8af08d ND	199	{
	200	u8 d = (u8 )dm + 4;
	201
	202	if (dm->type != 0xB1)
	203	return;
	204	switch ((((u32 )d) >> 9) & 0x03) {
	205	case 0x00:
	206	printk(KERN_INFO "dmi type 0xB1 record - unknown flag\n");
	207	break;
	208	case 0x01: /* set pci=bfsort */
	209	smbios_type_b1_flag = 1;
	210	break;
	211	case 0x02: /* do not set pci=bfsort */
	212	smbios_type_b1_flag = 2;
	213	break;
	214	default:
	215	break;
	216	}
	217	}
	218
4ac9cbfa	219	static int __init find_sort_method(const struct dmi_system_id *d)
6e8af08d ND	220	{
	221	dmi_walk(read_dmi_type_b1, NULL);
	222
	223	if (smbios_type_b1_flag == 1) {
	224	set_bf_sort(d);
	225	return 0;
	226	}
	227	return -1;
	228	}
	229
8c4b2cf9 BK	230	/*
	231	* Enable renumbering of PCI bus# ranges to reach all PCI busses (Cardbus)
	232	*/
	233	#ifdef __i386__
4ac9cbfa	234	static int __init assign_all_busses(const struct dmi_system_id *d)
8c4b2cf9 BK	235	{
	236	pci_probe \|= PCI_ASSIGN_ALL_BUSSES;
	237	printk(KERN_INFO "%s detected: enabling PCI bus# renumbering"
	238	" (pci=assign-busses)\n", d->ident);
	239	return 0;
	240	}
	241	#endif
	242
4ac9cbfa	243	static int __init set_scan_all(const struct dmi_system_id *d)
284f5f9d BH	244	{
	245	printk(KERN_INFO "PCI: %s detected, enabling pci=pcie_scan_all\n",
	246	d->ident);
	247	pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
	248	return 0;
	249	}
	250
4ac9cbfa	251	static const struct dmi_system_id pciprobe_dmi_table[] __initconst = {
6b4b78fe	252	#ifdef __i386__
8c4b2cf9 BK	253	/*
	254	* Laptops which need pci=assign-busses to see Cardbus cards
	255	*/
8c4b2cf9 BK	256	{
	257	.callback = assign_all_busses,
	258	.ident = "Samsung X20 Laptop",
	259	.matches = {
	260	DMI_MATCH(DMI_SYS_VENDOR, "Samsung Electronics"),
	261	DMI_MATCH(DMI_PRODUCT_NAME, "SX20S"),
	262	},
	263	},
	264	#endif /* __i386__ */
6b4b78fe MD	265	{
	266	.callback = set_bf_sort,
	267	.ident = "Dell PowerEdge 1950",
	268	.matches = {
	269	DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
	270	DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1950"),
	271	},
	272	},
	273	{
	274	.callback = set_bf_sort,
	275	.ident = "Dell PowerEdge 1955",
	276	.matches = {
	277	DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
	278	DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1955"),
	279	},
	280	},
	281	{
	282	.callback = set_bf_sort,
	283	.ident = "Dell PowerEdge 2900",
	284	.matches = {
	285	DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
	286	DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2900"),
	287	},
	288	},
	289	{
	290	.callback = set_bf_sort,
	291	.ident = "Dell PowerEdge 2950",
	292	.matches = {
	293	DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
	294	DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2950"),
	295	},
	296	},
f7a9dae7 MD	297	{
	298	.callback = set_bf_sort,
	299	.ident = "Dell PowerEdge R900",
	300	.matches = {
	301	DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
	302	DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge R900"),
	303	},
	304	},
9b373ed1 ND	305	{
	306	.callback = find_sort_method,
	307	.ident = "Dell System",
	308	.matches = {
	309	DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
	310	},
	311	},
f52383d3 AG	312	{
	313	.callback = set_bf_sort,
	314	.ident = "HP ProLiant BL20p G3",
	315	.matches = {
	316	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	317	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G3"),
	318	},
	319	},
	320	{
	321	.callback = set_bf_sort,
	322	.ident = "HP ProLiant BL20p G4",
	323	.matches = {
	324	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	325	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G4"),
	326	},
	327	},
	328	{
	329	.callback = set_bf_sort,
	330	.ident = "HP ProLiant BL30p G1",
	331	.matches = {
	332	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	333	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL30p G1"),
	334	},
	335	},
	336	{
	337	.callback = set_bf_sort,
	338	.ident = "HP ProLiant BL25p G1",
	339	.matches = {
	340	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	341	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL25p G1"),
	342	},
	343	},
	344	{
	345	.callback = set_bf_sort,
	346	.ident = "HP ProLiant BL35p G1",
	347	.matches = {
	348	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	349	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL35p G1"),
	350	},
	351	},
	352	{
	353	.callback = set_bf_sort,
	354	.ident = "HP ProLiant BL45p G1",
	355	.matches = {
	356	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	357	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G1"),
	358	},
	359	},
	360	{
	361	.callback = set_bf_sort,
	362	.ident = "HP ProLiant BL45p G2",
	363	.matches = {
	364	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	365	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G2"),
	366	},
	367	},
	368	{
	369	.callback = set_bf_sort,
	370	.ident = "HP ProLiant BL460c G1",
	371	.matches = {
	372	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	373	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL460c G1"),
	374	},
	375	},
376	{
377	.callback = set_bf_sort,
378	.ident = "HP ProLiant BL465c G1",
379	.matches = {
380	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
381	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL465c G1"),
382	},
383	},
384	{
385	.callback = set_bf_sort,
386	.ident = "HP ProLiant BL480c G1",
387	.matches = {
388	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
389	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL480c G1"),
390	},
391	},
392	{
393	.callback = set_bf_sort,
394	.ident = "HP ProLiant BL685c G1",
395	.matches = {
396	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
397	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL685c G1"),
398	},
399	},
8f8ae1a7 MS	400	{
8f8ae1a7 MS	401	.callback = set_bf_sort,
8d64c781	402	.ident = "HP ProLiant DL360",
8f8ae1a7 MS	403	.matches = {
8f8ae1a7 MS	404	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
8d64c781	405	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL360"),
8f8ae1a7 MS	406	},
	407	},
	408	{
	409	.callback = set_bf_sort,
8d64c781	410	.ident = "HP ProLiant DL380",
8f8ae1a7 MS	411	.matches = {
8f8ae1a7 MS	412	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
8d64c781	413	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL380"),
8f8ae1a7 MS	414	},
8f8ae1a7 MS	415	},
5b1ea82f JL	416	#ifdef __i386__
	417	{
	418	.callback = assign_all_busses,
	419	.ident = "Compaq EVO N800c",
	420	.matches = {
	421	DMI_MATCH(DMI_SYS_VENDOR, "Compaq"),
	422	DMI_MATCH(DMI_PRODUCT_NAME, "EVO N800c"),
	423	},
	424	},
	425	#endif
c82bc5ad MS	426	{
c82bc5ad MS	427	.callback = set_bf_sort,
739db07f	428	.ident = "HP ProLiant DL385 G2",
c82bc5ad MS	429	.matches = {
c82bc5ad MS	430	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
739db07f	431	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL385 G2"),
c82bc5ad MS	432	},
	433	},
	434	{
	435	.callback = set_bf_sort,
739db07f	436	.ident = "HP ProLiant DL585 G2",
c82bc5ad MS	437	.matches = {
c82bc5ad MS	438	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
739db07f	439	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL585 G2"),
c82bc5ad MS	440	},
c82bc5ad MS	441	},
284f5f9d BH	442	{
	443	.callback = set_scan_all,
	444	.ident = "Stratus/NEC ftServer",
	445	.matches = {
1278998f MS	446	DMI_MATCH(DMI_SYS_VENDOR, "Stratus"),
1278998f MS	447	DMI_MATCH(DMI_PRODUCT_NAME, "ftServer"),
284f5f9d BH	448	},
284f5f9d BH	449	},
51ac3d2f CR	450	{
	451	.callback = set_scan_all,
	452	.ident = "Stratus/NEC ftServer",
	453	.matches = {
	454	DMI_MATCH(DMI_SYS_VENDOR, "NEC"),
	455	DMI_MATCH(DMI_PRODUCT_NAME, "Express5800/R32"),
	456	},
	457	},
	458	{
	459	.callback = set_scan_all,
	460	.ident = "Stratus/NEC ftServer",
	461	.matches = {
	462	DMI_MATCH(DMI_SYS_VENDOR, "NEC"),
	463	DMI_MATCH(DMI_PRODUCT_NAME, "Express5800/R31"),
	464	},
	465	},
8c4b2cf9 BK	466	{}
8c4b2cf9 BK	467	};
1da177e4	468
0df18ff3 YL	469	void __init dmi_check_pciprobe(void)
	470	{
	471	dmi_check_system(pciprobe_dmi_table);
	472	}
	473
49886cf4	474	void pcibios_scan_root(int busnum)
1da177e4	475	{
289a24a6 BH	476	struct pci_bus *bus;
	477	struct pci_sysdata *sd;
	478	LIST_HEAD(resources);
	479
	480	sd = kzalloc(sizeof(*sd), GFP_KERNEL);
	481	if (!sd) {
	482	printk(KERN_ERR "PCI: OOM, skipping PCI bus %02x\n", busnum);
49886cf4	483	return;
289a24a6	484	}
6616dbdf	485	sd->node = x86_pci_root_bus_node(busnum);
289a24a6 BH	486	x86_pci_root_bus_resources(busnum, &resources);
	487	printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busnum);
	488	bus = pci_scan_root_bus(NULL, busnum, &pci_root_ops, sd, &resources);
	489	if (!bus) {
	490	pci_free_resource_list(&resources);
	491	kfree(sd);
b97ea289	492	return;
289a24a6	493	}
b97ea289	494	pci_bus_add_devices(bus);
1da177e4	495	}
c57ca65a	496
44de3395	497	void __init pcibios_set_cache_line_size(void)
1da177e4 LT	498	{
	499	struct cpuinfo_x86 *c = &boot_cpu_data;
	500
1da177e4	501	/*
76b1a87b DJ	502	* Set PCI cacheline size to that of the CPU if the CPU has reported it.
	503	* (For older CPUs that don't support cpuid, we se it to 32 bytes
	504	* It's also good for 386/486s (which actually have 16)
1da177e4 LT	505	* as quite a few PCI devices do not support smaller values.
1da177e4 LT	506	*/
76b1a87b DJ	507	if (c->x86_clflush_size > 0) {
	508	pci_dfl_cache_line_size = c->x86_clflush_size >> 2;
	509	printk(KERN_DEBUG "PCI: pci_cache_line_size set to %d bytes\n",
	510	pci_dfl_cache_line_size << 2);
	511	} else {
	512	pci_dfl_cache_line_size = 32 >> 2;
	513	printk(KERN_DEBUG "PCI: Unknown cacheline size. Setting to 32 bytes\n");
	514	}
44de3395 AN	515	}
	516
	517	int __init pcibios_init(void)
	518	{
	519	if (!raw_pci_ops) {
	520	printk(KERN_WARNING "PCI: System does not support PCI\n");
	521	return 0;
	522	}
1da177e4	523
44de3395	524	pcibios_set_cache_line_size();
1da177e4 LT	525	pcibios_resource_survey();
1da177e4 LT	526
6b4b78fe MD	527	if (pci_bf_sort >= pci_force_bf)
6b4b78fe MD	528	pci_sort_breadthfirst();
1da177e4 LT	529	return 0;
	530	}
	531
4ac9cbfa	532	char __init pcibios_setup(char str)
1da177e4 LT	533	{
	534	if (!strcmp(str, "off")) {
	535	pci_probe = 0;
	536	return NULL;
6b4b78fe MD	537	} else if (!strcmp(str, "bfsort")) {
	538	pci_bf_sort = pci_force_bf;
	539	return NULL;
	540	} else if (!strcmp(str, "nobfsort")) {
	541	pci_bf_sort = pci_force_nobf;
	542	return NULL;
1da177e4 LT	543	}
	544	#ifdef CONFIG_PCI_BIOS
	545	else if (!strcmp(str, "bios")) {
	546	pci_probe = PCI_PROBE_BIOS;
	547	return NULL;
	548	} else if (!strcmp(str, "nobios")) {
	549	pci_probe &= ~PCI_PROBE_BIOS;
	550	return NULL;
1da177e4 LT	551	} else if (!strcmp(str, "biosirq")) {
	552	pci_probe \|= PCI_BIOS_IRQ_SCAN;
	553	return NULL;
120bb424	554	} else if (!strncmp(str, "pirqaddr=", 9)) {
	555	pirq_table_addr = simple_strtoul(str+9, NULL, 0);
	556	return NULL;
1da177e4 LT	557	}
	558	#endif
	559	#ifdef CONFIG_PCI_DIRECT
	560	else if (!strcmp(str, "conf1")) {
	561	pci_probe = PCI_PROBE_CONF1 \| PCI_NO_CHECKS;
	562	return NULL;
	563	}
	564	else if (!strcmp(str, "conf2")) {
	565	pci_probe = PCI_PROBE_CONF2 \| PCI_NO_CHECKS;
	566	return NULL;
	567	}
	568	#endif
	569	#ifdef CONFIG_PCI_MMCONFIG
	570	else if (!strcmp(str, "nommconf")) {
	571	pci_probe &= ~PCI_PROBE_MMCONF;
	572	return NULL;
	573	}
5f0b2976 YL	574	else if (!strcmp(str, "check_enable_amd_mmconf")) {
	575	pci_probe \|= PCI_CHECK_ENABLE_AMD_MMCONF;
	576	return NULL;
	577	}
1da177e4 LT	578	#endif
	579	else if (!strcmp(str, "noacpi")) {
	580	acpi_noirq_set();
	581	return NULL;
	582	}
0637a70a AK	583	else if (!strcmp(str, "noearly")) {
	584	pci_probe \|= PCI_PROBE_NOEARLY;
	585	return NULL;
	586	}
1da177e4 LT	587	else if (!strcmp(str, "usepirqmask")) {
	588	pci_probe \|= PCI_USE_PIRQ_MASK;
	589	return NULL;
	590	} else if (!strncmp(str, "irqmask=", 8)) {
	591	pcibios_irq_mask = simple_strtol(str+8, NULL, 0);
	592	return NULL;
	593	} else if (!strncmp(str, "lastbus=", 8)) {
	594	pcibios_last_bus = simple_strtol(str+8, NULL, 0);
	595	return NULL;
c5f9ee3d	596	} else if (!strcmp(str, "rom")) {
1da177e4 LT	597	pci_probe \|= PCI_ASSIGN_ROMS;
1da177e4 LT	598	return NULL;
bb71ad88 GH	599	} else if (!strcmp(str, "norom")) {
	600	pci_probe \|= PCI_NOASSIGN_ROMS;
	601	return NULL;
7bd1c365 MH	602	} else if (!strcmp(str, "nobar")) {
	603	pci_probe \|= PCI_NOASSIGN_BARS;
	604	return NULL;
1da177e4 LT	605	} else if (!strcmp(str, "assign-busses")) {
	606	pci_probe \|= PCI_ASSIGN_ALL_BUSSES;
	607	return NULL;
236e946b LT	608	} else if (!strcmp(str, "use_crs")) {
236e946b LT	609	pci_probe \|= PCI_USE__CRS;
62f420f8	610	return NULL;
7bc5e3f2 BH	611	} else if (!strcmp(str, "nocrs")) {
	612	pci_probe \|= PCI_ROOT_NO_CRS;
	613	return NULL;
e3f2baeb YL	614	} else if (!strcmp(str, "earlydump")) {
	615	pci_early_dump_regs = 1;
	616	return NULL;
1da177e4 LT	617	} else if (!strcmp(str, "routeirq")) {
	618	pci_routeirq = 1;
	619	return NULL;
13a6ddb0 YL	620	} else if (!strcmp(str, "skip_isa_align")) {
	621	pci_probe \|= PCI_CAN_SKIP_ISA_ALIGN;
	622	return NULL;
a9322f64 SA	623	} else if (!strcmp(str, "noioapicquirk")) {
	624	noioapicquirk = 1;
	625	return NULL;
9197979b SA	626	} else if (!strcmp(str, "ioapicreroute")) {
	627	if (noioapicreroute != -1)
	628	noioapicreroute = 0;
	629	return NULL;
41b9eb26 SA	630	} else if (!strcmp(str, "noioapicreroute")) {
	631	if (noioapicreroute != -1)
	632	noioapicreroute = 1;
	633	return NULL;
1da177e4 LT	634	}
	635	return str;
	636	}
	637
	638	unsigned int pcibios_assign_all_busses(void)
	639	{
	640	return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
	641	}
	642
f9a37be0 MG	643	int pcibios_add_device(struct pci_dev *dev)
	644	{
	645	struct setup_data *data;
	646	struct pci_setup_rom *rom;
	647	u64 pa_data;
	648
	649	pa_data = boot_params.hdr.setup_data;
	650	while (pa_data) {
65694c5a MF	651	data = ioremap(pa_data, sizeof(*rom));
	652	if (!data)
	653	return -ENOMEM;
f9a37be0 MG	654
	655	if (data->type == SETUP_PCI) {
	656	rom = (struct pci_setup_rom *)data;
	657
	658	if ((pci_domain_nr(dev->bus) == rom->segment) &&
	659	(dev->bus->number == rom->bus) &&
	660	(PCI_SLOT(dev->devfn) == rom->device) &&
	661	(PCI_FUNC(dev->devfn) == rom->function) &&
	662	(dev->vendor == rom->vendor) &&
	663	(dev->device == rom->devid)) {
dbd3fc33 BH	664	dev->rom = pa_data +
dbd3fc33 BH	665	offsetof(struct pci_setup_rom, romdata);
f9a37be0 MG	666	dev->romlen = rom->pcilen;
	667	}
	668	}
	669	pa_data = data->next;
65694c5a	670	iounmap(data);
f9a37be0 MG	671	}
	672	return 0;
	673	}
	674
991de2e5	675	int pcibios_alloc_irq(struct pci_dev *dev)
1da177e4	676	{
991de2e5	677	return pcibios_enable_irq(dev);
1da177e4	678	}
87bec66b	679
991de2e5	680	void pcibios_free_irq(struct pci_dev *dev)
9e8ce4b9	681	{
991de2e5	682	if (pcibios_disable_irq)
9e8ce4b9 RW	683	pcibios_disable_irq(dev);
	684	}
	685
991de2e5 JL	686	int pcibios_enable_device(struct pci_dev *dev, int mask)
	687	{
	688	return pci_enable_resources(dev, mask);
	689	}
	690
642c92da	691	int pci_ext_cfg_avail(void)
0ef5f8f6 AP	692	{
	693	if (raw_pci_ext_ops)
	694	return 1;
	695	else
	696	return 0;
	697	}