[deliverable/linux.git] / arch / x86 / pci / common.c

/*
 *	Low-Level PCI Support for PC
 *
 *	(c) 1999--2000 Martin Mares <mj@ucw.cz>
 */

#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/dmi.h>
#include <linux/slab.h>

#include <asm-generic/pci-bridge.h>
#include <asm/acpi.h>
#include <asm/segment.h>
#include <asm/io.h>
#include <asm/smp.h>
#include <asm/pci_x86.h>

unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2 |
				PCI_PROBE_MMCONF;

unsigned int pci_early_dump_regs;
static int pci_bf_sort;
static int smbios_type_b1_flag;
int pci_routeirq;
int noioapicquirk;
#ifdef CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS
int noioapicreroute = 0;
#else
int noioapicreroute = 1;
#endif
int pcibios_last_bus = -1;
unsigned long pirq_table_addr;
struct pci_bus *pci_root_bus;
const struct pci_raw_ops *__read_mostly raw_pci_ops;
const struct pci_raw_ops *__read_mostly raw_pci_ext_ops;

int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
						int reg, int len, u32 *val)
{
	if (domain == 0 && reg < 256 && raw_pci_ops)
		return raw_pci_ops->read(domain, bus, devfn, reg, len, val);
	if (raw_pci_ext_ops)
		return raw_pci_ext_ops->read(domain, bus, devfn, reg, len, val);
	return -EINVAL;
}

int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
						int reg, int len, u32 val)
{
	if (domain == 0 && reg < 256 && raw_pci_ops)
		return raw_pci_ops->write(domain, bus, devfn, reg, len, val);
	if (raw_pci_ext_ops)
		return raw_pci_ext_ops->write(domain, bus, devfn, reg, len, val);
	return -EINVAL;
}

static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
{
	return raw_pci_read(pci_domain_nr(bus), bus->number,
				 devfn, where, size, value);
}

static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
{
	return raw_pci_write(pci_domain_nr(bus), bus->number,
				  devfn, where, size, value);
}

struct pci_ops pci_root_ops = {
	.read = pci_read,
	.write = pci_write,
};

/*
 * This interrupt-safe spinlock protects all accesses to PCI
 * configuration space.
 */
DEFINE_RAW_SPINLOCK(pci_config_lock);

static int __devinit can_skip_ioresource_align(const struct dmi_system_id *d)
{
	pci_probe |= PCI_CAN_SKIP_ISA_ALIGN;
	printk(KERN_INFO "PCI: %s detected, can skip ISA alignment\n", d->ident);
	return 0;
}

static const struct dmi_system_id can_skip_pciprobe_dmi_table[] __devinitconst = {
/*
 * Systems where PCI IO resource ISA alignment can be skipped
 * when the ISA enable bit in the bridge control is not set
 */
	{
		.callback = can_skip_ioresource_align,
		.ident = "IBM System x3800",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "x3800"),
		},
	},
	{
		.callback = can_skip_ioresource_align,
		.ident = "IBM System x3850",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "x3850"),
		},
	},
	{
		.callback = can_skip_ioresource_align,
		.ident = "IBM System x3950",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "x3950"),
		},
	},
	{}
};

void __init dmi_check_skip_isa_align(void)
{
	dmi_check_system(can_skip_pciprobe_dmi_table);
}

static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
{
	struct resource *rom_r = &dev->resource[PCI_ROM_RESOURCE];
	struct resource *bar_r;
	int bar;

	if (pci_probe & PCI_NOASSIGN_BARS) {
		/*
		* If the BIOS did not assign the BAR, zero out the
		* resource so the kernel doesn't attmept to assign
		* it later on in pci_assign_unassigned_resources
		*/
		for (bar = 0; bar <= PCI_STD_RESOURCE_END; bar++) {
			bar_r = &dev->resource[bar];
			if (bar_r->start == 0 && bar_r->end != 0) {
				bar_r->flags = 0;
				bar_r->end = 0;
			}
		}
	}

	if (pci_probe & PCI_NOASSIGN_ROMS) {
		if (rom_r->parent)
			return;
		if (rom_r->start) {
			/* we deal with BIOS assigned ROM later */
			return;
		}
		rom_r->start = rom_r->end = rom_r->flags = 0;
	}
}

/*
 *  Called after each bus is probed, but before its children
 *  are examined.
 */

void __devinit pcibios_fixup_bus(struct pci_bus *b)
{
	struct pci_dev *dev;

	pci_read_bridge_bases(b);
	list_for_each_entry(dev, &b->devices, bus_list)
		pcibios_fixup_device_resources(dev);
}

/*
 * Only use DMI information to set this if nothing was passed
 * on the kernel command line (which was parsed earlier).
 */

static int __devinit set_bf_sort(const struct dmi_system_id *d)
{
	if (pci_bf_sort == pci_bf_sort_default) {
		pci_bf_sort = pci_dmi_bf;
		printk(KERN_INFO "PCI: %s detected, enabling pci=bfsort.\n", d->ident);
	}
	return 0;
}

static void __devinit read_dmi_type_b1(const struct dmi_header *dm,
				       void *private_data)
{
	u8 *d = (u8 *)dm + 4;

	if (dm->type != 0xB1)
		return;
	switch (((*(u32 *)d) >> 9) & 0x03) {
	case 0x00:
		printk(KERN_INFO "dmi type 0xB1 record - unknown flag\n");
		break;
	case 0x01: /* set pci=bfsort */
		smbios_type_b1_flag = 1;
		break;
	case 0x02: /* do not set pci=bfsort */
		smbios_type_b1_flag = 2;
		break;
	default:
		break;
	}
}

static int __devinit find_sort_method(const struct dmi_system_id *d)
{
	dmi_walk(read_dmi_type_b1, NULL);

	if (smbios_type_b1_flag == 1) {
		set_bf_sort(d);
		return 0;
	}
	return -1;
}

/*
 * Enable renumbering of PCI bus# ranges to reach all PCI busses (Cardbus)
 */
#ifdef __i386__
static int __devinit assign_all_busses(const struct dmi_system_id *d)
{
	pci_probe |= PCI_ASSIGN_ALL_BUSSES;
	printk(KERN_INFO "%s detected: enabling PCI bus# renumbering"
			" (pci=assign-busses)\n", d->ident);
	return 0;
}
#endif

static int __devinit set_scan_all(const struct dmi_system_id *d)
{
	printk(KERN_INFO "PCI: %s detected, enabling pci=pcie_scan_all\n",
	       d->ident);
	pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
	return 0;
}

static const struct dmi_system_id __devinitconst pciprobe_dmi_table[] = {
#ifdef __i386__
/*
 * Laptops which need pci=assign-busses to see Cardbus cards
 */
	{
		.callback = assign_all_busses,
		.ident = "Samsung X20 Laptop",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Samsung Electronics"),
			DMI_MATCH(DMI_PRODUCT_NAME, "SX20S"),
		},
	},
#endif		/* __i386__ */
	{
		.callback = set_bf_sort,
		.ident = "Dell PowerEdge 1950",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1950"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "Dell PowerEdge 1955",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1955"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "Dell PowerEdge 2900",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2900"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "Dell PowerEdge 2950",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2950"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "Dell PowerEdge R900",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge R900"),
		},
	},
	{
		.callback = find_sort_method,
		.ident = "Dell System",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL20p G3",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G3"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL20p G4",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G4"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL30p G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL30p G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL25p G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL25p G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL35p G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL35p G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL45p G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL45p G2",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G2"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL460c G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL460c G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL465c G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL465c G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL480c G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL480c G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL685c G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL685c G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant DL360",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL360"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant DL380",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL380"),
		},
	},
#ifdef __i386__
	{
		.callback = assign_all_busses,
		.ident = "Compaq EVO N800c",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Compaq"),
			DMI_MATCH(DMI_PRODUCT_NAME, "EVO N800c"),
		},
	},
#endif
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant DL385 G2",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL385 G2"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant DL585 G2",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL585 G2"),
		},
	},
	{
		.callback = set_scan_all,
		.ident = "Stratus/NEC ftServer",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "ftServer"),
		},
	},
	{}
};

void __init dmi_check_pciprobe(void)
{
	dmi_check_system(pciprobe_dmi_table);
}

struct pci_bus * __devinit pcibios_scan_root(int busnum)
{
	struct pci_bus *bus = NULL;

	while ((bus = pci_find_next_bus(bus)) != NULL) {
		if (bus->number == busnum) {
			/* Already scanned */
			return bus;
		}
	}

	return pci_scan_bus_on_node(busnum, &pci_root_ops,
					get_mp_bus_to_node(busnum));
}

void __init pcibios_set_cache_line_size(void)
{
	struct cpuinfo_x86 *c = &boot_cpu_data;

	/*
	 * Set PCI cacheline size to that of the CPU if the CPU has reported it.
	 * (For older CPUs that don't support cpuid, we se it to 32 bytes
	 * It's also good for 386/486s (which actually have 16)
	 * as quite a few PCI devices do not support smaller values.
	 */
	if (c->x86_clflush_size > 0) {
		pci_dfl_cache_line_size = c->x86_clflush_size >> 2;
		printk(KERN_DEBUG "PCI: pci_cache_line_size set to %d bytes\n",
			pci_dfl_cache_line_size << 2);
	} else {
 		pci_dfl_cache_line_size = 32 >> 2;
		printk(KERN_DEBUG "PCI: Unknown cacheline size. Setting to 32 bytes\n");
	}
}

int __init pcibios_init(void)
{
	if (!raw_pci_ops) {
		printk(KERN_WARNING "PCI: System does not support PCI\n");
		return 0;
	}

	pcibios_set_cache_line_size();
	pcibios_resource_survey();

	if (pci_bf_sort >= pci_force_bf)
		pci_sort_breadthfirst();
	return 0;
}

char * __init pcibios_setup(char *str)
{
	if (!strcmp(str, "off")) {
		pci_probe = 0;
		return NULL;
	} else if (!strcmp(str, "bfsort")) {
		pci_bf_sort = pci_force_bf;
		return NULL;
	} else if (!strcmp(str, "nobfsort")) {
		pci_bf_sort = pci_force_nobf;
		return NULL;
	}
#ifdef CONFIG_PCI_BIOS
	else if (!strcmp(str, "bios")) {
		pci_probe = PCI_PROBE_BIOS;
		return NULL;
	} else if (!strcmp(str, "nobios")) {
		pci_probe &= ~PCI_PROBE_BIOS;
		return NULL;
	} else if (!strcmp(str, "biosirq")) {
		pci_probe |= PCI_BIOS_IRQ_SCAN;
		return NULL;
	} else if (!strncmp(str, "pirqaddr=", 9)) {
		pirq_table_addr = simple_strtoul(str+9, NULL, 0);
		return NULL;
	}
#endif
#ifdef CONFIG_PCI_DIRECT
	else if (!strcmp(str, "conf1")) {
		pci_probe = PCI_PROBE_CONF1 | PCI_NO_CHECKS;
		return NULL;
	}
	else if (!strcmp(str, "conf2")) {
		pci_probe = PCI_PROBE_CONF2 | PCI_NO_CHECKS;
		return NULL;
	}
#endif
#ifdef CONFIG_PCI_MMCONFIG
	else if (!strcmp(str, "nommconf")) {
		pci_probe &= ~PCI_PROBE_MMCONF;
		return NULL;
	}
	else if (!strcmp(str, "check_enable_amd_mmconf")) {
		pci_probe |= PCI_CHECK_ENABLE_AMD_MMCONF;
		return NULL;
	}
#endif
	else if (!strcmp(str, "noacpi")) {
		acpi_noirq_set();
		return NULL;
	}
	else if (!strcmp(str, "noearly")) {
		pci_probe |= PCI_PROBE_NOEARLY;
		return NULL;
	}
#ifndef CONFIG_X86_VISWS
	else if (!strcmp(str, "usepirqmask")) {
		pci_probe |= PCI_USE_PIRQ_MASK;
		return NULL;
	} else if (!strncmp(str, "irqmask=", 8)) {
		pcibios_irq_mask = simple_strtol(str+8, NULL, 0);
		return NULL;
	} else if (!strncmp(str, "lastbus=", 8)) {
		pcibios_last_bus = simple_strtol(str+8, NULL, 0);
		return NULL;
	}
#endif
	else if (!strcmp(str, "rom")) {
		pci_probe |= PCI_ASSIGN_ROMS;
		return NULL;
	} else if (!strcmp(str, "norom")) {
		pci_probe |= PCI_NOASSIGN_ROMS;
		return NULL;
	} else if (!strcmp(str, "nobar")) {
		pci_probe |= PCI_NOASSIGN_BARS;
		return NULL;
	} else if (!strcmp(str, "assign-busses")) {
		pci_probe |= PCI_ASSIGN_ALL_BUSSES;
		return NULL;
	} else if (!strcmp(str, "use_crs")) {
		pci_probe |= PCI_USE__CRS;
		return NULL;
	} else if (!strcmp(str, "nocrs")) {
		pci_probe |= PCI_ROOT_NO_CRS;
		return NULL;
	} else if (!strcmp(str, "earlydump")) {
		pci_early_dump_regs = 1;
		return NULL;
	} else if (!strcmp(str, "routeirq")) {
		pci_routeirq = 1;
		return NULL;
	} else if (!strcmp(str, "skip_isa_align")) {
		pci_probe |= PCI_CAN_SKIP_ISA_ALIGN;
		return NULL;
	} else if (!strcmp(str, "noioapicquirk")) {
		noioapicquirk = 1;
		return NULL;
	} else if (!strcmp(str, "ioapicreroute")) {
		if (noioapicreroute != -1)
			noioapicreroute = 0;
		return NULL;
	} else if (!strcmp(str, "noioapicreroute")) {
		if (noioapicreroute != -1)
			noioapicreroute = 1;
		return NULL;
	}
	return str;
}

unsigned int pcibios_assign_all_busses(void)
{
	return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
}

int pcibios_enable_device(struct pci_dev *dev, int mask)
{
	int err;

	if ((err = pci_enable_resources(dev, mask)) < 0)
		return err;

	if (!pci_dev_msi_enabled(dev))
		return pcibios_enable_irq(dev);
	return 0;
}

void pcibios_disable_device (struct pci_dev *dev)
{
	if (!pci_dev_msi_enabled(dev) && pcibios_disable_irq)
		pcibios_disable_irq(dev);
}

int pci_ext_cfg_avail(struct pci_dev *dev)
{
	if (raw_pci_ext_ops)
		return 1;
	else
		return 0;
}

struct pci_bus * __devinit pci_scan_bus_on_node(int busno, struct pci_ops *ops, int node)
{
	LIST_HEAD(resources);
	struct pci_bus *bus = NULL;
	struct pci_sysdata *sd;

	/*
	 * Allocate per-root-bus (not per bus) arch-specific data.
	 * TODO: leak; this memory is never freed.
	 * It's arguable whether it's worth the trouble to care.
	 */
	sd = kzalloc(sizeof(*sd), GFP_KERNEL);
	if (!sd) {
		printk(KERN_ERR "PCI: OOM, skipping PCI bus %02x\n", busno);
		return NULL;
	}
	sd->node = node;
	x86_pci_root_bus_resources(busno, &resources);
	printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busno);
	bus = pci_scan_root_bus(NULL, busno, ops, sd, &resources);
	if (!bus) {
		pci_free_resource_list(&resources);
		kfree(sd);
	}

	return bus;
}

struct pci_bus * __devinit pci_scan_bus_with_sysdata(int busno)
{
	return pci_scan_bus_on_node(busno, &pci_root_ops, -1);
}

/*
 * NUMA info for PCI busses
 *
 * Early arch code is responsible for filling in reasonable values here.
 * A node id of "-1" means "use current node".  In other words, if a bus
 * has a -1 node id, it's not tightly coupled to any particular chunk
 * of memory (as is the case on some Nehalem systems).
 */
#ifdef CONFIG_NUMA

#define BUS_NR 256

#ifdef CONFIG_X86_64

static int mp_bus_to_node[BUS_NR] = {
	[0 ... BUS_NR - 1] = -1
};

void set_mp_bus_to_node(int busnum, int node)
{
	if (busnum >= 0 &&  busnum < BUS_NR)
		mp_bus_to_node[busnum] = node;
}

int get_mp_bus_to_node(int busnum)
{
	int node = -1;

	if (busnum < 0 || busnum > (BUS_NR - 1))
		return node;

	node = mp_bus_to_node[busnum];

	/*
	 * let numa_node_id to decide it later in dma_alloc_pages
	 * if there is no ram on that node
	 */
	if (node != -1 && !node_online(node))
		node = -1;

	return node;
}

#else /* CONFIG_X86_32 */

static int mp_bus_to_node[BUS_NR] = {
	[0 ... BUS_NR - 1] = -1
};

void set_mp_bus_to_node(int busnum, int node)
{
	if (busnum >= 0 &&  busnum < BUS_NR)
	mp_bus_to_node[busnum] = (unsigned char) node;
}

int get_mp_bus_to_node(int busnum)
{
	int node;

	if (busnum < 0 || busnum > (BUS_NR - 1))
		return 0;
	node = mp_bus_to_node[busnum];
	return node;
}

#endif /* CONFIG_X86_32 */

#endif /* CONFIG_NUMA */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Low-Level PCI Support for PC
	3	*
	4	* (c) 1999--2000 Martin Mares <mj@ucw.cz>
	5	*/
	6
	7	#include <linux/sched.h>
	8	#include <linux/pci.h>
	9	#include <linux/ioport.h>
	10	#include <linux/init.h>
8c4b2cf9	11	#include <linux/dmi.h>
5a0e3ad6	12	#include <linux/slab.h>
1da177e4	13
284f5f9d	14	#include <asm-generic/pci-bridge.h>
1da177e4 LT	15	#include <asm/acpi.h>
	16	#include <asm/segment.h>
	17	#include <asm/io.h>
	18	#include <asm/smp.h>
82487711	19	#include <asm/pci_x86.h>
1da177e4	20
1da177e4 LT	21	unsigned int pci_probe = PCI_PROBE_BIOS \| PCI_PROBE_CONF1 \| PCI_PROBE_CONF2 \|
	22	PCI_PROBE_MMCONF;
	23
e3f2baeb	24	unsigned int pci_early_dump_regs;
2b290da0	25	static int pci_bf_sort;
6e8af08d	26	static int smbios_type_b1_flag;
1da177e4	27	int pci_routeirq;
a9322f64	28	int noioapicquirk;
41b9eb26 SA	29	#ifdef CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS
	30	int noioapicreroute = 0;
	31	#else
9197979b	32	int noioapicreroute = 1;
41b9eb26	33	#endif
1da177e4	34	int pcibios_last_bus = -1;
120bb424	35	unsigned long pirq_table_addr;
120bb424	36	struct pci_bus *pci_root_bus;
72da0b07 JB	37	const struct pci_raw_ops *__read_mostly raw_pci_ops;
72da0b07 JB	38	const struct pci_raw_ops *__read_mostly raw_pci_ext_ops;
b6ce068a MW	39
	40	int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
	41	int reg, int len, u32 *val)
	42	{
beef3129	43	if (domain == 0 && reg < 256 && raw_pci_ops)
b6ce068a MW	44	return raw_pci_ops->read(domain, bus, devfn, reg, len, val);
	45	if (raw_pci_ext_ops)
	46	return raw_pci_ext_ops->read(domain, bus, devfn, reg, len, val);
	47	return -EINVAL;
	48	}
	49
	50	int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
	51	int reg, int len, u32 val)
	52	{
beef3129	53	if (domain == 0 && reg < 256 && raw_pci_ops)
b6ce068a MW	54	return raw_pci_ops->write(domain, bus, devfn, reg, len, val);
	55	if (raw_pci_ext_ops)
	56	return raw_pci_ext_ops->write(domain, bus, devfn, reg, len, val);
	57	return -EINVAL;
	58	}
1da177e4 LT	59
	60	static int pci_read(struct pci_bus bus, unsigned int devfn, int where, int size, u32 value)
	61	{
b6ce068a	62	return raw_pci_read(pci_domain_nr(bus), bus->number,
a79e4198	63	devfn, where, size, value);
1da177e4 LT	64	}
	65
	66	static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
	67	{
b6ce068a	68	return raw_pci_write(pci_domain_nr(bus), bus->number,
a79e4198	69	devfn, where, size, value);
1da177e4 LT	70	}
	71
	72	struct pci_ops pci_root_ops = {
	73	.read = pci_read,
	74	.write = pci_write,
	75	};
	76
1da177e4 LT	77	/*
	78	* This interrupt-safe spinlock protects all accesses to PCI
	79	* configuration space.
	80	*/
d19f61f0	81	DEFINE_RAW_SPINLOCK(pci_config_lock);
1da177e4	82
13a6ddb0 YL	83	static int __devinit can_skip_ioresource_align(const struct dmi_system_id *d)
	84	{
	85	pci_probe \|= PCI_CAN_SKIP_ISA_ALIGN;
	86	printk(KERN_INFO "PCI: %s detected, can skip ISA alignment\n", d->ident);
	87	return 0;
	88	}
	89
821508d4	90	static const struct dmi_system_id can_skip_pciprobe_dmi_table[] __devinitconst = {
13a6ddb0 YL	91	/*
	92	* Systems where PCI IO resource ISA alignment can be skipped
	93	* when the ISA enable bit in the bridge control is not set
	94	*/
	95	{
	96	.callback = can_skip_ioresource_align,
	97	.ident = "IBM System x3800",
	98	.matches = {
	99	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
	100	DMI_MATCH(DMI_PRODUCT_NAME, "x3800"),
	101	},
	102	},
	103	{
	104	.callback = can_skip_ioresource_align,
	105	.ident = "IBM System x3850",
	106	.matches = {
	107	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
	108	DMI_MATCH(DMI_PRODUCT_NAME, "x3850"),
	109	},
	110	},
	111	{
	112	.callback = can_skip_ioresource_align,
	113	.ident = "IBM System x3950",
	114	.matches = {
	115	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
	116	DMI_MATCH(DMI_PRODUCT_NAME, "x3950"),
	117	},
	118	},
	119	{}
	120	};
	121
	122	void __init dmi_check_skip_isa_align(void)
	123	{
	124	dmi_check_system(can_skip_pciprobe_dmi_table);
	125	}
	126
bb71ad88 GH	127	static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
	128	{
	129	struct resource *rom_r = &dev->resource[PCI_ROM_RESOURCE];
7bd1c365 MH	130	struct resource *bar_r;
	131	int bar;
	132
	133	if (pci_probe & PCI_NOASSIGN_BARS) {
	134	/*
	135	* If the BIOS did not assign the BAR, zero out the
	136	* resource so the kernel doesn't attmept to assign
	137	* it later on in pci_assign_unassigned_resources
	138	*/
	139	for (bar = 0; bar <= PCI_STD_RESOURCE_END; bar++) {
	140	bar_r = &dev->resource[bar];
	141	if (bar_r->start == 0 && bar_r->end != 0) {
	142	bar_r->flags = 0;
	143	bar_r->end = 0;
	144	}
	145	}
	146	}
bb71ad88 GH	147
	148	if (pci_probe & PCI_NOASSIGN_ROMS) {
	149	if (rom_r->parent)
	150	return;
	151	if (rom_r->start) {
	152	/* we deal with BIOS assigned ROM later */
	153	return;
	154	}
	155	rom_r->start = rom_r->end = rom_r->flags = 0;
	156	}
	157	}
	158
1da177e4 LT	159	/*
	160	* Called after each bus is probed, but before its children
	161	* are examined.
	162	*/
	163
0bb1be3e	164	void __devinit pcibios_fixup_bus(struct pci_bus *b)
1da177e4	165	{
bb71ad88 GH	166	struct pci_dev *dev;
bb71ad88 GH	167
1da177e4	168	pci_read_bridge_bases(b);
bb71ad88 GH	169	list_for_each_entry(dev, &b->devices, bus_list)
bb71ad88 GH	170	pcibios_fixup_device_resources(dev);
1da177e4 LT	171	}
1da177e4 LT	172
6b4b78fe MD	173	/*
	174	* Only use DMI information to set this if nothing was passed
	175	* on the kernel command line (which was parsed earlier).
	176	*/
	177
1855256c	178	static int __devinit set_bf_sort(const struct dmi_system_id *d)
6b4b78fe MD	179	{
	180	if (pci_bf_sort == pci_bf_sort_default) {
	181	pci_bf_sort = pci_dmi_bf;
	182	printk(KERN_INFO "PCI: %s detected, enabling pci=bfsort.\n", d->ident);
	183	}
	184	return 0;
	185	}
	186
6e8af08d ND	187	static void __devinit read_dmi_type_b1(const struct dmi_header *dm,
	188	void *private_data)
	189	{
	190	u8 d = (u8 )dm + 4;
	191
	192	if (dm->type != 0xB1)
	193	return;
	194	switch ((((u32 )d) >> 9) & 0x03) {
	195	case 0x00:
	196	printk(KERN_INFO "dmi type 0xB1 record - unknown flag\n");
	197	break;
	198	case 0x01: /* set pci=bfsort */
	199	smbios_type_b1_flag = 1;
	200	break;
	201	case 0x02: /* do not set pci=bfsort */
	202	smbios_type_b1_flag = 2;
	203	break;
	204	default:
	205	break;
	206	}
	207	}
	208
	209	static int __devinit find_sort_method(const struct dmi_system_id *d)
	210	{
	211	dmi_walk(read_dmi_type_b1, NULL);
	212
	213	if (smbios_type_b1_flag == 1) {
	214	set_bf_sort(d);
	215	return 0;
	216	}
	217	return -1;
	218	}
	219
8c4b2cf9 BK	220	/*
	221	* Enable renumbering of PCI bus# ranges to reach all PCI busses (Cardbus)
	222	*/
	223	#ifdef __i386__
1855256c	224	static int __devinit assign_all_busses(const struct dmi_system_id *d)
8c4b2cf9 BK	225	{
	226	pci_probe \|= PCI_ASSIGN_ALL_BUSSES;
	227	printk(KERN_INFO "%s detected: enabling PCI bus# renumbering"
	228	" (pci=assign-busses)\n", d->ident);
	229	return 0;
	230	}
	231	#endif
	232
284f5f9d BH	233	static int __devinit set_scan_all(const struct dmi_system_id *d)
	234	{
	235	printk(KERN_INFO "PCI: %s detected, enabling pci=pcie_scan_all\n",
	236	d->ident);
	237	pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
	238	return 0;
	239	}
	240
821508d4	241	static const struct dmi_system_id __devinitconst pciprobe_dmi_table[] = {
6b4b78fe	242	#ifdef __i386__
8c4b2cf9 BK	243	/*
	244	* Laptops which need pci=assign-busses to see Cardbus cards
	245	*/
8c4b2cf9 BK	246	{
	247	.callback = assign_all_busses,
	248	.ident = "Samsung X20 Laptop",
	249	.matches = {
	250	DMI_MATCH(DMI_SYS_VENDOR, "Samsung Electronics"),
	251	DMI_MATCH(DMI_PRODUCT_NAME, "SX20S"),
	252	},
	253	},
	254	#endif /* __i386__ */
6b4b78fe MD	255	{
	256	.callback = set_bf_sort,
	257	.ident = "Dell PowerEdge 1950",
	258	.matches = {
	259	DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
	260	DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1950"),
	261	},
	262	},
	263	{
	264	.callback = set_bf_sort,
	265	.ident = "Dell PowerEdge 1955",
	266	.matches = {
	267	DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
	268	DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1955"),
	269	},
	270	},
	271	{
	272	.callback = set_bf_sort,
	273	.ident = "Dell PowerEdge 2900",
	274	.matches = {
	275	DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
	276	DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2900"),
	277	},
	278	},
	279	{
	280	.callback = set_bf_sort,
	281	.ident = "Dell PowerEdge 2950",
	282	.matches = {
	283	DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
	284	DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2950"),
	285	},
	286	},
f7a9dae7 MD	287	{
	288	.callback = set_bf_sort,
	289	.ident = "Dell PowerEdge R900",
	290	.matches = {
	291	DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
	292	DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge R900"),
	293	},
	294	},
9b373ed1 ND	295	{
	296	.callback = find_sort_method,
	297	.ident = "Dell System",
	298	.matches = {
	299	DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
	300	},
	301	},
f52383d3 AG	302	{
	303	.callback = set_bf_sort,
	304	.ident = "HP ProLiant BL20p G3",
	305	.matches = {
	306	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	307	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G3"),
	308	},
	309	},
	310	{
	311	.callback = set_bf_sort,
	312	.ident = "HP ProLiant BL20p G4",
	313	.matches = {
	314	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	315	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G4"),
	316	},
	317	},
	318	{
	319	.callback = set_bf_sort,
	320	.ident = "HP ProLiant BL30p G1",
	321	.matches = {
	322	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	323	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL30p G1"),
	324	},
	325	},
	326	{
	327	.callback = set_bf_sort,
	328	.ident = "HP ProLiant BL25p G1",
	329	.matches = {
	330	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	331	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL25p G1"),
	332	},
	333	},
	334	{
	335	.callback = set_bf_sort,
	336	.ident = "HP ProLiant BL35p G1",
	337	.matches = {
	338	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	339	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL35p G1"),
	340	},
	341	},
	342	{
	343	.callback = set_bf_sort,
	344	.ident = "HP ProLiant BL45p G1",
	345	.matches = {
	346	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	347	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G1"),
	348	},
	349	},
	350	{
	351	.callback = set_bf_sort,
	352	.ident = "HP ProLiant BL45p G2",
	353	.matches = {
	354	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	355	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G2"),
	356	},
	357	},
	358	{
	359	.callback = set_bf_sort,
	360	.ident = "HP ProLiant BL460c G1",
	361	.matches = {
	362	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	363	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL460c G1"),
	364	},
	365	},
366	{
367	.callback = set_bf_sort,
368	.ident = "HP ProLiant BL465c G1",
369	.matches = {
370	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
371	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL465c G1"),
372	},
373	},
374	{
375	.callback = set_bf_sort,
376	.ident = "HP ProLiant BL480c G1",
377	.matches = {
378	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
379	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL480c G1"),
380	},
381	},
382	{
383	.callback = set_bf_sort,
384	.ident = "HP ProLiant BL685c G1",
385	.matches = {
386	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
387	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL685c G1"),
388	},
389	},
8f8ae1a7 MS	390	{
8f8ae1a7 MS	391	.callback = set_bf_sort,
8d64c781	392	.ident = "HP ProLiant DL360",
8f8ae1a7 MS	393	.matches = {
8f8ae1a7 MS	394	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
8d64c781	395	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL360"),
8f8ae1a7 MS	396	},
	397	},
	398	{
	399	.callback = set_bf_sort,
8d64c781	400	.ident = "HP ProLiant DL380",
8f8ae1a7 MS	401	.matches = {
8f8ae1a7 MS	402	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
8d64c781	403	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL380"),
8f8ae1a7 MS	404	},
8f8ae1a7 MS	405	},
5b1ea82f JL	406	#ifdef __i386__
	407	{
	408	.callback = assign_all_busses,
	409	.ident = "Compaq EVO N800c",
	410	.matches = {
	411	DMI_MATCH(DMI_SYS_VENDOR, "Compaq"),
	412	DMI_MATCH(DMI_PRODUCT_NAME, "EVO N800c"),
	413	},
	414	},
	415	#endif
c82bc5ad MS	416	{
c82bc5ad MS	417	.callback = set_bf_sort,
739db07f	418	.ident = "HP ProLiant DL385 G2",
c82bc5ad MS	419	.matches = {
c82bc5ad MS	420	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
739db07f	421	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL385 G2"),
c82bc5ad MS	422	},
	423	},
	424	{
	425	.callback = set_bf_sort,
739db07f	426	.ident = "HP ProLiant DL585 G2",
c82bc5ad MS	427	.matches = {
c82bc5ad MS	428	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
739db07f	429	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL585 G2"),
c82bc5ad MS	430	},
c82bc5ad MS	431	},
284f5f9d BH	432	{
	433	.callback = set_scan_all,
	434	.ident = "Stratus/NEC ftServer",
	435	.matches = {
	436	DMI_MATCH(DMI_SYS_VENDOR, "ftServer"),
	437	},
	438	},
8c4b2cf9 BK	439	{}
8c4b2cf9 BK	440	};
1da177e4	441
0df18ff3 YL	442	void __init dmi_check_pciprobe(void)
	443	{
	444	dmi_check_system(pciprobe_dmi_table);
	445	}
	446
1da177e4 LT	447	struct pci_bus * __devinit pcibios_scan_root(int busnum)
	448	{
	449	struct pci_bus *bus = NULL;
	450
	451	while ((bus = pci_find_next_bus(bus)) != NULL) {
	452	if (bus->number == busnum) {
	453	/* Already scanned */
	454	return bus;
	455	}
	456	}
	457
c57ca65a YL	458	return pci_scan_bus_on_node(busnum, &pci_root_ops,
c57ca65a YL	459	get_mp_bus_to_node(busnum));
1da177e4	460	}
c57ca65a	461
44de3395	462	void __init pcibios_set_cache_line_size(void)
1da177e4 LT	463	{
	464	struct cpuinfo_x86 *c = &boot_cpu_data;
	465
1da177e4	466	/*
76b1a87b DJ	467	* Set PCI cacheline size to that of the CPU if the CPU has reported it.
	468	* (For older CPUs that don't support cpuid, we se it to 32 bytes
	469	* It's also good for 386/486s (which actually have 16)
1da177e4 LT	470	* as quite a few PCI devices do not support smaller values.
1da177e4 LT	471	*/
76b1a87b DJ	472	if (c->x86_clflush_size > 0) {
	473	pci_dfl_cache_line_size = c->x86_clflush_size >> 2;
	474	printk(KERN_DEBUG "PCI: pci_cache_line_size set to %d bytes\n",
	475	pci_dfl_cache_line_size << 2);
	476	} else {
	477	pci_dfl_cache_line_size = 32 >> 2;
	478	printk(KERN_DEBUG "PCI: Unknown cacheline size. Setting to 32 bytes\n");
	479	}
44de3395 AN	480	}
	481
	482	int __init pcibios_init(void)
	483	{
	484	if (!raw_pci_ops) {
	485	printk(KERN_WARNING "PCI: System does not support PCI\n");
	486	return 0;
	487	}
1da177e4	488
44de3395	489	pcibios_set_cache_line_size();
1da177e4 LT	490	pcibios_resource_survey();
1da177e4 LT	491
6b4b78fe MD	492	if (pci_bf_sort >= pci_force_bf)
6b4b78fe MD	493	pci_sort_breadthfirst();
1da177e4 LT	494	return 0;
	495	}
	496
15fa325b	497	char * __init pcibios_setup(char *str)
1da177e4 LT	498	{
	499	if (!strcmp(str, "off")) {
	500	pci_probe = 0;
	501	return NULL;
6b4b78fe MD	502	} else if (!strcmp(str, "bfsort")) {
	503	pci_bf_sort = pci_force_bf;
	504	return NULL;
	505	} else if (!strcmp(str, "nobfsort")) {
	506	pci_bf_sort = pci_force_nobf;
	507	return NULL;
1da177e4 LT	508	}
	509	#ifdef CONFIG_PCI_BIOS
	510	else if (!strcmp(str, "bios")) {
	511	pci_probe = PCI_PROBE_BIOS;
	512	return NULL;
	513	} else if (!strcmp(str, "nobios")) {
	514	pci_probe &= ~PCI_PROBE_BIOS;
	515	return NULL;
1da177e4 LT	516	} else if (!strcmp(str, "biosirq")) {
	517	pci_probe \|= PCI_BIOS_IRQ_SCAN;
	518	return NULL;
120bb424	519	} else if (!strncmp(str, "pirqaddr=", 9)) {
	520	pirq_table_addr = simple_strtoul(str+9, NULL, 0);
	521	return NULL;
1da177e4 LT	522	}
	523	#endif
	524	#ifdef CONFIG_PCI_DIRECT
	525	else if (!strcmp(str, "conf1")) {
	526	pci_probe = PCI_PROBE_CONF1 \| PCI_NO_CHECKS;
	527	return NULL;
	528	}
	529	else if (!strcmp(str, "conf2")) {
	530	pci_probe = PCI_PROBE_CONF2 \| PCI_NO_CHECKS;
	531	return NULL;
	532	}
	533	#endif
	534	#ifdef CONFIG_PCI_MMCONFIG
	535	else if (!strcmp(str, "nommconf")) {
	536	pci_probe &= ~PCI_PROBE_MMCONF;
	537	return NULL;
	538	}
5f0b2976 YL	539	else if (!strcmp(str, "check_enable_amd_mmconf")) {
	540	pci_probe \|= PCI_CHECK_ENABLE_AMD_MMCONF;
	541	return NULL;
	542	}
1da177e4 LT	543	#endif
	544	else if (!strcmp(str, "noacpi")) {
	545	acpi_noirq_set();
	546	return NULL;
	547	}
0637a70a AK	548	else if (!strcmp(str, "noearly")) {
	549	pci_probe \|= PCI_PROBE_NOEARLY;
	550	return NULL;
	551	}
1da177e4 LT	552	#ifndef CONFIG_X86_VISWS
	553	else if (!strcmp(str, "usepirqmask")) {
	554	pci_probe \|= PCI_USE_PIRQ_MASK;
	555	return NULL;
	556	} else if (!strncmp(str, "irqmask=", 8)) {
	557	pcibios_irq_mask = simple_strtol(str+8, NULL, 0);
	558	return NULL;
	559	} else if (!strncmp(str, "lastbus=", 8)) {
	560	pcibios_last_bus = simple_strtol(str+8, NULL, 0);
	561	return NULL;
	562	}
	563	#endif
	564	else if (!strcmp(str, "rom")) {
	565	pci_probe \|= PCI_ASSIGN_ROMS;
	566	return NULL;
bb71ad88 GH	567	} else if (!strcmp(str, "norom")) {
	568	pci_probe \|= PCI_NOASSIGN_ROMS;
	569	return NULL;
7bd1c365 MH	570	} else if (!strcmp(str, "nobar")) {
	571	pci_probe \|= PCI_NOASSIGN_BARS;
	572	return NULL;
1da177e4 LT	573	} else if (!strcmp(str, "assign-busses")) {
	574	pci_probe \|= PCI_ASSIGN_ALL_BUSSES;
	575	return NULL;
236e946b LT	576	} else if (!strcmp(str, "use_crs")) {
236e946b LT	577	pci_probe \|= PCI_USE__CRS;
62f420f8	578	return NULL;
7bc5e3f2 BH	579	} else if (!strcmp(str, "nocrs")) {
	580	pci_probe \|= PCI_ROOT_NO_CRS;
	581	return NULL;
e3f2baeb YL	582	} else if (!strcmp(str, "earlydump")) {
	583	pci_early_dump_regs = 1;
	584	return NULL;
1da177e4 LT	585	} else if (!strcmp(str, "routeirq")) {
	586	pci_routeirq = 1;
	587	return NULL;
13a6ddb0 YL	588	} else if (!strcmp(str, "skip_isa_align")) {
	589	pci_probe \|= PCI_CAN_SKIP_ISA_ALIGN;
	590	return NULL;
a9322f64 SA	591	} else if (!strcmp(str, "noioapicquirk")) {
	592	noioapicquirk = 1;
	593	return NULL;
9197979b SA	594	} else if (!strcmp(str, "ioapicreroute")) {
	595	if (noioapicreroute != -1)
	596	noioapicreroute = 0;
	597	return NULL;
41b9eb26 SA	598	} else if (!strcmp(str, "noioapicreroute")) {
	599	if (noioapicreroute != -1)
	600	noioapicreroute = 1;
	601	return NULL;
1da177e4 LT	602	}
	603	return str;
	604	}
	605
	606	unsigned int pcibios_assign_all_busses(void)
	607	{
	608	return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
	609	}
	610
	611	int pcibios_enable_device(struct pci_dev *dev, int mask)
	612	{
	613	int err;
	614
b81d988c	615	if ((err = pci_enable_resources(dev, mask)) < 0)
1da177e4 LT	616	return err;
1da177e4 LT	617
16cf0ebc	618	if (!pci_dev_msi_enabled(dev))
bba6f6fc EB	619	return pcibios_enable_irq(dev);
bba6f6fc EB	620	return 0;
1da177e4	621	}
87bec66b DSL	622
	623	void pcibios_disable_device (struct pci_dev *dev)
	624	{
16cf0ebc	625	if (!pci_dev_msi_enabled(dev) && pcibios_disable_irq)
87bec66b DSL	626	pcibios_disable_irq(dev);
87bec66b DSL	627	}
73c59afc	628
0ef5f8f6 AP	629	int pci_ext_cfg_avail(struct pci_dev *dev)
	630	{
	631	if (raw_pci_ext_ops)
	632	return 1;
	633	else
	634	return 0;
	635	}
	636
98db6f19	637	struct pci_bus * __devinit pci_scan_bus_on_node(int busno, struct pci_ops *ops, int node)
73c59afc	638	{
2cd6975a	639	LIST_HEAD(resources);
73c59afc MBY	640	struct pci_bus *bus = NULL;
	641	struct pci_sysdata *sd;
	642
	643	/*
	644	* Allocate per-root-bus (not per bus) arch-specific data.
	645	* TODO: leak; this memory is never freed.
	646	* It's arguable whether it's worth the trouble to care.
	647	*/
	648	sd = kzalloc(sizeof(*sd), GFP_KERNEL);
	649	if (!sd) {
	650	printk(KERN_ERR "PCI: OOM, skipping PCI bus %02x\n", busno);
	651	return NULL;
	652	}
871d5f8d	653	sd->node = node;
2cd6975a	654	x86_pci_root_bus_resources(busno, &resources);
c57ca65a	655	printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busno);
2cd6975a BH	656	bus = pci_scan_root_bus(NULL, busno, ops, sd, &resources);
	657	if (!bus) {
	658	pci_free_resource_list(&resources);
73c59afc	659	kfree(sd);
2cd6975a	660	}
73c59afc MBY	661
	662	return bus;
	663	}
871d5f8d	664
98db6f19	665	struct pci_bus * __devinit pci_scan_bus_with_sysdata(int busno)
871d5f8d YL	666	{
	667	return pci_scan_bus_on_node(busno, &pci_root_ops, -1);
	668	}
2547089c JB	669
	670	/*
	671	* NUMA info for PCI busses
	672	*
	673	* Early arch code is responsible for filling in reasonable values here.
	674	* A node id of "-1" means "use current node". In other words, if a bus
	675	* has a -1 node id, it's not tightly coupled to any particular chunk
	676	* of memory (as is the case on some Nehalem systems).
	677	*/
	678	#ifdef CONFIG_NUMA
	679
	680	#define BUS_NR 256
	681
	682	#ifdef CONFIG_X86_64
	683
	684	static int mp_bus_to_node[BUS_NR] = {
	685	[0 ... BUS_NR - 1] = -1
	686	};
	687
	688	void set_mp_bus_to_node(int busnum, int node)
	689	{
	690	if (busnum >= 0 && busnum < BUS_NR)
	691	mp_bus_to_node[busnum] = node;
	692	}
	693
	694	int get_mp_bus_to_node(int busnum)
	695	{
	696	int node = -1;
	697
	698	if (busnum < 0 \|\| busnum > (BUS_NR - 1))
	699	return node;
	700
	701	node = mp_bus_to_node[busnum];
	702
	703	/*
	704	* let numa_node_id to decide it later in dma_alloc_pages
	705	* if there is no ram on that node
	706	*/
	707	if (node != -1 && !node_online(node))
	708	node = -1;
	709
	710	return node;
	711	}
	712
	713	#else /* CONFIG_X86_32 */
	714
76baeebf	715	static int mp_bus_to_node[BUS_NR] = {
2547089c JB	716	[0 ... BUS_NR - 1] = -1
	717	};
	718
	719	void set_mp_bus_to_node(int busnum, int node)
	720	{
	721	if (busnum >= 0 && busnum < BUS_NR)
	722	mp_bus_to_node[busnum] = (unsigned char) node;
	723	}
	724
	725	int get_mp_bus_to_node(int busnum)
	726	{
	727	int node;
	728
	729	if (busnum < 0 \|\| busnum > (BUS_NR - 1))
	730	return 0;
	731	node = mp_bus_to_node[busnum];
	732	return node;
	733	}
	734
	735	#endif /* CONFIG_X86_32 */
	736
	737	#endif /* CONFIG_NUMA */