[deliverable/linux.git] / arch / x86 / pci / common.c

/*
 *	Low-Level PCI Support for PC
 *
 *	(c) 1999--2000 Martin Mares <mj@ucw.cz>
 */

#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/dmi.h>
#include <linux/slab.h>

#include <asm-generic/pci-bridge.h>
#include <asm/acpi.h>
#include <asm/segment.h>
#include <asm/io.h>
#include <asm/smp.h>
#include <asm/pci_x86.h>
#include <asm/setup.h>

unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2 |
				PCI_PROBE_MMCONF;

unsigned int pci_early_dump_regs;
static int pci_bf_sort;
static int smbios_type_b1_flag;
int pci_routeirq;
int noioapicquirk;
#ifdef CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS
int noioapicreroute = 0;
#else
int noioapicreroute = 1;
#endif
int pcibios_last_bus = -1;
unsigned long pirq_table_addr;
const struct pci_raw_ops *__read_mostly raw_pci_ops;
const struct pci_raw_ops *__read_mostly raw_pci_ext_ops;

int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
						int reg, int len, u32 *val)
{
	if (domain == 0 && reg < 256 && raw_pci_ops)
		return raw_pci_ops->read(domain, bus, devfn, reg, len, val);
	if (raw_pci_ext_ops)
		return raw_pci_ext_ops->read(domain, bus, devfn, reg, len, val);
	return -EINVAL;
}

int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
						int reg, int len, u32 val)
{
	if (domain == 0 && reg < 256 && raw_pci_ops)
		return raw_pci_ops->write(domain, bus, devfn, reg, len, val);
	if (raw_pci_ext_ops)
		return raw_pci_ext_ops->write(domain, bus, devfn, reg, len, val);
	return -EINVAL;
}

static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
{
	return raw_pci_read(pci_domain_nr(bus), bus->number,
				 devfn, where, size, value);
}

static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
{
	return raw_pci_write(pci_domain_nr(bus), bus->number,
				  devfn, where, size, value);
}

struct pci_ops pci_root_ops = {
	.read = pci_read,
	.write = pci_write,
};

/*
 * This interrupt-safe spinlock protects all accesses to PCI
 * configuration space.
 */
DEFINE_RAW_SPINLOCK(pci_config_lock);

static int can_skip_ioresource_align(const struct dmi_system_id *d)
{
	pci_probe |= PCI_CAN_SKIP_ISA_ALIGN;
	printk(KERN_INFO "PCI: %s detected, can skip ISA alignment\n", d->ident);
	return 0;
}

static const struct dmi_system_id can_skip_pciprobe_dmi_table[] = {
/*
 * Systems where PCI IO resource ISA alignment can be skipped
 * when the ISA enable bit in the bridge control is not set
 */
	{
		.callback = can_skip_ioresource_align,
		.ident = "IBM System x3800",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "x3800"),
		},
	},
	{
		.callback = can_skip_ioresource_align,
		.ident = "IBM System x3850",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "x3850"),
		},
	},
	{
		.callback = can_skip_ioresource_align,
		.ident = "IBM System x3950",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "x3950"),
		},
	},
	{}
};

void __init dmi_check_skip_isa_align(void)
{
	dmi_check_system(can_skip_pciprobe_dmi_table);
}

static void pcibios_fixup_device_resources(struct pci_dev *dev)
{
	struct resource *rom_r = &dev->resource[PCI_ROM_RESOURCE];
	struct resource *bar_r;
	int bar;

	if (pci_probe & PCI_NOASSIGN_BARS) {
		/*
		* If the BIOS did not assign the BAR, zero out the
		* resource so the kernel doesn't attmept to assign
		* it later on in pci_assign_unassigned_resources
		*/
		for (bar = 0; bar <= PCI_STD_RESOURCE_END; bar++) {
			bar_r = &dev->resource[bar];
			if (bar_r->start == 0 && bar_r->end != 0) {
				bar_r->flags = 0;
				bar_r->end = 0;
			}
		}
	}

	if (pci_probe & PCI_NOASSIGN_ROMS) {
		if (rom_r->parent)
			return;
		if (rom_r->start) {
			/* we deal with BIOS assigned ROM later */
			return;
		}
		rom_r->start = rom_r->end = rom_r->flags = 0;
	}
}

/*
 *  Called after each bus is probed, but before its children
 *  are examined.
 */

void pcibios_fixup_bus(struct pci_bus *b)
{
	struct pci_dev *dev;

	pci_read_bridge_bases(b);
	list_for_each_entry(dev, &b->devices, bus_list)
		pcibios_fixup_device_resources(dev);
}

/*
 * Only use DMI information to set this if nothing was passed
 * on the kernel command line (which was parsed earlier).
 */

static int set_bf_sort(const struct dmi_system_id *d)
{
	if (pci_bf_sort == pci_bf_sort_default) {
		pci_bf_sort = pci_dmi_bf;
		printk(KERN_INFO "PCI: %s detected, enabling pci=bfsort.\n", d->ident);
	}
	return 0;
}

static void read_dmi_type_b1(const struct dmi_header *dm,
				       void *private_data)
{
	u8 *d = (u8 *)dm + 4;

	if (dm->type != 0xB1)
		return;
	switch (((*(u32 *)d) >> 9) & 0x03) {
	case 0x00:
		printk(KERN_INFO "dmi type 0xB1 record - unknown flag\n");
		break;
	case 0x01: /* set pci=bfsort */
		smbios_type_b1_flag = 1;
		break;
	case 0x02: /* do not set pci=bfsort */
		smbios_type_b1_flag = 2;
		break;
	default:
		break;
	}
}

static int find_sort_method(const struct dmi_system_id *d)
{
	dmi_walk(read_dmi_type_b1, NULL);

	if (smbios_type_b1_flag == 1) {
		set_bf_sort(d);
		return 0;
	}
	return -1;
}

/*
 * Enable renumbering of PCI bus# ranges to reach all PCI busses (Cardbus)
 */
#ifdef __i386__
static int assign_all_busses(const struct dmi_system_id *d)
{
	pci_probe |= PCI_ASSIGN_ALL_BUSSES;
	printk(KERN_INFO "%s detected: enabling PCI bus# renumbering"
			" (pci=assign-busses)\n", d->ident);
	return 0;
}
#endif

static int set_scan_all(const struct dmi_system_id *d)
{
	printk(KERN_INFO "PCI: %s detected, enabling pci=pcie_scan_all\n",
	       d->ident);
	pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
	return 0;
}

static const struct dmi_system_id pciprobe_dmi_table[] = {
#ifdef __i386__
/*
 * Laptops which need pci=assign-busses to see Cardbus cards
 */
	{
		.callback = assign_all_busses,
		.ident = "Samsung X20 Laptop",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Samsung Electronics"),
			DMI_MATCH(DMI_PRODUCT_NAME, "SX20S"),
		},
	},
#endif		/* __i386__ */
	{
		.callback = set_bf_sort,
		.ident = "Dell PowerEdge 1950",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1950"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "Dell PowerEdge 1955",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1955"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "Dell PowerEdge 2900",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2900"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "Dell PowerEdge 2950",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2950"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "Dell PowerEdge R900",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
			DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge R900"),
		},
	},
	{
		.callback = find_sort_method,
		.ident = "Dell System",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL20p G3",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G3"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL20p G4",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G4"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL30p G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL30p G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL25p G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL25p G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL35p G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL35p G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL45p G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL45p G2",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G2"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL460c G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL460c G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL465c G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL465c G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL480c G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL480c G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant BL685c G1",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL685c G1"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant DL360",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL360"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant DL380",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL380"),
		},
	},
#ifdef __i386__
	{
		.callback = assign_all_busses,
		.ident = "Compaq EVO N800c",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Compaq"),
			DMI_MATCH(DMI_PRODUCT_NAME, "EVO N800c"),
		},
	},
#endif
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant DL385 G2",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL385 G2"),
		},
	},
	{
		.callback = set_bf_sort,
		.ident = "HP ProLiant DL585 G2",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "HP"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL585 G2"),
		},
	},
	{
		.callback = set_scan_all,
		.ident = "Stratus/NEC ftServer",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "Stratus"),
			DMI_MATCH(DMI_PRODUCT_NAME, "ftServer"),
		},
	},
	{}
};

void __init dmi_check_pciprobe(void)
{
	dmi_check_system(pciprobe_dmi_table);
}

struct pci_bus *pcibios_scan_root(int busnum)
{
	struct pci_bus *bus = NULL;

	while ((bus = pci_find_next_bus(bus)) != NULL) {
		if (bus->number == busnum) {
			/* Already scanned */
			return bus;
		}
	}

	return pci_scan_bus_on_node(busnum, &pci_root_ops,
					get_mp_bus_to_node(busnum));
}

void __init pcibios_set_cache_line_size(void)
{
	struct cpuinfo_x86 *c = &boot_cpu_data;

	/*
	 * Set PCI cacheline size to that of the CPU if the CPU has reported it.
	 * (For older CPUs that don't support cpuid, we se it to 32 bytes
	 * It's also good for 386/486s (which actually have 16)
	 * as quite a few PCI devices do not support smaller values.
	 */
	if (c->x86_clflush_size > 0) {
		pci_dfl_cache_line_size = c->x86_clflush_size >> 2;
		printk(KERN_DEBUG "PCI: pci_cache_line_size set to %d bytes\n",
			pci_dfl_cache_line_size << 2);
	} else {
 		pci_dfl_cache_line_size = 32 >> 2;
		printk(KERN_DEBUG "PCI: Unknown cacheline size. Setting to 32 bytes\n");
	}
}

int __init pcibios_init(void)
{
	if (!raw_pci_ops) {
		printk(KERN_WARNING "PCI: System does not support PCI\n");
		return 0;
	}

	pcibios_set_cache_line_size();
	pcibios_resource_survey();

	if (pci_bf_sort >= pci_force_bf)
		pci_sort_breadthfirst();
	return 0;
}

char * __init pcibios_setup(char *str)
{
	if (!strcmp(str, "off")) {
		pci_probe = 0;
		return NULL;
	} else if (!strcmp(str, "bfsort")) {
		pci_bf_sort = pci_force_bf;
		return NULL;
	} else if (!strcmp(str, "nobfsort")) {
		pci_bf_sort = pci_force_nobf;
		return NULL;
	}
#ifdef CONFIG_PCI_BIOS
	else if (!strcmp(str, "bios")) {
		pci_probe = PCI_PROBE_BIOS;
		return NULL;
	} else if (!strcmp(str, "nobios")) {
		pci_probe &= ~PCI_PROBE_BIOS;
		return NULL;
	} else if (!strcmp(str, "biosirq")) {
		pci_probe |= PCI_BIOS_IRQ_SCAN;
		return NULL;
	} else if (!strncmp(str, "pirqaddr=", 9)) {
		pirq_table_addr = simple_strtoul(str+9, NULL, 0);
		return NULL;
	}
#endif
#ifdef CONFIG_PCI_DIRECT
	else if (!strcmp(str, "conf1")) {
		pci_probe = PCI_PROBE_CONF1 | PCI_NO_CHECKS;
		return NULL;
	}
	else if (!strcmp(str, "conf2")) {
		pci_probe = PCI_PROBE_CONF2 | PCI_NO_CHECKS;
		return NULL;
	}
#endif
#ifdef CONFIG_PCI_MMCONFIG
	else if (!strcmp(str, "nommconf")) {
		pci_probe &= ~PCI_PROBE_MMCONF;
		return NULL;
	}
	else if (!strcmp(str, "check_enable_amd_mmconf")) {
		pci_probe |= PCI_CHECK_ENABLE_AMD_MMCONF;
		return NULL;
	}
#endif
	else if (!strcmp(str, "noacpi")) {
		acpi_noirq_set();
		return NULL;
	}
	else if (!strcmp(str, "noearly")) {
		pci_probe |= PCI_PROBE_NOEARLY;
		return NULL;
	}
#ifndef CONFIG_X86_VISWS
	else if (!strcmp(str, "usepirqmask")) {
		pci_probe |= PCI_USE_PIRQ_MASK;
		return NULL;
	} else if (!strncmp(str, "irqmask=", 8)) {
		pcibios_irq_mask = simple_strtol(str+8, NULL, 0);
		return NULL;
	} else if (!strncmp(str, "lastbus=", 8)) {
		pcibios_last_bus = simple_strtol(str+8, NULL, 0);
		return NULL;
	}
#endif
	else if (!strcmp(str, "rom")) {
		pci_probe |= PCI_ASSIGN_ROMS;
		return NULL;
	} else if (!strcmp(str, "norom")) {
		pci_probe |= PCI_NOASSIGN_ROMS;
		return NULL;
	} else if (!strcmp(str, "nobar")) {
		pci_probe |= PCI_NOASSIGN_BARS;
		return NULL;
	} else if (!strcmp(str, "assign-busses")) {
		pci_probe |= PCI_ASSIGN_ALL_BUSSES;
		return NULL;
	} else if (!strcmp(str, "use_crs")) {
		pci_probe |= PCI_USE__CRS;
		return NULL;
	} else if (!strcmp(str, "nocrs")) {
		pci_probe |= PCI_ROOT_NO_CRS;
		return NULL;
	} else if (!strcmp(str, "earlydump")) {
		pci_early_dump_regs = 1;
		return NULL;
	} else if (!strcmp(str, "routeirq")) {
		pci_routeirq = 1;
		return NULL;
	} else if (!strcmp(str, "skip_isa_align")) {
		pci_probe |= PCI_CAN_SKIP_ISA_ALIGN;
		return NULL;
	} else if (!strcmp(str, "noioapicquirk")) {
		noioapicquirk = 1;
		return NULL;
	} else if (!strcmp(str, "ioapicreroute")) {
		if (noioapicreroute != -1)
			noioapicreroute = 0;
		return NULL;
	} else if (!strcmp(str, "noioapicreroute")) {
		if (noioapicreroute != -1)
			noioapicreroute = 1;
		return NULL;
	}
	return str;
}

unsigned int pcibios_assign_all_busses(void)
{
	return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
}

int pcibios_add_device(struct pci_dev *dev)
{
	struct setup_data *data;
	struct pci_setup_rom *rom;
	u64 pa_data;

	pa_data = boot_params.hdr.setup_data;
	while (pa_data) {
		data = phys_to_virt(pa_data);

		if (data->type == SETUP_PCI) {
			rom = (struct pci_setup_rom *)data;

			if ((pci_domain_nr(dev->bus) == rom->segment) &&
			    (dev->bus->number == rom->bus) &&
			    (PCI_SLOT(dev->devfn) == rom->device) &&
			    (PCI_FUNC(dev->devfn) == rom->function) &&
			    (dev->vendor == rom->vendor) &&
			    (dev->device == rom->devid)) {
				dev->rom = pa_data +
				      offsetof(struct pci_setup_rom, romdata);
				dev->romlen = rom->pcilen;
			}
		}
		pa_data = data->next;
	}
	return 0;
}

int pcibios_enable_device(struct pci_dev *dev, int mask)
{
	int err;

	if ((err = pci_enable_resources(dev, mask)) < 0)
		return err;

	if (!pci_dev_msi_enabled(dev))
		return pcibios_enable_irq(dev);
	return 0;
}

void pcibios_disable_device (struct pci_dev *dev)
{
	if (!pci_dev_msi_enabled(dev) && pcibios_disable_irq)
		pcibios_disable_irq(dev);
}

int pci_ext_cfg_avail(void)
{
	if (raw_pci_ext_ops)
		return 1;
	else
		return 0;
}

struct pci_bus *pci_scan_bus_on_node(int busno, struct pci_ops *ops, int node)
{
	LIST_HEAD(resources);
	struct pci_bus *bus = NULL;
	struct pci_sysdata *sd;

	/*
	 * Allocate per-root-bus (not per bus) arch-specific data.
	 * TODO: leak; this memory is never freed.
	 * It's arguable whether it's worth the trouble to care.
	 */
	sd = kzalloc(sizeof(*sd), GFP_KERNEL);
	if (!sd) {
		printk(KERN_ERR "PCI: OOM, skipping PCI bus %02x\n", busno);
		return NULL;
	}
	sd->node = node;
	x86_pci_root_bus_resources(busno, &resources);
	printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busno);
	bus = pci_scan_root_bus(NULL, busno, ops, sd, &resources);
	if (!bus) {
		pci_free_resource_list(&resources);
		kfree(sd);
	}

	return bus;
}

struct pci_bus *pci_scan_bus_with_sysdata(int busno)
{
	return pci_scan_bus_on_node(busno, &pci_root_ops, -1);
}

/*
 * NUMA info for PCI busses
 *
 * Early arch code is responsible for filling in reasonable values here.
 * A node id of "-1" means "use current node".  In other words, if a bus
 * has a -1 node id, it's not tightly coupled to any particular chunk
 * of memory (as is the case on some Nehalem systems).
 */
#ifdef CONFIG_NUMA

#define BUS_NR 256

#ifdef CONFIG_X86_64

static int mp_bus_to_node[BUS_NR] = {
	[0 ... BUS_NR - 1] = -1
};

void set_mp_bus_to_node(int busnum, int node)
{
	if (busnum >= 0 &&  busnum < BUS_NR)
		mp_bus_to_node[busnum] = node;
}

int get_mp_bus_to_node(int busnum)
{
	int node = -1;

	if (busnum < 0 || busnum > (BUS_NR - 1))
		return node;

	node = mp_bus_to_node[busnum];

	/*
	 * let numa_node_id to decide it later in dma_alloc_pages
	 * if there is no ram on that node
	 */
	if (node != -1 && !node_online(node))
		node = -1;

	return node;
}

#else /* CONFIG_X86_32 */

static int mp_bus_to_node[BUS_NR] = {
	[0 ... BUS_NR - 1] = -1
};

void set_mp_bus_to_node(int busnum, int node)
{
	if (busnum >= 0 &&  busnum < BUS_NR)
	mp_bus_to_node[busnum] = (unsigned char) node;
}

int get_mp_bus_to_node(int busnum)
{
	int node;

	if (busnum < 0 || busnum > (BUS_NR - 1))
		return 0;
	node = mp_bus_to_node[busnum];
	return node;
}

#endif /* CONFIG_X86_32 */

#endif /* CONFIG_NUMA */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Low-Level PCI Support for PC
	3	*
	4	* (c) 1999--2000 Martin Mares <mj@ucw.cz>
	5	*/
	6
	7	#include <linux/sched.h>
	8	#include <linux/pci.h>
	9	#include <linux/ioport.h>
	10	#include <linux/init.h>
8c4b2cf9	11	#include <linux/dmi.h>
5a0e3ad6	12	#include <linux/slab.h>
1da177e4	13
284f5f9d	14	#include <asm-generic/pci-bridge.h>
1da177e4 LT	15	#include <asm/acpi.h>
	16	#include <asm/segment.h>
	17	#include <asm/io.h>
	18	#include <asm/smp.h>
82487711	19	#include <asm/pci_x86.h>
f9a37be0	20	#include <asm/setup.h>
1da177e4	21
1da177e4 LT	22	unsigned int pci_probe = PCI_PROBE_BIOS \| PCI_PROBE_CONF1 \| PCI_PROBE_CONF2 \|
	23	PCI_PROBE_MMCONF;
	24
e3f2baeb	25	unsigned int pci_early_dump_regs;
2b290da0	26	static int pci_bf_sort;
6e8af08d	27	static int smbios_type_b1_flag;
1da177e4	28	int pci_routeirq;
a9322f64	29	int noioapicquirk;
41b9eb26 SA	30	#ifdef CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS
	31	int noioapicreroute = 0;
	32	#else
9197979b	33	int noioapicreroute = 1;
41b9eb26	34	#endif
1da177e4	35	int pcibios_last_bus = -1;
120bb424	36	unsigned long pirq_table_addr;
72da0b07 JB	37	const struct pci_raw_ops *__read_mostly raw_pci_ops;
72da0b07 JB	38	const struct pci_raw_ops *__read_mostly raw_pci_ext_ops;
b6ce068a MW	39
	40	int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
	41	int reg, int len, u32 *val)
	42	{
beef3129	43	if (domain == 0 && reg < 256 && raw_pci_ops)
b6ce068a MW	44	return raw_pci_ops->read(domain, bus, devfn, reg, len, val);
	45	if (raw_pci_ext_ops)
	46	return raw_pci_ext_ops->read(domain, bus, devfn, reg, len, val);
	47	return -EINVAL;
	48	}
	49
	50	int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
	51	int reg, int len, u32 val)
	52	{
beef3129	53	if (domain == 0 && reg < 256 && raw_pci_ops)
b6ce068a MW	54	return raw_pci_ops->write(domain, bus, devfn, reg, len, val);
	55	if (raw_pci_ext_ops)
	56	return raw_pci_ext_ops->write(domain, bus, devfn, reg, len, val);
	57	return -EINVAL;
	58	}
1da177e4 LT	59
	60	static int pci_read(struct pci_bus bus, unsigned int devfn, int where, int size, u32 value)
	61	{
b6ce068a	62	return raw_pci_read(pci_domain_nr(bus), bus->number,
a79e4198	63	devfn, where, size, value);
1da177e4 LT	64	}
	65
	66	static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
	67	{
b6ce068a	68	return raw_pci_write(pci_domain_nr(bus), bus->number,
a79e4198	69	devfn, where, size, value);
1da177e4 LT	70	}
	71
	72	struct pci_ops pci_root_ops = {
	73	.read = pci_read,
	74	.write = pci_write,
	75	};
	76
1da177e4 LT	77	/*
	78	* This interrupt-safe spinlock protects all accesses to PCI
	79	* configuration space.
	80	*/
d19f61f0	81	DEFINE_RAW_SPINLOCK(pci_config_lock);
1da177e4	82
a18e3690	83	static int can_skip_ioresource_align(const struct dmi_system_id *d)
13a6ddb0 YL	84	{
	85	pci_probe \|= PCI_CAN_SKIP_ISA_ALIGN;
	86	printk(KERN_INFO "PCI: %s detected, can skip ISA alignment\n", d->ident);
	87	return 0;
	88	}
	89
a18e3690	90	static const struct dmi_system_id can_skip_pciprobe_dmi_table[] = {
13a6ddb0 YL	91	/*
	92	* Systems where PCI IO resource ISA alignment can be skipped
	93	* when the ISA enable bit in the bridge control is not set
	94	*/
	95	{
	96	.callback = can_skip_ioresource_align,
	97	.ident = "IBM System x3800",
	98	.matches = {
	99	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
	100	DMI_MATCH(DMI_PRODUCT_NAME, "x3800"),
	101	},
	102	},
	103	{
	104	.callback = can_skip_ioresource_align,
	105	.ident = "IBM System x3850",
	106	.matches = {
	107	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
	108	DMI_MATCH(DMI_PRODUCT_NAME, "x3850"),
	109	},
	110	},
	111	{
	112	.callback = can_skip_ioresource_align,
	113	.ident = "IBM System x3950",
	114	.matches = {
	115	DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
	116	DMI_MATCH(DMI_PRODUCT_NAME, "x3950"),
	117	},
	118	},
	119	{}
	120	};
	121
	122	void __init dmi_check_skip_isa_align(void)
	123	{
	124	dmi_check_system(can_skip_pciprobe_dmi_table);
	125	}
	126
a18e3690	127	static void pcibios_fixup_device_resources(struct pci_dev *dev)
bb71ad88 GH	128	{
bb71ad88 GH	129	struct resource *rom_r = &dev->resource[PCI_ROM_RESOURCE];
7bd1c365 MH	130	struct resource *bar_r;
	131	int bar;
	132
	133	if (pci_probe & PCI_NOASSIGN_BARS) {
	134	/*
	135	* If the BIOS did not assign the BAR, zero out the
	136	* resource so the kernel doesn't attmept to assign
	137	* it later on in pci_assign_unassigned_resources
	138	*/
	139	for (bar = 0; bar <= PCI_STD_RESOURCE_END; bar++) {
	140	bar_r = &dev->resource[bar];
	141	if (bar_r->start == 0 && bar_r->end != 0) {
	142	bar_r->flags = 0;
	143	bar_r->end = 0;
	144	}
	145	}
	146	}
bb71ad88 GH	147
	148	if (pci_probe & PCI_NOASSIGN_ROMS) {
	149	if (rom_r->parent)
	150	return;
	151	if (rom_r->start) {
	152	/* we deal with BIOS assigned ROM later */
	153	return;
	154	}
	155	rom_r->start = rom_r->end = rom_r->flags = 0;
	156	}
	157	}
	158
1da177e4 LT	159	/*
	160	* Called after each bus is probed, but before its children
	161	* are examined.
	162	*/
	163
a18e3690	164	void pcibios_fixup_bus(struct pci_bus *b)
1da177e4	165	{
bb71ad88 GH	166	struct pci_dev *dev;
bb71ad88 GH	167
1da177e4	168	pci_read_bridge_bases(b);
bb71ad88 GH	169	list_for_each_entry(dev, &b->devices, bus_list)
bb71ad88 GH	170	pcibios_fixup_device_resources(dev);
1da177e4 LT	171	}
1da177e4 LT	172
6b4b78fe MD	173	/*
	174	* Only use DMI information to set this if nothing was passed
	175	* on the kernel command line (which was parsed earlier).
	176	*/
	177
a18e3690	178	static int set_bf_sort(const struct dmi_system_id *d)
6b4b78fe MD	179	{
	180	if (pci_bf_sort == pci_bf_sort_default) {
	181	pci_bf_sort = pci_dmi_bf;
	182	printk(KERN_INFO "PCI: %s detected, enabling pci=bfsort.\n", d->ident);
	183	}
	184	return 0;
	185	}
	186
a18e3690	187	static void read_dmi_type_b1(const struct dmi_header *dm,
6e8af08d ND	188	void *private_data)
	189	{
	190	u8 d = (u8 )dm + 4;
	191
	192	if (dm->type != 0xB1)
	193	return;
	194	switch ((((u32 )d) >> 9) & 0x03) {
	195	case 0x00:
	196	printk(KERN_INFO "dmi type 0xB1 record - unknown flag\n");
	197	break;
	198	case 0x01: /* set pci=bfsort */
	199	smbios_type_b1_flag = 1;
	200	break;
	201	case 0x02: /* do not set pci=bfsort */
	202	smbios_type_b1_flag = 2;
	203	break;
	204	default:
	205	break;
	206	}
	207	}
	208
a18e3690	209	static int find_sort_method(const struct dmi_system_id *d)
6e8af08d ND	210	{
	211	dmi_walk(read_dmi_type_b1, NULL);
	212
	213	if (smbios_type_b1_flag == 1) {
	214	set_bf_sort(d);
	215	return 0;
	216	}
	217	return -1;
	218	}
	219
8c4b2cf9 BK	220	/*
	221	* Enable renumbering of PCI bus# ranges to reach all PCI busses (Cardbus)
	222	*/
	223	#ifdef __i386__
a18e3690	224	static int assign_all_busses(const struct dmi_system_id *d)
8c4b2cf9 BK	225	{
	226	pci_probe \|= PCI_ASSIGN_ALL_BUSSES;
	227	printk(KERN_INFO "%s detected: enabling PCI bus# renumbering"
	228	" (pci=assign-busses)\n", d->ident);
	229	return 0;
	230	}
	231	#endif
	232
a18e3690	233	static int set_scan_all(const struct dmi_system_id *d)
284f5f9d BH	234	{
	235	printk(KERN_INFO "PCI: %s detected, enabling pci=pcie_scan_all\n",
	236	d->ident);
	237	pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
	238	return 0;
	239	}
	240
a18e3690	241	static const struct dmi_system_id pciprobe_dmi_table[] = {
6b4b78fe	242	#ifdef __i386__
8c4b2cf9 BK	243	/*
	244	* Laptops which need pci=assign-busses to see Cardbus cards
	245	*/
8c4b2cf9 BK	246	{
	247	.callback = assign_all_busses,
	248	.ident = "Samsung X20 Laptop",
	249	.matches = {
	250	DMI_MATCH(DMI_SYS_VENDOR, "Samsung Electronics"),
	251	DMI_MATCH(DMI_PRODUCT_NAME, "SX20S"),
	252	},
	253	},
	254	#endif /* __i386__ */
6b4b78fe MD	255	{
	256	.callback = set_bf_sort,
	257	.ident = "Dell PowerEdge 1950",
	258	.matches = {
	259	DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
	260	DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1950"),
	261	},
	262	},
	263	{
	264	.callback = set_bf_sort,
	265	.ident = "Dell PowerEdge 1955",
	266	.matches = {
	267	DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
	268	DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 1955"),
	269	},
	270	},
	271	{
	272	.callback = set_bf_sort,
	273	.ident = "Dell PowerEdge 2900",
	274	.matches = {
	275	DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
	276	DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2900"),
	277	},
	278	},
	279	{
	280	.callback = set_bf_sort,
	281	.ident = "Dell PowerEdge 2950",
	282	.matches = {
	283	DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
	284	DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge 2950"),
	285	},
	286	},
f7a9dae7 MD	287	{
	288	.callback = set_bf_sort,
	289	.ident = "Dell PowerEdge R900",
	290	.matches = {
	291	DMI_MATCH(DMI_SYS_VENDOR, "Dell"),
	292	DMI_MATCH(DMI_PRODUCT_NAME, "PowerEdge R900"),
	293	},
	294	},
9b373ed1 ND	295	{
	296	.callback = find_sort_method,
	297	.ident = "Dell System",
	298	.matches = {
	299	DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc"),
	300	},
	301	},
f52383d3 AG	302	{
	303	.callback = set_bf_sort,
	304	.ident = "HP ProLiant BL20p G3",
	305	.matches = {
	306	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	307	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G3"),
	308	},
	309	},
	310	{
	311	.callback = set_bf_sort,
	312	.ident = "HP ProLiant BL20p G4",
	313	.matches = {
	314	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	315	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL20p G4"),
	316	},
	317	},
	318	{
	319	.callback = set_bf_sort,
	320	.ident = "HP ProLiant BL30p G1",
	321	.matches = {
	322	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	323	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL30p G1"),
	324	},
	325	},
	326	{
	327	.callback = set_bf_sort,
	328	.ident = "HP ProLiant BL25p G1",
	329	.matches = {
	330	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	331	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL25p G1"),
	332	},
	333	},
	334	{
	335	.callback = set_bf_sort,
	336	.ident = "HP ProLiant BL35p G1",
	337	.matches = {
	338	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	339	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL35p G1"),
	340	},
	341	},
	342	{
	343	.callback = set_bf_sort,
	344	.ident = "HP ProLiant BL45p G1",
	345	.matches = {
	346	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	347	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G1"),
	348	},
	349	},
	350	{
	351	.callback = set_bf_sort,
	352	.ident = "HP ProLiant BL45p G2",
	353	.matches = {
	354	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	355	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL45p G2"),
	356	},
	357	},
	358	{
	359	.callback = set_bf_sort,
	360	.ident = "HP ProLiant BL460c G1",
	361	.matches = {
	362	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
	363	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL460c G1"),
	364	},
	365	},
366	{
367	.callback = set_bf_sort,
368	.ident = "HP ProLiant BL465c G1",
369	.matches = {
370	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
371	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL465c G1"),
372	},
373	},
374	{
375	.callback = set_bf_sort,
376	.ident = "HP ProLiant BL480c G1",
377	.matches = {
378	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
379	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL480c G1"),
380	},
381	},
382	{
383	.callback = set_bf_sort,
384	.ident = "HP ProLiant BL685c G1",
385	.matches = {
386	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
387	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant BL685c G1"),
388	},
389	},
8f8ae1a7 MS	390	{
8f8ae1a7 MS	391	.callback = set_bf_sort,
8d64c781	392	.ident = "HP ProLiant DL360",
8f8ae1a7 MS	393	.matches = {
8f8ae1a7 MS	394	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
8d64c781	395	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL360"),
8f8ae1a7 MS	396	},
	397	},
	398	{
	399	.callback = set_bf_sort,
8d64c781	400	.ident = "HP ProLiant DL380",
8f8ae1a7 MS	401	.matches = {
8f8ae1a7 MS	402	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
8d64c781	403	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL380"),
8f8ae1a7 MS	404	},
8f8ae1a7 MS	405	},
5b1ea82f JL	406	#ifdef __i386__
	407	{
	408	.callback = assign_all_busses,
	409	.ident = "Compaq EVO N800c",
	410	.matches = {
	411	DMI_MATCH(DMI_SYS_VENDOR, "Compaq"),
	412	DMI_MATCH(DMI_PRODUCT_NAME, "EVO N800c"),
	413	},
	414	},
	415	#endif
c82bc5ad MS	416	{
c82bc5ad MS	417	.callback = set_bf_sort,
739db07f	418	.ident = "HP ProLiant DL385 G2",
c82bc5ad MS	419	.matches = {
c82bc5ad MS	420	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
739db07f	421	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL385 G2"),
c82bc5ad MS	422	},
	423	},
	424	{
	425	.callback = set_bf_sort,
739db07f	426	.ident = "HP ProLiant DL585 G2",
c82bc5ad MS	427	.matches = {
c82bc5ad MS	428	DMI_MATCH(DMI_SYS_VENDOR, "HP"),
739db07f	429	DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL585 G2"),
c82bc5ad MS	430	},
c82bc5ad MS	431	},
284f5f9d BH	432	{
	433	.callback = set_scan_all,
	434	.ident = "Stratus/NEC ftServer",
	435	.matches = {
1278998f MS	436	DMI_MATCH(DMI_SYS_VENDOR, "Stratus"),
1278998f MS	437	DMI_MATCH(DMI_PRODUCT_NAME, "ftServer"),
284f5f9d BH	438	},
284f5f9d BH	439	},
8c4b2cf9 BK	440	{}
8c4b2cf9 BK	441	};
1da177e4	442
0df18ff3 YL	443	void __init dmi_check_pciprobe(void)
	444	{
	445	dmi_check_system(pciprobe_dmi_table);
	446	}
	447
a18e3690	448	struct pci_bus *pcibios_scan_root(int busnum)
1da177e4 LT	449	{
	450	struct pci_bus *bus = NULL;
	451
	452	while ((bus = pci_find_next_bus(bus)) != NULL) {
	453	if (bus->number == busnum) {
	454	/* Already scanned */
	455	return bus;
	456	}
	457	}
	458
c57ca65a YL	459	return pci_scan_bus_on_node(busnum, &pci_root_ops,
c57ca65a YL	460	get_mp_bus_to_node(busnum));
1da177e4	461	}
c57ca65a	462
44de3395	463	void __init pcibios_set_cache_line_size(void)
1da177e4 LT	464	{
	465	struct cpuinfo_x86 *c = &boot_cpu_data;
	466
1da177e4	467	/*
76b1a87b DJ	468	* Set PCI cacheline size to that of the CPU if the CPU has reported it.
	469	* (For older CPUs that don't support cpuid, we se it to 32 bytes
	470	* It's also good for 386/486s (which actually have 16)
1da177e4 LT	471	* as quite a few PCI devices do not support smaller values.
1da177e4 LT	472	*/
76b1a87b DJ	473	if (c->x86_clflush_size > 0) {
	474	pci_dfl_cache_line_size = c->x86_clflush_size >> 2;
	475	printk(KERN_DEBUG "PCI: pci_cache_line_size set to %d bytes\n",
	476	pci_dfl_cache_line_size << 2);
	477	} else {
	478	pci_dfl_cache_line_size = 32 >> 2;
	479	printk(KERN_DEBUG "PCI: Unknown cacheline size. Setting to 32 bytes\n");
	480	}
44de3395 AN	481	}
	482
	483	int __init pcibios_init(void)
	484	{
	485	if (!raw_pci_ops) {
	486	printk(KERN_WARNING "PCI: System does not support PCI\n");
	487	return 0;
	488	}
1da177e4	489
44de3395	490	pcibios_set_cache_line_size();
1da177e4 LT	491	pcibios_resource_survey();
1da177e4 LT	492
6b4b78fe MD	493	if (pci_bf_sort >= pci_force_bf)
6b4b78fe MD	494	pci_sort_breadthfirst();
1da177e4 LT	495	return 0;
	496	}
	497
15fa325b	498	char * __init pcibios_setup(char *str)
1da177e4 LT	499	{
	500	if (!strcmp(str, "off")) {
	501	pci_probe = 0;
	502	return NULL;
6b4b78fe MD	503	} else if (!strcmp(str, "bfsort")) {
	504	pci_bf_sort = pci_force_bf;
	505	return NULL;
	506	} else if (!strcmp(str, "nobfsort")) {
	507	pci_bf_sort = pci_force_nobf;
	508	return NULL;
1da177e4 LT	509	}
	510	#ifdef CONFIG_PCI_BIOS
	511	else if (!strcmp(str, "bios")) {
	512	pci_probe = PCI_PROBE_BIOS;
	513	return NULL;
	514	} else if (!strcmp(str, "nobios")) {
	515	pci_probe &= ~PCI_PROBE_BIOS;
	516	return NULL;
1da177e4 LT	517	} else if (!strcmp(str, "biosirq")) {
	518	pci_probe \|= PCI_BIOS_IRQ_SCAN;
	519	return NULL;
120bb424	520	} else if (!strncmp(str, "pirqaddr=", 9)) {
	521	pirq_table_addr = simple_strtoul(str+9, NULL, 0);
	522	return NULL;
1da177e4 LT	523	}
	524	#endif
	525	#ifdef CONFIG_PCI_DIRECT
	526	else if (!strcmp(str, "conf1")) {
	527	pci_probe = PCI_PROBE_CONF1 \| PCI_NO_CHECKS;
	528	return NULL;
	529	}
	530	else if (!strcmp(str, "conf2")) {
	531	pci_probe = PCI_PROBE_CONF2 \| PCI_NO_CHECKS;
	532	return NULL;
	533	}
	534	#endif
	535	#ifdef CONFIG_PCI_MMCONFIG
	536	else if (!strcmp(str, "nommconf")) {
	537	pci_probe &= ~PCI_PROBE_MMCONF;
	538	return NULL;
	539	}
5f0b2976 YL	540	else if (!strcmp(str, "check_enable_amd_mmconf")) {
	541	pci_probe \|= PCI_CHECK_ENABLE_AMD_MMCONF;
	542	return NULL;
	543	}
1da177e4 LT	544	#endif
	545	else if (!strcmp(str, "noacpi")) {
	546	acpi_noirq_set();
	547	return NULL;
	548	}
0637a70a AK	549	else if (!strcmp(str, "noearly")) {
	550	pci_probe \|= PCI_PROBE_NOEARLY;
	551	return NULL;
	552	}
1da177e4 LT	553	#ifndef CONFIG_X86_VISWS
	554	else if (!strcmp(str, "usepirqmask")) {
	555	pci_probe \|= PCI_USE_PIRQ_MASK;
	556	return NULL;
	557	} else if (!strncmp(str, "irqmask=", 8)) {
	558	pcibios_irq_mask = simple_strtol(str+8, NULL, 0);
	559	return NULL;
	560	} else if (!strncmp(str, "lastbus=", 8)) {
	561	pcibios_last_bus = simple_strtol(str+8, NULL, 0);
	562	return NULL;
	563	}
	564	#endif
	565	else if (!strcmp(str, "rom")) {
	566	pci_probe \|= PCI_ASSIGN_ROMS;
	567	return NULL;
bb71ad88 GH	568	} else if (!strcmp(str, "norom")) {
	569	pci_probe \|= PCI_NOASSIGN_ROMS;
	570	return NULL;
7bd1c365 MH	571	} else if (!strcmp(str, "nobar")) {
	572	pci_probe \|= PCI_NOASSIGN_BARS;
	573	return NULL;
1da177e4 LT	574	} else if (!strcmp(str, "assign-busses")) {
	575	pci_probe \|= PCI_ASSIGN_ALL_BUSSES;
	576	return NULL;
236e946b LT	577	} else if (!strcmp(str, "use_crs")) {
236e946b LT	578	pci_probe \|= PCI_USE__CRS;
62f420f8	579	return NULL;
7bc5e3f2 BH	580	} else if (!strcmp(str, "nocrs")) {
	581	pci_probe \|= PCI_ROOT_NO_CRS;
	582	return NULL;
e3f2baeb YL	583	} else if (!strcmp(str, "earlydump")) {
	584	pci_early_dump_regs = 1;
	585	return NULL;
1da177e4 LT	586	} else if (!strcmp(str, "routeirq")) {
	587	pci_routeirq = 1;
	588	return NULL;
13a6ddb0 YL	589	} else if (!strcmp(str, "skip_isa_align")) {
	590	pci_probe \|= PCI_CAN_SKIP_ISA_ALIGN;
	591	return NULL;
a9322f64 SA	592	} else if (!strcmp(str, "noioapicquirk")) {
	593	noioapicquirk = 1;
	594	return NULL;
9197979b SA	595	} else if (!strcmp(str, "ioapicreroute")) {
	596	if (noioapicreroute != -1)
	597	noioapicreroute = 0;
	598	return NULL;
41b9eb26 SA	599	} else if (!strcmp(str, "noioapicreroute")) {
	600	if (noioapicreroute != -1)
	601	noioapicreroute = 1;
	602	return NULL;
1da177e4 LT	603	}
	604	return str;
	605	}
	606
	607	unsigned int pcibios_assign_all_busses(void)
	608	{
	609	return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
	610	}
	611
f9a37be0 MG	612	int pcibios_add_device(struct pci_dev *dev)
	613	{
	614	struct setup_data *data;
	615	struct pci_setup_rom *rom;
	616	u64 pa_data;
	617
	618	pa_data = boot_params.hdr.setup_data;
	619	while (pa_data) {
	620	data = phys_to_virt(pa_data);
	621
	622	if (data->type == SETUP_PCI) {
	623	rom = (struct pci_setup_rom *)data;
	624
	625	if ((pci_domain_nr(dev->bus) == rom->segment) &&
	626	(dev->bus->number == rom->bus) &&
	627	(PCI_SLOT(dev->devfn) == rom->device) &&
	628	(PCI_FUNC(dev->devfn) == rom->function) &&
	629	(dev->vendor == rom->vendor) &&
	630	(dev->device == rom->devid)) {
dbd3fc33 BH	631	dev->rom = pa_data +
dbd3fc33 BH	632	offsetof(struct pci_setup_rom, romdata);
f9a37be0 MG	633	dev->romlen = rom->pcilen;
	634	}
	635	}
	636	pa_data = data->next;
	637	}
	638	return 0;
	639	}
	640
1da177e4 LT	641	int pcibios_enable_device(struct pci_dev *dev, int mask)
	642	{
	643	int err;
	644
b81d988c	645	if ((err = pci_enable_resources(dev, mask)) < 0)
1da177e4 LT	646	return err;
1da177e4 LT	647
16cf0ebc	648	if (!pci_dev_msi_enabled(dev))
bba6f6fc EB	649	return pcibios_enable_irq(dev);
bba6f6fc EB	650	return 0;
1da177e4	651	}
87bec66b DSL	652
	653	void pcibios_disable_device (struct pci_dev *dev)
	654	{
16cf0ebc	655	if (!pci_dev_msi_enabled(dev) && pcibios_disable_irq)
87bec66b DSL	656	pcibios_disable_irq(dev);
87bec66b DSL	657	}
73c59afc	658
642c92da	659	int pci_ext_cfg_avail(void)
0ef5f8f6 AP	660	{
	661	if (raw_pci_ext_ops)
	662	return 1;
	663	else
	664	return 0;
	665	}
	666
a18e3690	667	struct pci_bus pci_scan_bus_on_node(int busno, struct pci_ops ops, int node)
73c59afc	668	{
2cd6975a	669	LIST_HEAD(resources);
73c59afc MBY	670	struct pci_bus *bus = NULL;
	671	struct pci_sysdata *sd;
	672
	673	/*
	674	* Allocate per-root-bus (not per bus) arch-specific data.
	675	* TODO: leak; this memory is never freed.
	676	* It's arguable whether it's worth the trouble to care.
	677	*/
	678	sd = kzalloc(sizeof(*sd), GFP_KERNEL);
	679	if (!sd) {
	680	printk(KERN_ERR "PCI: OOM, skipping PCI bus %02x\n", busno);
	681	return NULL;
	682	}
871d5f8d	683	sd->node = node;
2cd6975a	684	x86_pci_root_bus_resources(busno, &resources);
c57ca65a	685	printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busno);
2cd6975a BH	686	bus = pci_scan_root_bus(NULL, busno, ops, sd, &resources);
	687	if (!bus) {
	688	pci_free_resource_list(&resources);
73c59afc	689	kfree(sd);
2cd6975a	690	}
73c59afc MBY	691
	692	return bus;
	693	}
871d5f8d	694
a18e3690	695	struct pci_bus *pci_scan_bus_with_sysdata(int busno)
871d5f8d YL	696	{
	697	return pci_scan_bus_on_node(busno, &pci_root_ops, -1);
	698	}
2547089c JB	699
	700	/*
	701	* NUMA info for PCI busses
	702	*
	703	* Early arch code is responsible for filling in reasonable values here.
	704	* A node id of "-1" means "use current node". In other words, if a bus
	705	* has a -1 node id, it's not tightly coupled to any particular chunk
	706	* of memory (as is the case on some Nehalem systems).
	707	*/
	708	#ifdef CONFIG_NUMA
	709
	710	#define BUS_NR 256
	711
	712	#ifdef CONFIG_X86_64
	713
	714	static int mp_bus_to_node[BUS_NR] = {
	715	[0 ... BUS_NR - 1] = -1
	716	};
	717
	718	void set_mp_bus_to_node(int busnum, int node)
	719	{
	720	if (busnum >= 0 && busnum < BUS_NR)
	721	mp_bus_to_node[busnum] = node;
	722	}
	723
	724	int get_mp_bus_to_node(int busnum)
	725	{
	726	int node = -1;
	727
	728	if (busnum < 0 \|\| busnum > (BUS_NR - 1))
	729	return node;
	730
	731	node = mp_bus_to_node[busnum];
	732
	733	/*
	734	* let numa_node_id to decide it later in dma_alloc_pages
	735	* if there is no ram on that node
	736	*/
	737	if (node != -1 && !node_online(node))
	738	node = -1;
	739
	740	return node;
	741	}
	742
	743	#else /* CONFIG_X86_32 */
	744
76baeebf	745	static int mp_bus_to_node[BUS_NR] = {
2547089c JB	746	[0 ... BUS_NR - 1] = -1
	747	};
	748
	749	void set_mp_bus_to_node(int busnum, int node)
	750	{
	751	if (busnum >= 0 && busnum < BUS_NR)
	752	mp_bus_to_node[busnum] = (unsigned char) node;
	753	}
	754
	755	int get_mp_bus_to_node(int busnum)
	756	{
	757	int node;
	758
	759	if (busnum < 0 \|\| busnum > (BUS_NR - 1))
	760	return 0;
	761	node = mp_bus_to_node[busnum];
	762	return node;
	763	}
	764
	765	#endif /* CONFIG_X86_32 */
	766
	767	#endif /* CONFIG_NUMA */