[deliverable/linux.git] / arch / x86 / pci / i386.c

/*
 *	Low-Level PCI Access for i386 machines
 *
 * Copyright 1993, 1994 Drew Eckhardt
 *      Visionary Computing
 *      (Unix and Linux consulting and custom programming)
 *      Drew@Colorado.EDU
 *      +1 (303) 786-7975
 *
 * Drew's work was sponsored by:
 *	iX Multiuser Multitasking Magazine
 *	Hannover, Germany
 *	hm@ix.de
 *
 * Copyright 1997--2000 Martin Mares <mj@ucw.cz>
 *
 * For more information, please consult the following manuals (look at
 * http://www.pcisig.com/ for how to get them):
 *
 * PCI BIOS Specification
 * PCI Local Bus Specification
 * PCI to PCI Bridge Specification
 * PCI System Design Guide
 *
 */

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/errno.h>
#include <linux/bootmem.h>

#include <asm/pat.h>
#include <asm/e820.h>
#include <asm/pci_x86.h>
#include <asm/io_apic.h>


static int
skip_isa_ioresource_align(struct pci_dev *dev) {

	if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) &&
	    !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
		return 1;
	return 0;
}

/*
 * We need to avoid collisions with `mirrored' VGA ports
 * and other strange ISA hardware, so we always want the
 * addresses to be allocated in the 0x000-0x0ff region
 * modulo 0x400.
 *
 * Why? Because some silly external IO cards only decode
 * the low 10 bits of the IO address. The 0x00-0xff region
 * is reserved for motherboard devices that decode all 16
 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
 * but we want to try to avoid allocating at 0x2900-0x2bff
 * which might have be mirrored at 0x0100-0x03ff..
 */
resource_size_t
pcibios_align_resource(void *data, const struct resource *res,
			resource_size_t size, resource_size_t align)
{
	struct pci_dev *dev = data;
	resource_size_t start = res->start;

	if (res->flags & IORESOURCE_IO) {
		if (skip_isa_ioresource_align(dev))
			return start;
		if (start & 0x300)
			start = (start + 0x3ff) & ~0x3ff;
	}
	return start;
}
EXPORT_SYMBOL(pcibios_align_resource);

/*
 *  Handle resources of PCI devices.  If the world were perfect, we could
 *  just allocate all the resource regions and do nothing more.  It isn't.
 *  On the other hand, we cannot just re-allocate all devices, as it would
 *  require us to know lots of host bridge internals.  So we attempt to
 *  keep as much of the original configuration as possible, but tweak it
 *  when it's found to be wrong.
 *
 *  Known BIOS problems we have to work around:
 *	- I/O or memory regions not configured
 *	- regions configured, but not enabled in the command register
 *	- bogus I/O addresses above 64K used
 *	- expansion ROMs left enabled (this may sound harmless, but given
 *	  the fact the PCI specs explicitly allow address decoders to be
 *	  shared between expansion ROMs and other resource regions, it's
 *	  at least dangerous)
 *	- bad resource sizes or overlaps with other regions
 *
 *  Our solution:
 *	(1) Allocate resources for all buses behind PCI-to-PCI bridges.
 *	    This gives us fixed barriers on where we can allocate.
 *	(2) Allocate resources for all enabled devices.  If there is
 *	    a collision, just mark the resource as unallocated. Also
 *	    disable expansion ROMs during this step.
 *	(3) Try to allocate resources for disabled devices.  If the
 *	    resources were assigned correctly, everything goes well,
 *	    if they weren't, they won't disturb allocation of other
 *	    resources.
 *	(4) Assign new addresses to resources which were either
 *	    not configured at all or misconfigured.  If explicitly
 *	    requested by the user, configure expansion ROM address
 *	    as well.
 */

static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
{
	struct pci_bus *bus;
	struct pci_dev *dev;
	int idx;
	struct resource *r;

	/* Depth-First Search on bus tree */
	list_for_each_entry(bus, bus_list, node) {
		if ((dev = bus->self)) {
			for (idx = PCI_BRIDGE_RESOURCES;
			    idx < PCI_NUM_RESOURCES; idx++) {
				r = &dev->resource[idx];
				if (!r->flags)
					continue;
				if (!r->start ||
				    pci_claim_resource(dev, idx) < 0) {
					/*
					 * Something is wrong with the region.
					 * Invalidate the resource to prevent
					 * child resource allocations in this
					 * range.
					 */
					r->start = r->end = 0;
					r->flags = 0;
				}
			}
		}
		pcibios_allocate_bus_resources(&bus->children);
	}
}

struct pci_check_idx_range {
	int start;
	int end;
};

static void __init pcibios_allocate_resources(int pass)
{
	struct pci_dev *dev = NULL;
	int idx, disabled, i;
	u16 command;
	struct resource *r;

	struct pci_check_idx_range idx_range[] = {
		{ PCI_STD_RESOURCES, PCI_STD_RESOURCE_END },
#ifdef CONFIG_PCI_IOV
		{ PCI_IOV_RESOURCES, PCI_IOV_RESOURCE_END },
#endif
	};

	for_each_pci_dev(dev) {
		pci_read_config_word(dev, PCI_COMMAND, &command);
		for (i = 0; i < ARRAY_SIZE(idx_range); i++)
		for (idx = idx_range[i].start; idx <= idx_range[i].end; idx++) {
			r = &dev->resource[idx];
			if (r->parent)		/* Already allocated */
				continue;
			if (!r->start)		/* Address not assigned at all */
				continue;
			if (r->flags & IORESOURCE_IO)
				disabled = !(command & PCI_COMMAND_IO);
			else
				disabled = !(command & PCI_COMMAND_MEMORY);
			if (pass == disabled) {
				dev_dbg(&dev->dev,
					"BAR %d: reserving %pr (d=%d, p=%d)\n",
					idx, r, disabled, pass);
				if (pci_claim_resource(dev, idx) < 0) {
					/* We'll assign a new address later */
					dev->fw_addr[idx] = r->start;
					r->end -= r->start;
					r->start = 0;
				}
			}
		}
		if (!pass) {
			r = &dev->resource[PCI_ROM_RESOURCE];
			if (r->flags & IORESOURCE_ROM_ENABLE) {
				/* Turn the ROM off, leave the resource region,
				 * but keep it unregistered. */
				u32 reg;
				dev_dbg(&dev->dev, "disabling ROM %pR\n", r);
				r->flags &= ~IORESOURCE_ROM_ENABLE;
				pci_read_config_dword(dev,
						dev->rom_base_reg, &reg);
				pci_write_config_dword(dev, dev->rom_base_reg,
						reg & ~PCI_ROM_ADDRESS_ENABLE);
			}
		}
	}
}

static int __init pcibios_assign_resources(void)
{
	struct pci_dev *dev = NULL;
	struct resource *r;

	if (!(pci_probe & PCI_ASSIGN_ROMS)) {
		/*
		 * Try to use BIOS settings for ROMs, otherwise let
		 * pci_assign_unassigned_resources() allocate the new
		 * addresses.
		 */
		for_each_pci_dev(dev) {
			r = &dev->resource[PCI_ROM_RESOURCE];
			if (!r->flags || !r->start)
				continue;
			if (pci_claim_resource(dev, PCI_ROM_RESOURCE) < 0) {
				r->end -= r->start;
				r->start = 0;
			}
		}
	}

	pci_assign_unassigned_resources();

	return 0;
}

void __init pcibios_resource_survey(void)
{
	DBG("PCI: Allocating resources\n");
	pcibios_allocate_bus_resources(&pci_root_buses);
	pcibios_allocate_resources(0);
	pcibios_allocate_resources(1);

	e820_reserve_resources_late();
	/*
	 * Insert the IO APIC resources after PCI initialization has
	 * occurred to handle IO APICS that are mapped in on a BAR in
	 * PCI space, but before trying to assign unassigned pci res.
	 */
	ioapic_insert_resources();
}

/**
 * called in fs_initcall (one below subsys_initcall),
 * give a chance for motherboard reserve resources
 */
fs_initcall(pcibios_assign_resources);

static const struct vm_operations_struct pci_mmap_ops = {
	.access = generic_access_phys,
};

int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
			enum pci_mmap_state mmap_state, int write_combine)
{
	unsigned long prot;

	/* I/O space cannot be accessed via normal processor loads and
	 * stores on this platform.
	 */
	if (mmap_state == pci_mmap_io)
		return -EINVAL;

	prot = pgprot_val(vma->vm_page_prot);

	/*
 	 * Return error if pat is not enabled and write_combine is requested.
 	 * Caller can followup with UC MINUS request and add a WC mtrr if there
 	 * is a free mtrr slot.
 	 */
	if (!pat_enabled && write_combine)
		return -EINVAL;

	if (pat_enabled && write_combine)
		prot |= _PAGE_CACHE_WC;
	else if (pat_enabled || boot_cpu_data.x86 > 3)
		/*
		 * ioremap() and ioremap_nocache() defaults to UC MINUS for now.
		 * To avoid attribute conflicts, request UC MINUS here
		 * as well.
		 */
		prot |= _PAGE_CACHE_UC_MINUS;

	prot |= _PAGE_IOMAP;	/* creating a mapping for IO */

	vma->vm_page_prot = __pgprot(prot);

	if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
			       vma->vm_end - vma->vm_start,
			       vma->vm_page_prot))
		return -EAGAIN;

	vma->vm_ops = &pci_mmap_ops;

	return 0;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Low-Level PCI Access for i386 machines
	3	*
	4	* Copyright 1993, 1994 Drew Eckhardt
	5	* Visionary Computing
	6	* (Unix and Linux consulting and custom programming)
	7	* Drew@Colorado.EDU
	8	* +1 (303) 786-7975
	9	*
	10	* Drew's work was sponsored by:
	11	* iX Multiuser Multitasking Magazine
	12	* Hannover, Germany
	13	* hm@ix.de
	14	*
	15	* Copyright 1997--2000 Martin Mares <mj@ucw.cz>
	16	*
	17	* For more information, please consult the following manuals (look at
	18	* http://www.pcisig.com/ for how to get them):
	19	*
	20	* PCI BIOS Specification
	21	* PCI Local Bus Specification
	22	* PCI to PCI Bridge Specification
	23	* PCI System Design Guide
	24	*
	25	*/
	26
	27	#include <linux/types.h>
	28	#include <linux/kernel.h>
69c60c88	29	#include <linux/export.h>
1da177e4 LT	30	#include <linux/pci.h>
	31	#include <linux/init.h>
	32	#include <linux/ioport.h>
	33	#include <linux/errno.h>
03d72aa1	34	#include <linux/bootmem.h>
	35
	36	#include <asm/pat.h>
58f7c988	37	#include <asm/e820.h>
82487711	38	#include <asm/pci_x86.h>
857fdc53	39	#include <asm/io_apic.h>
1da177e4	40
1da177e4	41
036fff4c GH	42	static int
	43	skip_isa_ioresource_align(struct pci_dev *dev) {
	44
	45	if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) &&
11949255	46	!(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
036fff4c GH	47	return 1;
	48	return 0;
	49	}
	50
1da177e4 LT	51	/*
	52	* We need to avoid collisions with `mirrored' VGA ports
	53	* and other strange ISA hardware, so we always want the
	54	* addresses to be allocated in the 0x000-0x0ff region
	55	* modulo 0x400.
	56	*
	57	* Why? Because some silly external IO cards only decode
	58	* the low 10 bits of the IO address. The 0x00-0xff region
	59	* is reserved for motherboard devices that decode all 16
	60	* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
	61	* but we want to try to avoid allocating at 0x2900-0x2bff
	62	* which might have be mirrored at 0x0100-0x03ff..
	63	*/
b26b2d49	64	resource_size_t
3b7a17fc	65	pcibios_align_resource(void data, const struct resource res,
e31dd6e4	66	resource_size_t size, resource_size_t align)
1da177e4	67	{
036fff4c	68	struct pci_dev *dev = data;
d14125ec	69	resource_size_t start = res->start;
036fff4c	70
1da177e4	71	if (res->flags & IORESOURCE_IO) {
d14125ec BH	72	if (skip_isa_ioresource_align(dev))
	73	return start;
	74	if (start & 0x300)
	75	start = (start + 0x3ff) & ~0x3ff;
1da177e4	76	}
b26b2d49	77	return start;
1da177e4	78	}
6c00a61e	79	EXPORT_SYMBOL(pcibios_align_resource);
1da177e4 LT	80
	81	/*
	82	* Handle resources of PCI devices. If the world were perfect, we could
	83	* just allocate all the resource regions and do nothing more. It isn't.
	84	* On the other hand, we cannot just re-allocate all devices, as it would
	85	* require us to know lots of host bridge internals. So we attempt to
	86	* keep as much of the original configuration as possible, but tweak it
	87	* when it's found to be wrong.
	88	*
	89	* Known BIOS problems we have to work around:
	90	* - I/O or memory regions not configured
	91	* - regions configured, but not enabled in the command register
	92	* - bogus I/O addresses above 64K used
	93	* - expansion ROMs left enabled (this may sound harmless, but given
	94	* the fact the PCI specs explicitly allow address decoders to be
	95	* shared between expansion ROMs and other resource regions, it's
	96	* at least dangerous)
837c4ef1	97	* - bad resource sizes or overlaps with other regions
1da177e4 LT	98	*
	99	* Our solution:
	100	* (1) Allocate resources for all buses behind PCI-to-PCI bridges.
	101	* This gives us fixed barriers on where we can allocate.
	102	* (2) Allocate resources for all enabled devices. If there is
	103	* a collision, just mark the resource as unallocated. Also
	104	* disable expansion ROMs during this step.
	105	* (3) Try to allocate resources for disabled devices. If the
	106	* resources were assigned correctly, everything goes well,
	107	* if they weren't, they won't disturb allocation of other
	108	* resources.
	109	* (4) Assign new addresses to resources which were either
	110	* not configured at all or misconfigured. If explicitly
	111	* requested by the user, configure expansion ROM address
	112	* as well.
	113	*/
	114
	115	static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
	116	{
	117	struct pci_bus *bus;
	118	struct pci_dev *dev;
	119	int idx;
a76117df	120	struct resource *r;
1da177e4 LT	121
	122	/* Depth-First Search on bus tree */
	123	list_for_each_entry(bus, bus_list, node) {
	124	if ((dev = bus->self)) {
7edab2f0 RD	125	for (idx = PCI_BRIDGE_RESOURCES;
7edab2f0 RD	126	idx < PCI_NUM_RESOURCES; idx++) {
1da177e4	127	r = &dev->resource[idx];
299de034	128	if (!r->flags)
1da177e4	129	continue;
a76117df MW	130	if (!r->start \|\|
a76117df MW	131	pci_claim_resource(dev, idx) < 0) {
7edab2f0 RD	132	/*
	133	* Something is wrong with the region.
	134	* Invalidate the resource to prevent
	135	* child resource allocations in this
	136	* range.
	137	*/
837c4ef1	138	r->start = r->end = 0;
299de034 IK	139	r->flags = 0;
299de034 IK	140	}
1da177e4 LT	141	}
	142	}
	143	pcibios_allocate_bus_resources(&bus->children);
	144	}
	145	}
	146
575939cf YL	147	struct pci_check_idx_range {
	148	int start;
	149	int end;
	150	};
	151
1da177e4 LT	152	static void __init pcibios_allocate_resources(int pass)
	153	{
	154	struct pci_dev *dev = NULL;
575939cf	155	int idx, disabled, i;
1da177e4	156	u16 command;
a76117df	157	struct resource *r;
1da177e4	158
575939cf YL	159	struct pci_check_idx_range idx_range[] = {
	160	{ PCI_STD_RESOURCES, PCI_STD_RESOURCE_END },
	161	#ifdef CONFIG_PCI_IOV
	162	{ PCI_IOV_RESOURCES, PCI_IOV_RESOURCE_END },
	163	#endif
	164	};
	165
1da177e4 LT	166	for_each_pci_dev(dev) {
1da177e4 LT	167	pci_read_config_word(dev, PCI_COMMAND, &command);
575939cf YL	168	for (i = 0; i < ARRAY_SIZE(idx_range); i++)
575939cf YL	169	for (idx = idx_range[i].start; idx <= idx_range[i].end; idx++) {
1da177e4 LT	170	r = &dev->resource[idx];
	171	if (r->parent) /* Already allocated */
	172	continue;
	173	if (!r->start) /* Address not assigned at all */
	174	continue;
	175	if (r->flags & IORESOURCE_IO)
	176	disabled = !(command & PCI_COMMAND_IO);
	177	else
	178	disabled = !(command & PCI_COMMAND_MEMORY);
	179	if (pass == disabled) {
c7dabef8	180	dev_dbg(&dev->dev,
865df576	181	"BAR %d: reserving %pr (d=%d, p=%d)\n",
c7dabef8	182	idx, r, disabled, pass);
a76117df	183	if (pci_claim_resource(dev, idx) < 0) {
1da177e4	184	/* We'll assign a new address later */
58c84eda	185	dev->fw_addr[idx] = r->start;
1da177e4 LT	186	r->end -= r->start;
	187	r->start = 0;
	188	}
	189	}
	190	}
	191	if (!pass) {
	192	r = &dev->resource[PCI_ROM_RESOURCE];
	193	if (r->flags & IORESOURCE_ROM_ENABLE) {
7edab2f0 RD	194	/* Turn the ROM off, leave the resource region,
7edab2f0 RD	195	* but keep it unregistered. */
1da177e4	196	u32 reg;
c7dabef8	197	dev_dbg(&dev->dev, "disabling ROM %pR\n", r);
1da177e4	198	r->flags &= ~IORESOURCE_ROM_ENABLE;
7edab2f0 RD	199	pci_read_config_dword(dev,
	200	dev->rom_base_reg, &reg);
	201	pci_write_config_dword(dev, dev->rom_base_reg,
	202	reg & ~PCI_ROM_ADDRESS_ENABLE);
1da177e4 LT	203	}
	204	}
	205	}
	206	}
	207
	208	static int __init pcibios_assign_resources(void)
	209	{
	210	struct pci_dev *dev = NULL;
a76117df	211	struct resource *r;
1da177e4	212
81d4af13	213	if (!(pci_probe & PCI_ASSIGN_ROMS)) {
7edab2f0 RD	214	/*
	215	* Try to use BIOS settings for ROMs, otherwise let
	216	* pci_assign_unassigned_resources() allocate the new
	217	* addresses.
	218	*/
81d4af13	219	for_each_pci_dev(dev) {
1da177e4	220	r = &dev->resource[PCI_ROM_RESOURCE];
81d4af13 IK	221	if (!r->flags \|\| !r->start)
81d4af13 IK	222	continue;
a76117df	223	if (pci_claim_resource(dev, PCI_ROM_RESOURCE) < 0) {
81d4af13 IK	224	r->end -= r->start;
	225	r->start = 0;
	226	}
1da177e4 LT	227	}
1da177e4 LT	228	}
81d4af13 IK	229
	230	pci_assign_unassigned_resources();
	231
1da177e4 LT	232	return 0;
	233	}
	234
	235	void __init pcibios_resource_survey(void)
	236	{
	237	DBG("PCI: Allocating resources\n");
	238	pcibios_allocate_bus_resources(&pci_root_buses);
	239	pcibios_allocate_resources(0);
	240	pcibios_allocate_resources(1);
a5444d15 IM	241
a5444d15 IM	242	e820_reserve_resources_late();
857fdc53 YL	243	/*
857fdc53 YL	244	* Insert the IO APIC resources after PCI initialization has
0d2eb44f	245	* occurred to handle IO APICS that are mapped in on a BAR in
857fdc53 YL	246	* PCI space, but before trying to assign unassigned pci res.
	247	*/
	248	ioapic_insert_resources();
1da177e4 LT	249	}
	250
	251	/**
	252	* called in fs_initcall (one below subsys_initcall),
	253	* give a chance for motherboard reserve resources
	254	*/
	255	fs_initcall(pcibios_assign_resources);
	256
f0f37e2f	257	static const struct vm_operations_struct pci_mmap_ops = {
7ae8ed50	258	.access = generic_access_phys,
03d72aa1	259	};
03d72aa1	260
1da177e4 LT	261	int pci_mmap_page_range(struct pci_dev dev, struct vm_area_struct vma,
	262	enum pci_mmap_state mmap_state, int write_combine)
	263	{
	264	unsigned long prot;
	265
	266	/* I/O space cannot be accessed via normal processor loads and
	267	* stores on this platform.
	268	*/
	269	if (mmap_state == pci_mmap_io)
	270	return -EINVAL;
	271
1da177e4	272	prot = pgprot_val(vma->vm_page_prot);
2992e545 SS	273
	274	/*
	275	* Return error if pat is not enabled and write_combine is requested.
	276	* Caller can followup with UC MINUS request and add a WC mtrr if there
	277	* is a free mtrr slot.
	278	*/
	279	if (!pat_enabled && write_combine)
	280	return -EINVAL;
	281
499f8f84	282	if (pat_enabled && write_combine)
03d72aa1	283	prot \|= _PAGE_CACHE_WC;
499f8f84	284	else if (pat_enabled \|\| boot_cpu_data.x86 > 3)
de33c442 SS	285	/*
	286	* ioremap() and ioremap_nocache() defaults to UC MINUS for now.
	287	* To avoid attribute conflicts, request UC MINUS here
0d2eb44f	288	* as well.
de33c442 SS	289	*/
de33c442 SS	290	prot \|= _PAGE_CACHE_UC_MINUS;
03d72aa1	291
5ee01f49 JF	292	prot \|= _PAGE_IOMAP; /* creating a mapping for IO */
5ee01f49 JF	293
1da177e4 LT	294	vma->vm_page_prot = __pgprot(prot);
1da177e4 LT	295
346d3882 MT	296	if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
	297	vma->vm_end - vma->vm_start,
	298	vma->vm_page_prot))
1da177e4 LT	299	return -EAGAIN;
1da177e4 LT	300
03d72aa1	301	vma->vm_ops = &pci_mmap_ops;
03d72aa1	302
1da177e4 LT	303	return 0;
1da177e4 LT	304	}