[deliverable/linux.git] / arch / x86 / pci / k8-bus_64.c

#include <linux/init.h>
#include <linux/pci.h>
#include <asm/pci-direct.h>
#include <asm/mpspec.h>
#include <linux/cpumask.h>
#include <linux/topology.h>

/*
 * This discovers the pcibus <-> node mapping on AMD K8.
 * also get peer root bus resource for io,mmio
 */


/*
 * sub bus (transparent) will use entres from 3 to store extra from root,
 * so need to make sure have enought slot there, increase PCI_BUS_NUM_RESOURCES?
 */
#define RES_NUM 16
struct pci_root_info {
	char name[12];
	unsigned int res_num;
	struct resource res[RES_NUM];
	int bus_min;
	int bus_max;
	int node;
	int link;
};

/* 4 at this time, it may become to 32 */
#define PCI_ROOT_NR 4
static int pci_root_num;
static struct pci_root_info pci_root_info[PCI_ROOT_NR];

#ifdef CONFIG_NUMA

#define BUS_NR 256

static int mp_bus_to_node[BUS_NR];

void set_mp_bus_to_node(int busnum, int node)
{
	if (busnum >= 0 &&  busnum < BUS_NR)
		mp_bus_to_node[busnum] = node;
}

int get_mp_bus_to_node(int busnum)
{
	int node = -1;

	if (busnum < 0 || busnum > (BUS_NR - 1))
		return node;

	node = mp_bus_to_node[busnum];

	/*
	 * let numa_node_id to decide it later in dma_alloc_pages
	 * if there is no ram on that node
	 */
	if (node != -1 && !node_online(node))
		node = -1;

	return node;
}
#endif

void set_pci_bus_resources_arch_default(struct pci_bus *b)
{
	int i;
	int j;
	struct pci_root_info *info;

	if (!pci_root_num)
		return;

	for (i = 0; i < pci_root_num; i++) {
		if (pci_root_info[i].bus_min == b->number)
			break;
	}

	if (i == pci_root_num)
		return;

	info = &pci_root_info[i];
	for (j = 0; j < info->res_num; j++) {
		struct resource *res;
		struct resource *root;

		res = &info->res[j];
		b->resource[j] = res;
		if (res->flags & IORESOURCE_IO)
			root = &ioport_resource;
		else
			root = &iomem_resource;
		insert_resource(root, res);
	}
}

#define RANGE_NUM 16

struct res_range {
	size_t start;
	size_t end;
};

static void __init update_range(struct res_range *range, size_t start,
				size_t end)
{
	int i;
	int j;

	for (j = 0; j < RANGE_NUM; j++) {
		if (!range[j].end)
			continue;
		if (start == range[j].start && end < range[j].end) {
			range[j].start = end + 1;
			break;
		} else if (start == range[j].start && end == range[j].end) {
			range[j].start = 0;
			range[j].end = 0;
			break;
		} else if (start > range[j].start && end == range[j].end) {
			range[j].end = start - 1;
			break;
		} else if (start > range[j].start && end < range[j].end) {
			/* find the new spare */
			for (i = 0; i < RANGE_NUM; i++) {
				if (range[i].end == 0)
					break;
			}
			if (i < RANGE_NUM) {
				range[i].end = range[j].end;
				range[i].start = end + 1;
			} else {
				printk(KERN_ERR "run of slot in ranges\n");
			}
			range[j].end = start - 1;
			break;
		}
	}
}

static void __init update_res(struct pci_root_info *info, size_t start,
			      size_t end, unsigned long flags, int merge)
{
	int i;
	struct resource *res;

	if (!merge)
		goto addit;

	/* try to merge it with old one */
	for (i = 0; i < info->res_num; i++) {
		res = &info->res[i];
		if (res->flags != flags)
			continue;
		if (res->end + 1 == start) {
			res->end = end;
			return;
		} else if (end + 1 == res->start) {
			res->start = start;
			return;
		}
	}

addit:

	/* need to add that */
	if (info->res_num >= RES_NUM)
		return;

	res = &info->res[info->res_num];
	res->name = info->name;
	res->flags = flags;
	res->start = start;
	res->end = end;
	res->child = NULL;
	info->res_num++;
}

struct pci_hostbridge_probe {
	u32 bus;
	u32 slot;
	u32 vendor;
	u32 device;
};

static struct pci_hostbridge_probe pci_probes[] __initdata = {
	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 },
	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
	{ 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
};

/**
 * early_fill_mp_bus_to_node()
 * called before pcibios_scan_root and pci_scan_bus
 * fills the mp_bus_to_cpumask array based according to the LDT Bus Number
 * Registers found in the K8 northbridge
 */
static int __init early_fill_mp_bus_info(void)
{
	int i;
	int j;
	unsigned bus;
	unsigned slot;
	int found;
	int node;
	int link;
	int def_node;
	int def_link;
	struct pci_root_info *info;
	u32 reg;
	struct resource *res;
	size_t start;
	size_t end;
	struct res_range range[RANGE_NUM];
	u64 val;
	u32 address;

#ifdef CONFIG_NUMA
	for (i = 0; i < BUS_NR; i++)
		mp_bus_to_node[i] = -1;
#endif

	if (!early_pci_allowed())
		return -1;

	found = 0;
	for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
		u32 id;
		u16 device;
		u16 vendor;

		bus = pci_probes[i].bus;
		slot = pci_probes[i].slot;
		id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);

		vendor = id & 0xffff;
		device = (id>>16) & 0xffff;
		if (pci_probes[i].vendor == vendor &&
		    pci_probes[i].device == device) {
			found = 1;
			break;
		}
	}

	if (!found)
		return 0;

	pci_root_num = 0;
	for (i = 0; i < 4; i++) {
		int min_bus;
		int max_bus;
		reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));

		/* Check if that register is enabled for bus range */
		if ((reg & 7) != 3)
			continue;

		min_bus = (reg >> 16) & 0xff;
		max_bus = (reg >> 24) & 0xff;
		node = (reg >> 4) & 0x07;
#ifdef CONFIG_NUMA
		for (j = min_bus; j <= max_bus; j++)
			mp_bus_to_node[j] = (unsigned char) node;
#endif
		link = (reg >> 8) & 0x03;

		info = &pci_root_info[pci_root_num];
		info->bus_min = min_bus;
		info->bus_max = max_bus;
		info->node = node;
		info->link = link;
		sprintf(info->name, "PCI Bus #%02x", min_bus);
		pci_root_num++;
	}

	/* get the default node and link for left over res */
	reg = read_pci_config(bus, slot, 0, 0x60);
	def_node = (reg >> 8) & 0x07;
	reg = read_pci_config(bus, slot, 0, 0x64);
	def_link = (reg >> 8) & 0x03;

	memset(range, 0, sizeof(range));
	range[0].end = 0xffff;
	/* io port resource */
	for (i = 0; i < 4; i++) {
		reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
		if (!(reg & 3))
			continue;

		start = reg & 0xfff000;
		reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
		node = reg & 0x07;
		link = (reg >> 4) & 0x03;
		end = (reg & 0xfff000) | 0xfff;

		/* find the position */
		for (j = 0; j < pci_root_num; j++) {
			info = &pci_root_info[j];
			if (info->node == node && info->link == link)
				break;
		}
		if (j == pci_root_num)
			continue; /* not found */

		info = &pci_root_info[j];
		update_res(info, start, end, IORESOURCE_IO, 0);
		update_range(range, start, end);
	}
	/* add left over io port range to def node/link, [0, 0xffff] */
	/* find the position */
	for (j = 0; j < pci_root_num; j++) {
		info = &pci_root_info[j];
		if (info->node == def_node && info->link == def_link)
			break;
	}
	if (j < pci_root_num) {
		info = &pci_root_info[j];
		for (i = 0; i < RANGE_NUM; i++) {
			if (!range[i].end)
				continue;

			update_res(info, range[i].start, range[i].end,
				   IORESOURCE_IO, 1);
		}
	}

	memset(range, 0, sizeof(range));
	/* 0xfd00000000-0xffffffffff for HT */
	/* 0xfc00000000-0xfcffffffff for Family 10h mmconfig*/
	range[0].end = 0xfbffffffffULL;

	/* need to take out [0, TOM) for RAM*/
	address = MSR_K8_TOP_MEM1;
	rdmsrl(address, val);
	end = (val & 0xffffff8000000ULL);
	printk(KERN_INFO "TOM: %016lx aka %ldM\n", end, end>>20);
	if (end < (1ULL<<32))
		update_range(range, 0, end - 1);

	/* mmio resource */
	for (i = 0; i < 8; i++) {
		reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
		if (!(reg & 3))
			continue;

		start = reg & 0xffffff00; /* 39:16 on 31:8*/
		start <<= 8;
		reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
		node = reg & 0x07;
		link = (reg >> 4) & 0x03;
		end = (reg & 0xffffff00);
		end <<= 8;
		end |= 0xffff;

		/* find the position */
		for (j = 0; j < pci_root_num; j++) {
			info = &pci_root_info[j];
			if (info->node == node && info->link == link)
				break;
		}
		if (j == pci_root_num)
			continue; /* not found */

		info = &pci_root_info[j];
		update_res(info, start, end, IORESOURCE_MEM, 0);
		update_range(range, start, end);
	}

	/* need to take out [4G, TOM2) for RAM*/
	/* SYS_CFG */
	address = MSR_K8_SYSCFG;
	rdmsrl(address, val);
	/* TOP_MEM2 is enabled? */
	if (val & (1<<21)) {
		/* TOP_MEM2 */
		address = MSR_K8_TOP_MEM2;
		rdmsrl(address, val);
		end = (val & 0xffffff8000000ULL);
		printk(KERN_INFO "TOM2: %016lx aka %ldM\n", end, end>>20);
		update_range(range, 1ULL<<32, end - 1);
	}

	/*
	 * add left over mmio range to def node/link ?
	 * that is tricky, just record range in from start_min to 4G
	 */
	for (j = 0; j < pci_root_num; j++) {
		info = &pci_root_info[j];
		if (info->node == def_node && info->link == def_link)
			break;
	}
	if (j < pci_root_num) {
		info = &pci_root_info[j];

		for (i = 0; i < RANGE_NUM; i++) {
			if (!range[i].end)
				continue;

			update_res(info, range[i].start, range[i].end,
				   IORESOURCE_MEM, 1);
		}
	}

#ifdef CONFIG_NUMA
	for (i = 0; i < BUS_NR; i++) {
		node = mp_bus_to_node[i];
		if (node >= 0)
			printk(KERN_DEBUG "bus: %02x to node: %02x\n", i, node);
	}
#endif

	for (i = 0; i < pci_root_num; i++) {
		int res_num;
		int busnum;

		info = &pci_root_info[i];
		res_num = info->res_num;
		busnum = info->bus_min;
		printk(KERN_DEBUG "bus: [%02x,%02x] on node %x link %x\n",
		       info->bus_min, info->bus_max, info->node, info->link);
		for (j = 0; j < res_num; j++) {
			res = &info->res[j];
			printk(KERN_DEBUG "bus: %02x index %x %s: [%llx, %llx]\n",
			       busnum, j,
			       (res->flags & IORESOURCE_IO)?"io port":"mmio",
			       res->start, res->end);
		}
	}

	return 0;
}

postcore_initcall(early_fill_mp_bus_info);
Commit	Line	Data
1da177e4 LT	1	#include <linux/init.h>
1da177e4 LT	2	#include <linux/pci.h>
871d5f8d	3	#include <asm/pci-direct.h>
1da177e4 LT	4	#include <asm/mpspec.h>
1da177e4 LT	5	#include <linux/cpumask.h>
871d5f8d	6	#include <linux/topology.h>
1da177e4 LT	7
	8	/*
	9	* This discovers the pcibus <-> node mapping on AMD K8.
30a18d6c	10	* also get peer root bus resource for io,mmio
1da177e4 LT	11	*/
1da177e4 LT	12
35ddd068	13
30a18d6c YL	14	/*
	15	* sub bus (transparent) will use entres from 3 to store extra from root,
	16	* so need to make sure have enought slot there, increase PCI_BUS_NUM_RESOURCES?
	17	*/
	18	#define RES_NUM 16
	19	struct pci_root_info {
	20	char name[12];
	21	unsigned int res_num;
	22	struct resource res[RES_NUM];
	23	int bus_min;
	24	int bus_max;
	25	int node;
	26	int link;
	27	};
	28
	29	/* 4 at this time, it may become to 32 */
	30	#define PCI_ROOT_NR 4
	31	static int pci_root_num;
	32	static struct pci_root_info pci_root_info[PCI_ROOT_NR];
1da177e4	33
871d5f8d YL	34	#ifdef CONFIG_NUMA
	35
	36	#define BUS_NR 256
	37
	38	static int mp_bus_to_node[BUS_NR];
	39
	40	void set_mp_bus_to_node(int busnum, int node)
	41	{
	42	if (busnum >= 0 && busnum < BUS_NR)
	43	mp_bus_to_node[busnum] = node;
	44	}
	45
	46	int get_mp_bus_to_node(int busnum)
	47	{
	48	int node = -1;
	49
	50	if (busnum < 0 \|\| busnum > (BUS_NR - 1))
	51	return node;
	52
	53	node = mp_bus_to_node[busnum];
	54
	55	/*
	56	* let numa_node_id to decide it later in dma_alloc_pages
	57	* if there is no ram on that node
	58	*/
	59	if (node != -1 && !node_online(node))
	60	node = -1;
	61
	62	return node;
	63	}
871d5f8d YL	64	#endif
871d5f8d YL	65
30a18d6c YL	66	void set_pci_bus_resources_arch_default(struct pci_bus *b)
	67	{
	68	int i;
	69	int j;
	70	struct pci_root_info *info;
	71
	72	if (!pci_root_num)
	73	return;
	74
	75	for (i = 0; i < pci_root_num; i++) {
	76	if (pci_root_info[i].bus_min == b->number)
	77	break;
	78	}
	79
	80	if (i == pci_root_num)
	81	return;
	82
	83	info = &pci_root_info[i];
	84	for (j = 0; j < info->res_num; j++) {
	85	struct resource *res;
	86	struct resource *root;
	87
	88	res = &info->res[j];
	89	b->resource[j] = res;
	90	if (res->flags & IORESOURCE_IO)
	91	root = &ioport_resource;
	92	else
	93	root = &iomem_resource;
	94	insert_resource(root, res);
	95	}
	96	}
	97
	98	#define RANGE_NUM 16
	99
	100	struct res_range {
	101	size_t start;
	102	size_t end;
	103	};
	104
	105	static void __init update_range(struct res_range *range, size_t start,
	106	size_t end)
	107	{
	108	int i;
	109	int j;
	110
	111	for (j = 0; j < RANGE_NUM; j++) {
	112	if (!range[j].end)
	113	continue;
	114	if (start == range[j].start && end < range[j].end) {
	115	range[j].start = end + 1;
	116	break;
	117	} else if (start == range[j].start && end == range[j].end) {
	118	range[j].start = 0;
	119	range[j].end = 0;
	120	break;
	121	} else if (start > range[j].start && end == range[j].end) {
	122	range[j].end = start - 1;
	123	break;
	124	} else if (start > range[j].start && end < range[j].end) {
	125	/* find the new spare */
	126	for (i = 0; i < RANGE_NUM; i++) {
	127	if (range[i].end == 0)
	128	break;
	129	}
130	if (i < RANGE_NUM) {
131	range[i].end = range[j].end;
132	range[i].start = end + 1;
133	} else {
134	printk(KERN_ERR "run of slot in ranges\n");
135	}
136	range[j].end = start - 1;
137	break;
138	}
139	}
140	}
141
142	static void __init update_res(struct pci_root_info *info, size_t start,
143	size_t end, unsigned long flags, int merge)
144	{
145	int i;
146	struct resource *res;
147
148	if (!merge)
149	goto addit;
150
151	/* try to merge it with old one */
152	for (i = 0; i < info->res_num; i++) {
153	res = &info->res[i];
154	if (res->flags != flags)
155	continue;
156	if (res->end + 1 == start) {
157	res->end = end;
158	return;
159	} else if (end + 1 == res->start) {
160	res->start = start;
161	return;
162	}
163	}
164
165	addit:
166
167	/* need to add that */
168	if (info->res_num >= RES_NUM)
169	return;
170
171	res = &info->res[info->res_num];
172	res->name = info->name;
173	res->flags = flags;
174	res->start = start;
175	res->end = end;
176	res->child = NULL;
177	info->res_num++;
178	}
179
180	struct pci_hostbridge_probe {
181	u32 bus;
182	u32 slot;
183	u32 vendor;
184	u32 device;
185	};
186
187	static struct pci_hostbridge_probe pci_probes[] __initdata = {
188	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 },
189	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
190	{ 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
191	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
192	};
193
1da177e4	194	/**
871d5f8d YL	195	* early_fill_mp_bus_to_node()
871d5f8d YL	196	* called before pcibios_scan_root and pci_scan_bus
1da177e4 LT	197	* fills the mp_bus_to_cpumask array based according to the LDT Bus Number
	198	* Registers found in the K8 northbridge
	199	*/
30a18d6c	200	static int __init early_fill_mp_bus_info(void)
1da177e4	201	{
30a18d6c YL	202	int i;
	203	int j;
	204	unsigned bus;
871d5f8d	205	unsigned slot;
30a18d6c	206	int found;
35ddd068	207	int node;
30a18d6c YL	208	int link;
	209	int def_node;
	210	int def_link;
	211	struct pci_root_info *info;
	212	u32 reg;
	213	struct resource *res;
	214	size_t start;
	215	size_t end;
	216	struct res_range range[RANGE_NUM];
	217	u64 val;
	218	u32 address;
1da177e4	219
30a18d6c	220	#ifdef CONFIG_NUMA
871d5f8d YL	221	for (i = 0; i < BUS_NR; i++)
871d5f8d YL	222	mp_bus_to_node[i] = -1;
30a18d6c	223	#endif
871d5f8d YL	224
	225	if (!early_pci_allowed())
	226	return -1;
	227
30a18d6c YL	228	found = 0;
	229	for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
	230	u32 id;
	231	u16 device;
	232	u16 vendor;
35ddd068	233
30a18d6c YL	234	bus = pci_probes[i].bus;
	235	slot = pci_probes[i].slot;
	236	id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
35ddd068	237
30a18d6c YL	238	vendor = id & 0xffff;
	239	device = (id>>16) & 0xffff;
	240	if (pci_probes[i].vendor == vendor &&
	241	pci_probes[i].device == device) {
	242	found = 1;
	243	break;
	244	}
	245	}
	246
	247	if (!found)
	248	return 0;
35ddd068	249
30a18d6c YL	250	pci_root_num = 0;
	251	for (i = 0; i < 4; i++) {
	252	int min_bus;
	253	int max_bus;
	254	reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));
35ddd068 YL	255
35ddd068 YL	256	/* Check if that register is enabled for bus range */
30a18d6c	257	if ((reg & 7) != 3)
35ddd068 YL	258	continue;
35ddd068 YL	259
30a18d6c YL	260	min_bus = (reg >> 16) & 0xff;
	261	max_bus = (reg >> 24) & 0xff;
	262	node = (reg >> 4) & 0x07;
	263	#ifdef CONFIG_NUMA
35ddd068 YL	264	for (j = min_bus; j <= max_bus; j++)
35ddd068 YL	265	mp_bus_to_node[j] = (unsigned char) node;
30a18d6c YL	266	#endif
	267	link = (reg >> 8) & 0x03;
	268
	269	info = &pci_root_info[pci_root_num];
	270	info->bus_min = min_bus;
	271	info->bus_max = max_bus;
	272	info->node = node;
	273	info->link = link;
	274	sprintf(info->name, "PCI Bus #%02x", min_bus);
	275	pci_root_num++;
1da177e4 LT	276	}
1da177e4 LT	277
30a18d6c YL	278	/* get the default node and link for left over res */
	279	reg = read_pci_config(bus, slot, 0, 0x60);
	280	def_node = (reg >> 8) & 0x07;
	281	reg = read_pci_config(bus, slot, 0, 0x64);
	282	def_link = (reg >> 8) & 0x03;
	283
	284	memset(range, 0, sizeof(range));
	285	range[0].end = 0xffff;
	286	/* io port resource */
	287	for (i = 0; i < 4; i++) {
	288	reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
	289	if (!(reg & 3))
	290	continue;
	291
	292	start = reg & 0xfff000;
	293	reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
	294	node = reg & 0x07;
	295	link = (reg >> 4) & 0x03;
	296	end = (reg & 0xfff000) \| 0xfff;
	297
	298	/* find the position */
	299	for (j = 0; j < pci_root_num; j++) {
	300	info = &pci_root_info[j];
	301	if (info->node == node && info->link == link)
	302	break;
	303	}
	304	if (j == pci_root_num)
	305	continue; /* not found */
	306
	307	info = &pci_root_info[j];
	308	update_res(info, start, end, IORESOURCE_IO, 0);
	309	update_range(range, start, end);
	310	}
	311	/* add left over io port range to def node/link, [0, 0xffff] */
	312	/* find the position */
	313	for (j = 0; j < pci_root_num; j++) {
	314	info = &pci_root_info[j];
	315	if (info->node == def_node && info->link == def_link)
	316	break;
	317	}
	318	if (j < pci_root_num) {
	319	info = &pci_root_info[j];
	320	for (i = 0; i < RANGE_NUM; i++) {
	321	if (!range[i].end)
	322	continue;
	323
	324	update_res(info, range[i].start, range[i].end,
	325	IORESOURCE_IO, 1);
	326	}
	327	}
	328
	329	memset(range, 0, sizeof(range));
	330	/* 0xfd00000000-0xffffffffff for HT */
	331	/* 0xfc00000000-0xfcffffffff for Family 10h mmconfig*/
	332	range[0].end = 0xfbffffffffULL;
	333
	334	/* need to take out [0, TOM) for RAM*/
	335	address = MSR_K8_TOP_MEM1;
	336	rdmsrl(address, val);
	337	end = (val & 0xffffff8000000ULL);
	338	printk(KERN_INFO "TOM: %016lx aka %ldM\n", end, end>>20);
	339	if (end < (1ULL<<32))
	340	update_range(range, 0, end - 1);
	341
342	/* mmio resource */
343	for (i = 0; i < 8; i++) {
344	reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
345	if (!(reg & 3))
346	continue;
347
348	start = reg & 0xffffff00; /* 39:16 on 31:8*/
349	start <<= 8;
350	reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
351	node = reg & 0x07;
352	link = (reg >> 4) & 0x03;
353	end = (reg & 0xffffff00);
354	end <<= 8;
355	end \|= 0xffff;
356
357	/* find the position */
358	for (j = 0; j < pci_root_num; j++) {
359	info = &pci_root_info[j];
360	if (info->node == node && info->link == link)
361	break;
362	}
363	if (j == pci_root_num)
364	continue; /* not found */
365
366	info = &pci_root_info[j];
367	update_res(info, start, end, IORESOURCE_MEM, 0);
368	update_range(range, start, end);
369	}
370
371	/* need to take out [4G, TOM2) for RAM*/
372	/* SYS_CFG */
373	address = MSR_K8_SYSCFG;
374	rdmsrl(address, val);
375	/* TOP_MEM2 is enabled? */
376	if (val & (1<<21)) {
377	/* TOP_MEM2 */
378	address = MSR_K8_TOP_MEM2;
379	rdmsrl(address, val);
380	end = (val & 0xffffff8000000ULL);
381	printk(KERN_INFO "TOM2: %016lx aka %ldM\n", end, end>>20);
382	update_range(range, 1ULL<<32, end - 1);
383	}
384
385	/*
386	* add left over mmio range to def node/link ?
387	* that is tricky, just record range in from start_min to 4G
388	*/
389	for (j = 0; j < pci_root_num; j++) {
390	info = &pci_root_info[j];
391	if (info->node == def_node && info->link == def_link)
392	break;
393	}
394	if (j < pci_root_num) {
395	info = &pci_root_info[j];
396
397	for (i = 0; i < RANGE_NUM; i++) {
398	if (!range[i].end)
399	continue;
400
401	update_res(info, range[i].start, range[i].end,
402	IORESOURCE_MEM, 1);
403	}
404	}
405
406	#ifdef CONFIG_NUMA
871d5f8d	407	for (i = 0; i < BUS_NR; i++) {
35ddd068	408	node = mp_bus_to_node[i];
871d5f8d YL	409	if (node >= 0)
	410	printk(KERN_DEBUG "bus: %02x to node: %02x\n", i, node);
	411	}
	412	#endif
30a18d6c YL	413
	414	for (i = 0; i < pci_root_num; i++) {
	415	int res_num;
	416	int busnum;
	417
	418	info = &pci_root_info[i];
	419	res_num = info->res_num;
	420	busnum = info->bus_min;
	421	printk(KERN_DEBUG "bus: [%02x,%02x] on node %x link %x\n",
	422	info->bus_min, info->bus_max, info->node, info->link);
	423	for (j = 0; j < res_num; j++) {
	424	res = &info->res[j];
	425	printk(KERN_DEBUG "bus: %02x index %x %s: [%llx, %llx]\n",
	426	busnum, j,
	427	(res->flags & IORESOURCE_IO)?"io port":"mmio",
	428	res->start, res->end);
	429	}
	430	}
	431
1da177e4 LT	432	return 0;
	433	}
	434
30a18d6c	435	postcore_initcall(early_fill_mp_bus_info);