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Merge tag 'iio-for-4.8a' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio...
[deliverable/linux.git] / arch / x86 / pci / mmconfig-shared.c
CommitLineData
b7867394
OG		 1/*
2 * mmconfig-shared.c - Low-level direct PCI config space access via
3 * MMCONFIG - common code between i386 and x86-64.
4 *
5 * This code does:
9358c693 6 * - known chipset handling
b7867394
OG		 7 * - ACPI decoding and validation
8 *
9 * Per-architecture code takes care of the mappings and accesses
10 * themselves.
11 */
12
13#include <linux/pci.h>
14#include <linux/init.h>
5f0db7a2 15#include <linux/sfi_acpi.h>
b7867394 16#include <linux/bitmap.h>
9a08f7d3 17#include <linux/dmi.h>
5a0e3ad6 18#include <linux/slab.h>
376f70ac
JL		 19#include <linux/mutex.h>
20#include <linux/rculist.h>
b7867394 21#include <asm/e820.h>
82487711 22#include <asm/pci_x86.h>
5f0db7a2 23#include <asm/acpi.h>
b7867394 24
f4a2d584 25#define PREFIX "PCI: "
a192a958 26
a5ba7971 27/* Indicate if the mmcfg resources have been placed into the resource table. */
95c5e92f 28static bool pci_mmcfg_running_state;
9c95111b 29static bool pci_mmcfg_arch_init_failed;
376f70ac 30static DEFINE_MUTEX(pci_mmcfg_lock);
a5ba7971 31
ff097ddd
BH		 32LIST_HEAD(pci_mmcfg_list);
33
64474b52 34static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg)
ba2afbab
BH		 35{
36 if (cfg->res.parent)
37 release_resource(&cfg->res);
38 list_del(&cfg->list);
39 kfree(cfg);
40}
41
64474b52 42static void __init free_all_mmcfg(void)
7da7d360 43{
ff097ddd 44 struct pci_mmcfg_region *cfg, *tmp;
56ddf4d3 45
7da7d360 46 pci_mmcfg_arch_free();
ba2afbab
BH		 47 list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list)
48 pci_mmconfig_remove(cfg);
ff097ddd
BH		 49}
50
a18e3690 51static void list_add_sorted(struct pci_mmcfg_region *new)
ff097ddd
BH		 52{
53 struct pci_mmcfg_region *cfg;
54
55 /* keep list sorted by segment and starting bus number */
376f70ac 56 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list) {
ff097ddd
BH		 57 if (cfg->segment > new->segment ||
58 (cfg->segment == new->segment &&
59 cfg->start_bus >= new->start_bus)) {
376f70ac 60 list_add_tail_rcu(&new->list, &cfg->list);
ff097ddd
BH		 61 return;
62 }
63 }
376f70ac 64 list_add_tail_rcu(&new->list, &pci_mmcfg_list);
7da7d360
BH		 65}
66
a18e3690
GKH		 67static struct pci_mmcfg_region *pci_mmconfig_alloc(int segment, int start,
68 int end, u64 addr)
068258bc 69{
d215a9c8 70 struct pci_mmcfg_region *new;
56ddf4d3 71 struct resource *res;
068258bc 72
f7ca6984
BH		 73 if (addr == 0)
74 return NULL;
75
ff097ddd 76 new = kzalloc(sizeof(*new), GFP_KERNEL);
068258bc 77 if (!new)
7da7d360 78 return NULL;
068258bc 79
95cf1cf0
BH		 80 new->address = addr;
81 new->segment = segment;
82 new->start_bus = start;
83 new->end_bus = end;
7da7d360 84
56ddf4d3
BH		 85 res = &new->res;
86 res->start = addr + PCI_MMCFG_BUS_OFFSET(start);
1ca98fa6 87 res->end = addr + PCI_MMCFG_BUS_OFFSET(end + 1) - 1;
56ddf4d3
BH		 88 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
89 snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN,
90 "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end);
91 res->name = new->name;
92
ff097ddd 93 return new;
068258bc
YL		 94}
95
64474b52 96static struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start,
846e4023
JL		 97 int end, u64 addr)
98{
99 struct pci_mmcfg_region *new;
100
101 new = pci_mmconfig_alloc(segment, start, end, addr);
376f70ac
JL		 102 if (new) {
103 mutex_lock(&pci_mmcfg_lock);
846e4023 104 list_add_sorted(new);
376f70ac 105 mutex_unlock(&pci_mmcfg_lock);
9c95111b 106
24c97f04 107 pr_info(PREFIX
9c95111b
JL		 108 "MMCONFIG for domain %04x [bus %02x-%02x] at %pR "
109 "(base %#lx)\n",
110 segment, start, end, &new->res, (unsigned long)addr);
376f70ac 111 }
846e4023
JL		 112
113 return new;
114}
115
f6e1d8cc
BH		 116struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus)
117{
118 struct pci_mmcfg_region *cfg;
119
376f70ac 120 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
f6e1d8cc
BH		 121 if (cfg->segment == segment &&
122 cfg->start_bus <= bus && bus <= cfg->end_bus)
123 return cfg;
124
125 return NULL;
126}
127
64474b52 128static const char *__init pci_mmcfg_e7520(void)
9358c693
OG		 129{
130 u32 win;
bb63b421 131 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
9358c693 132
b5229dbb 133 win = win & 0xf000;
068258bc
YL		 134 if (win == 0x0000 || win == 0xf000)
135 return NULL;
136
7da7d360 137 if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL)
068258bc
YL		 138 return NULL;
139
9358c693
OG		 140 return "Intel Corporation E7520 Memory Controller Hub";
141}
142
64474b52 143static const char *__init pci_mmcfg_intel_945(void)
9358c693
OG		 144{
145 u32 pciexbar, mask = 0, len = 0;
146
bb63b421 147 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
9358c693
OG		 148
149 /* Enable bit */
150 if (!(pciexbar & 1))
068258bc 151 return NULL;
9358c693
OG		 152
153 /* Size bits */
154 switch ((pciexbar >> 1) & 3) {
155 case 0:
156 mask = 0xf0000000U;
157 len = 0x10000000U;
158 break;
159 case 1:
160 mask = 0xf8000000U;
161 len = 0x08000000U;
162 break;
163 case 2:
164 mask = 0xfc000000U;
165 len = 0x04000000U;
166 break;
167 default:
068258bc 168 return NULL;
9358c693
OG		 169 }
170
171 /* Errata #2, things break when not aligned on a 256Mb boundary */
172 /* Can only happen in 64M/128M mode */
173
174 if ((pciexbar & mask) & 0x0fffffffU)
068258bc 175 return NULL;
9358c693 176
b5229dbb
OG		 177 /* Don't hit the APIC registers and their friends */
178 if ((pciexbar & mask) >= 0xf0000000U)
068258bc
YL		 179 return NULL;
180
7da7d360 181 if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL)
068258bc
YL		 182 return NULL;
183
9358c693
OG		 184 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
185}
186
64474b52 187static const char *__init pci_mmcfg_amd_fam10h(void)
7fd0da40
YL		 188{
189 u32 low, high, address;
190 u64 base, msr;
191 int i;
7da7d360 192 unsigned segnbits = 0, busnbits, end_bus;
7fd0da40 193
5f0b2976
YL		 194 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
195 return NULL;
196
7fd0da40
YL		 197 address = MSR_FAM10H_MMIO_CONF_BASE;
198 if (rdmsr_safe(address, &low, &high))
199 return NULL;
200
201 msr = high;
202 msr <<= 32;
203 msr |= low;
204
205 /* mmconfig is not enable */
206 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
207 return NULL;
208
209 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
210
211 busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
212 FAM10H_MMIO_CONF_BUSRANGE_MASK;
213
214 /*
215 * only handle bus 0 ?
216 * need to skip it
217 */
218 if (!busnbits)
219 return NULL;
220
221 if (busnbits > 8) {
222 segnbits = busnbits - 8;
223 busnbits = 8;
224 }
225
7da7d360 226 end_bus = (1 << busnbits) - 1;
068258bc 227 for (i = 0; i < (1 << segnbits); i++)
7da7d360
BH		 228 if (pci_mmconfig_add(i, 0, end_bus,
229 base + (1<<28) * i) == NULL) {
230 free_all_mmcfg();
231 return NULL;
232 }
7fd0da40
YL		 233
234 return "AMD Family 10h NB";
235}
236
5546d6f5 237static bool __initdata mcp55_checked;
64474b52 238static const char *__init pci_mmcfg_nvidia_mcp55(void)
5546d6f5
ES		 239{
240 int bus;
241 int mcp55_mmconf_found = 0;
242
776f7ad6
MK		 243 static const u32 extcfg_regnum __initconst = 0x90;
244 static const u32 extcfg_regsize __initconst = 4;
245 static const u32 extcfg_enable_mask __initconst = 1 << 31;
246 static const u32 extcfg_start_mask __initconst = 0xff << 16;
247 static const int extcfg_start_shift __initconst = 16;
248 static const u32 extcfg_size_mask __initconst = 0x3 << 28;
249 static const int extcfg_size_shift __initconst = 28;
250 static const int extcfg_sizebus[] __initconst = {
251 0x100, 0x80, 0x40, 0x20
252 };
253 static const u32 extcfg_base_mask[] __initconst = {
254 0x7ff8, 0x7ffc, 0x7ffe, 0x7fff
255 };
256 static const int extcfg_base_lshift __initconst = 25;
5546d6f5
ES		 257
258 /*
259 * do check if amd fam10h already took over
260 */
ff097ddd 261 if (!acpi_disabled || !list_empty(&pci_mmcfg_list) || mcp55_checked)
5546d6f5
ES		 262 return NULL;
263
264 mcp55_checked = true;
265 for (bus = 0; bus < 256; bus++) {
266 u64 base;
267 u32 l, extcfg;
268 u16 vendor, device;
269 int start, size_index, end;
270
271 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
272 vendor = l & 0xffff;
273 device = (l >> 16) & 0xffff;
274
275 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
276 continue;
277
278 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
279 extcfg_regsize, &extcfg);
280
281 if (!(extcfg & extcfg_enable_mask))
282 continue;
283
5546d6f5
ES		 284 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
285 base = extcfg & extcfg_base_mask[size_index];
286 /* base could > 4G */
287 base <<= extcfg_base_lshift;
288 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
289 end = start + extcfg_sizebus[size_index] - 1;
7da7d360
BH		 290 if (pci_mmconfig_add(0, start, end, base) == NULL)
291 continue;
5546d6f5
ES		 292 mcp55_mmconf_found++;
293 }
294
295 if (!mcp55_mmconf_found)
296 return NULL;
297
298 return "nVidia MCP55";
299}
300
9358c693 301struct pci_mmcfg_hostbridge_probe {
7fd0da40
YL		 302 u32 bus;
303 u32 devfn;
9358c693
OG		 304 u32 vendor;
305 u32 device;
306 const char *(*probe)(void);
307};
308
6af13bac 309static const struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initconst = {
7fd0da40
YL		 310 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
311 PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
312 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
313 PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
314 { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
315 0x1200, pci_mmcfg_amd_fam10h },
316 { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
317 0x1200, pci_mmcfg_amd_fam10h },
5546d6f5
ES		 318 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
319 0x0369, pci_mmcfg_nvidia_mcp55 },
9358c693
OG		 320};
321
068258bc
YL		 322static void __init pci_mmcfg_check_end_bus_number(void)
323{
987c367b 324 struct pci_mmcfg_region *cfg, *cfgx;
068258bc 325
bb8d4133 326 /* Fixup overlaps */
ff097ddd 327 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
d7e6b66f
BH		 328 if (cfg->end_bus < cfg->start_bus)
329 cfg->end_bus = 255;
068258bc 330
bb8d4133
TG		 331 /* Don't access the list head ! */
332 if (cfg->list.next == &pci_mmcfg_list)
333 break;
334
ff097ddd 335 cfgx = list_entry(cfg->list.next, typeof(*cfg), list);
bb8d4133 336 if (cfg->end_bus >= cfgx->start_bus)
d7e6b66f 337 cfg->end_bus = cfgx->start_bus - 1;
068258bc
YL		 338 }
339}
340
9358c693
OG		 341static int __init pci_mmcfg_check_hostbridge(void)
342{
343 u32 l;
7fd0da40 344 u32 bus, devfn;
9358c693
OG		 345 u16 vendor, device;
346 int i;
347 const char *name;
348
bb63b421
YL		 349 if (!raw_pci_ops)
350 return 0;
351
7da7d360 352 free_all_mmcfg();
9358c693 353
068258bc 354 for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
7fd0da40
YL		 355 bus = pci_mmcfg_probes[i].bus;
356 devfn = pci_mmcfg_probes[i].devfn;
bb63b421 357 raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
7fd0da40
YL		 358 vendor = l & 0xffff;
359 device = (l >> 16) & 0xffff;
360
068258bc 361 name = NULL;
429d512e
OH		 362 if (pci_mmcfg_probes[i].vendor == vendor &&
363 pci_mmcfg_probes[i].device == device)
9358c693
OG		 364 name = pci_mmcfg_probes[i].probe();
365
068258bc 366 if (name)
24c97f04 367 pr_info(PREFIX "%s with MMCONFIG support\n", name);
9358c693
OG		 368 }
369
068258bc
YL		 370 /* some end_bus_number is crazy, fix it */
371 pci_mmcfg_check_end_bus_number();
372
ff097ddd 373 return !list_empty(&pci_mmcfg_list);
9358c693
OG		 374}
375
a18e3690 376static acpi_status check_mcfg_resource(struct acpi_resource *res, void *data)
7752d5cf
RH		 377{
378 struct resource *mcfg_res = data;
379 struct acpi_resource_address64 address;
380 acpi_status status;
381
382 if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
383 struct acpi_resource_fixed_memory32 *fixmem32 =
384 &res->data.fixed_memory32;
385 if (!fixmem32)
386 return AE_OK;
387 if ((mcfg_res->start >= fixmem32->address) &&
75e613cd 388 (mcfg_res->end < (fixmem32->address +
7752d5cf
RH		 389 fixmem32->address_length))) {
390 mcfg_res->flags = 1;
391 return AE_CTRL_TERMINATE;
392 }
393 }
394 if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
395 (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
396 return AE_OK;
397
398 status = acpi_resource_to_address64(res, &address);
399 if (ACPI_FAILURE(status) ||
a45de93e 400 (address.address.address_length <= 0) ||
7752d5cf
RH		 401 (address.resource_type != ACPI_MEMORY_RANGE))
402 return AE_OK;
403
a45de93e
LZ		 404 if ((mcfg_res->start >= address.address.minimum) &&
405 (mcfg_res->end < (address.address.minimum + address.address.address_length))) {
7752d5cf
RH		 406 mcfg_res->flags = 1;
407 return AE_CTRL_TERMINATE;
408 }
409 return AE_OK;
410}
411
a18e3690
GKH		 412static acpi_status find_mboard_resource(acpi_handle handle, u32 lvl,
413 void *context, void **rv)
7752d5cf
RH		 414{
415 struct resource *mcfg_res = context;
416
417 acpi_walk_resources(handle, METHOD_NAME__CRS,
418 check_mcfg_resource, context);
419
420 if (mcfg_res->flags)
421 return AE_CTRL_TERMINATE;
422
423 return AE_OK;
424}
425
a18e3690 426static int is_acpi_reserved(u64 start, u64 end, unsigned not_used)
7752d5cf
RH		 427{
428 struct resource mcfg_res;
429
430 mcfg_res.start = start;
75e613cd 431 mcfg_res.end = end - 1;
7752d5cf
RH		 432 mcfg_res.flags = 0;
433
434 acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
435
436 if (!mcfg_res.flags)
437 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
438 NULL);
439
440 return mcfg_res.flags;
441}
442
a83fe32f
YL		 443typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
444
95c5e92f
JL		 445static int __ref is_mmconf_reserved(check_reserved_t is_reserved,
446 struct pci_mmcfg_region *cfg,
447 struct device *dev, int with_e820)
a83fe32f 448{
2f2a8b9c
BH		 449 u64 addr = cfg->res.start;
450 u64 size = resource_size(&cfg->res);
a83fe32f 451 u64 old_size = size;
95c5e92f
JL		 452 int num_buses;
453 char *method = with_e820 ? "E820" : "ACPI motherboard resources";
a83fe32f 454
044cd809 455 while (!is_reserved(addr, addr + size, E820_RESERVED)) {
a83fe32f
YL		 456 size >>= 1;
457 if (size < (16UL<<20))
458 break;
459 }
460
95c5e92f
JL		 461 if (size < (16UL<<20) && size != old_size)
462 return 0;
463
464 if (dev)
465 dev_info(dev, "MMCONFIG at %pR reserved in %s\n",
466 &cfg->res, method);
467 else
24c97f04 468 pr_info(PREFIX "MMCONFIG at %pR reserved in %s\n",
95c5e92f
JL		 469 &cfg->res, method);
470
471 if (old_size != size) {
472 /* update end_bus */
473 cfg->end_bus = cfg->start_bus + ((size>>20) - 1);
474 num_buses = cfg->end_bus - cfg->start_bus + 1;
475 cfg->res.end = cfg->res.start +
476 PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
477 snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN,
478 "PCI MMCONFIG %04x [bus %02x-%02x]",
479 cfg->segment, cfg->start_bus, cfg->end_bus);
480
481 if (dev)
482 dev_info(dev,
483 "MMCONFIG "
484 "at %pR (base %#lx) (size reduced!)\n",
485 &cfg->res, (unsigned long) cfg->address);
486 else
24c97f04 487 pr_info(PREFIX
95c5e92f
JL		 488 "MMCONFIG for %04x [bus%02x-%02x] "
489 "at %pR (base %#lx) (size reduced!)\n",
490 cfg->segment, cfg->start_bus, cfg->end_bus,
491 &cfg->res, (unsigned long) cfg->address);
a83fe32f
YL		 492 }
493
95c5e92f 494 return 1;
a83fe32f
YL		 495}
496
95c5e92f
JL		 497static int __ref pci_mmcfg_check_reserved(struct device *dev,
498 struct pci_mmcfg_region *cfg, int early)
2a76c450
JL		 499{
500 if (!early && !acpi_disabled) {
95c5e92f 501 if (is_mmconf_reserved(is_acpi_reserved, cfg, dev, 0))
2a76c450 502 return 1;
95c5e92f
JL		 503
504 if (dev)
505 dev_info(dev, FW_INFO
506 "MMCONFIG at %pR not reserved in "
507 "ACPI motherboard resources\n",
508 &cfg->res);
2a76c450 509 else
24c97f04 510 pr_info(FW_INFO PREFIX
2a76c450
JL		 511 "MMCONFIG at %pR not reserved in "
512 "ACPI motherboard resources\n",
513 &cfg->res);
514 }
515
95c5e92f
JL		 516 /*
517 * e820_all_mapped() is marked as __init.
518 * All entries from ACPI MCFG table have been checked at boot time.
519 * For MCFG information constructed from hotpluggable host bridge's
520 * _CBA method, just assume it's reserved.
521 */
522 if (pci_mmcfg_running_state)
523 return 1;
524
2a76c450
JL		 525 /* Don't try to do this check unless configuration
526 type 1 is available. how about type 2 ?*/
527 if (raw_pci_ops)
95c5e92f 528 return is_mmconf_reserved(e820_all_mapped, cfg, dev, 1);
2a76c450
JL		 529
530 return 0;
531}
532
bb63b421 533static void __init pci_mmcfg_reject_broken(int early)
44de0203 534{
987c367b 535 struct pci_mmcfg_region *cfg;
26054ed0 536
ff097ddd 537 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
95c5e92f 538 if (pci_mmcfg_check_reserved(NULL, cfg, early) == 0) {
24c97f04 539 pr_info(PREFIX "not using MMCONFIG\n");
2a76c450
JL		 540 free_all_mmcfg();
541 return;
a02ce953 542 }
44de0203
OH		 543 }
544}
545
9a08f7d3
BH		 546static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
547 struct acpi_mcfg_allocation *cfg)
c4bf2f37 548{
9a08f7d3
BH		 549 int year;
550
551 if (cfg->address < 0xFFFFFFFF)
552 return 0;
553
526018bc 554 if (!strncmp(mcfg->header.oem_id, "SGI", 3))
9a08f7d3 555 return 0;
c4bf2f37 556
9a08f7d3
BH		 557 if (mcfg->header.revision >= 1) {
558 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
559 year >= 2010)
560 return 0;
561 }
562
24c97f04 563 pr_err(PREFIX "MCFG region for %04x [bus %02x-%02x] at %#llx "
9a08f7d3
BH		 564 "is above 4GB, ignored\n", cfg->pci_segment,
565 cfg->start_bus_number, cfg->end_bus_number, cfg->address);
566 return -EINVAL;
c4bf2f37
LB		 567}
568
569static int __init pci_parse_mcfg(struct acpi_table_header *header)
570{
571 struct acpi_table_mcfg *mcfg;
d3578ef7 572 struct acpi_mcfg_allocation *cfg_table, *cfg;
c4bf2f37 573 unsigned long i;
7da7d360 574 int entries;
c4bf2f37
LB		 575
576 if (!header)
577 return -EINVAL;
578
579 mcfg = (struct acpi_table_mcfg *)header;
580
581 /* how many config structures do we have */
7da7d360 582 free_all_mmcfg();
e823d6ff 583 entries = 0;
c4bf2f37
LB		 584 i = header->length - sizeof(struct acpi_table_mcfg);
585 while (i >= sizeof(struct acpi_mcfg_allocation)) {
e823d6ff 586 entries++;
c4bf2f37 587 i -= sizeof(struct acpi_mcfg_allocation);
4b8073e4 588 }
e823d6ff 589 if (entries == 0) {
24c97f04 590 pr_err(PREFIX "MMCONFIG has no entries\n");
c4bf2f37
LB		 591 return -ENODEV;
592 }
593
d3578ef7 594 cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1];
e823d6ff 595 for (i = 0; i < entries; i++) {
d3578ef7
BH		 596 cfg = &cfg_table[i];
597 if (acpi_mcfg_check_entry(mcfg, cfg)) {
7da7d360 598 free_all_mmcfg();
c4bf2f37
LB		 599 return -ENODEV;
600 }
7da7d360
BH		 601
602 if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number,
603 cfg->end_bus_number, cfg->address) == NULL) {
24c97f04 604 pr_warn(PREFIX "no memory for MCFG entries\n");
7da7d360
BH		 605 free_all_mmcfg();
606 return -ENOMEM;
607 }
c4bf2f37
LB		 608 }
609
610 return 0;
611}
612
d91525eb
CG		 613#ifdef CONFIG_ACPI_APEI
614extern int (*arch_apei_filter_addr)(int (*func)(__u64 start, __u64 size,
615 void *data), void *data);
616
617static int pci_mmcfg_for_each_region(int (*func)(__u64 start, __u64 size,
618 void *data), void *data)
619{
620 struct pci_mmcfg_region *cfg;
621 int rc;
622
623 if (list_empty(&pci_mmcfg_list))
624 return 0;
625
626 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
627 rc = func(cfg->res.start, resource_size(&cfg->res), data);
628 if (rc)
629 return rc;
630 }
631
632 return 0;
633}
634#define set_apei_filter() (arch_apei_filter_addr = pci_mmcfg_for_each_region)
635#else
636#define set_apei_filter()
637#endif
638
968cbfad 639static void __init __pci_mmcfg_init(int early)
b7867394 640{
068258bc 641 pci_mmcfg_reject_broken(early);
ff097ddd 642 if (list_empty(&pci_mmcfg_list))
b7867394
OG		 643 return;
644
a3170c1f
JB		 645 if (pcibios_last_bus < 0) {
646 const struct pci_mmcfg_region *cfg;
647
648 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
649 if (cfg->segment)
650 break;
651 pcibios_last_bus = cfg->end_bus;
652 }
653 }
654
ebd60cd6 655 if (pci_mmcfg_arch_init())
b7867394 656 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
ebd60cd6 657 else {
66e8850a 658 free_all_mmcfg();
9c95111b 659 pci_mmcfg_arch_init_failed = true;
b7867394
OG		 660 }
661}
a5ba7971 662
574a5941
JL		 663static int __initdata known_bridge;
664
bb63b421 665void __init pci_mmcfg_early_init(void)
05c58b8a 666{
574a5941
JL		 667 if (pci_probe & PCI_PROBE_MMCONF) {
668 if (pci_mmcfg_check_hostbridge())
669 known_bridge = 1;
670 else
671 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
672 __pci_mmcfg_init(1);
d91525eb
CG		 673
674 set_apei_filter();
574a5941 675 }
05c58b8a
YL		 676}
677
678void __init pci_mmcfg_late_init(void)
679{
574a5941
JL		 680 /* MMCONFIG disabled */
681 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
682 return;
683
684 if (known_bridge)
685 return;
686
687 /* MMCONFIG hasn't been enabled yet, try again */
688 if (pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF) {
689 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
690 __pci_mmcfg_init(0);
691 }
05c58b8a
YL		 692}
693
a5ba7971
AD		 694static int __init pci_mmcfg_late_insert_resources(void)
695{
66e8850a
JL		 696 struct pci_mmcfg_region *cfg;
697
95c5e92f
JL		 698 pci_mmcfg_running_state = true;
699
66e8850a
JL		 700 /* If we are not using MMCONFIG, don't insert the resources. */
701 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
a5ba7971
AD		 702 return 1;
703
704 /*
705 * Attempt to insert the mmcfg resources but not with the busy flag
706 * marked so it won't cause request errors when __request_region is
707 * called.
708 */
66e8850a
JL		 709 list_for_each_entry(cfg, &pci_mmcfg_list, list)
710 if (!cfg->res.parent)
711 insert_resource(&iomem_resource, &cfg->res);
a5ba7971
AD		 712
713 return 0;
714}
715
716/*
717 * Perform MMCONFIG resource insertion after PCI initialization to allow for
718 * misprogrammed MCFG tables that state larger sizes but actually conflict
719 * with other system resources.
720 */
721late_initcall(pci_mmcfg_late_insert_resources);
9c95111b
JL		 722
723/* Add MMCFG information for host bridges */
a18e3690
GKH		 724int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,
725 phys_addr_t addr)
9c95111b
JL		 726{
727 int rc;
728 struct resource *tmp = NULL;
729 struct pci_mmcfg_region *cfg;
730
731 if (!(pci_probe & PCI_PROBE_MMCONF) || pci_mmcfg_arch_init_failed)
732 return -ENODEV;
733
67d470e0 734 if (start > end)
9c95111b
JL		 735 return -EINVAL;
736
737 mutex_lock(&pci_mmcfg_lock);
738 cfg = pci_mmconfig_lookup(seg, start);
739 if (cfg) {
740 if (cfg->end_bus < end)
741 dev_info(dev, FW_INFO
742 "MMCONFIG for "
743 "domain %04x [bus %02x-%02x] "
744 "only partially covers this bridge\n",
745 cfg->segment, cfg->start_bus, cfg->end_bus);
746 mutex_unlock(&pci_mmcfg_lock);
747 return -EEXIST;
748 }
749
67d470e0
BH		 750 if (!addr) {
751 mutex_unlock(&pci_mmcfg_lock);
752 return -EINVAL;
753 }
754
9c95111b
JL		 755 rc = -EBUSY;
756 cfg = pci_mmconfig_alloc(seg, start, end, addr);
757 if (cfg == NULL) {
758 dev_warn(dev, "fail to add MMCONFIG (out of memory)\n");
759 rc = -ENOMEM;
760 } else if (!pci_mmcfg_check_reserved(dev, cfg, 0)) {
761 dev_warn(dev, FW_BUG "MMCONFIG %pR isn't reserved\n",
762 &cfg->res);
763 } else {
764 /* Insert resource if it's not in boot stage */
765 if (pci_mmcfg_running_state)
766 tmp = insert_resource_conflict(&iomem_resource,
767 &cfg->res);
768
769 if (tmp) {
770 dev_warn(dev,
771 "MMCONFIG %pR conflicts with "
772 "%s %pR\n",
773 &cfg->res, tmp->name, tmp);
774 } else if (pci_mmcfg_arch_map(cfg)) {
775 dev_warn(dev, "fail to map MMCONFIG %pR.\n",
776 &cfg->res);
777 } else {
778 list_add_sorted(cfg);
779 dev_info(dev, "MMCONFIG at %pR (base %#lx)\n",
780 &cfg->res, (unsigned long)addr);
781 cfg = NULL;
782 rc = 0;
783 }
784 }
785
786 if (cfg) {
787 if (cfg->res.parent)
788 release_resource(&cfg->res);
789 kfree(cfg);
790 }
791
792 mutex_unlock(&pci_mmcfg_lock);
793
794 return rc;
795}
796
797/* Delete MMCFG information for host bridges */
798int pci_mmconfig_delete(u16 seg, u8 start, u8 end)
799{
800 struct pci_mmcfg_region *cfg;
801
802 mutex_lock(&pci_mmcfg_lock);
803 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
804 if (cfg->segment == seg && cfg->start_bus == start &&
805 cfg->end_bus == end) {
806 list_del_rcu(&cfg->list);
807 synchronize_rcu();
808 pci_mmcfg_arch_unmap(cfg);
809 if (cfg->res.parent)
810 release_resource(&cfg->res);
811 mutex_unlock(&pci_mmcfg_lock);
812 kfree(cfg);
813 return 0;
814 }
815 mutex_unlock(&pci_mmcfg_lock);
816
817 return -ENOENT;
818}
Linux kernel - Deliverables
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