Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Low-Level PCI Access for i386 machines. | |
3 | * | |
4 | * (c) 1999 Martin Mares <mj@ucw.cz> | |
5 | */ | |
6 | ||
7 | #undef DEBUG | |
8 | ||
9 | #ifdef DEBUG | |
10 | #define DBG(x...) printk(x) | |
11 | #else | |
12 | #define DBG(x...) | |
13 | #endif | |
14 | ||
15 | #define PCI_PROBE_BIOS 0x0001 | |
16 | #define PCI_PROBE_CONF1 0x0002 | |
17 | #define PCI_PROBE_CONF2 0x0004 | |
18 | #define PCI_PROBE_MMCONF 0x0008 | |
79e453d4 | 19 | #define PCI_PROBE_MASK 0x000f |
0637a70a | 20 | #define PCI_PROBE_NOEARLY 0x0010 |
1da177e4 | 21 | |
1da177e4 LT |
22 | #define PCI_NO_CHECKS 0x0400 |
23 | #define PCI_USE_PIRQ_MASK 0x0800 | |
24 | #define PCI_ASSIGN_ROMS 0x1000 | |
25 | #define PCI_BIOS_IRQ_SCAN 0x2000 | |
26 | #define PCI_ASSIGN_ALL_BUSSES 0x4000 | |
036fff4c | 27 | #define PCI_CAN_SKIP_ISA_ALIGN 0x8000 |
62f420f8 | 28 | #define PCI_USE__CRS 0x10000 |
5f0b2976 | 29 | #define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000 |
1da177e4 LT |
30 | |
31 | extern unsigned int pci_probe; | |
120bb424 | 32 | extern unsigned long pirq_table_addr; |
1da177e4 | 33 | |
6b4b78fe MD |
34 | enum pci_bf_sort_state { |
35 | pci_bf_sort_default, | |
36 | pci_force_nobf, | |
37 | pci_force_bf, | |
38 | pci_dmi_bf, | |
39 | }; | |
40 | ||
0df18ff3 | 41 | extern void __init dmi_check_pciprobe(void); |
13a6ddb0 YL |
42 | extern void __init dmi_check_skip_isa_align(void); |
43 | ||
1da177e4 LT |
44 | /* pci-i386.c */ |
45 | ||
46 | extern unsigned int pcibios_max_latency; | |
47 | ||
48 | void pcibios_resource_survey(void); | |
1da177e4 LT |
49 | |
50 | /* pci-pc.c */ | |
51 | ||
52 | extern int pcibios_last_bus; | |
53 | extern struct pci_bus *pci_root_bus; | |
54 | extern struct pci_ops pci_root_ops; | |
55 | ||
56 | /* pci-irq.c */ | |
57 | ||
58 | struct irq_info { | |
59 | u8 bus, devfn; /* Bus, device and function */ | |
60 | struct { | |
61 | u8 link; /* IRQ line ID, chipset dependent, 0=not routed */ | |
62 | u16 bitmap; /* Available IRQs */ | |
63 | } __attribute__((packed)) irq[4]; | |
64 | u8 slot; /* Slot number, 0=onboard */ | |
65 | u8 rfu; | |
66 | } __attribute__((packed)); | |
67 | ||
68 | struct irq_routing_table { | |
69 | u32 signature; /* PIRQ_SIGNATURE should be here */ | |
70 | u16 version; /* PIRQ_VERSION */ | |
71 | u16 size; /* Table size in bytes */ | |
72 | u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */ | |
73 | u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */ | |
74 | u16 rtr_vendor, rtr_device; /* Vendor and device ID of interrupt router */ | |
75 | u32 miniport_data; /* Crap */ | |
76 | u8 rfu[11]; | |
77 | u8 checksum; /* Modulo 256 checksum must give zero */ | |
78 | struct irq_info slots[0]; | |
79 | } __attribute__((packed)); | |
80 | ||
81 | extern unsigned int pcibios_irq_mask; | |
82 | ||
83 | extern int pcibios_scanned; | |
84 | extern spinlock_t pci_config_lock; | |
85 | ||
86 | extern int (*pcibios_enable_irq)(struct pci_dev *dev); | |
87bec66b | 87 | extern void (*pcibios_disable_irq)(struct pci_dev *dev); |
928cf8c6 | 88 | |
b6ce068a MW |
89 | struct pci_raw_ops { |
90 | int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn, | |
91 | int reg, int len, u32 *val); | |
92 | int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn, | |
93 | int reg, int len, u32 val); | |
94 | }; | |
95 | ||
96 | extern struct pci_raw_ops *raw_pci_ops; | |
97 | extern struct pci_raw_ops *raw_pci_ext_ops; | |
98 | ||
99 | extern struct pci_raw_ops pci_direct_conf1; | |
928cf8c6 | 100 | |
5e544d61 AK |
101 | extern int pci_direct_probe(void); |
102 | extern void pci_direct_init(int type); | |
92c05fc1 | 103 | extern void pci_pcbios_init(void); |
2bdd1b03 | 104 | extern int pci_olpc_init(void); |
5e544d61 | 105 | |
b7867394 OG |
106 | /* pci-mmconfig.c */ |
107 | ||
429d512e | 108 | extern int __init pci_mmcfg_arch_init(void); |
0b64ad71 | 109 | extern void __init pci_mmcfg_arch_free(void); |
3320ad99 | 110 | |
111 | /* | |
112 | * AMD Fam10h CPUs are buggy, and cannot access MMIO config space | |
113 | * on their northbrige except through the * %eax register. As such, you MUST | |
114 | * NOT use normal IOMEM accesses, you need to only use the magic mmio-config | |
115 | * accessor functions. | |
116 | * In fact just use pci_config_*, nothing else please. | |
117 | */ | |
118 | static inline unsigned char mmio_config_readb(void __iomem *pos) | |
119 | { | |
120 | u8 val; | |
121 | asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos)); | |
122 | return val; | |
123 | } | |
124 | ||
125 | static inline unsigned short mmio_config_readw(void __iomem *pos) | |
126 | { | |
127 | u16 val; | |
128 | asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos)); | |
129 | return val; | |
130 | } | |
131 | ||
132 | static inline unsigned int mmio_config_readl(void __iomem *pos) | |
133 | { | |
134 | u32 val; | |
135 | asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos)); | |
136 | return val; | |
137 | } | |
138 | ||
139 | static inline void mmio_config_writeb(void __iomem *pos, u8 val) | |
140 | { | |
141 | asm volatile("movb %%al,(%1)" :: "a" (val), "r" (pos) : "memory"); | |
142 | } | |
143 | ||
144 | static inline void mmio_config_writew(void __iomem *pos, u16 val) | |
145 | { | |
146 | asm volatile("movw %%ax,(%1)" :: "a" (val), "r" (pos) : "memory"); | |
147 | } | |
148 | ||
149 | static inline void mmio_config_writel(void __iomem *pos, u32 val) | |
150 | { | |
151 | asm volatile("movl %%eax,(%1)" :: "a" (val), "r" (pos) : "memory"); | |
152 | } |