[deliverable/linux.git] / arch / x86 / pci / pci.h

/*
 *	Low-Level PCI Access for i386 machines.
 *
 *	(c) 1999 Martin Mares <mj@ucw.cz>
 */

#undef DEBUG

#ifdef DEBUG
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif

#define PCI_PROBE_BIOS		0x0001
#define PCI_PROBE_CONF1		0x0002
#define PCI_PROBE_CONF2		0x0004
#define PCI_PROBE_MMCONF	0x0008
#define PCI_PROBE_MASK		0x000f
#define PCI_PROBE_NOEARLY	0x0010

#define PCI_NO_CHECKS		0x0400
#define PCI_USE_PIRQ_MASK	0x0800
#define PCI_ASSIGN_ROMS		0x1000
#define PCI_BIOS_IRQ_SCAN	0x2000
#define PCI_ASSIGN_ALL_BUSSES	0x4000
#define PCI_CAN_SKIP_ISA_ALIGN	0x8000
#define PCI_USE__CRS		0x10000

extern unsigned int pci_probe;
extern unsigned long pirq_table_addr;

enum pci_bf_sort_state {
	pci_bf_sort_default,
	pci_force_nobf,
	pci_force_bf,
	pci_dmi_bf,
};

/* pci-i386.c */

extern unsigned int pcibios_max_latency;

void pcibios_resource_survey(void);

/* pci-pc.c */

extern int pcibios_last_bus;
extern struct pci_bus *pci_root_bus;
extern struct pci_ops pci_root_ops;

/* pci-irq.c */

struct irq_info {
	u8 bus, devfn;			/* Bus, device and function */
	struct {
		u8 link;		/* IRQ line ID, chipset dependent, 0=not routed */
		u16 bitmap;		/* Available IRQs */
	} __attribute__((packed)) irq[4];
	u8 slot;			/* Slot number, 0=onboard */
	u8 rfu;
} __attribute__((packed));

struct irq_routing_table {
	u32 signature;			/* PIRQ_SIGNATURE should be here */
	u16 version;			/* PIRQ_VERSION */
	u16 size;			/* Table size in bytes */
	u8 rtr_bus, rtr_devfn;		/* Where the interrupt router lies */
	u16 exclusive_irqs;		/* IRQs devoted exclusively to PCI usage */
	u16 rtr_vendor, rtr_device;	/* Vendor and device ID of interrupt router */
	u32 miniport_data;		/* Crap */
	u8 rfu[11];
	u8 checksum;			/* Modulo 256 checksum must give zero */
	struct irq_info slots[0];
} __attribute__((packed));

extern unsigned int pcibios_irq_mask;

extern int pcibios_scanned;
extern spinlock_t pci_config_lock;

extern int (*pcibios_enable_irq)(struct pci_dev *dev);
extern void (*pcibios_disable_irq)(struct pci_dev *dev);

struct pci_raw_ops {
	int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
						int reg, int len, u32 *val);
	int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
						int reg, int len, u32 val);
};

extern struct pci_raw_ops *raw_pci_ops;
extern struct pci_raw_ops *raw_pci_ext_ops;

extern struct pci_raw_ops pci_direct_conf1;

extern int pci_direct_probe(void);
extern void pci_direct_init(int type);
extern void pci_pcbios_init(void);

/* pci-mmconfig.c */

extern int __init pci_mmcfg_arch_init(void);
extern void __init pci_mmcfg_arch_free(void);

/*
 * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
 * on their northbrige except through the * %eax register. As such, you MUST
 * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
 * accessor functions.
 * In fact just use pci_config_*, nothing else please.
 */
static inline unsigned char mmio_config_readb(void __iomem *pos)
{
	u8 val;
	asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
	return val;
}

static inline unsigned short mmio_config_readw(void __iomem *pos)
{
	u16 val;
	asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
	return val;
}

static inline unsigned int mmio_config_readl(void __iomem *pos)
{
	u32 val;
	asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
	return val;
}

static inline void mmio_config_writeb(void __iomem *pos, u8 val)
{
	asm volatile("movb %%al,(%1)" :: "a" (val), "r" (pos) : "memory");
}

static inline void mmio_config_writew(void __iomem *pos, u16 val)
{
	asm volatile("movw %%ax,(%1)" :: "a" (val), "r" (pos) : "memory");
}

static inline void mmio_config_writel(void __iomem *pos, u32 val)
{
	asm volatile("movl %%eax,(%1)" :: "a" (val), "r" (pos) : "memory");
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Low-Level PCI Access for i386 machines.
	3	*
	4	* (c) 1999 Martin Mares <mj@ucw.cz>
	5	*/
	6
	7	#undef DEBUG
	8
	9	#ifdef DEBUG
	10	#define DBG(x...) printk(x)
	11	#else
	12	#define DBG(x...)
	13	#endif
	14
	15	#define PCI_PROBE_BIOS 0x0001
	16	#define PCI_PROBE_CONF1 0x0002
	17	#define PCI_PROBE_CONF2 0x0004
	18	#define PCI_PROBE_MMCONF 0x0008
79e453d4	19	#define PCI_PROBE_MASK 0x000f
0637a70a	20	#define PCI_PROBE_NOEARLY 0x0010
1da177e4	21
1da177e4 LT	22	#define PCI_NO_CHECKS 0x0400
	23	#define PCI_USE_PIRQ_MASK 0x0800
	24	#define PCI_ASSIGN_ROMS 0x1000
	25	#define PCI_BIOS_IRQ_SCAN 0x2000
	26	#define PCI_ASSIGN_ALL_BUSSES 0x4000
036fff4c	27	#define PCI_CAN_SKIP_ISA_ALIGN 0x8000
62f420f8	28	#define PCI_USE__CRS 0x10000
1da177e4 LT	29
1da177e4 LT	30	extern unsigned int pci_probe;
120bb424	31	extern unsigned long pirq_table_addr;
1da177e4	32
6b4b78fe MD	33	enum pci_bf_sort_state {
	34	pci_bf_sort_default,
	35	pci_force_nobf,
	36	pci_force_bf,
	37	pci_dmi_bf,
	38	};
	39
1da177e4 LT	40	/* pci-i386.c */
	41
	42	extern unsigned int pcibios_max_latency;
	43
	44	void pcibios_resource_survey(void);
1da177e4 LT	45
	46	/* pci-pc.c */
	47
	48	extern int pcibios_last_bus;
	49	extern struct pci_bus *pci_root_bus;
	50	extern struct pci_ops pci_root_ops;
	51
	52	/* pci-irq.c */
	53
	54	struct irq_info {
	55	u8 bus, devfn; /* Bus, device and function */
	56	struct {
	57	u8 link; /* IRQ line ID, chipset dependent, 0=not routed */
	58	u16 bitmap; /* Available IRQs */
	59	} __attribute__((packed)) irq[4];
	60	u8 slot; /* Slot number, 0=onboard */
	61	u8 rfu;
	62	} __attribute__((packed));
	63
	64	struct irq_routing_table {
	65	u32 signature; /* PIRQ_SIGNATURE should be here */
	66	u16 version; /* PIRQ_VERSION */
	67	u16 size; /* Table size in bytes */
	68	u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
	69	u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */
	70	u16 rtr_vendor, rtr_device; /* Vendor and device ID of interrupt router */
	71	u32 miniport_data; /* Crap */
	72	u8 rfu[11];
	73	u8 checksum; /* Modulo 256 checksum must give zero */
	74	struct irq_info slots[0];
	75	} __attribute__((packed));
	76
	77	extern unsigned int pcibios_irq_mask;
	78
	79	extern int pcibios_scanned;
	80	extern spinlock_t pci_config_lock;
	81
	82	extern int (pcibios_enable_irq)(struct pci_dev dev);
87bec66b	83	extern void (pcibios_disable_irq)(struct pci_dev dev);
928cf8c6	84
b6ce068a MW	85	struct pci_raw_ops {
	86	int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
	87	int reg, int len, u32 *val);
	88	int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
	89	int reg, int len, u32 val);
	90	};
	91
	92	extern struct pci_raw_ops *raw_pci_ops;
	93	extern struct pci_raw_ops *raw_pci_ext_ops;
	94
	95	extern struct pci_raw_ops pci_direct_conf1;
928cf8c6	96
5e544d61 AK	97	extern int pci_direct_probe(void);
5e544d61 AK	98	extern void pci_direct_init(int type);
92c05fc1	99	extern void pci_pcbios_init(void);
5e544d61	100
b7867394 OG	101	/* pci-mmconfig.c */
b7867394 OG	102
429d512e	103	extern int __init pci_mmcfg_arch_init(void);
0b64ad71	104	extern void __init pci_mmcfg_arch_free(void);
3320ad99	105
	106	/*
	107	* AMD Fam10h CPUs are buggy, and cannot access MMIO config space
	108	* on their northbrige except through the * %eax register. As such, you MUST
	109	* NOT use normal IOMEM accesses, you need to only use the magic mmio-config
	110	* accessor functions.
	111	* In fact just use pci_config_*, nothing else please.
	112	*/
	113	static inline unsigned char mmio_config_readb(void __iomem *pos)
	114	{
	115	u8 val;
	116	asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
	117	return val;
	118	}
	119
	120	static inline unsigned short mmio_config_readw(void __iomem *pos)
	121	{
	122	u16 val;
	123	asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
	124	return val;
	125	}
	126
	127	static inline unsigned int mmio_config_readl(void __iomem *pos)
	128	{
	129	u32 val;
	130	asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
	131	return val;
	132	}
	133
	134	static inline void mmio_config_writeb(void __iomem *pos, u8 val)
	135	{
	136	asm volatile("movb %%al,(%1)" :: "a" (val), "r" (pos) : "memory");
	137	}
	138
	139	static inline void mmio_config_writew(void __iomem *pos, u16 val)
	140	{
	141	asm volatile("movw %%ax,(%1)" :: "a" (val), "r" (pos) : "memory");
	142	}
	143
	144	static inline void mmio_config_writel(void __iomem *pos, u32 val)
	145	{
	146	asm volatile("movl %%eax,(%1)" :: "a" (val), "r" (pos) : "memory");
	147	}