[deliverable/linux.git] / arch / x86 / pci / xen.c

/*
 * Xen PCI - handle PCI (INTx) and MSI infrastructure calls for PV, HVM and
 * initial domain support. We also handle the DSDT _PRT callbacks for GSI's
 * used in HVM and initial domain mode (PV does not parse ACPI, so it has no
 * concept of GSIs). Under PV we hook under the pnbbios API for IRQs and
 * 0xcf8 PCI configuration read/write.
 *
 *   Author: Ryan Wilson <hap9@epoch.ncsc.mil>
 *           Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
 *           Stefano Stabellini <stefano.stabellini@eu.citrix.com>
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/acpi.h>

#include <linux/io.h>
#include <asm/io_apic.h>
#include <asm/pci_x86.h>

#include <asm/xen/hypervisor.h>

#include <xen/features.h>
#include <xen/events.h>
#include <asm/xen/pci.h>

static int xen_pcifront_enable_irq(struct pci_dev *dev)
{
	int rc;
	int share = 1;
	int pirq;
	u8 gsi;

	rc = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &gsi);
	if (rc < 0) {
		dev_warn(&dev->dev, "Xen PCI: failed to read interrupt line: %d\n",
			 rc);
		return rc;
	}
	/* In PV DomU the Xen PCI backend puts the PIRQ in the interrupt line.*/
	pirq = gsi;

	if (gsi < NR_IRQS_LEGACY)
		share = 0;

	rc = xen_bind_pirq_gsi_to_irq(gsi, pirq, share, "pcifront");
	if (rc < 0) {
		dev_warn(&dev->dev, "Xen PCI: failed to bind GSI%d (PIRQ%d) to IRQ: %d\n",
			 gsi, pirq, rc);
		return rc;
	}

	dev->irq = rc;
	dev_info(&dev->dev, "Xen PCI mapped GSI%d to IRQ%d\n", gsi, dev->irq);
	return 0;
}

#ifdef CONFIG_ACPI
static int xen_register_pirq(u32 gsi, int gsi_override, int triggering,
			     bool set_pirq)
{
	int rc, pirq = -1, irq = -1;
	struct physdev_map_pirq map_irq;
	int shareable = 0;
	char *name;

	irq = xen_irq_from_gsi(gsi);
	if (irq > 0)
		return irq;

	if (set_pirq)
		pirq = gsi;

	map_irq.domid = DOMID_SELF;
	map_irq.type = MAP_PIRQ_TYPE_GSI;
	map_irq.index = gsi;
	map_irq.pirq = pirq;

	rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
	if (rc) {
		printk(KERN_WARNING "xen map irq failed %d\n", rc);
		return -1;
	}

	if (triggering == ACPI_EDGE_SENSITIVE) {
		shareable = 0;
		name = "ioapic-edge";
	} else {
		shareable = 1;
		name = "ioapic-level";
	}

	if (gsi_override >= 0)
		gsi = gsi_override;

	irq = xen_bind_pirq_gsi_to_irq(gsi, map_irq.pirq, shareable, name);
	if (irq < 0)
		goto out;

	printk(KERN_DEBUG "xen: --> pirq=%d -> irq=%d (gsi=%d)\n", map_irq.pirq, irq, gsi);
out:
	return irq;
}

static int acpi_register_gsi_xen_hvm(struct device *dev, u32 gsi,
				     int trigger, int polarity)
{
	if (!xen_hvm_domain())
		return -1;

	return xen_register_pirq(gsi, -1 /* no GSI override */, trigger,
				 false /* no mapping of GSI to PIRQ */);
}

#ifdef CONFIG_XEN_DOM0
static int xen_register_gsi(u32 gsi, int gsi_override, int triggering, int polarity)
{
	int rc, irq;
	struct physdev_setup_gsi setup_gsi;

	if (!xen_pv_domain())
		return -1;

	printk(KERN_DEBUG "xen: registering gsi %u triggering %d polarity %d\n",
			gsi, triggering, polarity);

	irq = xen_register_pirq(gsi, gsi_override, triggering, true);

	setup_gsi.gsi = gsi;
	setup_gsi.triggering = (triggering == ACPI_EDGE_SENSITIVE ? 0 : 1);
	setup_gsi.polarity = (polarity == ACPI_ACTIVE_HIGH ? 0 : 1);

	rc = HYPERVISOR_physdev_op(PHYSDEVOP_setup_gsi, &setup_gsi);
	if (rc == -EEXIST)
		printk(KERN_INFO "Already setup the GSI :%d\n", gsi);
	else if (rc) {
		printk(KERN_ERR "Failed to setup GSI :%d, err_code:%d\n",
				gsi, rc);
	}

	return irq;
}

static int acpi_register_gsi_xen(struct device *dev, u32 gsi,
				 int trigger, int polarity)
{
	return xen_register_gsi(gsi, -1 /* no GSI override */, trigger, polarity);
}
#endif
#endif

#if defined(CONFIG_PCI_MSI)
#include <linux/msi.h>
#include <asm/msidef.h>

struct xen_pci_frontend_ops *xen_pci_frontend;
EXPORT_SYMBOL_GPL(xen_pci_frontend);

static int xen_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
{
	int irq, ret, i;
	struct msi_desc *msidesc;
	int *v;

	if (type == PCI_CAP_ID_MSI && nvec > 1)
		return 1;

	v = kzalloc(sizeof(int) * max(1, nvec), GFP_KERNEL);
	if (!v)
		return -ENOMEM;

	if (type == PCI_CAP_ID_MSIX)
		ret = xen_pci_frontend_enable_msix(dev, v, nvec);
	else
		ret = xen_pci_frontend_enable_msi(dev, v);
	if (ret)
		goto error;
	i = 0;
	list_for_each_entry(msidesc, &dev->msi_list, list) {
		irq = xen_bind_pirq_msi_to_irq(dev, msidesc, v[i],
					       (type == PCI_CAP_ID_MSI) ? nvec : 1,
					       (type == PCI_CAP_ID_MSIX) ?
					       "pcifront-msi-x" :
					       "pcifront-msi",
						DOMID_SELF);
		if (irq < 0) {
			ret = irq;
			goto free;
		}
		i++;
	}
	kfree(v);
	return 0;

error:
	dev_err(&dev->dev, "Xen PCI frontend has not registered MSI/MSI-X support!\n");
free:
	kfree(v);
	return ret;
}

#define XEN_PIRQ_MSI_DATA  (MSI_DATA_TRIGGER_EDGE | \
		MSI_DATA_LEVEL_ASSERT | (3 << 8) | MSI_DATA_VECTOR(0))

static void xen_msi_compose_msg(struct pci_dev *pdev, unsigned int pirq,
		struct msi_msg *msg)
{
	/* We set vector == 0 to tell the hypervisor we don't care about it,
	 * but we want a pirq setup instead.
	 * We use the dest_id field to pass the pirq that we want. */
	msg->address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(pirq);
	msg->address_lo =
		MSI_ADDR_BASE_LO |
		MSI_ADDR_DEST_MODE_PHYSICAL |
		MSI_ADDR_REDIRECTION_CPU |
		MSI_ADDR_DEST_ID(pirq);

	msg->data = XEN_PIRQ_MSI_DATA;
}

static int xen_hvm_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
{
	int irq, pirq;
	struct msi_desc *msidesc;
	struct msi_msg msg;

	if (type == PCI_CAP_ID_MSI && nvec > 1)
		return 1;

	list_for_each_entry(msidesc, &dev->msi_list, list) {
		__read_msi_msg(msidesc, &msg);
		pirq = MSI_ADDR_EXT_DEST_ID(msg.address_hi) |
			((msg.address_lo >> MSI_ADDR_DEST_ID_SHIFT) & 0xff);
		if (msg.data != XEN_PIRQ_MSI_DATA ||
		    xen_irq_from_pirq(pirq) < 0) {
			pirq = xen_allocate_pirq_msi(dev, msidesc);
			if (pirq < 0) {
				irq = -ENODEV;
				goto error;
			}
			xen_msi_compose_msg(dev, pirq, &msg);
			__write_msi_msg(msidesc, &msg);
			dev_dbg(&dev->dev, "xen: msi bound to pirq=%d\n", pirq);
		} else {
			dev_dbg(&dev->dev,
				"xen: msi already bound to pirq=%d\n", pirq);
		}
		irq = xen_bind_pirq_msi_to_irq(dev, msidesc, pirq,
					       (type == PCI_CAP_ID_MSI) ? nvec : 1,
					       (type == PCI_CAP_ID_MSIX) ?
					       "msi-x" : "msi",
					       DOMID_SELF);
		if (irq < 0)
			goto error;
		dev_dbg(&dev->dev,
			"xen: msi --> pirq=%d --> irq=%d\n", pirq, irq);
	}
	return 0;

error:
	dev_err(&dev->dev,
		"Xen PCI frontend has not registered MSI/MSI-X support!\n");
	return irq;
}

#ifdef CONFIG_XEN_DOM0
static bool __read_mostly pci_seg_supported = true;

static int xen_initdom_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
{
	int ret = 0;
	struct msi_desc *msidesc;

	list_for_each_entry(msidesc, &dev->msi_list, list) {
		struct physdev_map_pirq map_irq;
		domid_t domid;

		domid = ret = xen_find_device_domain_owner(dev);
		/* N.B. Casting int's -ENODEV to uint16_t results in 0xFFED,
		 * hence check ret value for < 0. */
		if (ret < 0)
			domid = DOMID_SELF;

		memset(&map_irq, 0, sizeof(map_irq));
		map_irq.domid = domid;
		map_irq.type = MAP_PIRQ_TYPE_MSI_SEG;
		map_irq.index = -1;
		map_irq.pirq = -1;
		map_irq.bus = dev->bus->number |
			      (pci_domain_nr(dev->bus) << 16);
		map_irq.devfn = dev->devfn;

		if (type == PCI_CAP_ID_MSI && nvec > 1) {
			map_irq.type = MAP_PIRQ_TYPE_MULTI_MSI;
			map_irq.entry_nr = nvec;
		} else if (type == PCI_CAP_ID_MSIX) {
			int pos;
			u32 table_offset, bir;

			pos = dev->msix_cap;
			pci_read_config_dword(dev, pos + PCI_MSIX_TABLE,
					      &table_offset);
			bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);

			map_irq.table_base = pci_resource_start(dev, bir);
			map_irq.entry_nr = msidesc->msi_attrib.entry_nr;
		}

		ret = -EINVAL;
		if (pci_seg_supported)
			ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq,
						    &map_irq);
		if (type == PCI_CAP_ID_MSI && nvec > 1 && ret) {
			/*
			 * If MAP_PIRQ_TYPE_MULTI_MSI is not available
			 * there's nothing else we can do in this case.
			 * Just set ret > 0 so driver can retry with
			 * single MSI.
			 */
			ret = 1;
			goto out;
		}
		if (ret == -EINVAL && !pci_domain_nr(dev->bus)) {
			map_irq.type = MAP_PIRQ_TYPE_MSI;
			map_irq.index = -1;
			map_irq.pirq = -1;
			map_irq.bus = dev->bus->number;
			ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq,
						    &map_irq);
			if (ret != -EINVAL)
				pci_seg_supported = false;
		}
		if (ret) {
			dev_warn(&dev->dev, "xen map irq failed %d for %d domain\n",
				 ret, domid);
			goto out;
		}

		ret = xen_bind_pirq_msi_to_irq(dev, msidesc, map_irq.pirq,
		                               (type == PCI_CAP_ID_MSI) ? nvec : 1,
		                               (type == PCI_CAP_ID_MSIX) ? "msi-x" : "msi",
		                               domid);
		if (ret < 0)
			goto out;
	}
	ret = 0;
out:
	return ret;
}

static void xen_initdom_restore_msi_irqs(struct pci_dev *dev)
{
	int ret = 0;

	if (pci_seg_supported) {
		struct physdev_pci_device restore_ext;

		restore_ext.seg = pci_domain_nr(dev->bus);
		restore_ext.bus = dev->bus->number;
		restore_ext.devfn = dev->devfn;
		ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi_ext,
					&restore_ext);
		if (ret == -ENOSYS)
			pci_seg_supported = false;
		WARN(ret && ret != -ENOSYS, "restore_msi_ext -> %d\n", ret);
	}
	if (!pci_seg_supported) {
		struct physdev_restore_msi restore;

		restore.bus = dev->bus->number;
		restore.devfn = dev->devfn;
		ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi, &restore);
		WARN(ret && ret != -ENOSYS, "restore_msi -> %d\n", ret);
	}
}
#endif

static void xen_teardown_msi_irqs(struct pci_dev *dev)
{
	struct msi_desc *msidesc;

	msidesc = list_entry(dev->msi_list.next, struct msi_desc, list);
	if (msidesc->msi_attrib.is_msix)
		xen_pci_frontend_disable_msix(dev);
	else
		xen_pci_frontend_disable_msi(dev);

	/* Free the IRQ's and the msidesc using the generic code. */
	default_teardown_msi_irqs(dev);
}

static void xen_teardown_msi_irq(unsigned int irq)
{
	xen_destroy_irq(irq);
}
static u32 xen_nop_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
{
	return 0;
}
static u32 xen_nop_msix_mask_irq(struct msi_desc *desc, u32 flag)
{
	return 0;
}
#endif

int __init pci_xen_init(void)
{
	if (!xen_pv_domain() || xen_initial_domain())
		return -ENODEV;

	printk(KERN_INFO "PCI: setting up Xen PCI frontend stub\n");

	pcibios_set_cache_line_size();

	pcibios_enable_irq = xen_pcifront_enable_irq;
	pcibios_disable_irq = NULL;

#ifdef CONFIG_ACPI
	/* Keep ACPI out of the picture */
	acpi_noirq = 1;
#endif

#ifdef CONFIG_PCI_MSI
	x86_msi.setup_msi_irqs = xen_setup_msi_irqs;
	x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
	x86_msi.teardown_msi_irqs = xen_teardown_msi_irqs;
	x86_msi.msi_mask_irq = xen_nop_msi_mask_irq;
	x86_msi.msix_mask_irq = xen_nop_msix_mask_irq;
#endif
	return 0;
}

int __init pci_xen_hvm_init(void)
{
	if (!xen_have_vector_callback || !xen_feature(XENFEAT_hvm_pirqs))
		return 0;

#ifdef CONFIG_ACPI
	/*
	 * We don't want to change the actual ACPI delivery model,
	 * just how GSIs get registered.
	 */
	__acpi_register_gsi = acpi_register_gsi_xen_hvm;
#endif

#ifdef CONFIG_PCI_MSI
	x86_msi.setup_msi_irqs = xen_hvm_setup_msi_irqs;
	x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
#endif
	return 0;
}

#ifdef CONFIG_XEN_DOM0
static __init void xen_setup_acpi_sci(void)
{
	int rc;
	int trigger, polarity;
	int gsi = acpi_sci_override_gsi;
	int irq = -1;
	int gsi_override = -1;

	if (!gsi)
		return;

	rc = acpi_get_override_irq(gsi, &trigger, &polarity);
	if (rc) {
		printk(KERN_WARNING "xen: acpi_get_override_irq failed for acpi"
				" sci, rc=%d\n", rc);
		return;
	}
	trigger = trigger ? ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE;
	polarity = polarity ? ACPI_ACTIVE_LOW : ACPI_ACTIVE_HIGH;

	printk(KERN_INFO "xen: sci override: global_irq=%d trigger=%d "
			"polarity=%d\n", gsi, trigger, polarity);

	/* Before we bind the GSI to a Linux IRQ, check whether
	 * we need to override it with bus_irq (IRQ) value. Usually for
	 * IRQs below IRQ_LEGACY_IRQ this holds IRQ == GSI, as so:
	 *  ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level)
	 * but there are oddballs where the IRQ != GSI:
	 *  ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 20 low level)
	 * which ends up being: gsi_to_irq[9] == 20
	 * (which is what acpi_gsi_to_irq ends up calling when starting the
	 * the ACPI interpreter and keels over since IRQ 9 has not been
	 * setup as we had setup IRQ 20 for it).
	 */
	if (acpi_gsi_to_irq(gsi, &irq) == 0) {
		/* Use the provided value if it's valid. */
		if (irq >= 0)
			gsi_override = irq;
	}

	gsi = xen_register_gsi(gsi, gsi_override, trigger, polarity);
	printk(KERN_INFO "xen: acpi sci %d\n", gsi);

	return;
}

int __init pci_xen_initial_domain(void)
{
	int irq;

#ifdef CONFIG_PCI_MSI
	x86_msi.setup_msi_irqs = xen_initdom_setup_msi_irqs;
	x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
	x86_msi.restore_msi_irqs = xen_initdom_restore_msi_irqs;
	x86_msi.msi_mask_irq = xen_nop_msi_mask_irq;
	x86_msi.msix_mask_irq = xen_nop_msix_mask_irq;
#endif
	xen_setup_acpi_sci();
	__acpi_register_gsi = acpi_register_gsi_xen;
	/* Pre-allocate legacy irqs */
	for (irq = 0; irq < NR_IRQS_LEGACY; irq++) {
		int trigger, polarity;

		if (acpi_get_override_irq(irq, &trigger, &polarity) == -1)
			continue;

		xen_register_pirq(irq, -1 /* no GSI override */,
			trigger ? ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE,
			true /* Map GSI to PIRQ */);
	}
	if (0 == nr_ioapics) {
		for (irq = 0; irq < NR_IRQS_LEGACY; irq++)
			xen_bind_pirq_gsi_to_irq(irq, irq, 0, "xt-pic");
	}
	return 0;
}

struct xen_device_domain_owner {
	domid_t domain;
	struct pci_dev *dev;
	struct list_head list;
};

static DEFINE_SPINLOCK(dev_domain_list_spinlock);
static struct list_head dev_domain_list = LIST_HEAD_INIT(dev_domain_list);

static struct xen_device_domain_owner *find_device(struct pci_dev *dev)
{
	struct xen_device_domain_owner *owner;

	list_for_each_entry(owner, &dev_domain_list, list) {
		if (owner->dev == dev)
			return owner;
	}
	return NULL;
}

int xen_find_device_domain_owner(struct pci_dev *dev)
{
	struct xen_device_domain_owner *owner;
	int domain = -ENODEV;

	spin_lock(&dev_domain_list_spinlock);
	owner = find_device(dev);
	if (owner)
		domain = owner->domain;
	spin_unlock(&dev_domain_list_spinlock);
	return domain;
}
EXPORT_SYMBOL_GPL(xen_find_device_domain_owner);

int xen_register_device_domain_owner(struct pci_dev *dev, uint16_t domain)
{
	struct xen_device_domain_owner *owner;

	owner = kzalloc(sizeof(struct xen_device_domain_owner), GFP_KERNEL);
	if (!owner)
		return -ENODEV;

	spin_lock(&dev_domain_list_spinlock);
	if (find_device(dev)) {
		spin_unlock(&dev_domain_list_spinlock);
		kfree(owner);
		return -EEXIST;
	}
	owner->domain = domain;
	owner->dev = dev;
	list_add_tail(&owner->list, &dev_domain_list);
	spin_unlock(&dev_domain_list_spinlock);
	return 0;
}
EXPORT_SYMBOL_GPL(xen_register_device_domain_owner);

int xen_unregister_device_domain_owner(struct pci_dev *dev)
{
	struct xen_device_domain_owner *owner;

	spin_lock(&dev_domain_list_spinlock);
	owner = find_device(dev);
	if (!owner) {
		spin_unlock(&dev_domain_list_spinlock);
		return -ENODEV;
	}
	list_del(&owner->list);
	spin_unlock(&dev_domain_list_spinlock);
	kfree(owner);
	return 0;
}
EXPORT_SYMBOL_GPL(xen_unregister_device_domain_owner);
#endif
Commit	Line	Data
b5401a96	1	/*
996c34ae KRW	2	* Xen PCI - handle PCI (INTx) and MSI infrastructure calls for PV, HVM and
	3	* initial domain support. We also handle the DSDT _PRT callbacks for GSI's
	4	* used in HVM and initial domain mode (PV does not parse ACPI, so it has no
	5	* concept of GSIs). Under PV we hook under the pnbbios API for IRQs and
	6	* 0xcf8 PCI configuration read/write.
b5401a96 AN	7	*
b5401a96 AN	8	* Author: Ryan Wilson <hap9@epoch.ncsc.mil>
996c34ae KRW	9	* Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
996c34ae KRW	10	* Stefano Stabellini <stefano.stabellini@eu.citrix.com>
b5401a96 AN	11	*/
	12	#include <linux/module.h>
	13	#include <linux/init.h>
	14	#include <linux/pci.h>
	15	#include <linux/acpi.h>
	16
	17	#include <linux/io.h>
0e058e52	18	#include <asm/io_apic.h>
b5401a96 AN	19	#include <asm/pci_x86.h>
	20
	21	#include <asm/xen/hypervisor.h>
	22
3942b740	23	#include <xen/features.h>
b5401a96 AN	24	#include <xen/events.h>
	25	#include <asm/xen/pci.h>
	26
fef6e262 KRW	27	static int xen_pcifront_enable_irq(struct pci_dev *dev)
	28	{
	29	int rc;
	30	int share = 1;
	31	int pirq;
	32	u8 gsi;
	33
	34	rc = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &gsi);
	35	if (rc < 0) {
	36	dev_warn(&dev->dev, "Xen PCI: failed to read interrupt line: %d\n",
	37	rc);
	38	return rc;
	39	}
78316ada KRW	40	/* In PV DomU the Xen PCI backend puts the PIRQ in the interrupt line.*/
78316ada KRW	41	pirq = gsi;
fef6e262 KRW	42
	43	if (gsi < NR_IRQS_LEGACY)
	44	share = 0;
	45
	46	rc = xen_bind_pirq_gsi_to_irq(gsi, pirq, share, "pcifront");
	47	if (rc < 0) {
	48	dev_warn(&dev->dev, "Xen PCI: failed to bind GSI%d (PIRQ%d) to IRQ: %d\n",
	49	gsi, pirq, rc);
	50	return rc;
	51	}
	52
	53	dev->irq = rc;
	54	dev_info(&dev->dev, "Xen PCI mapped GSI%d to IRQ%d\n", gsi, dev->irq);
	55	return 0;
	56	}
	57
42a1de56	58	#ifdef CONFIG_ACPI
ed89eb63	59	static int xen_register_pirq(u32 gsi, int gsi_override, int triggering,
78316ada	60	bool set_pirq)
42a1de56	61	{
ed89eb63	62	int rc, pirq = -1, irq = -1;
42a1de56 SS	63	struct physdev_map_pirq map_irq;
	64	int shareable = 0;
	65	char *name;
	66
68c2c39a SS	67	irq = xen_irq_from_gsi(gsi);
	68	if (irq > 0)
	69	return irq;
	70
78316ada KRW	71	if (set_pirq)
	72	pirq = gsi;
	73
fef6e262 KRW	74	map_irq.domid = DOMID_SELF;
	75	map_irq.type = MAP_PIRQ_TYPE_GSI;
	76	map_irq.index = gsi;
	77	map_irq.pirq = pirq;
	78
	79	rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
	80	if (rc) {
	81	printk(KERN_WARNING "xen map irq failed %d\n", rc);
	82	return -1;
	83	}
	84
30bd35ed KRW	85	if (triggering == ACPI_EDGE_SENSITIVE) {
	86	shareable = 0;
	87	name = "ioapic-edge";
	88	} else {
	89	shareable = 1;
	90	name = "ioapic-level";
	91	}
	92
	93	if (gsi_override >= 0)
	94	gsi = gsi_override;
	95
ed89eb63	96	irq = xen_bind_pirq_gsi_to_irq(gsi, map_irq.pirq, shareable, name);
30bd35ed KRW	97	if (irq < 0)
	98	goto out;
	99
ed89eb63	100	printk(KERN_DEBUG "xen: --> pirq=%d -> irq=%d (gsi=%d)\n", map_irq.pirq, irq, gsi);
fef6e262 KRW	101	out:
	102	return irq;
	103	}
	104
ed89eb63 KRW	105	static int acpi_register_gsi_xen_hvm(struct device *dev, u32 gsi,
	106	int trigger, int polarity)
	107	{
	108	if (!xen_hvm_domain())
	109	return -1;
	110
78316ada KRW	111	return xen_register_pirq(gsi, -1 /* no GSI override */, trigger,
78316ada KRW	112	false /* no mapping of GSI to PIRQ */);
ed89eb63 KRW	113	}
	114
	115	#ifdef CONFIG_XEN_DOM0
fef6e262 KRW	116	static int xen_register_gsi(u32 gsi, int gsi_override, int triggering, int polarity)
	117	{
	118	int rc, irq;
	119	struct physdev_setup_gsi setup_gsi;
	120
	121	if (!xen_pv_domain())
	122	return -1;
	123
	124	printk(KERN_DEBUG "xen: registering gsi %u triggering %d polarity %d\n",
	125	gsi, triggering, polarity);
	126
ed89eb63	127	irq = xen_register_pirq(gsi, gsi_override, triggering, true);
fef6e262 KRW	128
	129	setup_gsi.gsi = gsi;
	130	setup_gsi.triggering = (triggering == ACPI_EDGE_SENSITIVE ? 0 : 1);
	131	setup_gsi.polarity = (polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
	132
	133	rc = HYPERVISOR_physdev_op(PHYSDEVOP_setup_gsi, &setup_gsi);
	134	if (rc == -EEXIST)
	135	printk(KERN_INFO "Already setup the GSI :%d\n", gsi);
	136	else if (rc) {
	137	printk(KERN_ERR "Failed to setup GSI :%d, err_code:%d\n",
	138	gsi, rc);
	139	}
	140
	141	return irq;
	142	}
	143
	144	static int acpi_register_gsi_xen(struct device *dev, u32 gsi,
	145	int trigger, int polarity)
	146	{
	147	return xen_register_gsi(gsi, -1 /* no GSI override */, trigger, polarity);
	148	}
	149	#endif
d92edd81	150	#endif
fef6e262	151
b5401a96 AN	152	#if defined(CONFIG_PCI_MSI)
b5401a96 AN	153	#include <linux/msi.h>
809f9267	154	#include <asm/msidef.h>
b5401a96 AN	155
	156	struct xen_pci_frontend_ops *xen_pci_frontend;
	157	EXPORT_SYMBOL_GPL(xen_pci_frontend);
	158
fef6e262 KRW	159	static int xen_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
	160	{
	161	int irq, ret, i;
	162	struct msi_desc *msidesc;
	163	int *v;
	164
884ac297 KRW	165	if (type == PCI_CAP_ID_MSI && nvec > 1)
	166	return 1;
	167
fef6e262 KRW	168	v = kzalloc(sizeof(int) * max(1, nvec), GFP_KERNEL);
	169	if (!v)
	170	return -ENOMEM;
	171
	172	if (type == PCI_CAP_ID_MSIX)
	173	ret = xen_pci_frontend_enable_msix(dev, v, nvec);
	174	else
	175	ret = xen_pci_frontend_enable_msi(dev, v);
	176	if (ret)
	177	goto error;
	178	i = 0;
	179	list_for_each_entry(msidesc, &dev->msi_list, list) {
dec02dea	180	irq = xen_bind_pirq_msi_to_irq(dev, msidesc, v[i],
4892c9b4	181	(type == PCI_CAP_ID_MSI) ? nvec : 1,
fef6e262 KRW	182	(type == PCI_CAP_ID_MSIX) ?
	183	"pcifront-msi-x" :
	184	"pcifront-msi",
	185	DOMID_SELF);
e6599225 KRW	186	if (irq < 0) {
e6599225 KRW	187	ret = irq;
fef6e262	188	goto free;
e6599225	189	}
fef6e262 KRW	190	i++;
	191	}
	192	kfree(v);
	193	return 0;
	194
	195	error:
	196	dev_err(&dev->dev, "Xen PCI frontend has not registered MSI/MSI-X support!\n");
	197	free:
	198	kfree(v);
	199	return ret;
	200	}
	201
af42b8d1 SS	202	#define XEN_PIRQ_MSI_DATA (MSI_DATA_TRIGGER_EDGE \| \
	203	MSI_DATA_LEVEL_ASSERT \| (3 << 8) \| MSI_DATA_VECTOR(0))
	204
809f9267 SS	205	static void xen_msi_compose_msg(struct pci_dev *pdev, unsigned int pirq,
	206	struct msi_msg *msg)
	207	{
	208	/* We set vector == 0 to tell the hypervisor we don't care about it,
	209	* but we want a pirq setup instead.
	210	* We use the dest_id field to pass the pirq that we want. */
	211	msg->address_hi = MSI_ADDR_BASE_HI \| MSI_ADDR_EXT_DEST_ID(pirq);
	212	msg->address_lo =
	213	MSI_ADDR_BASE_LO \|
	214	MSI_ADDR_DEST_MODE_PHYSICAL \|
	215	MSI_ADDR_REDIRECTION_CPU \|
	216	MSI_ADDR_DEST_ID(pirq);
	217
af42b8d1	218	msg->data = XEN_PIRQ_MSI_DATA;
809f9267 SS	219	}
	220
	221	static int xen_hvm_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
	222	{
bf480d95	223	int irq, pirq;
809f9267 SS	224	struct msi_desc *msidesc;
	225	struct msi_msg msg;
	226
884ac297 KRW	227	if (type == PCI_CAP_ID_MSI && nvec > 1)
	228	return 1;
	229
809f9267	230	list_for_each_entry(msidesc, &dev->msi_list, list) {
af42b8d1 SS	231	__read_msi_msg(msidesc, &msg);
	232	pirq = MSI_ADDR_EXT_DEST_ID(msg.address_hi) \|
	233	((msg.address_lo >> MSI_ADDR_DEST_ID_SHIFT) & 0xff);
bf480d95 IC	234	if (msg.data != XEN_PIRQ_MSI_DATA \|\|
	235	xen_irq_from_pirq(pirq) < 0) {
	236	pirq = xen_allocate_pirq_msi(dev, msidesc);
e6599225 KRW	237	if (pirq < 0) {
e6599225 KRW	238	irq = -ENODEV;
af42b8d1	239	goto error;
e6599225	240	}
bf480d95 IC	241	xen_msi_compose_msg(dev, pirq, &msg);
	242	__write_msi_msg(msidesc, &msg);
	243	dev_dbg(&dev->dev, "xen: msi bound to pirq=%d\n", pirq);
	244	} else {
	245	dev_dbg(&dev->dev,
	246	"xen: msi already bound to pirq=%d\n", pirq);
af42b8d1	247	}
dec02dea	248	irq = xen_bind_pirq_msi_to_irq(dev, msidesc, pirq,
4892c9b4	249	(type == PCI_CAP_ID_MSI) ? nvec : 1,
bf480d95	250	(type == PCI_CAP_ID_MSIX) ?
beafbdc1 KRW	251	"msi-x" : "msi",
beafbdc1 KRW	252	DOMID_SELF);
bf480d95	253	if (irq < 0)
809f9267	254	goto error;
bf480d95 IC	255	dev_dbg(&dev->dev,
bf480d95 IC	256	"xen: msi --> pirq=%d --> irq=%d\n", pirq, irq);
809f9267 SS	257	}
	258	return 0;
	259
809f9267	260	error:
bf480d95 IC	261	dev_err(&dev->dev,
bf480d95 IC	262	"Xen PCI frontend has not registered MSI/MSI-X support!\n");
e6599225	263	return irq;
809f9267 SS	264	}
809f9267 SS	265
260a7d4c	266	#ifdef CONFIG_XEN_DOM0
55e901fc JB	267	static bool __read_mostly pci_seg_supported = true;
55e901fc JB	268
f731e3ef QH	269	static int xen_initdom_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
f731e3ef QH	270	{
71eef7d1	271	int ret = 0;
f731e3ef QH	272	struct msi_desc *msidesc;
	273
	274	list_for_each_entry(msidesc, &dev->msi_list, list) {
71eef7d1	275	struct physdev_map_pirq map_irq;
beafbdc1 KRW	276	domid_t domid;
	277
	278	domid = ret = xen_find_device_domain_owner(dev);
	279	/* N.B. Casting int's -ENODEV to uint16_t results in 0xFFED,
	280	* hence check ret value for < 0. */
	281	if (ret < 0)
	282	domid = DOMID_SELF;
71eef7d1 IC	283
71eef7d1 IC	284	memset(&map_irq, 0, sizeof(map_irq));
beafbdc1	285	map_irq.domid = domid;
55e901fc	286	map_irq.type = MAP_PIRQ_TYPE_MSI_SEG;
71eef7d1 IC	287	map_irq.index = -1;
71eef7d1 IC	288	map_irq.pirq = -1;
55e901fc JB	289	map_irq.bus = dev->bus->number \|
55e901fc JB	290	(pci_domain_nr(dev->bus) << 16);
71eef7d1 IC	291	map_irq.devfn = dev->devfn;
71eef7d1 IC	292
4892c9b4 RPM	293	if (type == PCI_CAP_ID_MSI && nvec > 1) {
	294	map_irq.type = MAP_PIRQ_TYPE_MULTI_MSI;
	295	map_irq.entry_nr = nvec;
	296	} else if (type == PCI_CAP_ID_MSIX) {
71eef7d1 IC	297	int pos;
	298	u32 table_offset, bir;
	299
7c86617d	300	pos = dev->msix_cap;
71eef7d1 IC	301	pci_read_config_dword(dev, pos + PCI_MSIX_TABLE,
71eef7d1 IC	302	&table_offset);
4be6bfe2	303	bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
71eef7d1 IC	304
	305	map_irq.table_base = pci_resource_start(dev, bir);
	306	map_irq.entry_nr = msidesc->msi_attrib.entry_nr;
	307	}
	308
55e901fc JB	309	ret = -EINVAL;
	310	if (pci_seg_supported)
	311	ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq,
	312	&map_irq);
4892c9b4 RPM	313	if (type == PCI_CAP_ID_MSI && nvec > 1 && ret) {
	314	/*
	315	* If MAP_PIRQ_TYPE_MULTI_MSI is not available
	316	* there's nothing else we can do in this case.
	317	* Just set ret > 0 so driver can retry with
	318	* single MSI.
	319	*/
	320	ret = 1;
	321	goto out;
	322	}
55e901fc JB	323	if (ret == -EINVAL && !pci_domain_nr(dev->bus)) {
	324	map_irq.type = MAP_PIRQ_TYPE_MSI;
	325	map_irq.index = -1;
	326	map_irq.pirq = -1;
	327	map_irq.bus = dev->bus->number;
	328	ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq,
	329	&map_irq);
	330	if (ret != -EINVAL)
	331	pci_seg_supported = false;
	332	}
71eef7d1	333	if (ret) {
beafbdc1 KRW	334	dev_warn(&dev->dev, "xen map irq failed %d for %d domain\n",
beafbdc1 KRW	335	ret, domid);
71eef7d1 IC	336	goto out;
	337	}
	338
4892c9b4 RPM	339	ret = xen_bind_pirq_msi_to_irq(dev, msidesc, map_irq.pirq,
	340	(type == PCI_CAP_ID_MSI) ? nvec : 1,
	341	(type == PCI_CAP_ID_MSIX) ? "msi-x" : "msi",
	342	domid);
71eef7d1 IC	343	if (ret < 0)
71eef7d1 IC	344	goto out;
f731e3ef	345	}
71eef7d1 IC	346	ret = 0;
	347	out:
	348	return ret;
f731e3ef	349	}
8605c684	350
ac8344c4	351	static void xen_initdom_restore_msi_irqs(struct pci_dev *dev)
8605c684 TL	352	{
	353	int ret = 0;
	354
	355	if (pci_seg_supported) {
	356	struct physdev_pci_device restore_ext;
	357
	358	restore_ext.seg = pci_domain_nr(dev->bus);
	359	restore_ext.bus = dev->bus->number;
	360	restore_ext.devfn = dev->devfn;
	361	ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi_ext,
	362	&restore_ext);
	363	if (ret == -ENOSYS)
	364	pci_seg_supported = false;
	365	WARN(ret && ret != -ENOSYS, "restore_msi_ext -> %d\n", ret);
	366	}
	367	if (!pci_seg_supported) {
	368	struct physdev_restore_msi restore;
	369
	370	restore.bus = dev->bus->number;
	371	restore.devfn = dev->devfn;
	372	ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi, &restore);
	373	WARN(ret && ret != -ENOSYS, "restore_msi -> %d\n", ret);
	374	}
	375	}
b5401a96 AN	376	#endif
b5401a96 AN	377
fef6e262	378	static void xen_teardown_msi_irqs(struct pci_dev *dev)
b5401a96	379	{
fef6e262	380	struct msi_desc *msidesc;
b5401a96	381
fef6e262 KRW	382	msidesc = list_entry(dev->msi_list.next, struct msi_desc, list);
	383	if (msidesc->msi_attrib.is_msix)
	384	xen_pci_frontend_disable_msix(dev);
	385	else
	386	xen_pci_frontend_disable_msi(dev);
b5401a96	387
fef6e262 KRW	388	/* Free the IRQ's and the msidesc using the generic code. */
	389	default_teardown_msi_irqs(dev);
	390	}
f4d0635b	391
fef6e262 KRW	392	static void xen_teardown_msi_irq(unsigned int irq)
	393	{
	394	xen_destroy_irq(irq);
	395	}
0e4ccb15 KRW	396	static u32 xen_nop_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
	397	{
	398	return 0;
	399	}
	400	static u32 xen_nop_msix_mask_irq(struct msi_desc *desc, u32 flag)
	401	{
	402	return 0;
	403	}
fef6e262	404	#endif
3f2a230c	405
b5401a96 AN	406	int __init pci_xen_init(void)
	407	{
	408	if (!xen_pv_domain() \|\| xen_initial_domain())
	409	return -ENODEV;
	410
	411	printk(KERN_INFO "PCI: setting up Xen PCI frontend stub\n");
	412
	413	pcibios_set_cache_line_size();
	414
	415	pcibios_enable_irq = xen_pcifront_enable_irq;
	416	pcibios_disable_irq = NULL;
	417
	418	#ifdef CONFIG_ACPI
	419	/* Keep ACPI out of the picture */
	420	acpi_noirq = 1;
	421	#endif
	422
b5401a96 AN	423	#ifdef CONFIG_PCI_MSI
	424	x86_msi.setup_msi_irqs = xen_setup_msi_irqs;
	425	x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
	426	x86_msi.teardown_msi_irqs = xen_teardown_msi_irqs;
0e4ccb15 KRW	427	x86_msi.msi_mask_irq = xen_nop_msi_mask_irq;
0e4ccb15 KRW	428	x86_msi.msix_mask_irq = xen_nop_msix_mask_irq;
b5401a96 AN	429	#endif
	430	return 0;
	431	}
3942b740 SS	432
	433	int __init pci_xen_hvm_init(void)
	434	{
207d543f	435	if (!xen_have_vector_callback \|\| !xen_feature(XENFEAT_hvm_pirqs))
3942b740 SS	436	return 0;
	437
	438	#ifdef CONFIG_ACPI
	439	/*
	440	* We don't want to change the actual ACPI delivery model,
	441	* just how GSIs get registered.
	442	*/
	443	__acpi_register_gsi = acpi_register_gsi_xen_hvm;
	444	#endif
809f9267 SS	445
	446	#ifdef CONFIG_PCI_MSI
	447	x86_msi.setup_msi_irqs = xen_hvm_setup_msi_irqs;
	448	x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
	449	#endif
3942b740 SS	450	return 0;
3942b740 SS	451	}
38aa66fc JF	452
38aa66fc JF	453	#ifdef CONFIG_XEN_DOM0
38aa66fc JF	454	static __init void xen_setup_acpi_sci(void)
	455	{
	456	int rc;
	457	int trigger, polarity;
	458	int gsi = acpi_sci_override_gsi;
ee339fe6 KRW	459	int irq = -1;
ee339fe6 KRW	460	int gsi_override = -1;
38aa66fc JF	461
	462	if (!gsi)
	463	return;
	464
	465	rc = acpi_get_override_irq(gsi, &trigger, &polarity);
	466	if (rc) {
	467	printk(KERN_WARNING "xen: acpi_get_override_irq failed for acpi"
	468	" sci, rc=%d\n", rc);
	469	return;
	470	}
	471	trigger = trigger ? ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE;
	472	polarity = polarity ? ACPI_ACTIVE_LOW : ACPI_ACTIVE_HIGH;
996c34ae	473
38aa66fc JF	474	printk(KERN_INFO "xen: sci override: global_irq=%d trigger=%d "
	475	"polarity=%d\n", gsi, trigger, polarity);
	476
ee339fe6 KRW	477	/* Before we bind the GSI to a Linux IRQ, check whether
	478	* we need to override it with bus_irq (IRQ) value. Usually for
	479	* IRQs below IRQ_LEGACY_IRQ this holds IRQ == GSI, as so:
	480	* ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level)
	481	* but there are oddballs where the IRQ != GSI:
	482	* ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 20 low level)
	483	* which ends up being: gsi_to_irq[9] == 20
	484	* (which is what acpi_gsi_to_irq ends up calling when starting the
	485	* the ACPI interpreter and keels over since IRQ 9 has not been
	486	* setup as we had setup IRQ 20 for it).
	487	*/
ee339fe6	488	if (acpi_gsi_to_irq(gsi, &irq) == 0) {
97ffab1f KRW	489	/* Use the provided value if it's valid. */
97ffab1f KRW	490	if (irq >= 0)
ee339fe6 KRW	491	gsi_override = irq;
	492	}
	493
	494	gsi = xen_register_gsi(gsi, gsi_override, trigger, polarity);
38aa66fc JF	495	printk(KERN_INFO "xen: acpi sci %d\n", gsi);
	496
	497	return;
	498	}
a0ee0567 KRW	499
a0ee0567 KRW	500	int __init pci_xen_initial_domain(void)
38aa66fc	501	{
78316ada	502	int irq;
a0ee0567	503
f731e3ef QH	504	#ifdef CONFIG_PCI_MSI
	505	x86_msi.setup_msi_irqs = xen_initdom_setup_msi_irqs;
	506	x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
8605c684	507	x86_msi.restore_msi_irqs = xen_initdom_restore_msi_irqs;
0e4ccb15 KRW	508	x86_msi.msi_mask_irq = xen_nop_msi_mask_irq;
0e4ccb15 KRW	509	x86_msi.msix_mask_irq = xen_nop_msix_mask_irq;
f731e3ef	510	#endif
38aa66fc JF	511	xen_setup_acpi_sci();
38aa66fc JF	512	__acpi_register_gsi = acpi_register_gsi_xen;
38aa66fc JF	513	/* Pre-allocate legacy irqs */
	514	for (irq = 0; irq < NR_IRQS_LEGACY; irq++) {
	515	int trigger, polarity;
	516
	517	if (acpi_get_override_irq(irq, &trigger, &polarity) == -1)
	518	continue;
	519
ee339fe6	520	xen_register_pirq(irq, -1 /* no GSI override */,
ed89eb63	521	trigger ? ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE,
78316ada	522	true /* Map GSI to PIRQ */);
38aa66fc	523	}
9b6519db	524	if (0 == nr_ioapics) {
78316ada KRW	525	for (irq = 0; irq < NR_IRQS_LEGACY; irq++)
78316ada KRW	526	xen_bind_pirq_gsi_to_irq(irq, irq, 0, "xt-pic");
9b6519db	527	}
a0ee0567	528	return 0;
38aa66fc	529	}
c55fa78b KRW	530
	531	struct xen_device_domain_owner {
	532	domid_t domain;
	533	struct pci_dev *dev;
	534	struct list_head list;
	535	};
	536
	537	static DEFINE_SPINLOCK(dev_domain_list_spinlock);
	538	static struct list_head dev_domain_list = LIST_HEAD_INIT(dev_domain_list);
	539
	540	static struct xen_device_domain_owner find_device(struct pci_dev dev)
	541	{
	542	struct xen_device_domain_owner *owner;
	543
	544	list_for_each_entry(owner, &dev_domain_list, list) {
	545	if (owner->dev == dev)
	546	return owner;
	547	}
	548	return NULL;
	549	}
	550
	551	int xen_find_device_domain_owner(struct pci_dev *dev)
	552	{
	553	struct xen_device_domain_owner *owner;
	554	int domain = -ENODEV;
	555
	556	spin_lock(&dev_domain_list_spinlock);
	557	owner = find_device(dev);
	558	if (owner)
	559	domain = owner->domain;
	560	spin_unlock(&dev_domain_list_spinlock);
	561	return domain;
	562	}
	563	EXPORT_SYMBOL_GPL(xen_find_device_domain_owner);
	564
	565	int xen_register_device_domain_owner(struct pci_dev *dev, uint16_t domain)
	566	{
	567	struct xen_device_domain_owner *owner;
	568
	569	owner = kzalloc(sizeof(struct xen_device_domain_owner), GFP_KERNEL);
	570	if (!owner)
	571	return -ENODEV;
	572
	573	spin_lock(&dev_domain_list_spinlock);
	574	if (find_device(dev)) {
	575	spin_unlock(&dev_domain_list_spinlock);
	576	kfree(owner);
	577	return -EEXIST;
	578	}
	579	owner->domain = domain;
	580	owner->dev = dev;
	581	list_add_tail(&owner->list, &dev_domain_list);
	582	spin_unlock(&dev_domain_list_spinlock);
	583	return 0;
	584	}
	585	EXPORT_SYMBOL_GPL(xen_register_device_domain_owner);
	586
	587	int xen_unregister_device_domain_owner(struct pci_dev *dev)
	588	{
	589	struct xen_device_domain_owner *owner;
	590
	591	spin_lock(&dev_domain_list_spinlock);
	592	owner = find_device(dev);
	593	if (!owner) {
594	spin_unlock(&dev_domain_list_spinlock);
595	return -ENODEV;
596	}
597	list_del(&owner->list);
598	spin_unlock(&dev_domain_list_spinlock);
599	kfree(owner);
600	return 0;
601	}
602	EXPORT_SYMBOL_GPL(xen_unregister_device_domain_owner);
7c1bfd68	603	#endif