[deliverable/linux.git] / arch / x86 / platform / intel-mid / sfi.c

/*
 * intel_mid_sfi.c: Intel MID SFI initialization code
 *
 * (C) Copyright 2013 Intel Corporation
 * Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; version 2
 * of the License.
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/scatterlist.h>
#include <linux/sfi.h>
#include <linux/intel_pmic_gpio.h>
#include <linux/spi/spi.h>
#include <linux/i2c.h>
#include <linux/skbuff.h>
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/notifier.h>
#include <linux/mmc/core.h>
#include <linux/mmc/card.h>
#include <linux/blkdev.h>

#include <asm/setup.h>
#include <asm/mpspec_def.h>
#include <asm/hw_irq.h>
#include <asm/apic.h>
#include <asm/io_apic.h>
#include <asm/intel-mid.h>
#include <asm/intel_mid_vrtc.h>
#include <asm/io.h>
#include <asm/i8259.h>
#include <asm/intel_scu_ipc.h>
#include <asm/apb_timer.h>
#include <asm/reboot.h>

#define	SFI_SIG_OEM0	"OEM0"
#define MAX_IPCDEVS	24
#define MAX_SCU_SPI	24
#define MAX_SCU_I2C	24

static struct platform_device *ipc_devs[MAX_IPCDEVS];
static struct spi_board_info *spi_devs[MAX_SCU_SPI];
static struct i2c_board_info *i2c_devs[MAX_SCU_I2C];
static struct sfi_gpio_table_entry *gpio_table;
static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
static int ipc_next_dev;
static int spi_next_dev;
static int i2c_next_dev;
static int i2c_bus[MAX_SCU_I2C];
static int gpio_num_entry;
static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
int sfi_mrtc_num;
int sfi_mtimer_num;

struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];
EXPORT_SYMBOL_GPL(sfi_mrtc_array);

struct blocking_notifier_head intel_scu_notifier =
			BLOCKING_NOTIFIER_INIT(intel_scu_notifier);
EXPORT_SYMBOL_GPL(intel_scu_notifier);

#define intel_mid_sfi_get_pdata(dev, priv)	\
	((dev)->get_platform_data ? (dev)->get_platform_data(priv) : NULL)

/* parse all the mtimer info to a static mtimer array */
int __init sfi_parse_mtmr(struct sfi_table_header *table)
{
	struct sfi_table_simple *sb;
	struct sfi_timer_table_entry *pentry;
	struct mpc_intsrc mp_irq;
	int totallen;

	sb = (struct sfi_table_simple *)table;
	if (!sfi_mtimer_num) {
		sfi_mtimer_num = SFI_GET_NUM_ENTRIES(sb,
					struct sfi_timer_table_entry);
		pentry = (struct sfi_timer_table_entry *) sb->pentry;
		totallen = sfi_mtimer_num * sizeof(*pentry);
		memcpy(sfi_mtimer_array, pentry, totallen);
	}

	pr_debug("SFI MTIMER info (num = %d):\n", sfi_mtimer_num);
	pentry = sfi_mtimer_array;
	for (totallen = 0; totallen < sfi_mtimer_num; totallen++, pentry++) {
		pr_debug("timer[%d]: paddr = 0x%08x, freq = %dHz, irq = %d\n",
			totallen, (u32)pentry->phys_addr,
			pentry->freq_hz, pentry->irq);
			if (!pentry->irq)
				continue;
			mp_irq.type = MP_INTSRC;
			mp_irq.irqtype = mp_INT;
/* triggering mode edge bit 2-3, active high polarity bit 0-1 */
			mp_irq.irqflag = 5;
			mp_irq.srcbus = MP_BUS_ISA;
			mp_irq.srcbusirq = pentry->irq;	/* IRQ */
			mp_irq.dstapic = MP_APIC_ALL;
			mp_irq.dstirq = pentry->irq;
			mp_save_irq(&mp_irq);
	}

	return 0;
}

struct sfi_timer_table_entry *sfi_get_mtmr(int hint)
{
	int i;
	if (hint < sfi_mtimer_num) {
		if (!sfi_mtimer_usage[hint]) {
			pr_debug("hint taken for timer %d irq %d\n",
				hint, sfi_mtimer_array[hint].irq);
			sfi_mtimer_usage[hint] = 1;
			return &sfi_mtimer_array[hint];
		}
	}
	/* take the first timer available */
	for (i = 0; i < sfi_mtimer_num;) {
		if (!sfi_mtimer_usage[i]) {
			sfi_mtimer_usage[i] = 1;
			return &sfi_mtimer_array[i];
		}
		i++;
	}
	return NULL;
}

void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr)
{
	int i;
	for (i = 0; i < sfi_mtimer_num;) {
		if (mtmr->irq == sfi_mtimer_array[i].irq) {
			sfi_mtimer_usage[i] = 0;
			return;
		}
		i++;
	}
}

/* parse all the mrtc info to a global mrtc array */
int __init sfi_parse_mrtc(struct sfi_table_header *table)
{
	struct sfi_table_simple *sb;
	struct sfi_rtc_table_entry *pentry;
	struct mpc_intsrc mp_irq;

	int totallen;

	sb = (struct sfi_table_simple *)table;
	if (!sfi_mrtc_num) {
		sfi_mrtc_num = SFI_GET_NUM_ENTRIES(sb,
						struct sfi_rtc_table_entry);
		pentry = (struct sfi_rtc_table_entry *)sb->pentry;
		totallen = sfi_mrtc_num * sizeof(*pentry);
		memcpy(sfi_mrtc_array, pentry, totallen);
	}

	pr_debug("SFI RTC info (num = %d):\n", sfi_mrtc_num);
	pentry = sfi_mrtc_array;
	for (totallen = 0; totallen < sfi_mrtc_num; totallen++, pentry++) {
		pr_debug("RTC[%d]: paddr = 0x%08x, irq = %d\n",
			totallen, (u32)pentry->phys_addr, pentry->irq);
		mp_irq.type = MP_INTSRC;
		mp_irq.irqtype = mp_INT;
		mp_irq.irqflag = 0xf;	/* level trigger and active low */
		mp_irq.srcbus = MP_BUS_ISA;
		mp_irq.srcbusirq = pentry->irq;	/* IRQ */
		mp_irq.dstapic = MP_APIC_ALL;
		mp_irq.dstirq = pentry->irq;
		mp_save_irq(&mp_irq);
	}
	return 0;
}


/*
 * Parsing GPIO table first, since the DEVS table will need this table
 * to map the pin name to the actual pin.
 */
static int __init sfi_parse_gpio(struct sfi_table_header *table)
{
	struct sfi_table_simple *sb;
	struct sfi_gpio_table_entry *pentry;
	int num, i;

	if (gpio_table)
		return 0;
	sb = (struct sfi_table_simple *)table;
	num = SFI_GET_NUM_ENTRIES(sb, struct sfi_gpio_table_entry);
	pentry = (struct sfi_gpio_table_entry *)sb->pentry;

	gpio_table = kmalloc(num * sizeof(*pentry), GFP_KERNEL);
	if (!gpio_table)
		return -1;
	memcpy(gpio_table, pentry, num * sizeof(*pentry));
	gpio_num_entry = num;

	pr_debug("GPIO pin info:\n");
	for (i = 0; i < num; i++, pentry++)
		pr_debug("info[%2d]: controller = %16.16s, pin_name = %16.16s,"
		" pin = %d\n", i,
			pentry->controller_name,
			pentry->pin_name,
			pentry->pin_no);
	return 0;
}

int get_gpio_by_name(const char *name)
{
	struct sfi_gpio_table_entry *pentry = gpio_table;
	int i;

	if (!pentry)
		return -1;
	for (i = 0; i < gpio_num_entry; i++, pentry++) {
		if (!strncmp(name, pentry->pin_name, SFI_NAME_LEN))
			return pentry->pin_no;
	}
	return -EINVAL;
}

void __init intel_scu_device_register(struct platform_device *pdev)
{
	if (ipc_next_dev == MAX_IPCDEVS)
		pr_err("too many SCU IPC devices");
	else
		ipc_devs[ipc_next_dev++] = pdev;
}

static void __init intel_scu_spi_device_register(struct spi_board_info *sdev)
{
	struct spi_board_info *new_dev;

	if (spi_next_dev == MAX_SCU_SPI) {
		pr_err("too many SCU SPI devices");
		return;
	}

	new_dev = kzalloc(sizeof(*sdev), GFP_KERNEL);
	if (!new_dev) {
		pr_err("failed to alloc mem for delayed spi dev %s\n",
			sdev->modalias);
		return;
	}
	*new_dev = *sdev;

	spi_devs[spi_next_dev++] = new_dev;
}

static void __init intel_scu_i2c_device_register(int bus,
						struct i2c_board_info *idev)
{
	struct i2c_board_info *new_dev;

	if (i2c_next_dev == MAX_SCU_I2C) {
		pr_err("too many SCU I2C devices");
		return;
	}

	new_dev = kzalloc(sizeof(*idev), GFP_KERNEL);
	if (!new_dev) {
		pr_err("failed to alloc mem for delayed i2c dev %s\n",
			idev->type);
		return;
	}
	*new_dev = *idev;

	i2c_bus[i2c_next_dev] = bus;
	i2c_devs[i2c_next_dev++] = new_dev;
}

/* Called by IPC driver */
void intel_scu_devices_create(void)
{
	int i;

	for (i = 0; i < ipc_next_dev; i++)
		platform_device_add(ipc_devs[i]);

	for (i = 0; i < spi_next_dev; i++)
		spi_register_board_info(spi_devs[i], 1);

	for (i = 0; i < i2c_next_dev; i++) {
		struct i2c_adapter *adapter;
		struct i2c_client *client;

		adapter = i2c_get_adapter(i2c_bus[i]);
		if (adapter) {
			client = i2c_new_device(adapter, i2c_devs[i]);
			if (!client)
				pr_err("can't create i2c device %s\n",
					i2c_devs[i]->type);
		} else
			i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1);
	}
	intel_scu_notifier_post(SCU_AVAILABLE, NULL);
}
EXPORT_SYMBOL_GPL(intel_scu_devices_create);

/* Called by IPC driver */
void intel_scu_devices_destroy(void)
{
	int i;

	intel_scu_notifier_post(SCU_DOWN, NULL);

	for (i = 0; i < ipc_next_dev; i++)
		platform_device_del(ipc_devs[i]);
}
EXPORT_SYMBOL_GPL(intel_scu_devices_destroy);

static void __init install_irq_resource(struct platform_device *pdev, int irq)
{
	/* Single threaded */
	static struct resource res __initdata = {
		.name = "IRQ",
		.flags = IORESOURCE_IRQ,
	};
	res.start = irq;
	platform_device_add_resources(pdev, &res, 1);
}

static void __init sfi_handle_ipc_dev(struct sfi_device_table_entry *pentry,
					struct devs_id *dev)
{
	struct platform_device *pdev;
	void *pdata = NULL;

	pr_debug("IPC bus, name = %16.16s, irq = 0x%2x\n",
		pentry->name, pentry->irq);
	pdata = intel_mid_sfi_get_pdata(dev, pentry);
	if (IS_ERR(pdata))
		return;

	pdev = platform_device_alloc(pentry->name, 0);
	if (pdev == NULL) {
		pr_err("out of memory for SFI platform device '%s'.\n",
			pentry->name);
		return;
	}
	install_irq_resource(pdev, pentry->irq);

	pdev->dev.platform_data = pdata;
	platform_device_add(pdev);
}

static void __init sfi_handle_spi_dev(struct sfi_device_table_entry *pentry,
					struct devs_id *dev)
{
	struct spi_board_info spi_info;
	void *pdata = NULL;

	memset(&spi_info, 0, sizeof(spi_info));
	strncpy(spi_info.modalias, pentry->name, SFI_NAME_LEN);
	spi_info.irq = ((pentry->irq == (u8)0xff) ? 0 : pentry->irq);
	spi_info.bus_num = pentry->host_num;
	spi_info.chip_select = pentry->addr;
	spi_info.max_speed_hz = pentry->max_freq;
	pr_debug("SPI bus=%d, name=%16.16s, irq=0x%2x, max_freq=%d, cs=%d\n",
		spi_info.bus_num,
		spi_info.modalias,
		spi_info.irq,
		spi_info.max_speed_hz,
		spi_info.chip_select);

	pdata = intel_mid_sfi_get_pdata(dev, &spi_info);
	if (IS_ERR(pdata))
		return;

	spi_info.platform_data = pdata;
	if (dev->delay)
		intel_scu_spi_device_register(&spi_info);
	else
		spi_register_board_info(&spi_info, 1);
}

static void __init sfi_handle_i2c_dev(struct sfi_device_table_entry *pentry,
					struct devs_id *dev)
{
	struct i2c_board_info i2c_info;
	void *pdata = NULL;

	memset(&i2c_info, 0, sizeof(i2c_info));
	strncpy(i2c_info.type, pentry->name, SFI_NAME_LEN);
	i2c_info.irq = ((pentry->irq == (u8)0xff) ? 0 : pentry->irq);
	i2c_info.addr = pentry->addr;
	pr_debug("I2C bus = %d, name = %16.16s, irq = 0x%2x, addr = 0x%x\n",
		pentry->host_num,
		i2c_info.type,
		i2c_info.irq,
		i2c_info.addr);
	pdata = intel_mid_sfi_get_pdata(dev, &i2c_info);
	i2c_info.platform_data = pdata;
	if (IS_ERR(pdata))
		return;

	if (dev->delay)
		intel_scu_i2c_device_register(pentry->host_num, &i2c_info);
	else
		i2c_register_board_info(pentry->host_num, &i2c_info, 1);
}

extern struct devs_id *const __x86_intel_mid_dev_start[],
		      *const __x86_intel_mid_dev_end[];

static struct devs_id __init *get_device_id(u8 type, char *name)
{
	struct devs_id *const *dev_table;

	for (dev_table = __x86_intel_mid_dev_start;
			dev_table < __x86_intel_mid_dev_end; dev_table++) {
		struct devs_id *dev = *dev_table;
		if (dev->type == type &&
			!strncmp(dev->name, name, SFI_NAME_LEN)) {
			return dev;
		}
	}

	return NULL;
}

static int __init sfi_parse_devs(struct sfi_table_header *table)
{
	struct sfi_table_simple *sb;
	struct sfi_device_table_entry *pentry;
	struct devs_id *dev = NULL;
	int num, i;
	int ioapic;
	struct io_apic_irq_attr irq_attr;

	sb = (struct sfi_table_simple *)table;
	num = SFI_GET_NUM_ENTRIES(sb, struct sfi_device_table_entry);
	pentry = (struct sfi_device_table_entry *)sb->pentry;

	for (i = 0; i < num; i++, pentry++) {
		int irq = pentry->irq;

		if (irq != (u8)0xff) { /* native RTE case */
			/* these SPI2 devices are not exposed to system as PCI
			 * devices, but they have separate RTE entry in IOAPIC
			 * so we have to enable them one by one here
			 */
			ioapic = mp_find_ioapic(irq);
			if (ioapic >= 0) {
				irq_attr.ioapic = ioapic;
				irq_attr.ioapic_pin = irq;
				irq_attr.trigger = 1;
				if (intel_mid_identify_cpu() ==
						INTEL_MID_CPU_CHIP_TANGIER) {
					if (!strncmp(pentry->name,
							"r69001-ts-i2c", 13))
						/* active low */
						irq_attr.polarity = 1;
					else if (!strncmp(pentry->name,
							"synaptics_3202", 14))
						/* active low */
						irq_attr.polarity = 1;
					else if (irq == 41)
						/* fast_int_1 */
						irq_attr.polarity = 1;
					else
						/* active high */
						irq_attr.polarity = 0;
				} else {
					/* PNW and CLV go with active low */
					irq_attr.polarity = 1;
				}
				WARN_ON(mp_map_gsi_to_irq(irq,
						IOAPIC_MAP_ALLOC) < 0);
				io_apic_set_pci_routing(NULL, irq, &irq_attr);
			}
		} else {
			irq = 0; /* No irq */
		}

		dev = get_device_id(pentry->type, pentry->name);

		if (!dev)
			continue;

		if (dev->device_handler) {
			dev->device_handler(pentry, dev);
		} else {
			switch (pentry->type) {
			case SFI_DEV_TYPE_IPC:
				sfi_handle_ipc_dev(pentry, dev);
				break;
			case SFI_DEV_TYPE_SPI:
				sfi_handle_spi_dev(pentry, dev);
				break;
			case SFI_DEV_TYPE_I2C:
				sfi_handle_i2c_dev(pentry, dev);
				break;
			case SFI_DEV_TYPE_UART:
			case SFI_DEV_TYPE_HSI:
			default:
				break;
			}
		}
	}
	return 0;
}

static int __init intel_mid_platform_init(void)
{
	sfi_table_parse(SFI_SIG_GPIO, NULL, NULL, sfi_parse_gpio);
	sfi_table_parse(SFI_SIG_DEVS, NULL, NULL, sfi_parse_devs);
	return 0;
}
arch_initcall(intel_mid_platform_init);
Commit	Line	Data
aeedb370 KS	1	/*
	2	* intel_mid_sfi.c: Intel MID SFI initialization code
	3	*
	4	* (C) Copyright 2013 Intel Corporation
	5	* Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* as published by the Free Software Foundation; version 2
	10	* of the License.
	11	*/
	12
	13	#include <linux/init.h>
	14	#include <linux/kernel.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/scatterlist.h>
	17	#include <linux/sfi.h>
	18	#include <linux/intel_pmic_gpio.h>
	19	#include <linux/spi/spi.h>
	20	#include <linux/i2c.h>
	21	#include <linux/skbuff.h>
	22	#include <linux/gpio.h>
	23	#include <linux/gpio_keys.h>
	24	#include <linux/input.h>
	25	#include <linux/platform_device.h>
	26	#include <linux/irq.h>
	27	#include <linux/module.h>
	28	#include <linux/notifier.h>
	29	#include <linux/mmc/core.h>
	30	#include <linux/mmc/card.h>
	31	#include <linux/blkdev.h>
	32
	33	#include <asm/setup.h>
	34	#include <asm/mpspec_def.h>
	35	#include <asm/hw_irq.h>
	36	#include <asm/apic.h>
	37	#include <asm/io_apic.h>
	38	#include <asm/intel-mid.h>
	39	#include <asm/intel_mid_vrtc.h>
	40	#include <asm/io.h>
	41	#include <asm/i8259.h>
	42	#include <asm/intel_scu_ipc.h>
	43	#include <asm/apb_timer.h>
	44	#include <asm/reboot.h>
aeedb370 KS	45
	46	#define SFI_SIG_OEM0 "OEM0"
	47	#define MAX_IPCDEVS 24
	48	#define MAX_SCU_SPI 24
	49	#define MAX_SCU_I2C 24
	50
	51	static struct platform_device *ipc_devs[MAX_IPCDEVS];
	52	static struct spi_board_info *spi_devs[MAX_SCU_SPI];
	53	static struct i2c_board_info *i2c_devs[MAX_SCU_I2C];
	54	static struct sfi_gpio_table_entry *gpio_table;
	55	static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
	56	static int ipc_next_dev;
	57	static int spi_next_dev;
	58	static int i2c_next_dev;
	59	static int i2c_bus[MAX_SCU_I2C];
	60	static int gpio_num_entry;
	61	static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
	62	int sfi_mrtc_num;
	63	int sfi_mtimer_num;
	64
	65	struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];
	66	EXPORT_SYMBOL_GPL(sfi_mrtc_array);
	67
	68	struct blocking_notifier_head intel_scu_notifier =
	69	BLOCKING_NOTIFIER_INIT(intel_scu_notifier);
	70	EXPORT_SYMBOL_GPL(intel_scu_notifier);
	71
0e6fdb5f DC	72	#define intel_mid_sfi_get_pdata(dev, priv) \
	73	((dev)->get_platform_data ? (dev)->get_platform_data(priv) : NULL)
	74
aeedb370 KS	75	/* parse all the mtimer info to a static mtimer array */
	76	int __init sfi_parse_mtmr(struct sfi_table_header *table)
	77	{
	78	struct sfi_table_simple *sb;
	79	struct sfi_timer_table_entry *pentry;
	80	struct mpc_intsrc mp_irq;
	81	int totallen;
	82
	83	sb = (struct sfi_table_simple *)table;
	84	if (!sfi_mtimer_num) {
	85	sfi_mtimer_num = SFI_GET_NUM_ENTRIES(sb,
	86	struct sfi_timer_table_entry);
	87	pentry = (struct sfi_timer_table_entry *) sb->pentry;
	88	totallen = sfi_mtimer_num * sizeof(*pentry);
	89	memcpy(sfi_mtimer_array, pentry, totallen);
	90	}
	91
	92	pr_debug("SFI MTIMER info (num = %d):\n", sfi_mtimer_num);
	93	pentry = sfi_mtimer_array;
	94	for (totallen = 0; totallen < sfi_mtimer_num; totallen++, pentry++) {
	95	pr_debug("timer[%d]: paddr = 0x%08x, freq = %dHz, irq = %d\n",
	96	totallen, (u32)pentry->phys_addr,
	97	pentry->freq_hz, pentry->irq);
	98	if (!pentry->irq)
	99	continue;
	100	mp_irq.type = MP_INTSRC;
	101	mp_irq.irqtype = mp_INT;
	102	/* triggering mode edge bit 2-3, active high polarity bit 0-1 */
	103	mp_irq.irqflag = 5;
	104	mp_irq.srcbus = MP_BUS_ISA;
	105	mp_irq.srcbusirq = pentry->irq; /* IRQ */
	106	mp_irq.dstapic = MP_APIC_ALL;
	107	mp_irq.dstirq = pentry->irq;
	108	mp_save_irq(&mp_irq);
	109	}
	110
	111	return 0;
	112	}
	113
	114	struct sfi_timer_table_entry *sfi_get_mtmr(int hint)
	115	{
	116	int i;
	117	if (hint < sfi_mtimer_num) {
	118	if (!sfi_mtimer_usage[hint]) {
	119	pr_debug("hint taken for timer %d irq %d\n",
	120	hint, sfi_mtimer_array[hint].irq);
	121	sfi_mtimer_usage[hint] = 1;
	122	return &sfi_mtimer_array[hint];
	123	}
	124	}
	125	/* take the first timer available */
	126	for (i = 0; i < sfi_mtimer_num;) {
	127	if (!sfi_mtimer_usage[i]) {
	128	sfi_mtimer_usage[i] = 1;
	129	return &sfi_mtimer_array[i];
	130	}
	131	i++;
	132	}
	133	return NULL;
	134	}
	135
	136	void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr)
	137	{
	138	int i;
139	for (i = 0; i < sfi_mtimer_num;) {
140	if (mtmr->irq == sfi_mtimer_array[i].irq) {
141	sfi_mtimer_usage[i] = 0;
142	return;
143	}
144	i++;
145	}
146	}
147
148	/* parse all the mrtc info to a global mrtc array */
149	int __init sfi_parse_mrtc(struct sfi_table_header *table)
150	{
151	struct sfi_table_simple *sb;
152	struct sfi_rtc_table_entry *pentry;
153	struct mpc_intsrc mp_irq;
154
155	int totallen;
156
157	sb = (struct sfi_table_simple *)table;
158	if (!sfi_mrtc_num) {
159	sfi_mrtc_num = SFI_GET_NUM_ENTRIES(sb,
160	struct sfi_rtc_table_entry);
161	pentry = (struct sfi_rtc_table_entry *)sb->pentry;
162	totallen = sfi_mrtc_num * sizeof(*pentry);
163	memcpy(sfi_mrtc_array, pentry, totallen);
164	}
165
166	pr_debug("SFI RTC info (num = %d):\n", sfi_mrtc_num);
167	pentry = sfi_mrtc_array;
168	for (totallen = 0; totallen < sfi_mrtc_num; totallen++, pentry++) {
169	pr_debug("RTC[%d]: paddr = 0x%08x, irq = %d\n",
170	totallen, (u32)pentry->phys_addr, pentry->irq);
171	mp_irq.type = MP_INTSRC;
172	mp_irq.irqtype = mp_INT;
173	mp_irq.irqflag = 0xf; /* level trigger and active low */
174	mp_irq.srcbus = MP_BUS_ISA;
175	mp_irq.srcbusirq = pentry->irq; /* IRQ */
176	mp_irq.dstapic = MP_APIC_ALL;
177	mp_irq.dstirq = pentry->irq;
178	mp_save_irq(&mp_irq);
179	}
180	return 0;
181	}
182
183
184	/*
185	* Parsing GPIO table first, since the DEVS table will need this table
186	* to map the pin name to the actual pin.
187	*/
188	static int __init sfi_parse_gpio(struct sfi_table_header *table)
189	{
190	struct sfi_table_simple *sb;
191	struct sfi_gpio_table_entry *pentry;
192	int num, i;
193
194	if (gpio_table)
195	return 0;
196	sb = (struct sfi_table_simple *)table;
197	num = SFI_GET_NUM_ENTRIES(sb, struct sfi_gpio_table_entry);
198	pentry = (struct sfi_gpio_table_entry *)sb->pentry;
199
200	gpio_table = kmalloc(num * sizeof(*pentry), GFP_KERNEL);
201	if (!gpio_table)
202	return -1;
203	memcpy(gpio_table, pentry, num * sizeof(*pentry));
204	gpio_num_entry = num;
205
206	pr_debug("GPIO pin info:\n");
207	for (i = 0; i < num; i++, pentry++)
208	pr_debug("info[%2d]: controller = %16.16s, pin_name = %16.16s,"
209	" pin = %d\n", i,
210	pentry->controller_name,
211	pentry->pin_name,
212	pentry->pin_no);
213	return 0;
214	}
215
216	int get_gpio_by_name(const char *name)
217	{
218	struct sfi_gpio_table_entry *pentry = gpio_table;
219	int i;
220
221	if (!pentry)
222	return -1;
223	for (i = 0; i < gpio_num_entry; i++, pentry++) {
224	if (!strncmp(name, pentry->pin_name, SFI_NAME_LEN))
225	return pentry->pin_no;
226	}
28c6a39b	227	return -EINVAL;
aeedb370 KS	228	}
	229
	230	void __init intel_scu_device_register(struct platform_device *pdev)
	231	{
	232	if (ipc_next_dev == MAX_IPCDEVS)
	233	pr_err("too many SCU IPC devices");
	234	else
	235	ipc_devs[ipc_next_dev++] = pdev;
	236	}
	237
	238	static void __init intel_scu_spi_device_register(struct spi_board_info *sdev)
	239	{
	240	struct spi_board_info *new_dev;
	241
	242	if (spi_next_dev == MAX_SCU_SPI) {
	243	pr_err("too many SCU SPI devices");
	244	return;
	245	}
	246
	247	new_dev = kzalloc(sizeof(*sdev), GFP_KERNEL);
	248	if (!new_dev) {
	249	pr_err("failed to alloc mem for delayed spi dev %s\n",
	250	sdev->modalias);
	251	return;
	252	}
ee87c751	253	new_dev = sdev;
aeedb370 KS	254
	255	spi_devs[spi_next_dev++] = new_dev;
	256	}
	257
	258	static void __init intel_scu_i2c_device_register(int bus,
	259	struct i2c_board_info *idev)
	260	{
	261	struct i2c_board_info *new_dev;
	262
	263	if (i2c_next_dev == MAX_SCU_I2C) {
	264	pr_err("too many SCU I2C devices");
	265	return;
	266	}
	267
	268	new_dev = kzalloc(sizeof(*idev), GFP_KERNEL);
	269	if (!new_dev) {
	270	pr_err("failed to alloc mem for delayed i2c dev %s\n",
	271	idev->type);
	272	return;
	273	}
ee87c751	274	new_dev = idev;
aeedb370 KS	275
	276	i2c_bus[i2c_next_dev] = bus;
	277	i2c_devs[i2c_next_dev++] = new_dev;
	278	}
	279
	280	/* Called by IPC driver */
	281	void intel_scu_devices_create(void)
	282	{
	283	int i;
	284
	285	for (i = 0; i < ipc_next_dev; i++)
	286	platform_device_add(ipc_devs[i]);
	287
	288	for (i = 0; i < spi_next_dev; i++)
	289	spi_register_board_info(spi_devs[i], 1);
	290
	291	for (i = 0; i < i2c_next_dev; i++) {
	292	struct i2c_adapter *adapter;
	293	struct i2c_client *client;
	294
	295	adapter = i2c_get_adapter(i2c_bus[i]);
	296	if (adapter) {
	297	client = i2c_new_device(adapter, i2c_devs[i]);
	298	if (!client)
	299	pr_err("can't create i2c device %s\n",
	300	i2c_devs[i]->type);
	301	} else
	302	i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1);
	303	}
	304	intel_scu_notifier_post(SCU_AVAILABLE, NULL);
	305	}
	306	EXPORT_SYMBOL_GPL(intel_scu_devices_create);
	307
	308	/* Called by IPC driver */
	309	void intel_scu_devices_destroy(void)
	310	{
	311	int i;
	312
	313	intel_scu_notifier_post(SCU_DOWN, NULL);
	314
	315	for (i = 0; i < ipc_next_dev; i++)
	316	platform_device_del(ipc_devs[i]);
	317	}
	318	EXPORT_SYMBOL_GPL(intel_scu_devices_destroy);
	319
	320	static void __init install_irq_resource(struct platform_device *pdev, int irq)
	321	{
	322	/* Single threaded */
	323	static struct resource res __initdata = {
	324	.name = "IRQ",
	325	.flags = IORESOURCE_IRQ,
	326	};
	327	res.start = irq;
	328	platform_device_add_resources(pdev, &res, 1);
	329	}
	330
	331	static void __init sfi_handle_ipc_dev(struct sfi_device_table_entry *pentry,
	332	struct devs_id *dev)
	333	{
	334	struct platform_device *pdev;
	335	void *pdata = NULL;
	336
	337	pr_debug("IPC bus, name = %16.16s, irq = 0x%2x\n",
	338	pentry->name, pentry->irq);
0e6fdb5f	339	pdata = intel_mid_sfi_get_pdata(dev, pentry);
acb20d73 DC	340	if (IS_ERR(pdata))
acb20d73 DC	341	return;
aeedb370 KS	342
	343	pdev = platform_device_alloc(pentry->name, 0);
	344	if (pdev == NULL) {
	345	pr_err("out of memory for SFI platform device '%s'.\n",
	346	pentry->name);
	347	return;
	348	}
	349	install_irq_resource(pdev, pentry->irq);
	350
	351	pdev->dev.platform_data = pdata;
	352	platform_device_add(pdev);
	353	}
	354
	355	static void __init sfi_handle_spi_dev(struct sfi_device_table_entry *pentry,
	356	struct devs_id *dev)
	357	{
	358	struct spi_board_info spi_info;
	359	void *pdata = NULL;
	360
	361	memset(&spi_info, 0, sizeof(spi_info));
	362	strncpy(spi_info.modalias, pentry->name, SFI_NAME_LEN);
	363	spi_info.irq = ((pentry->irq == (u8)0xff) ? 0 : pentry->irq);
	364	spi_info.bus_num = pentry->host_num;
	365	spi_info.chip_select = pentry->addr;
	366	spi_info.max_speed_hz = pentry->max_freq;
	367	pr_debug("SPI bus=%d, name=%16.16s, irq=0x%2x, max_freq=%d, cs=%d\n",
	368	spi_info.bus_num,
	369	spi_info.modalias,
	370	spi_info.irq,
	371	spi_info.max_speed_hz,
	372	spi_info.chip_select);
	373
0e6fdb5f	374	pdata = intel_mid_sfi_get_pdata(dev, &spi_info);
acb20d73 DC	375	if (IS_ERR(pdata))
acb20d73 DC	376	return;
aeedb370 KS	377
	378	spi_info.platform_data = pdata;
	379	if (dev->delay)
	380	intel_scu_spi_device_register(&spi_info);
	381	else
	382	spi_register_board_info(&spi_info, 1);
	383	}
	384
	385	static void __init sfi_handle_i2c_dev(struct sfi_device_table_entry *pentry,
	386	struct devs_id *dev)
	387	{
	388	struct i2c_board_info i2c_info;
	389	void *pdata = NULL;
	390
	391	memset(&i2c_info, 0, sizeof(i2c_info));
	392	strncpy(i2c_info.type, pentry->name, SFI_NAME_LEN);
	393	i2c_info.irq = ((pentry->irq == (u8)0xff) ? 0 : pentry->irq);
	394	i2c_info.addr = pentry->addr;
	395	pr_debug("I2C bus = %d, name = %16.16s, irq = 0x%2x, addr = 0x%x\n",
	396	pentry->host_num,
	397	i2c_info.type,
	398	i2c_info.irq,
	399	i2c_info.addr);
0e6fdb5f	400	pdata = intel_mid_sfi_get_pdata(dev, &i2c_info);
aeedb370	401	i2c_info.platform_data = pdata;
acb20d73 DC	402	if (IS_ERR(pdata))
acb20d73 DC	403	return;
aeedb370 KS	404
	405	if (dev->delay)
	406	intel_scu_i2c_device_register(pentry->host_num, &i2c_info);
	407	else
	408	i2c_register_board_info(pentry->host_num, &i2c_info, 1);
	409	}
	410
40a96d54 DC	411	extern struct devs_id *const __x86_intel_mid_dev_start[],
	412	*const __x86_intel_mid_dev_end[];
	413
aeedb370 KS	414	static struct devs_id __init get_device_id(u8 type, char name)
aeedb370 KS	415	{
40a96d54	416	struct devs_id const dev_table;
aeedb370	417
40a96d54 DC	418	for (dev_table = __x86_intel_mid_dev_start;
	419	dev_table < __x86_intel_mid_dev_end; dev_table++) {
	420	struct devs_id dev = dev_table;
aeedb370 KS	421	if (dev->type == type &&
	422	!strncmp(dev->name, name, SFI_NAME_LEN)) {
	423	return dev;
	424	}
aeedb370 KS	425	}
	426
	427	return NULL;
	428	}
	429
	430	static int __init sfi_parse_devs(struct sfi_table_header *table)
	431	{
	432	struct sfi_table_simple *sb;
	433	struct sfi_device_table_entry *pentry;
	434	struct devs_id *dev = NULL;
	435	int num, i;
	436	int ioapic;
	437	struct io_apic_irq_attr irq_attr;
	438
	439	sb = (struct sfi_table_simple *)table;
	440	num = SFI_GET_NUM_ENTRIES(sb, struct sfi_device_table_entry);
	441	pentry = (struct sfi_device_table_entry *)sb->pentry;
	442
	443	for (i = 0; i < num; i++, pentry++) {
	444	int irq = pentry->irq;
	445
	446	if (irq != (u8)0xff) { /* native RTE case */
	447	/* these SPI2 devices are not exposed to system as PCI
	448	* devices, but they have separate RTE entry in IOAPIC
	449	* so we have to enable them one by one here
	450	*/
	451	ioapic = mp_find_ioapic(irq);
bc20aa48 DC	452	if (ioapic >= 0) {
	453	irq_attr.ioapic = ioapic;
	454	irq_attr.ioapic_pin = irq;
	455	irq_attr.trigger = 1;
	456	if (intel_mid_identify_cpu() ==
	457	INTEL_MID_CPU_CHIP_TANGIER) {
	458	if (!strncmp(pentry->name,
	459	"r69001-ts-i2c", 13))
	460	/* active low */
	461	irq_attr.polarity = 1;
	462	else if (!strncmp(pentry->name,
	463	"synaptics_3202", 14))
	464	/* active low */
	465	irq_attr.polarity = 1;
	466	else if (irq == 41)
	467	/* fast_int_1 */
	468	irq_attr.polarity = 1;
	469	else
	470	/* active high */
	471	irq_attr.polarity = 0;
	472	} else {
	473	/* PNW and CLV go with active low */
	474	irq_attr.polarity = 1;
	475	}
1b5d3e00 JL	476	WARN_ON(mp_map_gsi_to_irq(irq,
1b5d3e00 JL	477	IOAPIC_MAP_ALLOC) < 0);
bc20aa48 DC	478	io_apic_set_pci_routing(NULL, irq, &irq_attr);
	479	}
	480	} else {
aeedb370	481	irq = 0; /* No irq */
bc20aa48	482	}
aeedb370 KS	483
	484	dev = get_device_id(pentry->type, pentry->name);
	485
0e6fdb5f	486	if (!dev)
aeedb370 KS	487	continue;
	488
	489	if (dev->device_handler) {
	490	dev->device_handler(pentry, dev);
	491	} else {
	492	switch (pentry->type) {
	493	case SFI_DEV_TYPE_IPC:
	494	sfi_handle_ipc_dev(pentry, dev);
	495	break;
	496	case SFI_DEV_TYPE_SPI:
	497	sfi_handle_spi_dev(pentry, dev);
	498	break;
	499	case SFI_DEV_TYPE_I2C:
	500	sfi_handle_i2c_dev(pentry, dev);
	501	break;
	502	case SFI_DEV_TYPE_UART:
	503	case SFI_DEV_TYPE_HSI:
	504	default:
	505	break;
	506	}
	507	}
	508	}
	509	return 0;
	510	}
	511
	512	static int __init intel_mid_platform_init(void)
	513	{
	514	sfi_table_parse(SFI_SIG_GPIO, NULL, NULL, sfi_parse_gpio);
	515	sfi_table_parse(SFI_SIG_DEVS, NULL, NULL, sfi_parse_devs);
	516	return 0;
	517	}
	518	arch_initcall(intel_mid_platform_init);