sched/clock, x86: Rewrite cyc2ns() to avoid the need to disable IRQs
[deliverable/linux.git] / arch / x86 / platform / uv / tlb_uv.c
CommitLineData
1812924b
CW
1/*
2 * SGI UltraViolet TLB flush routines.
3 *
8b6e511e 4 * (c) 2008-2012 Cliff Wickman <cpw@sgi.com>, SGI.
1812924b
CW
5 *
6 * This code is released under the GNU General Public License version 2 or
7 * later.
8 */
aef8f5b8 9#include <linux/seq_file.h>
1812924b 10#include <linux/proc_fs.h>
e8e5e8a8 11#include <linux/debugfs.h>
1812924b 12#include <linux/kernel.h>
5a0e3ad6 13#include <linux/slab.h>
ca444564 14#include <linux/delay.h>
1812924b 15
1812924b 16#include <asm/mmu_context.h>
bdbcdd48 17#include <asm/uv/uv.h>
1812924b 18#include <asm/uv/uv_mmrs.h>
b4c286e6 19#include <asm/uv/uv_hub.h>
1812924b 20#include <asm/uv/uv_bau.h>
7b6aa335 21#include <asm/apic.h>
b4c286e6 22#include <asm/idle.h>
b194b120 23#include <asm/tsc.h>
99dd8713 24#include <asm/irq_vectors.h>
b8f7fb13 25#include <asm/timer.h>
1812924b 26
12a6611f
CW
27/* timeouts in nanoseconds (indexed by UVH_AGING_PRESCALE_SEL urgency7 30:28) */
28static int timeout_base_ns[] = {
29 20,
30 160,
31 1280,
32 10240,
33 81920,
34 655360,
35 5242880,
36 167772160
37};
f073cc8f 38
12a6611f 39static int timeout_us;
e8e5e8a8 40static int nobau;
26ef8577 41static int nobau_perm;
50fb55ac 42static cycles_t congested_cycles;
12a6611f 43
e8e5e8a8 44/* tunables: */
f073cc8f
CW
45static int max_concurr = MAX_BAU_CONCURRENT;
46static int max_concurr_const = MAX_BAU_CONCURRENT;
47static int plugged_delay = PLUGGED_DELAY;
48static int plugsb4reset = PLUGSB4RESET;
8b6e511e 49static int giveup_limit = GIVEUP_LIMIT;
f073cc8f
CW
50static int timeoutsb4reset = TIMEOUTSB4RESET;
51static int ipi_reset_limit = IPI_RESET_LIMIT;
52static int complete_threshold = COMPLETE_THRESHOLD;
53static int congested_respns_us = CONGESTED_RESPONSE_US;
54static int congested_reps = CONGESTED_REPS;
8b6e511e 55static int disabled_period = DISABLED_PERIOD;
f073cc8f
CW
56
57static struct tunables tunables[] = {
58 {&max_concurr, MAX_BAU_CONCURRENT}, /* must be [0] */
59 {&plugged_delay, PLUGGED_DELAY},
60 {&plugsb4reset, PLUGSB4RESET},
61 {&timeoutsb4reset, TIMEOUTSB4RESET},
62 {&ipi_reset_limit, IPI_RESET_LIMIT},
63 {&complete_threshold, COMPLETE_THRESHOLD},
64 {&congested_respns_us, CONGESTED_RESPONSE_US},
65 {&congested_reps, CONGESTED_REPS},
8b6e511e
CW
66 {&disabled_period, DISABLED_PERIOD},
67 {&giveup_limit, GIVEUP_LIMIT}
f073cc8f
CW
68};
69
e8e5e8a8
CW
70static struct dentry *tunables_dir;
71static struct dentry *tunables_file;
b4c286e6 72
f073cc8f
CW
73/* these correspond to the statistics printed by ptc_seq_show() */
74static char *stat_description[] = {
75 "sent: number of shootdown messages sent",
76 "stime: time spent sending messages",
77 "numuvhubs: number of hubs targeted with shootdown",
78 "numuvhubs16: number times 16 or more hubs targeted",
79 "numuvhubs8: number times 8 or more hubs targeted",
80 "numuvhubs4: number times 4 or more hubs targeted",
81 "numuvhubs2: number times 2 or more hubs targeted",
82 "numuvhubs1: number times 1 hub targeted",
83 "numcpus: number of cpus targeted with shootdown",
84 "dto: number of destination timeouts",
85 "retries: destination timeout retries sent",
86 "rok: : destination timeouts successfully retried",
87 "resetp: ipi-style resource resets for plugs",
88 "resett: ipi-style resource resets for timeouts",
89 "giveup: fall-backs to ipi-style shootdowns",
90 "sto: number of source timeouts",
91 "bz: number of stay-busy's",
92 "throt: number times spun in throttle",
93 "swack: image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE",
94 "recv: shootdown messages received",
95 "rtime: time spent processing messages",
96 "all: shootdown all-tlb messages",
97 "one: shootdown one-tlb messages",
98 "mult: interrupts that found multiple messages",
99 "none: interrupts that found no messages",
100 "retry: number of retry messages processed",
101 "canc: number messages canceled by retries",
102 "nocan: number retries that found nothing to cancel",
103 "reset: number of ipi-style reset requests processed",
104 "rcan: number messages canceled by reset requests",
105 "disable: number times use of the BAU was disabled",
106 "enable: number times use of the BAU was re-enabled"
107};
108
109static int __init
110setup_nobau(char *arg)
b8f7fb13
CW
111{
112 nobau = 1;
113 return 0;
114}
115early_param("nobau", setup_nobau);
b4c286e6 116
b8f7fb13 117/* base pnode in this partition */
f073cc8f 118static int uv_base_pnode __read_mostly;
1812924b 119
dc163a41
IM
120static DEFINE_PER_CPU(struct ptc_stats, ptcstats);
121static DEFINE_PER_CPU(struct bau_control, bau_control);
b8f7fb13
CW
122static DEFINE_PER_CPU(cpumask_var_t, uv_flush_tlb_mask);
123
26ef8577
CW
124static void
125set_bau_on(void)
126{
127 int cpu;
128 struct bau_control *bcp;
129
130 if (nobau_perm) {
131 pr_info("BAU not initialized; cannot be turned on\n");
132 return;
133 }
134 nobau = 0;
135 for_each_present_cpu(cpu) {
136 bcp = &per_cpu(bau_control, cpu);
137 bcp->nobau = 0;
138 }
139 pr_info("BAU turned on\n");
140 return;
141}
142
143static void
144set_bau_off(void)
145{
146 int cpu;
147 struct bau_control *bcp;
148
149 nobau = 1;
150 for_each_present_cpu(cpu) {
151 bcp = &per_cpu(bau_control, cpu);
152 bcp->nobau = 1;
153 }
154 pr_info("BAU turned off\n");
155 return;
156}
157
9674f35b 158/*
b8f7fb13
CW
159 * Determine the first node on a uvhub. 'Nodes' are used for kernel
160 * memory allocation.
9674f35b 161 */
b8f7fb13 162static int __init uvhub_to_first_node(int uvhub)
9674f35b
CW
163{
164 int node, b;
165
166 for_each_online_node(node) {
167 b = uv_node_to_blade_id(node);
b8f7fb13 168 if (uvhub == b)
9674f35b
CW
169 return node;
170 }
b8f7fb13 171 return -1;
9674f35b
CW
172}
173
174/*
b8f7fb13 175 * Determine the apicid of the first cpu on a uvhub.
9674f35b 176 */
b8f7fb13 177static int __init uvhub_to_first_apicid(int uvhub)
9674f35b
CW
178{
179 int cpu;
180
181 for_each_present_cpu(cpu)
b8f7fb13 182 if (uvhub == uv_cpu_to_blade_id(cpu))
9674f35b
CW
183 return per_cpu(x86_cpu_to_apicid, cpu);
184 return -1;
185}
186
1812924b
CW
187/*
188 * Free a software acknowledge hardware resource by clearing its Pending
189 * bit. This will return a reply to the sender.
190 * If the message has timed out, a reply has already been sent by the
191 * hardware but the resource has not been released. In that case our
192 * clear of the Timeout bit (as well) will free the resource. No reply will
193 * be sent (the hardware will only do one reply per message).
194 */
c5d35d39
CW
195static void reply_to_message(struct msg_desc *mdp, struct bau_control *bcp,
196 int do_acknowledge)
1812924b 197{
b194b120 198 unsigned long dw;
f073cc8f 199 struct bau_pq_entry *msg;
1812924b 200
b8f7fb13 201 msg = mdp->msg;
c5d35d39 202 if (!msg->canceled && do_acknowledge) {
f073cc8f
CW
203 dw = (msg->swack_vec << UV_SW_ACK_NPENDING) | msg->swack_vec;
204 write_mmr_sw_ack(dw);
b8f7fb13 205 }
1812924b 206 msg->replied_to = 1;
f073cc8f 207 msg->swack_vec = 0;
1812924b
CW
208}
209
210/*
b8f7fb13 211 * Process the receipt of a RETRY message
1812924b 212 */
f073cc8f
CW
213static void bau_process_retry_msg(struct msg_desc *mdp,
214 struct bau_control *bcp)
1812924b 215{
b8f7fb13
CW
216 int i;
217 int cancel_count = 0;
b8f7fb13
CW
218 unsigned long msg_res;
219 unsigned long mmr = 0;
f073cc8f
CW
220 struct bau_pq_entry *msg = mdp->msg;
221 struct bau_pq_entry *msg2;
222 struct ptc_stats *stat = bcp->statp;
1812924b 223
b8f7fb13
CW
224 stat->d_retries++;
225 /*
226 * cancel any message from msg+1 to the retry itself
227 */
228 for (msg2 = msg+1, i = 0; i < DEST_Q_SIZE; msg2++, i++) {
f073cc8f
CW
229 if (msg2 > mdp->queue_last)
230 msg2 = mdp->queue_first;
b8f7fb13
CW
231 if (msg2 == msg)
232 break;
233
f073cc8f 234 /* same conditions for cancellation as do_reset */
b8f7fb13 235 if ((msg2->replied_to == 0) && (msg2->canceled == 0) &&
f073cc8f
CW
236 (msg2->swack_vec) && ((msg2->swack_vec &
237 msg->swack_vec) == 0) &&
b8f7fb13
CW
238 (msg2->sending_cpu == msg->sending_cpu) &&
239 (msg2->msg_type != MSG_NOOP)) {
f073cc8f
CW
240 mmr = read_mmr_sw_ack();
241 msg_res = msg2->swack_vec;
b8f7fb13
CW
242 /*
243 * This is a message retry; clear the resources held
244 * by the previous message only if they timed out.
245 * If it has not timed out we have an unexpected
246 * situation to report.
247 */
39847e7f 248 if (mmr & (msg_res << UV_SW_ACK_NPENDING)) {
f073cc8f 249 unsigned long mr;
b8f7fb13 250 /*
c5d35d39
CW
251 * Is the resource timed out?
252 * Make everyone ignore the cancelled message.
b8f7fb13
CW
253 */
254 msg2->canceled = 1;
255 stat->d_canceled++;
256 cancel_count++;
f073cc8f
CW
257 mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res;
258 write_mmr_sw_ack(mr);
39847e7f 259 }
b8f7fb13
CW
260 }
261 }
262 if (!cancel_count)
263 stat->d_nocanceled++;
264}
1812924b 265
b8f7fb13
CW
266/*
267 * Do all the things a cpu should do for a TLB shootdown message.
268 * Other cpu's may come here at the same time for this message.
269 */
c5d35d39
CW
270static void bau_process_message(struct msg_desc *mdp, struct bau_control *bcp,
271 int do_acknowledge)
b8f7fb13 272{
b8f7fb13 273 short socket_ack_count = 0;
f073cc8f
CW
274 short *sp;
275 struct atomic_short *asp;
276 struct ptc_stats *stat = bcp->statp;
277 struct bau_pq_entry *msg = mdp->msg;
b8f7fb13 278 struct bau_control *smaster = bcp->socket_master;
1812924b 279
b8f7fb13
CW
280 /*
281 * This must be a normal message, or retry of a normal message
282 */
1812924b
CW
283 if (msg->address == TLB_FLUSH_ALL) {
284 local_flush_tlb();
b8f7fb13 285 stat->d_alltlb++;
1812924b
CW
286 } else {
287 __flush_tlb_one(msg->address);
b8f7fb13 288 stat->d_onetlb++;
1812924b 289 }
b8f7fb13
CW
290 stat->d_requestee++;
291
292 /*
293 * One cpu on each uvhub has the additional job on a RETRY
294 * of releasing the resource held by the message that is
295 * being retried. That message is identified by sending
296 * cpu number.
297 */
298 if (msg->msg_type == MSG_RETRY && bcp == bcp->uvhub_master)
f073cc8f 299 bau_process_retry_msg(mdp, bcp);
1812924b 300
b8f7fb13 301 /*
f073cc8f 302 * This is a swack message, so we have to reply to it.
b8f7fb13
CW
303 * Count each responding cpu on the socket. This avoids
304 * pinging the count's cache line back and forth between
305 * the sockets.
306 */
f073cc8f
CW
307 sp = &smaster->socket_acknowledge_count[mdp->msg_slot];
308 asp = (struct atomic_short *)sp;
309 socket_ack_count = atom_asr(1, asp);
b8f7fb13 310 if (socket_ack_count == bcp->cpus_in_socket) {
f073cc8f 311 int msg_ack_count;
b8f7fb13
CW
312 /*
313 * Both sockets dump their completed count total into
314 * the message's count.
315 */
8b6e511e 316 *sp = 0;
f073cc8f
CW
317 asp = (struct atomic_short *)&msg->acknowledge_count;
318 msg_ack_count = atom_asr(socket_ack_count, asp);
b8f7fb13
CW
319
320 if (msg_ack_count == bcp->cpus_in_uvhub) {
321 /*
322 * All cpus in uvhub saw it; reply
c5d35d39 323 * (unless we are in the UV2 workaround)
b8f7fb13 324 */
c5d35d39 325 reply_to_message(mdp, bcp, do_acknowledge);
b8f7fb13
CW
326 }
327 }
1812924b 328
b8f7fb13 329 return;
1812924b
CW
330}
331
332/*
485f07d3 333 * Determine the first cpu on a pnode.
b8f7fb13 334 */
485f07d3 335static int pnode_to_first_cpu(int pnode, struct bau_control *smaster)
b8f7fb13
CW
336{
337 int cpu;
485f07d3 338 struct hub_and_pnode *hpp;
339
340 for_each_present_cpu(cpu) {
341 hpp = &smaster->thp[cpu];
342 if (pnode == hpp->pnode)
b8f7fb13 343 return cpu;
485f07d3 344 }
b8f7fb13
CW
345 return -1;
346}
347
348/*
349 * Last resort when we get a large number of destination timeouts is
350 * to clear resources held by a given cpu.
351 * Do this with IPI so that all messages in the BAU message queue
f073cc8f 352 * can be identified by their nonzero swack_vec field.
1812924b 353 *
b8f7fb13
CW
354 * This is entered for a single cpu on the uvhub.
355 * The sender want's this uvhub to free a specific message's
f073cc8f 356 * swack resources.
1812924b 357 */
f073cc8f 358static void do_reset(void *ptr)
1812924b 359{
b4c286e6 360 int i;
f073cc8f
CW
361 struct bau_control *bcp = &per_cpu(bau_control, smp_processor_id());
362 struct reset_args *rap = (struct reset_args *)ptr;
363 struct bau_pq_entry *msg;
364 struct ptc_stats *stat = bcp->statp;
1812924b 365
b8f7fb13 366 stat->d_resets++;
b8f7fb13
CW
367 /*
368 * We're looking for the given sender, and
f073cc8f 369 * will free its swack resource.
b8f7fb13
CW
370 * If all cpu's finally responded after the timeout, its
371 * message 'replied_to' was set.
372 */
f073cc8f
CW
373 for (msg = bcp->queue_first, i = 0; i < DEST_Q_SIZE; msg++, i++) {
374 unsigned long msg_res;
375 /* do_reset: same conditions for cancellation as
376 bau_process_retry_msg() */
b8f7fb13
CW
377 if ((msg->replied_to == 0) &&
378 (msg->canceled == 0) &&
379 (msg->sending_cpu == rap->sender) &&
f073cc8f 380 (msg->swack_vec) &&
b8f7fb13 381 (msg->msg_type != MSG_NOOP)) {
f073cc8f
CW
382 unsigned long mmr;
383 unsigned long mr;
b8f7fb13
CW
384 /*
385 * make everyone else ignore this message
386 */
387 msg->canceled = 1;
b8f7fb13
CW
388 /*
389 * only reset the resource if it is still pending
390 */
f073cc8f
CW
391 mmr = read_mmr_sw_ack();
392 msg_res = msg->swack_vec;
393 mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res;
b8f7fb13
CW
394 if (mmr & msg_res) {
395 stat->d_rcanceled++;
f073cc8f 396 write_mmr_sw_ack(mr);
dc163a41 397 }
dc163a41
IM
398 }
399 }
b8f7fb13 400 return;
dc163a41
IM
401}
402
403/*
b8f7fb13
CW
404 * Use IPI to get all target uvhubs to release resources held by
405 * a given sending cpu number.
dc163a41 406 */
a456eaab 407static void reset_with_ipi(struct pnmask *distribution, struct bau_control *bcp)
dc163a41 408{
485f07d3 409 int pnode;
410 int apnode;
f073cc8f 411 int maskbits;
485f07d3 412 int sender = bcp->cpu;
442d3924 413 cpumask_t *mask = bcp->uvhub_master->cpumask;
485f07d3 414 struct bau_control *smaster = bcp->socket_master;
b8f7fb13 415 struct reset_args reset_args;
dc163a41 416
b8f7fb13 417 reset_args.sender = sender;
442d3924 418 cpus_clear(*mask);
b8f7fb13 419 /* find a single cpu for each uvhub in this distribution mask */
a456eaab 420 maskbits = sizeof(struct pnmask) * BITSPERBYTE;
485f07d3 421 /* each bit is a pnode relative to the partition base pnode */
422 for (pnode = 0; pnode < maskbits; pnode++) {
f073cc8f 423 int cpu;
485f07d3 424 if (!bau_uvhub_isset(pnode, distribution))
b194b120 425 continue;
485f07d3 426 apnode = pnode + bcp->partition_base_pnode;
427 cpu = pnode_to_first_cpu(apnode, smaster);
442d3924 428 cpu_set(cpu, *mask);
1812924b 429 }
f073cc8f
CW
430
431 /* IPI all cpus; preemption is already disabled */
442d3924 432 smp_call_function_many(mask, do_reset, (void *)&reset_args, 1);
b8f7fb13
CW
433 return;
434}
435
20d1c86a
PZ
436/*
437 * Not to be confused with cycles_2_ns() from tsc.c; this gives a relative
438 * number, not an absolute. It converts a duration in cycles to a duration in
439 * ns.
440 */
441static inline unsigned long long cycles_2_ns(unsigned long long cyc)
b8f7fb13 442{
20d1c86a 443 struct cyc2ns_data *data = cyc2ns_read_begin();
b8f7fb13 444 unsigned long long ns;
f073cc8f 445
20d1c86a
PZ
446 ns = mul_u64_u32_shr(cyc, data->cyc2ns_mul, data->cyc2ns_shift);
447
448 cyc2ns_read_end(data);
449 return ns;
450}
451
452/*
453 * The reverse of the above; converts a duration in ns to a duration in cycles.
454 */
455static inline unsigned long long ns_2_cycles(unsigned long long ns)
456{
457 struct cyc2ns_data *data = cyc2ns_read_begin();
458 unsigned long long cyc;
459
460 cyc = (ns << data->cyc2ns_shift) / data->cyc2ns_mul;
461
462 cyc2ns_read_end(data);
463 return cyc;
464}
465
466static inline unsigned long cycles_2_us(unsigned long long cyc)
467{
468 return cycles_2_ns(cyc) / NSEC_PER_USEC;
469}
470
471static inline cycles_t sec_2_cycles(unsigned long sec)
472{
473 return ns_2_cycles(sec * NSEC_PER_SEC);
474}
475
476static inline unsigned long long usec_2_cycles(unsigned long usec)
477{
478 return ns_2_cycles(usec * NSEC_PER_USEC);
1812924b
CW
479}
480
b194b120 481/*
b8f7fb13
CW
482 * wait for all cpus on this hub to finish their sends and go quiet
483 * leaves uvhub_quiesce set so that no new broadcasts are started by
484 * bau_flush_send_and_wait()
485 */
f073cc8f 486static inline void quiesce_local_uvhub(struct bau_control *hmaster)
b8f7fb13 487{
f073cc8f 488 atom_asr(1, (struct atomic_short *)&hmaster->uvhub_quiesce);
b8f7fb13
CW
489}
490
491/*
492 * mark this quiet-requestor as done
493 */
f073cc8f 494static inline void end_uvhub_quiesce(struct bau_control *hmaster)
b8f7fb13 495{
f073cc8f
CW
496 atom_asr(-1, (struct atomic_short *)&hmaster->uvhub_quiesce);
497}
498
499static unsigned long uv1_read_status(unsigned long mmr_offset, int right_shift)
500{
501 unsigned long descriptor_status;
502
503 descriptor_status = uv_read_local_mmr(mmr_offset);
504 descriptor_status >>= right_shift;
505 descriptor_status &= UV_ACT_STATUS_MASK;
506 return descriptor_status;
b8f7fb13
CW
507}
508
509/*
510 * Wait for completion of a broadcast software ack message
511 * return COMPLETE, RETRY(PLUGGED or TIMEOUT) or GIVEUP
b194b120 512 */
2a919596 513static int uv1_wait_completion(struct bau_desc *bau_desc,
f073cc8f
CW
514 unsigned long mmr_offset, int right_shift,
515 struct bau_control *bcp, long try)
b194b120 516{
b194b120 517 unsigned long descriptor_status;
f073cc8f 518 cycles_t ttm;
712157aa 519 struct ptc_stats *stat = bcp->statp;
b194b120 520
f073cc8f 521 descriptor_status = uv1_read_status(mmr_offset, right_shift);
b8f7fb13 522 /* spin on the status MMR, waiting for it to go idle */
f073cc8f 523 while ((descriptor_status != DS_IDLE)) {
b194b120 524 /*
2a919596
JS
525 * Our software ack messages may be blocked because
526 * there are no swack resources available. As long
527 * as none of them has timed out hardware will NACK
528 * our message and its state will stay IDLE.
b194b120 529 */
f073cc8f 530 if (descriptor_status == DS_SOURCE_TIMEOUT) {
b8f7fb13
CW
531 stat->s_stimeout++;
532 return FLUSH_GIVEUP;
f073cc8f 533 } else if (descriptor_status == DS_DESTINATION_TIMEOUT) {
2a919596 534 stat->s_dtimeout++;
f073cc8f 535 ttm = get_cycles();
2a919596
JS
536
537 /*
538 * Our retries may be blocked by all destination
539 * swack resources being consumed, and a timeout
540 * pending. In that case hardware returns the
541 * ERROR that looks like a destination timeout.
542 */
f073cc8f 543 if (cycles_2_us(ttm - bcp->send_message) < timeout_us) {
2a919596
JS
544 bcp->conseccompletes = 0;
545 return FLUSH_RETRY_PLUGGED;
546 }
547
548 bcp->conseccompletes = 0;
549 return FLUSH_RETRY_TIMEOUT;
550 } else {
551 /*
552 * descriptor_status is still BUSY
553 */
554 cpu_relax();
555 }
f073cc8f 556 descriptor_status = uv1_read_status(mmr_offset, right_shift);
2a919596
JS
557 }
558 bcp->conseccompletes++;
559 return FLUSH_COMPLETE;
560}
561
f073cc8f 562/*
8b6e511e
CW
563 * UV2 could have an extra bit of status in the ACTIVATION_STATUS_2 register.
564 * But not currently used.
f073cc8f 565 */
c5d35d39 566static unsigned long uv2_read_status(unsigned long offset, int rshft, int desc)
2a919596
JS
567{
568 unsigned long descriptor_status;
f073cc8f 569
8b6e511e
CW
570 descriptor_status =
571 ((read_lmmr(offset) >> rshft) & UV_ACT_STATUS_MASK) << 1;
f073cc8f
CW
572 return descriptor_status;
573}
574
c5d35d39
CW
575/*
576 * Return whether the status of the descriptor that is normally used for this
577 * cpu (the one indexed by its hub-relative cpu number) is busy.
578 * The status of the original 32 descriptors is always reflected in the 64
579 * bits of UVH_LB_BAU_SB_ACTIVATION_STATUS_0.
580 * The bit provided by the activation_status_2 register is irrelevant to
581 * the status if it is only being tested for busy or not busy.
582 */
583int normal_busy(struct bau_control *bcp)
584{
585 int cpu = bcp->uvhub_cpu;
586 int mmr_offset;
587 int right_shift;
588
589 mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
590 right_shift = cpu * UV_ACT_STATUS_SIZE;
591 return (((((read_lmmr(mmr_offset) >> right_shift) &
592 UV_ACT_STATUS_MASK)) << 1) == UV2H_DESC_BUSY);
593}
594
595/*
596 * Entered when a bau descriptor has gone into a permanent busy wait because
597 * of a hardware bug.
598 * Workaround the bug.
599 */
600int handle_uv2_busy(struct bau_control *bcp)
601{
c5d35d39 602 struct ptc_stats *stat = bcp->statp;
c5d35d39
CW
603
604 stat->s_uv2_wars++;
8b6e511e
CW
605 bcp->busy = 1;
606 return FLUSH_GIVEUP;
c5d35d39
CW
607}
608
f073cc8f
CW
609static int uv2_wait_completion(struct bau_desc *bau_desc,
610 unsigned long mmr_offset, int right_shift,
611 struct bau_control *bcp, long try)
612{
613 unsigned long descriptor_stat;
614 cycles_t ttm;
8b6e511e 615 int desc = bcp->uvhub_cpu;
c5d35d39 616 long busy_reps = 0;
2a919596
JS
617 struct ptc_stats *stat = bcp->statp;
618
c5d35d39 619 descriptor_stat = uv2_read_status(mmr_offset, right_shift, desc);
f073cc8f 620
2a919596 621 /* spin on the status MMR, waiting for it to go idle */
f073cc8f 622 while (descriptor_stat != UV2H_DESC_IDLE) {
8b6e511e
CW
623 if ((descriptor_stat == UV2H_DESC_SOURCE_TIMEOUT)) {
624 /*
625 * A h/w bug on the destination side may
626 * have prevented the message being marked
627 * pending, thus it doesn't get replied to
628 * and gets continually nacked until it times
629 * out with a SOURCE_TIMEOUT.
630 */
2a919596
JS
631 stat->s_stimeout++;
632 return FLUSH_GIVEUP;
f073cc8f 633 } else if (descriptor_stat == UV2H_DESC_DEST_TIMEOUT) {
8b6e511e
CW
634 ttm = get_cycles();
635
636 /*
637 * Our retries may be blocked by all destination
638 * swack resources being consumed, and a timeout
639 * pending. In that case hardware returns the
640 * ERROR that looks like a destination timeout.
641 * Without using the extended status we have to
642 * deduce from the short time that this was a
643 * strong nack.
644 */
645 if (cycles_2_us(ttm - bcp->send_message) < timeout_us) {
646 bcp->conseccompletes = 0;
647 stat->s_plugged++;
648 /* FLUSH_RETRY_PLUGGED causes hang on boot */
649 return FLUSH_GIVEUP;
650 }
b8f7fb13 651 stat->s_dtimeout++;
b8f7fb13 652 bcp->conseccompletes = 0;
8b6e511e
CW
653 /* FLUSH_RETRY_TIMEOUT causes hang on boot */
654 return FLUSH_GIVEUP;
b8f7fb13 655 } else {
c5d35d39
CW
656 busy_reps++;
657 if (busy_reps > 1000000) {
658 /* not to hammer on the clock */
659 busy_reps = 0;
660 ttm = get_cycles();
661 if ((ttm - bcp->send_message) >
8b6e511e 662 bcp->timeout_interval)
c5d35d39 663 return handle_uv2_busy(bcp);
c5d35d39 664 }
b8f7fb13 665 /*
f073cc8f 666 * descriptor_stat is still BUSY
b8f7fb13
CW
667 */
668 cpu_relax();
b194b120 669 }
c5d35d39
CW
670 descriptor_stat = uv2_read_status(mmr_offset, right_shift,
671 desc);
b194b120 672 }
b8f7fb13 673 bcp->conseccompletes++;
b194b120
CW
674 return FLUSH_COMPLETE;
675}
676
f073cc8f
CW
677/*
678 * There are 2 status registers; each and array[32] of 2 bits. Set up for
679 * which register to read and position in that register based on cpu in
680 * current hub.
681 */
682static int wait_completion(struct bau_desc *bau_desc,
683 struct bau_control *bcp, long try)
2a919596 684{
f073cc8f
CW
685 int right_shift;
686 unsigned long mmr_offset;
8b6e511e 687 int desc = bcp->uvhub_cpu;
f073cc8f 688
c5d35d39 689 if (desc < UV_CPUS_PER_AS) {
f073cc8f 690 mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
c5d35d39 691 right_shift = desc * UV_ACT_STATUS_SIZE;
f073cc8f
CW
692 } else {
693 mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1;
c5d35d39 694 right_shift = ((desc - UV_CPUS_PER_AS) * UV_ACT_STATUS_SIZE);
f073cc8f
CW
695 }
696
da87c937 697 if (bcp->uvhub_version == 1)
2a919596 698 return uv1_wait_completion(bau_desc, mmr_offset, right_shift,
f073cc8f 699 bcp, try);
2a919596
JS
700 else
701 return uv2_wait_completion(bau_desc, mmr_offset, right_shift,
f073cc8f 702 bcp, try);
2a919596
JS
703}
704
b8f7fb13 705/*
f073cc8f 706 * Our retries are blocked by all destination sw ack resources being
f6d8a566
CW
707 * in use, and a timeout is pending. In that case hardware immediately
708 * returns the ERROR that looks like a destination timeout.
709 */
f073cc8f
CW
710static void destination_plugged(struct bau_desc *bau_desc,
711 struct bau_control *bcp,
f6d8a566
CW
712 struct bau_control *hmaster, struct ptc_stats *stat)
713{
714 udelay(bcp->plugged_delay);
715 bcp->plugged_tries++;
f073cc8f 716
f6d8a566
CW
717 if (bcp->plugged_tries >= bcp->plugsb4reset) {
718 bcp->plugged_tries = 0;
f073cc8f 719
f6d8a566 720 quiesce_local_uvhub(hmaster);
f073cc8f 721
f6d8a566 722 spin_lock(&hmaster->queue_lock);
485f07d3 723 reset_with_ipi(&bau_desc->distribution, bcp);
f6d8a566 724 spin_unlock(&hmaster->queue_lock);
f073cc8f 725
f6d8a566 726 end_uvhub_quiesce(hmaster);
f073cc8f 727
f6d8a566
CW
728 bcp->ipi_attempts++;
729 stat->s_resets_plug++;
730 }
731}
732
f073cc8f
CW
733static void destination_timeout(struct bau_desc *bau_desc,
734 struct bau_control *bcp, struct bau_control *hmaster,
735 struct ptc_stats *stat)
f6d8a566 736{
f073cc8f 737 hmaster->max_concurr = 1;
f6d8a566
CW
738 bcp->timeout_tries++;
739 if (bcp->timeout_tries >= bcp->timeoutsb4reset) {
740 bcp->timeout_tries = 0;
f073cc8f 741
f6d8a566 742 quiesce_local_uvhub(hmaster);
f073cc8f 743
f6d8a566 744 spin_lock(&hmaster->queue_lock);
485f07d3 745 reset_with_ipi(&bau_desc->distribution, bcp);
f6d8a566 746 spin_unlock(&hmaster->queue_lock);
f073cc8f 747
f6d8a566 748 end_uvhub_quiesce(hmaster);
f073cc8f 749
f6d8a566
CW
750 bcp->ipi_attempts++;
751 stat->s_resets_timeout++;
752 }
753}
754
50fb55ac 755/*
8b6e511e
CW
756 * Stop all cpus on a uvhub from using the BAU for a period of time.
757 * This is reversed by check_enable.
50fb55ac 758 */
8b6e511e 759static void disable_for_period(struct bau_control *bcp, struct ptc_stats *stat)
50fb55ac 760{
8b6e511e
CW
761 int tcpu;
762 struct bau_control *tbcp;
763 struct bau_control *hmaster;
764 cycles_t tm1;
765
766 hmaster = bcp->uvhub_master;
767 spin_lock(&hmaster->disable_lock);
768 if (!bcp->baudisabled) {
50fb55ac 769 stat->s_bau_disabled++;
8b6e511e 770 tm1 = get_cycles();
50fb55ac
CW
771 for_each_present_cpu(tcpu) {
772 tbcp = &per_cpu(bau_control, tcpu);
8b6e511e
CW
773 if (tbcp->uvhub_master == hmaster) {
774 tbcp->baudisabled = 1;
775 tbcp->set_bau_on_time =
776 tm1 + bcp->disabled_period;
777 }
50fb55ac
CW
778 }
779 }
8b6e511e 780 spin_unlock(&hmaster->disable_lock);
50fb55ac
CW
781}
782
f073cc8f
CW
783static void count_max_concurr(int stat, struct bau_control *bcp,
784 struct bau_control *hmaster)
785{
786 bcp->plugged_tries = 0;
787 bcp->timeout_tries = 0;
788 if (stat != FLUSH_COMPLETE)
789 return;
790 if (bcp->conseccompletes <= bcp->complete_threshold)
791 return;
792 if (hmaster->max_concurr >= hmaster->max_concurr_const)
793 return;
794 hmaster->max_concurr++;
795}
796
797static void record_send_stats(cycles_t time1, cycles_t time2,
798 struct bau_control *bcp, struct ptc_stats *stat,
799 int completion_status, int try)
800{
801 cycles_t elapsed;
802
803 if (time2 > time1) {
804 elapsed = time2 - time1;
805 stat->s_time += elapsed;
806
807 if ((completion_status == FLUSH_COMPLETE) && (try == 1)) {
808 bcp->period_requests++;
809 bcp->period_time += elapsed;
810 if ((elapsed > congested_cycles) &&
8b6e511e
CW
811 (bcp->period_requests > bcp->cong_reps) &&
812 ((bcp->period_time / bcp->period_requests) >
813 congested_cycles)) {
814 stat->s_congested++;
815 disable_for_period(bcp, stat);
816 }
f073cc8f
CW
817 }
818 } else
819 stat->s_requestor--;
820
821 if (completion_status == FLUSH_COMPLETE && try > 1)
822 stat->s_retriesok++;
8b6e511e 823 else if (completion_status == FLUSH_GIVEUP) {
f073cc8f 824 stat->s_giveup++;
8b6e511e
CW
825 if (get_cycles() > bcp->period_end)
826 bcp->period_giveups = 0;
827 bcp->period_giveups++;
828 if (bcp->period_giveups == 1)
829 bcp->period_end = get_cycles() + bcp->disabled_period;
830 if (bcp->period_giveups > bcp->giveup_limit) {
831 disable_for_period(bcp, stat);
832 stat->s_giveuplimit++;
833 }
834 }
f073cc8f
CW
835}
836
837/*
838 * Because of a uv1 hardware bug only a limited number of concurrent
839 * requests can be made.
840 */
841static void uv1_throttle(struct bau_control *hmaster, struct ptc_stats *stat)
842{
843 spinlock_t *lock = &hmaster->uvhub_lock;
844 atomic_t *v;
845
846 v = &hmaster->active_descriptor_count;
847 if (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr)) {
848 stat->s_throttles++;
849 do {
850 cpu_relax();
851 } while (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr));
852 }
853}
854
855/*
856 * Handle the completion status of a message send.
857 */
858static void handle_cmplt(int completion_status, struct bau_desc *bau_desc,
859 struct bau_control *bcp, struct bau_control *hmaster,
860 struct ptc_stats *stat)
861{
862 if (completion_status == FLUSH_RETRY_PLUGGED)
863 destination_plugged(bau_desc, bcp, hmaster, stat);
864 else if (completion_status == FLUSH_RETRY_TIMEOUT)
865 destination_timeout(bau_desc, bcp, hmaster, stat);
866}
867
868/*
b8f7fb13 869 * Send a broadcast and wait for it to complete.
b194b120 870 *
f6d8a566 871 * The flush_mask contains the cpus the broadcast is to be sent to including
b8f7fb13 872 * cpus that are on the local uvhub.
b194b120 873 *
450a007e
CW
874 * Returns 0 if all flushing represented in the mask was done.
875 * Returns 1 if it gives up entirely and the original cpu mask is to be
876 * returned to the kernel.
b194b120 877 */
8b6e511e
CW
878int uv_flush_send_and_wait(struct cpumask *flush_mask, struct bau_control *bcp,
879 struct bau_desc *bau_desc)
b194b120 880{
b8f7fb13 881 int seq_number = 0;
f073cc8f 882 int completion_stat = 0;
da87c937 883 int uv1 = 0;
b8f7fb13 884 long try = 0;
b4c286e6 885 unsigned long index;
b194b120
CW
886 cycles_t time1;
887 cycles_t time2;
712157aa 888 struct ptc_stats *stat = bcp->statp;
b8f7fb13 889 struct bau_control *hmaster = bcp->uvhub_master;
da87c937
CW
890 struct uv1_bau_msg_header *uv1_hdr = NULL;
891 struct uv2_bau_msg_header *uv2_hdr = NULL;
b8f7fb13 892
8b6e511e
CW
893 if (bcp->uvhub_version == 1) {
894 uv1 = 1;
f073cc8f 895 uv1_throttle(hmaster, stat);
8b6e511e 896 }
f073cc8f 897
b8f7fb13
CW
898 while (hmaster->uvhub_quiesce)
899 cpu_relax();
b194b120 900
b194b120 901 time1 = get_cycles();
8b6e511e
CW
902 if (uv1)
903 uv1_hdr = &bau_desc->header.uv1_hdr;
904 else
905 uv2_hdr = &bau_desc->header.uv2_hdr;
906
b194b120 907 do {
8b6e511e 908 if (try == 0) {
da87c937
CW
909 if (uv1)
910 uv1_hdr->msg_type = MSG_REGULAR;
911 else
912 uv2_hdr->msg_type = MSG_REGULAR;
b8f7fb13
CW
913 seq_number = bcp->message_number++;
914 } else {
da87c937
CW
915 if (uv1)
916 uv1_hdr->msg_type = MSG_RETRY;
917 else
918 uv2_hdr->msg_type = MSG_RETRY;
b8f7fb13
CW
919 stat->s_retry_messages++;
920 }
f073cc8f 921
da87c937
CW
922 if (uv1)
923 uv1_hdr->sequence = seq_number;
924 else
925 uv2_hdr->sequence = seq_number;
8b6e511e 926 index = (1UL << AS_PUSH_SHIFT) | bcp->uvhub_cpu;
b8f7fb13 927 bcp->send_message = get_cycles();
f073cc8f
CW
928
929 write_mmr_activation(index);
930
b8f7fb13 931 try++;
f073cc8f
CW
932 completion_stat = wait_completion(bau_desc, bcp, try);
933
934 handle_cmplt(completion_stat, bau_desc, bcp, hmaster, stat);
b8f7fb13 935
e8e5e8a8 936 if (bcp->ipi_attempts >= bcp->ipi_reset_limit) {
b8f7fb13 937 bcp->ipi_attempts = 0;
8b6e511e 938 stat->s_overipilimit++;
f073cc8f 939 completion_stat = FLUSH_GIVEUP;
b8f7fb13
CW
940 break;
941 }
942 cpu_relax();
f073cc8f
CW
943 } while ((completion_stat == FLUSH_RETRY_PLUGGED) ||
944 (completion_stat == FLUSH_RETRY_TIMEOUT));
945
b194b120 946 time2 = get_cycles();
f073cc8f
CW
947
948 count_max_concurr(completion_stat, bcp, hmaster);
949
b8f7fb13
CW
950 while (hmaster->uvhub_quiesce)
951 cpu_relax();
f073cc8f 952
b8f7fb13 953 atomic_dec(&hmaster->active_descriptor_count);
f073cc8f
CW
954
955 record_send_stats(time1, time2, bcp, stat, completion_stat, try);
956
957 if (completion_stat == FLUSH_GIVEUP)
c5d35d39 958 /* FLUSH_GIVEUP will fall back to using IPI's for tlb flush */
f073cc8f
CW
959 return 1;
960 return 0;
961}
962
963/*
8b6e511e
CW
964 * The BAU is disabled for this uvhub. When the disabled time period has
965 * expired re-enable it.
966 * Return 0 if it is re-enabled for all cpus on this uvhub.
f073cc8f
CW
967 */
968static int check_enable(struct bau_control *bcp, struct ptc_stats *stat)
969{
970 int tcpu;
971 struct bau_control *tbcp;
8b6e511e 972 struct bau_control *hmaster;
f073cc8f 973
8b6e511e
CW
974 hmaster = bcp->uvhub_master;
975 spin_lock(&hmaster->disable_lock);
976 if (bcp->baudisabled && (get_cycles() >= bcp->set_bau_on_time)) {
977 stat->s_bau_reenabled++;
978 for_each_present_cpu(tcpu) {
979 tbcp = &per_cpu(bau_control, tcpu);
980 if (tbcp->uvhub_master == hmaster) {
f073cc8f
CW
981 tbcp->baudisabled = 0;
982 tbcp->period_requests = 0;
983 tbcp->period_time = 0;
8b6e511e 984 tbcp->period_giveups = 0;
50fb55ac
CW
985 }
986 }
8b6e511e
CW
987 spin_unlock(&hmaster->disable_lock);
988 return 0;
f073cc8f 989 }
8b6e511e 990 spin_unlock(&hmaster->disable_lock);
f073cc8f
CW
991 return -1;
992}
993
994static void record_send_statistics(struct ptc_stats *stat, int locals, int hubs,
995 int remotes, struct bau_desc *bau_desc)
996{
997 stat->s_requestor++;
998 stat->s_ntargcpu += remotes + locals;
999 stat->s_ntargremotes += remotes;
1000 stat->s_ntarglocals += locals;
1001
1002 /* uvhub statistics */
1003 hubs = bau_uvhub_weight(&bau_desc->distribution);
1004 if (locals) {
1005 stat->s_ntarglocaluvhub++;
1006 stat->s_ntargremoteuvhub += (hubs - 1);
e8e5e8a8 1007 } else
f073cc8f
CW
1008 stat->s_ntargremoteuvhub += hubs;
1009
1010 stat->s_ntarguvhub += hubs;
1011
1012 if (hubs >= 16)
1013 stat->s_ntarguvhub16++;
1014 else if (hubs >= 8)
1015 stat->s_ntarguvhub8++;
1016 else if (hubs >= 4)
1017 stat->s_ntarguvhub4++;
1018 else if (hubs >= 2)
1019 stat->s_ntarguvhub2++;
1020 else
1021 stat->s_ntarguvhub1++;
1022}
1023
1024/*
1025 * Translate a cpu mask to the uvhub distribution mask in the BAU
1026 * activation descriptor.
1027 */
1028static int set_distrib_bits(struct cpumask *flush_mask, struct bau_control *bcp,
1029 struct bau_desc *bau_desc, int *localsp, int *remotesp)
1030{
1031 int cpu;
1032 int pnode;
1033 int cnt = 0;
1034 struct hub_and_pnode *hpp;
1035
1036 for_each_cpu(cpu, flush_mask) {
1037 /*
1038 * The distribution vector is a bit map of pnodes, relative
1039 * to the partition base pnode (and the partition base nasid
1040 * in the header).
1041 * Translate cpu to pnode and hub using a local memory array.
1042 */
1043 hpp = &bcp->socket_master->thp[cpu];
1044 pnode = hpp->pnode - bcp->partition_base_pnode;
1045 bau_uvhub_set(pnode, &bau_desc->distribution);
1046 cnt++;
1047 if (hpp->uvhub == bcp->uvhub)
1048 (*localsp)++;
1049 else
1050 (*remotesp)++;
b194b120 1051 }
f073cc8f
CW
1052 if (!cnt)
1053 return 1;
450a007e 1054 return 0;
b194b120
CW
1055}
1056
f073cc8f
CW
1057/*
1058 * globally purge translation cache of a virtual address or all TLB's
bdbcdd48 1059 * @cpumask: mask of all cpu's in which the address is to be removed
1812924b 1060 * @mm: mm_struct containing virtual address range
57c4f430
AS
1061 * @start: start virtual address to be removed from TLB
1062 * @end: end virtual address to be remove from TLB
bdbcdd48 1063 * @cpu: the current cpu
1812924b
CW
1064 *
1065 * This is the entry point for initiating any UV global TLB shootdown.
1066 *
1067 * Purges the translation caches of all specified processors of the given
1068 * virtual address, or purges all TLB's on specified processors.
1069 *
bdbcdd48
TH
1070 * The caller has derived the cpumask from the mm_struct. This function
1071 * is called only if there are bits set in the mask. (e.g. flush_tlb_page())
1812924b 1072 *
b8f7fb13
CW
1073 * The cpumask is converted into a uvhubmask of the uvhubs containing
1074 * those cpus.
b194b120 1075 *
bdbcdd48
TH
1076 * Note that this function should be called with preemption disabled.
1077 *
1078 * Returns NULL if all remote flushing was done.
1079 * Returns pointer to cpumask if some remote flushing remains to be
1080 * done. The returned pointer is valid till preemption is re-enabled.
1812924b 1081 */
bdbcdd48 1082const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
e7b52ffd 1083 struct mm_struct *mm, unsigned long start,
57c4f430 1084 unsigned long end, unsigned int cpu)
1812924b 1085{
b194b120 1086 int locals = 0;
450a007e
CW
1087 int remotes = 0;
1088 int hubs = 0;
dc163a41 1089 struct bau_desc *bau_desc;
b8f7fb13
CW
1090 struct cpumask *flush_mask;
1091 struct ptc_stats *stat;
1092 struct bau_control *bcp;
8b6e511e
CW
1093 unsigned long descriptor_status;
1094 unsigned long status;
bdbcdd48 1095
b8f7fb13 1096 bcp = &per_cpu(bau_control, cpu);
26ef8577
CW
1097
1098 if (bcp->nobau)
1099 return cpumask;
50fb55ac 1100
3eae49ca 1101 stat = bcp->statp;
1102 stat->s_enters++;
1103
8b6e511e
CW
1104 if (bcp->busy) {
1105 descriptor_status =
1106 read_lmmr(UVH_LB_BAU_SB_ACTIVATION_STATUS_0);
1107 status = ((descriptor_status >> (bcp->uvhub_cpu *
1108 UV_ACT_STATUS_SIZE)) & UV_ACT_STATUS_MASK) << 1;
1109 if (status == UV2H_DESC_BUSY)
1110 return cpumask;
1111 bcp->busy = 0;
1112 }
1113
50fb55ac
CW
1114 /* bau was disabled due to slow response */
1115 if (bcp->baudisabled) {
8b6e511e
CW
1116 if (check_enable(bcp, stat)) {
1117 stat->s_ipifordisabled++;
f073cc8f 1118 return cpumask;
8b6e511e 1119 }
50fb55ac 1120 }
e8e5e8a8 1121
b8f7fb13
CW
1122 /*
1123 * Each sending cpu has a per-cpu mask which it fills from the caller's
450a007e
CW
1124 * cpu mask. All cpus are converted to uvhubs and copied to the
1125 * activation descriptor.
b8f7fb13
CW
1126 */
1127 flush_mask = (struct cpumask *)per_cpu(uv_flush_tlb_mask, cpu);
450a007e 1128 /* don't actually do a shootdown of the local cpu */
b8f7fb13 1129 cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu));
f073cc8f 1130
b8f7fb13 1131 if (cpu_isset(cpu, *cpumask))
450a007e 1132 stat->s_ntargself++;
1812924b 1133
b8f7fb13 1134 bau_desc = bcp->descriptor_base;
8b6e511e 1135 bau_desc += (ITEMS_PER_DESC * bcp->uvhub_cpu);
b8f7fb13 1136 bau_uvhubs_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE);
f073cc8f 1137 if (set_distrib_bits(flush_mask, bcp, bau_desc, &locals, &remotes))
450a007e 1138 return NULL;
450a007e 1139
f073cc8f 1140 record_send_statistics(stat, locals, hubs, remotes, bau_desc);
1812924b 1141
57c4f430
AS
1142 if (!end || (end - start) <= PAGE_SIZE)
1143 bau_desc->payload.address = start;
1144 else
1145 bau_desc->payload.address = TLB_FLUSH_ALL;
bdbcdd48 1146 bau_desc->payload.sending_cpu = cpu;
b8f7fb13 1147 /*
450a007e
CW
1148 * uv_flush_send_and_wait returns 0 if all cpu's were messaged,
1149 * or 1 if it gave up and the original cpumask should be returned.
b8f7fb13 1150 */
8b6e511e 1151 if (!uv_flush_send_and_wait(flush_mask, bcp, bau_desc))
450a007e
CW
1152 return NULL;
1153 else
1154 return cpumask;
1812924b
CW
1155}
1156
c5d35d39 1157/*
8b6e511e
CW
1158 * Search the message queue for any 'other' unprocessed message with the
1159 * same software acknowledge resource bit vector as the 'msg' message.
c5d35d39
CW
1160 */
1161struct bau_pq_entry *find_another_by_swack(struct bau_pq_entry *msg,
8b6e511e 1162 struct bau_control *bcp)
c5d35d39
CW
1163{
1164 struct bau_pq_entry *msg_next = msg + 1;
8b6e511e 1165 unsigned char swack_vec = msg->swack_vec;
c5d35d39
CW
1166
1167 if (msg_next > bcp->queue_last)
1168 msg_next = bcp->queue_first;
8b6e511e
CW
1169 while (msg_next != msg) {
1170 if ((msg_next->canceled == 0) && (msg_next->replied_to == 0) &&
1171 (msg_next->swack_vec == swack_vec))
c5d35d39
CW
1172 return msg_next;
1173 msg_next++;
1174 if (msg_next > bcp->queue_last)
1175 msg_next = bcp->queue_first;
1176 }
1177 return NULL;
1178}
1179
1180/*
1181 * UV2 needs to work around a bug in which an arriving message has not
1182 * set a bit in the UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE register.
1183 * Such a message must be ignored.
1184 */
1185void process_uv2_message(struct msg_desc *mdp, struct bau_control *bcp)
1186{
1187 unsigned long mmr_image;
1188 unsigned char swack_vec;
1189 struct bau_pq_entry *msg = mdp->msg;
1190 struct bau_pq_entry *other_msg;
1191
1192 mmr_image = read_mmr_sw_ack();
1193 swack_vec = msg->swack_vec;
1194
1195 if ((swack_vec & mmr_image) == 0) {
1196 /*
1197 * This message was assigned a swack resource, but no
1198 * reserved acknowlegment is pending.
1199 * The bug has prevented this message from setting the MMR.
c5d35d39 1200 */
c5d35d39 1201 /*
8b6e511e
CW
1202 * Some message has set the MMR 'pending' bit; it might have
1203 * been another message. Look for that message.
c5d35d39 1204 */
8b6e511e
CW
1205 other_msg = find_another_by_swack(msg, bcp);
1206 if (other_msg) {
1207 /*
1208 * There is another. Process this one but do not
1209 * ack it.
1210 */
1211 bau_process_message(mdp, bcp, 0);
1212 /*
1213 * Let the natural processing of that other message
1214 * acknowledge it. Don't get the processing of sw_ack's
1215 * out of order.
1216 */
1217 return;
1218 }
c5d35d39
CW
1219 }
1220
1221 /*
8b6e511e
CW
1222 * Either the MMR shows this one pending a reply or there is no
1223 * other message using this sw_ack, so it is safe to acknowledge it.
c5d35d39
CW
1224 */
1225 bau_process_message(mdp, bcp, 1);
1226
1227 return;
1228}
1229
1812924b
CW
1230/*
1231 * The BAU message interrupt comes here. (registered by set_intr_gate)
1232 * See entry_64.S
1233 *
1234 * We received a broadcast assist message.
1235 *
b8f7fb13 1236 * Interrupts are disabled; this interrupt could represent
1812924b
CW
1237 * the receipt of several messages.
1238 *
b8f7fb13
CW
1239 * All cores/threads on this hub get this interrupt.
1240 * The last one to see it does the software ack.
1812924b 1241 * (the resource will not be freed until noninterruptable cpus see this
b8f7fb13 1242 * interrupt; hardware may timeout the s/w ack and reply ERROR)
1812924b 1243 */
b194b120 1244void uv_bau_message_interrupt(struct pt_regs *regs)
1812924b 1245{
1812924b 1246 int count = 0;
b8f7fb13 1247 cycles_t time_start;
f073cc8f 1248 struct bau_pq_entry *msg;
b8f7fb13
CW
1249 struct bau_control *bcp;
1250 struct ptc_stats *stat;
1251 struct msg_desc msgdesc;
1252
88ed9dd7 1253 ack_APIC_irq();
b8f7fb13 1254 time_start = get_cycles();
f073cc8f 1255
b8f7fb13 1256 bcp = &per_cpu(bau_control, smp_processor_id());
712157aa 1257 stat = bcp->statp;
f073cc8f
CW
1258
1259 msgdesc.queue_first = bcp->queue_first;
1260 msgdesc.queue_last = bcp->queue_last;
1261
b8f7fb13 1262 msg = bcp->bau_msg_head;
f073cc8f 1263 while (msg->swack_vec) {
1812924b 1264 count++;
f073cc8f
CW
1265
1266 msgdesc.msg_slot = msg - msgdesc.queue_first;
b8f7fb13 1267 msgdesc.msg = msg;
c5d35d39
CW
1268 if (bcp->uvhub_version == 2)
1269 process_uv2_message(&msgdesc, bcp);
1270 else
1271 bau_process_message(&msgdesc, bcp, 1);
f073cc8f 1272
1812924b 1273 msg++;
f073cc8f
CW
1274 if (msg > msgdesc.queue_last)
1275 msg = msgdesc.queue_first;
b8f7fb13 1276 bcp->bau_msg_head = msg;
1812924b 1277 }
b8f7fb13 1278 stat->d_time += (get_cycles() - time_start);
1812924b 1279 if (!count)
b8f7fb13 1280 stat->d_nomsg++;
1812924b 1281 else if (count > 1)
b8f7fb13 1282 stat->d_multmsg++;
1812924b
CW
1283}
1284
c4c4688f 1285/*
f073cc8f 1286 * Each target uvhub (i.e. a uvhub that has cpu's) needs to have
c4c4688f
CW
1287 * shootdown message timeouts enabled. The timeout does not cause
1288 * an interrupt, but causes an error message to be returned to
1289 * the sender.
1290 */
f073cc8f 1291static void __init enable_timeouts(void)
1812924b 1292{
b8f7fb13
CW
1293 int uvhub;
1294 int nuvhubs;
1812924b 1295 int pnode;
c4c4688f 1296 unsigned long mmr_image;
1812924b 1297
b8f7fb13 1298 nuvhubs = uv_num_possible_blades();
1812924b 1299
b8f7fb13
CW
1300 for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
1301 if (!uv_blade_nr_possible_cpus(uvhub))
1812924b 1302 continue;
c4c4688f 1303
b8f7fb13 1304 pnode = uv_blade_to_pnode(uvhub);
f073cc8f 1305 mmr_image = read_mmr_misc_control(pnode);
c4c4688f
CW
1306 /*
1307 * Set the timeout period and then lock it in, in three
1308 * steps; captures and locks in the period.
1309 *
1310 * To program the period, the SOFT_ACK_MODE must be off.
1311 */
f073cc8f
CW
1312 mmr_image &= ~(1L << SOFTACK_MSHIFT);
1313 write_mmr_misc_control(pnode, mmr_image);
c4c4688f
CW
1314 /*
1315 * Set the 4-bit period.
1316 */
f073cc8f
CW
1317 mmr_image &= ~((unsigned long)0xf << SOFTACK_PSHIFT);
1318 mmr_image |= (SOFTACK_TIMEOUT_PERIOD << SOFTACK_PSHIFT);
1319 write_mmr_misc_control(pnode, mmr_image);
c4c4688f 1320 /*
2a919596 1321 * UV1:
c4c4688f
CW
1322 * Subsequent reversals of the timebase bit (3) cause an
1323 * immediate timeout of one or all INTD resources as
1324 * indicated in bits 2:0 (7 causes all of them to timeout).
1325 */
f073cc8f 1326 mmr_image |= (1L << SOFTACK_MSHIFT);
2a919596 1327 if (is_uv2_hub()) {
8b6e511e
CW
1328 /* hw bug workaround; do not use extended status */
1329 mmr_image &= ~(1L << UV2_EXT_SHFT);
2a919596 1330 }
f073cc8f 1331 write_mmr_misc_control(pnode, mmr_image);
1812924b 1332 }
1812924b
CW
1333}
1334
f073cc8f 1335static void *ptc_seq_start(struct seq_file *file, loff_t *offset)
1812924b
CW
1336{
1337 if (*offset < num_possible_cpus())
1338 return offset;
1339 return NULL;
1340}
1341
f073cc8f 1342static void *ptc_seq_next(struct seq_file *file, void *data, loff_t *offset)
1812924b
CW
1343{
1344 (*offset)++;
1345 if (*offset < num_possible_cpus())
1346 return offset;
1347 return NULL;
1348}
1349
f073cc8f 1350static void ptc_seq_stop(struct seq_file *file, void *data)
1812924b
CW
1351{
1352}
1353
1354/*
f073cc8f 1355 * Display the statistics thru /proc/sgi_uv/ptc_statistics
b8f7fb13 1356 * 'data' points to the cpu number
f073cc8f 1357 * Note: see the descriptions in stat_description[].
1812924b 1358 */
f073cc8f 1359static int ptc_seq_show(struct seq_file *file, void *data)
1812924b
CW
1360{
1361 struct ptc_stats *stat;
26ef8577 1362 struct bau_control *bcp;
1812924b
CW
1363 int cpu;
1364
1365 cpu = *(loff_t *)data;
1812924b
CW
1366 if (!cpu) {
1367 seq_printf(file,
8b6e511e 1368 "# cpu bauoff sent stime self locals remotes ncpus localhub ");
450a007e
CW
1369 seq_printf(file,
1370 "remotehub numuvhubs numuvhubs16 numuvhubs8 ");
1812924b 1371 seq_printf(file,
8b6e511e
CW
1372 "numuvhubs4 numuvhubs2 numuvhubs1 dto snacks retries ");
1373 seq_printf(file,
1374 "rok resetp resett giveup sto bz throt disable ");
b8f7fb13 1375 seq_printf(file,
8b6e511e 1376 "enable wars warshw warwaits enters ipidis plugged ");
b8f7fb13 1377 seq_printf(file,
8b6e511e 1378 "ipiover glim cong swack recv rtime all one mult ");
50fb55ac 1379 seq_printf(file,
8b6e511e 1380 "none retry canc nocan reset rcan\n");
1812924b
CW
1381 }
1382 if (cpu < num_possible_cpus() && cpu_online(cpu)) {
26ef8577
CW
1383 bcp = &per_cpu(bau_control, cpu);
1384 stat = bcp->statp;
b8f7fb13
CW
1385 /* source side statistics */
1386 seq_printf(file,
8b6e511e 1387 "cpu %d %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ",
26ef8577
CW
1388 cpu, bcp->nobau, stat->s_requestor,
1389 cycles_2_us(stat->s_time),
450a007e
CW
1390 stat->s_ntargself, stat->s_ntarglocals,
1391 stat->s_ntargremotes, stat->s_ntargcpu,
1392 stat->s_ntarglocaluvhub, stat->s_ntargremoteuvhub,
1393 stat->s_ntarguvhub, stat->s_ntarguvhub16);
b54bd9be 1394 seq_printf(file, "%ld %ld %ld %ld %ld %ld ",
b8f7fb13
CW
1395 stat->s_ntarguvhub8, stat->s_ntarguvhub4,
1396 stat->s_ntarguvhub2, stat->s_ntarguvhub1,
b54bd9be 1397 stat->s_dtimeout, stat->s_strongnacks);
8b6e511e 1398 seq_printf(file, "%ld %ld %ld %ld %ld %ld %ld %ld ",
b8f7fb13
CW
1399 stat->s_retry_messages, stat->s_retriesok,
1400 stat->s_resets_plug, stat->s_resets_timeout,
1401 stat->s_giveup, stat->s_stimeout,
8b6e511e
CW
1402 stat->s_busy, stat->s_throttles);
1403 seq_printf(file, "%ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ",
1404 stat->s_bau_disabled, stat->s_bau_reenabled,
1405 stat->s_uv2_wars, stat->s_uv2_wars_hw,
1406 stat->s_uv2_war_waits, stat->s_enters,
1407 stat->s_ipifordisabled, stat->s_plugged,
1408 stat->s_overipilimit, stat->s_giveuplimit,
1409 stat->s_congested);
e8e5e8a8 1410
b8f7fb13
CW
1411 /* destination side statistics */
1412 seq_printf(file,
8b6e511e 1413 "%lx %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld\n",
f073cc8f 1414 read_gmmr_sw_ack(uv_cpu_to_pnode(cpu)),
b8f7fb13
CW
1415 stat->d_requestee, cycles_2_us(stat->d_time),
1416 stat->d_alltlb, stat->d_onetlb, stat->d_multmsg,
1417 stat->d_nomsg, stat->d_retries, stat->d_canceled,
1418 stat->d_nocanceled, stat->d_resets,
1419 stat->d_rcanceled);
1812924b 1420 }
1812924b
CW
1421 return 0;
1422}
1423
e8e5e8a8
CW
1424/*
1425 * Display the tunables thru debugfs
1426 */
1427static ssize_t tunables_read(struct file *file, char __user *userbuf,
f073cc8f 1428 size_t count, loff_t *ppos)
e8e5e8a8 1429{
b365a85c 1430 char *buf;
e8e5e8a8
CW
1431 int ret;
1432
8b6e511e
CW
1433 buf = kasprintf(GFP_KERNEL, "%s %s %s\n%d %d %d %d %d %d %d %d %d %d\n",
1434 "max_concur plugged_delay plugsb4reset timeoutsb4reset",
1435 "ipi_reset_limit complete_threshold congested_response_us",
1436 "congested_reps disabled_period giveup_limit",
f073cc8f 1437 max_concurr, plugged_delay, plugsb4reset,
e8e5e8a8 1438 timeoutsb4reset, ipi_reset_limit, complete_threshold,
8b6e511e
CW
1439 congested_respns_us, congested_reps, disabled_period,
1440 giveup_limit);
e8e5e8a8 1441
b365a85c
DC
1442 if (!buf)
1443 return -ENOMEM;
1444
1445 ret = simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf));
1446 kfree(buf);
1447 return ret;
e8e5e8a8
CW
1448}
1449
1812924b 1450/*
f073cc8f
CW
1451 * handle a write to /proc/sgi_uv/ptc_statistics
1452 * -1: reset the statistics
1812924b 1453 * 0: display meaning of the statistics
1812924b 1454 */
f073cc8f
CW
1455static ssize_t ptc_proc_write(struct file *file, const char __user *user,
1456 size_t count, loff_t *data)
1812924b 1457{
b8f7fb13 1458 int cpu;
f073cc8f
CW
1459 int i;
1460 int elements;
b8f7fb13 1461 long input_arg;
1812924b 1462 char optstr[64];
b8f7fb13 1463 struct ptc_stats *stat;
1812924b 1464
e7eb8726 1465 if (count == 0 || count > sizeof(optstr))
cef53278 1466 return -EINVAL;
1812924b
CW
1467 if (copy_from_user(optstr, user, count))
1468 return -EFAULT;
1469 optstr[count - 1] = '\0';
f073cc8f 1470
26ef8577
CW
1471 if (!strcmp(optstr, "on")) {
1472 set_bau_on();
1473 return count;
1474 } else if (!strcmp(optstr, "off")) {
1475 set_bau_off();
1476 return count;
1477 }
1478
b8f7fb13 1479 if (strict_strtol(optstr, 10, &input_arg) < 0) {
1812924b
CW
1480 printk(KERN_DEBUG "%s is invalid\n", optstr);
1481 return -EINVAL;
1482 }
1483
b8f7fb13 1484 if (input_arg == 0) {
64441745 1485 elements = ARRAY_SIZE(stat_description);
1812924b 1486 printk(KERN_DEBUG "# cpu: cpu number\n");
b8f7fb13 1487 printk(KERN_DEBUG "Sender statistics:\n");
f073cc8f
CW
1488 for (i = 0; i < elements; i++)
1489 printk(KERN_DEBUG "%s\n", stat_description[i]);
b8f7fb13
CW
1490 } else if (input_arg == -1) {
1491 for_each_present_cpu(cpu) {
1492 stat = &per_cpu(ptcstats, cpu);
1493 memset(stat, 0, sizeof(struct ptc_stats));
1494 }
e8e5e8a8
CW
1495 }
1496
1497 return count;
1498}
1499
1500static int local_atoi(const char *name)
1501{
1502 int val = 0;
1503
1504 for (;; name++) {
1505 switch (*name) {
1506 case '0' ... '9':
1507 val = 10*val+(*name-'0');
1508 break;
1509 default:
1510 return val;
b8f7fb13 1511 }
1812924b 1512 }
e8e5e8a8
CW
1513}
1514
1515/*
f073cc8f
CW
1516 * Parse the values written to /sys/kernel/debug/sgi_uv/bau_tunables.
1517 * Zero values reset them to defaults.
e8e5e8a8 1518 */
f073cc8f
CW
1519static int parse_tunables_write(struct bau_control *bcp, char *instr,
1520 int count)
e8e5e8a8 1521{
e8e5e8a8
CW
1522 char *p;
1523 char *q;
f073cc8f
CW
1524 int cnt = 0;
1525 int val;
64441745 1526 int e = ARRAY_SIZE(tunables);
e8e5e8a8 1527
e8e5e8a8
CW
1528 p = instr + strspn(instr, WHITESPACE);
1529 q = p;
1530 for (; *p; p = q + strspn(q, WHITESPACE)) {
1531 q = p + strcspn(p, WHITESPACE);
1532 cnt++;
1533 if (q == p)
1534 break;
1535 }
f073cc8f
CW
1536 if (cnt != e) {
1537 printk(KERN_INFO "bau tunable error: should be %d values\n", e);
e8e5e8a8
CW
1538 return -EINVAL;
1539 }
1540
1541 p = instr + strspn(instr, WHITESPACE);
1542 q = p;
1543 for (cnt = 0; *p; p = q + strspn(q, WHITESPACE), cnt++) {
1544 q = p + strcspn(p, WHITESPACE);
1545 val = local_atoi(p);
1546 switch (cnt) {
1547 case 0:
1548 if (val == 0) {
f073cc8f
CW
1549 max_concurr = MAX_BAU_CONCURRENT;
1550 max_concurr_const = MAX_BAU_CONCURRENT;
e8e5e8a8
CW
1551 continue;
1552 }
e8e5e8a8
CW
1553 if (val < 1 || val > bcp->cpus_in_uvhub) {
1554 printk(KERN_DEBUG
1555 "Error: BAU max concurrent %d is invalid\n",
1556 val);
1557 return -EINVAL;
1558 }
f073cc8f
CW
1559 max_concurr = val;
1560 max_concurr_const = val;
e8e5e8a8 1561 continue;
f073cc8f 1562 default:
e8e5e8a8 1563 if (val == 0)
f073cc8f 1564 *tunables[cnt].tunp = tunables[cnt].deflt;
e8e5e8a8 1565 else
f073cc8f 1566 *tunables[cnt].tunp = val;
e8e5e8a8
CW
1567 continue;
1568 }
1569 if (q == p)
1570 break;
1571 }
f073cc8f
CW
1572 return 0;
1573}
1574
1575/*
1576 * Handle a write to debugfs. (/sys/kernel/debug/sgi_uv/bau_tunables)
1577 */
1578static ssize_t tunables_write(struct file *file, const char __user *user,
1579 size_t count, loff_t *data)
1580{
1581 int cpu;
1582 int ret;
1583 char instr[100];
1584 struct bau_control *bcp;
1585
1586 if (count == 0 || count > sizeof(instr)-1)
1587 return -EINVAL;
1588 if (copy_from_user(instr, user, count))
1589 return -EFAULT;
1590
1591 instr[count] = '\0';
1592
00b30cf0 1593 cpu = get_cpu();
1594 bcp = &per_cpu(bau_control, cpu);
f073cc8f 1595 ret = parse_tunables_write(bcp, instr, count);
00b30cf0 1596 put_cpu();
f073cc8f
CW
1597 if (ret)
1598 return ret;
1599
e8e5e8a8
CW
1600 for_each_present_cpu(cpu) {
1601 bcp = &per_cpu(bau_control, cpu);
f073cc8f
CW
1602 bcp->max_concurr = max_concurr;
1603 bcp->max_concurr_const = max_concurr;
1604 bcp->plugged_delay = plugged_delay;
1605 bcp->plugsb4reset = plugsb4reset;
1606 bcp->timeoutsb4reset = timeoutsb4reset;
1607 bcp->ipi_reset_limit = ipi_reset_limit;
1608 bcp->complete_threshold = complete_threshold;
1609 bcp->cong_response_us = congested_respns_us;
1610 bcp->cong_reps = congested_reps;
8b6e511e
CW
1611 bcp->disabled_period = sec_2_cycles(disabled_period);
1612 bcp->giveup_limit = giveup_limit;
e8e5e8a8 1613 }
1812924b
CW
1614 return count;
1615}
1616
1617static const struct seq_operations uv_ptc_seq_ops = {
f073cc8f
CW
1618 .start = ptc_seq_start,
1619 .next = ptc_seq_next,
1620 .stop = ptc_seq_stop,
1621 .show = ptc_seq_show
1812924b
CW
1622};
1623
f073cc8f 1624static int ptc_proc_open(struct inode *inode, struct file *file)
1812924b
CW
1625{
1626 return seq_open(file, &uv_ptc_seq_ops);
1627}
1628
e8e5e8a8
CW
1629static int tunables_open(struct inode *inode, struct file *file)
1630{
1631 return 0;
1632}
1633
1812924b 1634static const struct file_operations proc_uv_ptc_operations = {
f073cc8f 1635 .open = ptc_proc_open,
b194b120 1636 .read = seq_read,
f073cc8f 1637 .write = ptc_proc_write,
b194b120
CW
1638 .llseek = seq_lseek,
1639 .release = seq_release,
1812924b
CW
1640};
1641
e8e5e8a8
CW
1642static const struct file_operations tunables_fops = {
1643 .open = tunables_open,
1644 .read = tunables_read,
1645 .write = tunables_write,
6038f373 1646 .llseek = default_llseek,
e8e5e8a8
CW
1647};
1648
b194b120 1649static int __init uv_ptc_init(void)
1812924b 1650{
b194b120 1651 struct proc_dir_entry *proc_uv_ptc;
1812924b
CW
1652
1653 if (!is_uv_system())
1654 return 0;
1655
10f02d11
AD
1656 proc_uv_ptc = proc_create(UV_PTC_BASENAME, 0444, NULL,
1657 &proc_uv_ptc_operations);
1812924b
CW
1658 if (!proc_uv_ptc) {
1659 printk(KERN_ERR "unable to create %s proc entry\n",
1660 UV_PTC_BASENAME);
1661 return -EINVAL;
1662 }
e8e5e8a8
CW
1663
1664 tunables_dir = debugfs_create_dir(UV_BAU_TUNABLES_DIR, NULL);
1665 if (!tunables_dir) {
1666 printk(KERN_ERR "unable to create debugfs directory %s\n",
1667 UV_BAU_TUNABLES_DIR);
1668 return -EINVAL;
1669 }
1670 tunables_file = debugfs_create_file(UV_BAU_TUNABLES_FILE, 0600,
f073cc8f 1671 tunables_dir, NULL, &tunables_fops);
e8e5e8a8
CW
1672 if (!tunables_file) {
1673 printk(KERN_ERR "unable to create debugfs file %s\n",
1674 UV_BAU_TUNABLES_FILE);
1675 return -EINVAL;
1676 }
1812924b
CW
1677 return 0;
1678}
1679
1812924b 1680/*
77ed23f8 1681 * Initialize the sending side's sending buffers.
1812924b 1682 */
f073cc8f 1683static void activation_descriptor_init(int node, int pnode, int base_pnode)
1812924b
CW
1684{
1685 int i;
b8f7fb13 1686 int cpu;
da87c937 1687 int uv1 = 0;
6a469e46 1688 unsigned long gpa;
1812924b 1689 unsigned long m;
b194b120 1690 unsigned long n;
f073cc8f 1691 size_t dsize;
b8f7fb13
CW
1692 struct bau_desc *bau_desc;
1693 struct bau_desc *bd2;
da87c937
CW
1694 struct uv1_bau_msg_header *uv1_hdr;
1695 struct uv2_bau_msg_header *uv2_hdr;
b8f7fb13 1696 struct bau_control *bcp;
b194b120 1697
0e2595cd 1698 /*
f073cc8f
CW
1699 * each bau_desc is 64 bytes; there are 8 (ITEMS_PER_DESC)
1700 * per cpu; and one per cpu on the uvhub (ADP_SZ)
0e2595cd 1701 */
f073cc8f
CW
1702 dsize = sizeof(struct bau_desc) * ADP_SZ * ITEMS_PER_DESC;
1703 bau_desc = kmalloc_node(dsize, GFP_KERNEL, node);
b8f7fb13 1704 BUG_ON(!bau_desc);
b4c286e6 1705
6a469e46
JS
1706 gpa = uv_gpa(bau_desc);
1707 n = uv_gpa_to_gnode(gpa);
1708 m = uv_gpa_to_offset(gpa);
da87c937
CW
1709 if (is_uv1_hub())
1710 uv1 = 1;
b4c286e6 1711
77ed23f8 1712 /* the 14-bit pnode */
f073cc8f 1713 write_mmr_descriptor_base(pnode, (n << UV_DESC_PSHIFT | m));
0e2595cd 1714 /*
f073cc8f 1715 * Initializing all 8 (ITEMS_PER_DESC) descriptors for each
0e2595cd 1716 * cpu even though we only use the first one; one descriptor can
b8f7fb13 1717 * describe a broadcast to 256 uv hubs.
0e2595cd 1718 */
f073cc8f 1719 for (i = 0, bd2 = bau_desc; i < (ADP_SZ * ITEMS_PER_DESC); i++, bd2++) {
b8f7fb13 1720 memset(bd2, 0, sizeof(struct bau_desc));
da87c937
CW
1721 if (uv1) {
1722 uv1_hdr = &bd2->header.uv1_hdr;
1723 uv1_hdr->swack_flag = 1;
1724 /*
1725 * The base_dest_nasid set in the message header
1726 * is the nasid of the first uvhub in the partition.
1727 * The bit map will indicate destination pnode numbers
1728 * relative to that base. They may not be consecutive
1729 * if nasid striding is being used.
1730 */
1731 uv1_hdr->base_dest_nasid =
1732 UV_PNODE_TO_NASID(base_pnode);
1733 uv1_hdr->dest_subnodeid = UV_LB_SUBNODEID;
1734 uv1_hdr->command = UV_NET_ENDPOINT_INTD;
1735 uv1_hdr->int_both = 1;
1736 /*
1737 * all others need to be set to zero:
1738 * fairness chaining multilevel count replied_to
1739 */
1740 } else {
8b6e511e
CW
1741 /*
1742 * BIOS uses legacy mode, but UV2 hardware always
1743 * uses native mode for selective broadcasts.
1744 */
da87c937
CW
1745 uv2_hdr = &bd2->header.uv2_hdr;
1746 uv2_hdr->swack_flag = 1;
1747 uv2_hdr->base_dest_nasid =
1748 UV_PNODE_TO_NASID(base_pnode);
1749 uv2_hdr->dest_subnodeid = UV_LB_SUBNODEID;
1750 uv2_hdr->command = UV_NET_ENDPOINT_INTD;
1751 }
b194b120 1752 }
b8f7fb13
CW
1753 for_each_present_cpu(cpu) {
1754 if (pnode != uv_blade_to_pnode(uv_cpu_to_blade_id(cpu)))
1755 continue;
1756 bcp = &per_cpu(bau_control, cpu);
1757 bcp->descriptor_base = bau_desc;
1758 }
b194b120
CW
1759}
1760
1761/*
1762 * initialize the destination side's receiving buffers
b8f7fb13
CW
1763 * entered for each uvhub in the partition
1764 * - node is first node (kernel memory notion) on the uvhub
1765 * - pnode is the uvhub's physical identifier
b194b120 1766 */
f073cc8f 1767static void pq_init(int node, int pnode)
b194b120 1768{
b8f7fb13 1769 int cpu;
f073cc8f 1770 size_t plsize;
b4c286e6 1771 char *cp;
f073cc8f
CW
1772 void *vp;
1773 unsigned long pn;
1774 unsigned long first;
1775 unsigned long pn_first;
1776 unsigned long last;
1777 struct bau_pq_entry *pqp;
b8f7fb13 1778 struct bau_control *bcp;
1812924b 1779
f073cc8f
CW
1780 plsize = (DEST_Q_SIZE + 1) * sizeof(struct bau_pq_entry);
1781 vp = kmalloc_node(plsize, GFP_KERNEL, node);
1782 pqp = (struct bau_pq_entry *)vp;
dc163a41 1783 BUG_ON(!pqp);
b4c286e6 1784
b194b120 1785 cp = (char *)pqp + 31;
f073cc8f 1786 pqp = (struct bau_pq_entry *)(((unsigned long)cp >> 5) << 5);
b8f7fb13
CW
1787
1788 for_each_present_cpu(cpu) {
1789 if (pnode != uv_cpu_to_pnode(cpu))
1790 continue;
1791 /* for every cpu on this pnode: */
1792 bcp = &per_cpu(bau_control, cpu);
f073cc8f
CW
1793 bcp->queue_first = pqp;
1794 bcp->bau_msg_head = pqp;
1795 bcp->queue_last = pqp + (DEST_Q_SIZE - 1);
b8f7fb13 1796 }
4ea3c51d 1797 /*
6a469e46 1798 * need the gnode of where the memory was really allocated
4ea3c51d 1799 */
6a469e46 1800 pn = uv_gpa_to_gnode(uv_gpa(pqp));
f073cc8f
CW
1801 first = uv_physnodeaddr(pqp);
1802 pn_first = ((unsigned long)pn << UV_PAYLOADQ_PNODE_SHIFT) | first;
1803 last = uv_physnodeaddr(pqp + (DEST_Q_SIZE - 1));
1804 write_mmr_payload_first(pnode, pn_first);
1805 write_mmr_payload_tail(pnode, first);
1806 write_mmr_payload_last(pnode, last);
c5d35d39 1807 write_gmmr_sw_ack(pnode, 0xffffUL);
f073cc8f 1808
b8f7fb13 1809 /* in effect, all msg_type's are set to MSG_NOOP */
f073cc8f 1810 memset(pqp, 0, sizeof(struct bau_pq_entry) * DEST_Q_SIZE);
b194b120 1811}
1812924b 1812
b194b120 1813/*
b8f7fb13 1814 * Initialization of each UV hub's structures
b194b120 1815 */
f073cc8f 1816static void __init init_uvhub(int uvhub, int vector, int base_pnode)
b194b120 1817{
9674f35b 1818 int node;
b194b120 1819 int pnode;
b194b120 1820 unsigned long apicid;
b8f7fb13
CW
1821
1822 node = uvhub_to_first_node(uvhub);
1823 pnode = uv_blade_to_pnode(uvhub);
f073cc8f
CW
1824
1825 activation_descriptor_init(node, pnode, base_pnode);
1826
1827 pq_init(node, pnode);
b194b120 1828 /*
77ed23f8
CW
1829 * The below initialization can't be in firmware because the
1830 * messaging IRQ will be determined by the OS.
b194b120 1831 */
8191c9f6 1832 apicid = uvhub_to_first_apicid(uvhub) | uv_apicid_hibits;
f073cc8f 1833 write_mmr_data_config(pnode, ((apicid << 32) | vector));
b8f7fb13
CW
1834}
1835
12a6611f
CW
1836/*
1837 * We will set BAU_MISC_CONTROL with a timeout period.
1838 * But the BIOS has set UVH_AGING_PRESCALE_SEL and UVH_TRANSACTION_TIMEOUT.
f073cc8f 1839 * So the destination timeout period has to be calculated from them.
12a6611f 1840 */
f073cc8f 1841static int calculate_destination_timeout(void)
12a6611f
CW
1842{
1843 unsigned long mmr_image;
1844 int mult1;
1845 int mult2;
1846 int index;
1847 int base;
1848 int ret;
1849 unsigned long ts_ns;
1850
2a919596 1851 if (is_uv1_hub()) {
f073cc8f 1852 mult1 = SOFTACK_TIMEOUT_PERIOD & BAU_MISC_CONTROL_MULT_MASK;
2a919596
JS
1853 mmr_image = uv_read_local_mmr(UVH_AGING_PRESCALE_SEL);
1854 index = (mmr_image >> BAU_URGENCY_7_SHIFT) & BAU_URGENCY_7_MASK;
1855 mmr_image = uv_read_local_mmr(UVH_TRANSACTION_TIMEOUT);
1856 mult2 = (mmr_image >> BAU_TRANS_SHIFT) & BAU_TRANS_MASK;
11cab711
CW
1857 ts_ns = timeout_base_ns[index];
1858 ts_ns *= (mult1 * mult2);
2a919596
JS
1859 ret = ts_ns / 1000;
1860 } else {
d059f9fa
CW
1861 /* 4 bits 0/1 for 10/80us base, 3 bits of multiplier */
1862 mmr_image = uv_read_local_mmr(UVH_LB_BAU_MISC_CONTROL);
2a919596 1863 mmr_image = (mmr_image & UV_SA_MASK) >> UV_SA_SHFT;
f073cc8f 1864 if (mmr_image & (1L << UV2_ACK_UNITS_SHFT))
d059f9fa 1865 base = 80;
2a919596 1866 else
d059f9fa
CW
1867 base = 10;
1868 mult1 = mmr_image & UV2_ACK_MASK;
2a919596
JS
1869 ret = mult1 * base;
1870 }
12a6611f
CW
1871 return ret;
1872}
1873
f073cc8f
CW
1874static void __init init_per_cpu_tunables(void)
1875{
1876 int cpu;
1877 struct bau_control *bcp;
1878
1879 for_each_present_cpu(cpu) {
1880 bcp = &per_cpu(bau_control, cpu);
1881 bcp->baudisabled = 0;
26ef8577
CW
1882 if (nobau)
1883 bcp->nobau = 1;
f073cc8f
CW
1884 bcp->statp = &per_cpu(ptcstats, cpu);
1885 /* time interval to catch a hardware stay-busy bug */
1886 bcp->timeout_interval = usec_2_cycles(2*timeout_us);
1887 bcp->max_concurr = max_concurr;
1888 bcp->max_concurr_const = max_concurr;
1889 bcp->plugged_delay = plugged_delay;
1890 bcp->plugsb4reset = plugsb4reset;
1891 bcp->timeoutsb4reset = timeoutsb4reset;
1892 bcp->ipi_reset_limit = ipi_reset_limit;
1893 bcp->complete_threshold = complete_threshold;
1894 bcp->cong_response_us = congested_respns_us;
1895 bcp->cong_reps = congested_reps;
8b6e511e
CW
1896 bcp->disabled_period = sec_2_cycles(disabled_period);
1897 bcp->giveup_limit = giveup_limit;
d2ebc71d
CW
1898 spin_lock_init(&bcp->queue_lock);
1899 spin_lock_init(&bcp->uvhub_lock);
8b6e511e 1900 spin_lock_init(&bcp->disable_lock);
f073cc8f
CW
1901 }
1902}
1903
b8f7fb13 1904/*
f073cc8f 1905 * Scan all cpus to collect blade and socket summaries.
b8f7fb13 1906 */
f073cc8f
CW
1907static int __init get_cpu_topology(int base_pnode,
1908 struct uvhub_desc *uvhub_descs,
1909 unsigned char *uvhub_mask)
b8f7fb13 1910{
b8f7fb13
CW
1911 int cpu;
1912 int pnode;
1913 int uvhub;
f073cc8f 1914 int socket;
b8f7fb13
CW
1915 struct bau_control *bcp;
1916 struct uvhub_desc *bdp;
1917 struct socket_desc *sdp;
b8f7fb13 1918
b8f7fb13
CW
1919 for_each_present_cpu(cpu) {
1920 bcp = &per_cpu(bau_control, cpu);
f073cc8f 1921
b8f7fb13 1922 memset(bcp, 0, sizeof(struct bau_control));
f073cc8f 1923
b8f7fb13 1924 pnode = uv_cpu_hub_info(cpu)->pnode;
f073cc8f 1925 if ((pnode - base_pnode) >= UV_DISTRIBUTION_SIZE) {
77ed23f8
CW
1926 printk(KERN_EMERG
1927 "cpu %d pnode %d-%d beyond %d; BAU disabled\n",
f073cc8f 1928 cpu, pnode, base_pnode, UV_DISTRIBUTION_SIZE);
77ed23f8
CW
1929 return 1;
1930 }
f073cc8f 1931
77ed23f8 1932 bcp->osnode = cpu_to_node(cpu);
f073cc8f
CW
1933 bcp->partition_base_pnode = base_pnode;
1934
b8f7fb13 1935 uvhub = uv_cpu_hub_info(cpu)->numa_blade_id;
c4026cfd 1936 *(uvhub_mask + (uvhub/8)) |= (1 << (uvhub%8));
b8f7fb13 1937 bdp = &uvhub_descs[uvhub];
f073cc8f 1938
b8f7fb13
CW
1939 bdp->num_cpus++;
1940 bdp->uvhub = uvhub;
1941 bdp->pnode = pnode;
f073cc8f 1942
a8328ee5
CW
1943 /* kludge: 'assuming' one node per socket, and assuming that
1944 disabling a socket just leaves a gap in node numbers */
77ed23f8 1945 socket = bcp->osnode & 1;
a8328ee5 1946 bdp->socket_mask |= (1 << socket);
b8f7fb13
CW
1947 sdp = &bdp->socket[socket];
1948 sdp->cpu_number[sdp->num_cpus] = cpu;
1949 sdp->num_cpus++;
cfa60917 1950 if (sdp->num_cpus > MAX_CPUS_PER_SOCKET) {
f073cc8f
CW
1951 printk(KERN_EMERG "%d cpus per socket invalid\n",
1952 sdp->num_cpus);
cfa60917
CW
1953 return 1;
1954 }
b8f7fb13 1955 }
f073cc8f
CW
1956 return 0;
1957}
1958
1959/*
1960 * Each socket is to get a local array of pnodes/hubs.
1961 */
1962static void make_per_cpu_thp(struct bau_control *smaster)
1963{
1964 int cpu;
1965 size_t hpsz = sizeof(struct hub_and_pnode) * num_possible_cpus();
1966
1967 smaster->thp = kmalloc_node(hpsz, GFP_KERNEL, smaster->osnode);
1968 memset(smaster->thp, 0, hpsz);
1969 for_each_present_cpu(cpu) {
1970 smaster->thp[cpu].pnode = uv_cpu_hub_info(cpu)->pnode;
1971 smaster->thp[cpu].uvhub = uv_cpu_hub_info(cpu)->numa_blade_id;
1972 }
1973}
1974
442d3924 1975/*
1976 * Each uvhub is to get a local cpumask.
1977 */
1978static void make_per_hub_cpumask(struct bau_control *hmaster)
1979{
1980 int sz = sizeof(cpumask_t);
1981
1982 hmaster->cpumask = kzalloc_node(sz, GFP_KERNEL, hmaster->osnode);
1983}
1984
f073cc8f
CW
1985/*
1986 * Initialize all the per_cpu information for the cpu's on a given socket,
1987 * given what has been gathered into the socket_desc struct.
1988 * And reports the chosen hub and socket masters back to the caller.
1989 */
1990static int scan_sock(struct socket_desc *sdp, struct uvhub_desc *bdp,
1991 struct bau_control **smasterp,
1992 struct bau_control **hmasterp)
1993{
1994 int i;
1995 int cpu;
1996 struct bau_control *bcp;
1997
1998 for (i = 0; i < sdp->num_cpus; i++) {
1999 cpu = sdp->cpu_number[i];
2000 bcp = &per_cpu(bau_control, cpu);
2001 bcp->cpu = cpu;
2002 if (i == 0) {
2003 *smasterp = bcp;
2004 if (!(*hmasterp))
2005 *hmasterp = bcp;
2006 }
2007 bcp->cpus_in_uvhub = bdp->num_cpus;
2008 bcp->cpus_in_socket = sdp->num_cpus;
2009 bcp->socket_master = *smasterp;
2010 bcp->uvhub = bdp->uvhub;
da87c937
CW
2011 if (is_uv1_hub())
2012 bcp->uvhub_version = 1;
2013 else if (is_uv2_hub())
2014 bcp->uvhub_version = 2;
2015 else {
2016 printk(KERN_EMERG "uvhub version not 1 or 2\n");
2017 return 1;
2018 }
f073cc8f
CW
2019 bcp->uvhub_master = *hmasterp;
2020 bcp->uvhub_cpu = uv_cpu_hub_info(cpu)->blade_processor_id;
2021 if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) {
2022 printk(KERN_EMERG "%d cpus per uvhub invalid\n",
2023 bcp->uvhub_cpu);
2024 return 1;
2025 }
2026 }
2027 return 0;
2028}
2029
2030/*
2031 * Summarize the blade and socket topology into the per_cpu structures.
2032 */
2033static int __init summarize_uvhub_sockets(int nuvhubs,
2034 struct uvhub_desc *uvhub_descs,
2035 unsigned char *uvhub_mask)
2036{
2037 int socket;
2038 int uvhub;
2039 unsigned short socket_mask;
2040
c4026cfd 2041 for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
f073cc8f
CW
2042 struct uvhub_desc *bdp;
2043 struct bau_control *smaster = NULL;
2044 struct bau_control *hmaster = NULL;
2045
c4026cfd
CW
2046 if (!(*(uvhub_mask + (uvhub/8)) & (1 << (uvhub%8))))
2047 continue;
f073cc8f 2048
b8f7fb13 2049 bdp = &uvhub_descs[uvhub];
a8328ee5
CW
2050 socket_mask = bdp->socket_mask;
2051 socket = 0;
2052 while (socket_mask) {
f073cc8f
CW
2053 struct socket_desc *sdp;
2054 if ((socket_mask & 1)) {
2055 sdp = &bdp->socket[socket];
2056 if (scan_sock(sdp, bdp, &smaster, &hmaster))
cfa60917 2057 return 1;
9c9153db 2058 make_per_cpu_thp(smaster);
b8f7fb13
CW
2059 }
2060 socket++;
a8328ee5 2061 socket_mask = (socket_mask >> 1);
b8f7fb13 2062 }
442d3924 2063 make_per_hub_cpumask(hmaster);
b8f7fb13 2064 }
f073cc8f
CW
2065 return 0;
2066}
2067
2068/*
2069 * initialize the bau_control structure for each cpu
2070 */
2071static int __init init_per_cpu(int nuvhubs, int base_part_pnode)
2072{
2073 unsigned char *uvhub_mask;
2074 void *vp;
2075 struct uvhub_desc *uvhub_descs;
2076
2077 timeout_us = calculate_destination_timeout();
2078
2079 vp = kmalloc(nuvhubs * sizeof(struct uvhub_desc), GFP_KERNEL);
2080 uvhub_descs = (struct uvhub_desc *)vp;
2081 memset(uvhub_descs, 0, nuvhubs * sizeof(struct uvhub_desc));
2082 uvhub_mask = kzalloc((nuvhubs+7)/8, GFP_KERNEL);
2083
2084 if (get_cpu_topology(base_part_pnode, uvhub_descs, uvhub_mask))
bbd270e6 2085 goto fail;
f073cc8f
CW
2086
2087 if (summarize_uvhub_sockets(nuvhubs, uvhub_descs, uvhub_mask))
bbd270e6 2088 goto fail;
f073cc8f 2089
b8f7fb13 2090 kfree(uvhub_descs);
c4026cfd 2091 kfree(uvhub_mask);
f073cc8f 2092 init_per_cpu_tunables();
cfa60917 2093 return 0;
bbd270e6 2094
2095fail:
2096 kfree(uvhub_descs);
2097 kfree(uvhub_mask);
2098 return 1;
b194b120
CW
2099}
2100
2101/*
2102 * Initialization of BAU-related structures
2103 */
2104static int __init uv_bau_init(void)
2105{
b8f7fb13
CW
2106 int uvhub;
2107 int pnode;
2108 int nuvhubs;
2c74d666 2109 int cur_cpu;
f073cc8f 2110 int cpus;
b8f7fb13 2111 int vector;
f073cc8f 2112 cpumask_var_t *mask;
b194b120
CW
2113
2114 if (!is_uv_system())
2115 return 0;
1812924b 2116
f073cc8f
CW
2117 for_each_possible_cpu(cur_cpu) {
2118 mask = &per_cpu(uv_flush_tlb_mask, cur_cpu);
2119 zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cur_cpu));
2120 }
76ba0ecd 2121
b8f7fb13 2122 nuvhubs = uv_num_possible_blades();
f073cc8f 2123 congested_cycles = usec_2_cycles(congested_respns_us);
9674f35b 2124
f073cc8f 2125 uv_base_pnode = 0x7fffffff;
77ed23f8 2126 for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
f073cc8f
CW
2127 cpus = uv_blade_nr_possible_cpus(uvhub);
2128 if (cpus && (uv_blade_to_pnode(uvhub) < uv_base_pnode))
2129 uv_base_pnode = uv_blade_to_pnode(uvhub);
77ed23f8
CW
2130 }
2131
d059f9fa
CW
2132 enable_timeouts();
2133
f073cc8f 2134 if (init_per_cpu(nuvhubs, uv_base_pnode)) {
26ef8577
CW
2135 set_bau_off();
2136 nobau_perm = 1;
77ed23f8
CW
2137 return 0;
2138 }
b8f7fb13
CW
2139
2140 vector = UV_BAU_MESSAGE;
2141 for_each_possible_blade(uvhub)
2142 if (uv_blade_nr_possible_cpus(uvhub))
f073cc8f 2143 init_uvhub(uvhub, vector, uv_base_pnode);
b8f7fb13 2144
b8f7fb13
CW
2145 alloc_intr_gate(vector, uv_bau_message_intr1);
2146
2147 for_each_possible_blade(uvhub) {
93a7ca0c 2148 if (uv_blade_nr_possible_cpus(uvhub)) {
f073cc8f
CW
2149 unsigned long val;
2150 unsigned long mmr;
93a7ca0c
CW
2151 pnode = uv_blade_to_pnode(uvhub);
2152 /* INIT the bau */
f073cc8f
CW
2153 val = 1L << 63;
2154 write_gmmr_activation(pnode, val);
93a7ca0c 2155 mmr = 1; /* should be 1 to broadcast to both sockets */
da87c937
CW
2156 if (!is_uv1_hub())
2157 write_mmr_data_broadcast(pnode, mmr);
93a7ca0c 2158 }
b8f7fb13 2159 }
b4c286e6 2160
1812924b
CW
2161 return 0;
2162}
b8f7fb13 2163core_initcall(uv_bau_init);
e8e5e8a8 2164fs_initcall(uv_ptc_init);
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