x86, UV: Add support for SGI UV2 hub chip
[deliverable/linux.git] / arch / x86 / platform / uv / tlb_uv.c
CommitLineData
1812924b
CW
1/*
2 * SGI UltraViolet TLB flush routines.
3 *
b8f7fb13 4 * (c) 2008-2010 Cliff Wickman <cpw@sgi.com>, SGI.
1812924b
CW
5 *
6 * This code is released under the GNU General Public License version 2 or
7 * later.
8 */
aef8f5b8 9#include <linux/seq_file.h>
1812924b 10#include <linux/proc_fs.h>
e8e5e8a8 11#include <linux/debugfs.h>
1812924b 12#include <linux/kernel.h>
5a0e3ad6 13#include <linux/slab.h>
ca444564 14#include <linux/delay.h>
1812924b 15
1812924b 16#include <asm/mmu_context.h>
bdbcdd48 17#include <asm/uv/uv.h>
1812924b 18#include <asm/uv/uv_mmrs.h>
b4c286e6 19#include <asm/uv/uv_hub.h>
1812924b 20#include <asm/uv/uv_bau.h>
7b6aa335 21#include <asm/apic.h>
b4c286e6 22#include <asm/idle.h>
b194b120 23#include <asm/tsc.h>
99dd8713 24#include <asm/irq_vectors.h>
b8f7fb13 25#include <asm/timer.h>
1812924b 26
12a6611f
CW
27/* timeouts in nanoseconds (indexed by UVH_AGING_PRESCALE_SEL urgency7 30:28) */
28static int timeout_base_ns[] = {
29 20,
30 160,
31 1280,
32 10240,
33 81920,
34 655360,
35 5242880,
36 167772160
37};
38static int timeout_us;
e8e5e8a8 39static int nobau;
50fb55ac
CW
40static int baudisabled;
41static spinlock_t disable_lock;
42static cycles_t congested_cycles;
12a6611f 43
e8e5e8a8
CW
44/* tunables: */
45static int max_bau_concurrent = MAX_BAU_CONCURRENT;
46static int max_bau_concurrent_constant = MAX_BAU_CONCURRENT;
47static int plugged_delay = PLUGGED_DELAY;
48static int plugsb4reset = PLUGSB4RESET;
49static int timeoutsb4reset = TIMEOUTSB4RESET;
50static int ipi_reset_limit = IPI_RESET_LIMIT;
51static int complete_threshold = COMPLETE_THRESHOLD;
52static int congested_response_us = CONGESTED_RESPONSE_US;
53static int congested_reps = CONGESTED_REPS;
54static int congested_period = CONGESTED_PERIOD;
55static struct dentry *tunables_dir;
56static struct dentry *tunables_file;
b4c286e6 57
b8f7fb13
CW
58static int __init setup_nobau(char *arg)
59{
60 nobau = 1;
61 return 0;
62}
63early_param("nobau", setup_nobau);
b4c286e6 64
b8f7fb13
CW
65/* base pnode in this partition */
66static int uv_partition_base_pnode __read_mostly;
67/* position of pnode (which is nasid>>1): */
68static int uv_nshift __read_mostly;
69static unsigned long uv_mmask __read_mostly;
1812924b 70
dc163a41
IM
71static DEFINE_PER_CPU(struct ptc_stats, ptcstats);
72static DEFINE_PER_CPU(struct bau_control, bau_control);
b8f7fb13
CW
73static DEFINE_PER_CPU(cpumask_var_t, uv_flush_tlb_mask);
74
9674f35b 75/*
b8f7fb13
CW
76 * Determine the first node on a uvhub. 'Nodes' are used for kernel
77 * memory allocation.
9674f35b 78 */
b8f7fb13 79static int __init uvhub_to_first_node(int uvhub)
9674f35b
CW
80{
81 int node, b;
82
83 for_each_online_node(node) {
84 b = uv_node_to_blade_id(node);
b8f7fb13 85 if (uvhub == b)
9674f35b
CW
86 return node;
87 }
b8f7fb13 88 return -1;
9674f35b
CW
89}
90
91/*
b8f7fb13 92 * Determine the apicid of the first cpu on a uvhub.
9674f35b 93 */
b8f7fb13 94static int __init uvhub_to_first_apicid(int uvhub)
9674f35b
CW
95{
96 int cpu;
97
98 for_each_present_cpu(cpu)
b8f7fb13 99 if (uvhub == uv_cpu_to_blade_id(cpu))
9674f35b
CW
100 return per_cpu(x86_cpu_to_apicid, cpu);
101 return -1;
102}
103
1812924b
CW
104/*
105 * Free a software acknowledge hardware resource by clearing its Pending
106 * bit. This will return a reply to the sender.
107 * If the message has timed out, a reply has already been sent by the
108 * hardware but the resource has not been released. In that case our
109 * clear of the Timeout bit (as well) will free the resource. No reply will
110 * be sent (the hardware will only do one reply per message).
111 */
b8f7fb13
CW
112static inline void uv_reply_to_message(struct msg_desc *mdp,
113 struct bau_control *bcp)
1812924b 114{
b194b120 115 unsigned long dw;
b8f7fb13 116 struct bau_payload_queue_entry *msg;
1812924b 117
b8f7fb13
CW
118 msg = mdp->msg;
119 if (!msg->canceled) {
120 dw = (msg->sw_ack_vector << UV_SW_ACK_NPENDING) |
121 msg->sw_ack_vector;
122 uv_write_local_mmr(
123 UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, dw);
124 }
1812924b
CW
125 msg->replied_to = 1;
126 msg->sw_ack_vector = 0;
1812924b
CW
127}
128
129/*
b8f7fb13 130 * Process the receipt of a RETRY message
1812924b 131 */
b8f7fb13
CW
132static inline void uv_bau_process_retry_msg(struct msg_desc *mdp,
133 struct bau_control *bcp)
1812924b 134{
b8f7fb13
CW
135 int i;
136 int cancel_count = 0;
137 int slot2;
138 unsigned long msg_res;
139 unsigned long mmr = 0;
140 struct bau_payload_queue_entry *msg;
141 struct bau_payload_queue_entry *msg2;
142 struct ptc_stats *stat;
1812924b 143
b8f7fb13 144 msg = mdp->msg;
712157aa 145 stat = bcp->statp;
b8f7fb13
CW
146 stat->d_retries++;
147 /*
148 * cancel any message from msg+1 to the retry itself
149 */
150 for (msg2 = msg+1, i = 0; i < DEST_Q_SIZE; msg2++, i++) {
151 if (msg2 > mdp->va_queue_last)
152 msg2 = mdp->va_queue_first;
153 if (msg2 == msg)
154 break;
155
156 /* same conditions for cancellation as uv_do_reset */
157 if ((msg2->replied_to == 0) && (msg2->canceled == 0) &&
158 (msg2->sw_ack_vector) && ((msg2->sw_ack_vector &
159 msg->sw_ack_vector) == 0) &&
160 (msg2->sending_cpu == msg->sending_cpu) &&
161 (msg2->msg_type != MSG_NOOP)) {
162 slot2 = msg2 - mdp->va_queue_first;
163 mmr = uv_read_local_mmr
164 (UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
39847e7f 165 msg_res = msg2->sw_ack_vector;
b8f7fb13
CW
166 /*
167 * This is a message retry; clear the resources held
168 * by the previous message only if they timed out.
169 * If it has not timed out we have an unexpected
170 * situation to report.
171 */
39847e7f 172 if (mmr & (msg_res << UV_SW_ACK_NPENDING)) {
b8f7fb13
CW
173 /*
174 * is the resource timed out?
175 * make everyone ignore the cancelled message.
176 */
177 msg2->canceled = 1;
178 stat->d_canceled++;
179 cancel_count++;
180 uv_write_local_mmr(
181 UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS,
39847e7f
CW
182 (msg_res << UV_SW_ACK_NPENDING) |
183 msg_res);
184 }
b8f7fb13
CW
185 }
186 }
187 if (!cancel_count)
188 stat->d_nocanceled++;
189}
1812924b 190
b8f7fb13
CW
191/*
192 * Do all the things a cpu should do for a TLB shootdown message.
193 * Other cpu's may come here at the same time for this message.
194 */
195static void uv_bau_process_message(struct msg_desc *mdp,
196 struct bau_control *bcp)
197{
198 int msg_ack_count;
199 short socket_ack_count = 0;
200 struct ptc_stats *stat;
201 struct bau_payload_queue_entry *msg;
202 struct bau_control *smaster = bcp->socket_master;
1812924b 203
b8f7fb13
CW
204 /*
205 * This must be a normal message, or retry of a normal message
206 */
207 msg = mdp->msg;
712157aa 208 stat = bcp->statp;
1812924b
CW
209 if (msg->address == TLB_FLUSH_ALL) {
210 local_flush_tlb();
b8f7fb13 211 stat->d_alltlb++;
1812924b
CW
212 } else {
213 __flush_tlb_one(msg->address);
b8f7fb13 214 stat->d_onetlb++;
1812924b 215 }
b8f7fb13
CW
216 stat->d_requestee++;
217
218 /*
219 * One cpu on each uvhub has the additional job on a RETRY
220 * of releasing the resource held by the message that is
221 * being retried. That message is identified by sending
222 * cpu number.
223 */
224 if (msg->msg_type == MSG_RETRY && bcp == bcp->uvhub_master)
225 uv_bau_process_retry_msg(mdp, bcp);
1812924b 226
b8f7fb13
CW
227 /*
228 * This is a sw_ack message, so we have to reply to it.
229 * Count each responding cpu on the socket. This avoids
230 * pinging the count's cache line back and forth between
231 * the sockets.
232 */
233 socket_ack_count = atomic_add_short_return(1, (struct atomic_short *)
234 &smaster->socket_acknowledge_count[mdp->msg_slot]);
235 if (socket_ack_count == bcp->cpus_in_socket) {
236 /*
237 * Both sockets dump their completed count total into
238 * the message's count.
239 */
240 smaster->socket_acknowledge_count[mdp->msg_slot] = 0;
241 msg_ack_count = atomic_add_short_return(socket_ack_count,
242 (struct atomic_short *)&msg->acknowledge_count);
243
244 if (msg_ack_count == bcp->cpus_in_uvhub) {
245 /*
246 * All cpus in uvhub saw it; reply
247 */
248 uv_reply_to_message(mdp, bcp);
249 }
250 }
1812924b 251
b8f7fb13 252 return;
1812924b
CW
253}
254
255/*
b8f7fb13
CW
256 * Determine the first cpu on a uvhub.
257 */
258static int uvhub_to_first_cpu(int uvhub)
259{
260 int cpu;
261 for_each_present_cpu(cpu)
262 if (uvhub == uv_cpu_to_blade_id(cpu))
263 return cpu;
264 return -1;
265}
266
267/*
268 * Last resort when we get a large number of destination timeouts is
269 * to clear resources held by a given cpu.
270 * Do this with IPI so that all messages in the BAU message queue
271 * can be identified by their nonzero sw_ack_vector field.
1812924b 272 *
b8f7fb13
CW
273 * This is entered for a single cpu on the uvhub.
274 * The sender want's this uvhub to free a specific message's
275 * sw_ack resources.
1812924b 276 */
b8f7fb13
CW
277static void
278uv_do_reset(void *ptr)
1812924b 279{
b4c286e6 280 int i;
b8f7fb13
CW
281 int slot;
282 int count = 0;
283 unsigned long mmr;
284 unsigned long msg_res;
285 struct bau_control *bcp;
286 struct reset_args *rap;
287 struct bau_payload_queue_entry *msg;
288 struct ptc_stats *stat;
1812924b 289
b8f7fb13
CW
290 bcp = &per_cpu(bau_control, smp_processor_id());
291 rap = (struct reset_args *)ptr;
712157aa 292 stat = bcp->statp;
b8f7fb13
CW
293 stat->d_resets++;
294
295 /*
296 * We're looking for the given sender, and
297 * will free its sw_ack resource.
298 * If all cpu's finally responded after the timeout, its
299 * message 'replied_to' was set.
300 */
301 for (msg = bcp->va_queue_first, i = 0; i < DEST_Q_SIZE; msg++, i++) {
302 /* uv_do_reset: same conditions for cancellation as
303 uv_bau_process_retry_msg() */
304 if ((msg->replied_to == 0) &&
305 (msg->canceled == 0) &&
306 (msg->sending_cpu == rap->sender) &&
307 (msg->sw_ack_vector) &&
308 (msg->msg_type != MSG_NOOP)) {
309 /*
310 * make everyone else ignore this message
311 */
312 msg->canceled = 1;
313 slot = msg - bcp->va_queue_first;
314 count++;
315 /*
316 * only reset the resource if it is still pending
317 */
318 mmr = uv_read_local_mmr
319 (UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
39847e7f 320 msg_res = msg->sw_ack_vector;
b8f7fb13
CW
321 if (mmr & msg_res) {
322 stat->d_rcanceled++;
323 uv_write_local_mmr(
324 UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS,
39847e7f
CW
325 (msg_res << UV_SW_ACK_NPENDING) |
326 msg_res);
dc163a41 327 }
dc163a41
IM
328 }
329 }
b8f7fb13 330 return;
dc163a41
IM
331}
332
333/*
b8f7fb13
CW
334 * Use IPI to get all target uvhubs to release resources held by
335 * a given sending cpu number.
dc163a41 336 */
b8f7fb13
CW
337static void uv_reset_with_ipi(struct bau_target_uvhubmask *distribution,
338 int sender)
dc163a41 339{
b8f7fb13
CW
340 int uvhub;
341 int cpu;
342 cpumask_t mask;
343 struct reset_args reset_args;
dc163a41 344
b8f7fb13 345 reset_args.sender = sender;
dc163a41 346
b8f7fb13
CW
347 cpus_clear(mask);
348 /* find a single cpu for each uvhub in this distribution mask */
349 for (uvhub = 0;
350 uvhub < sizeof(struct bau_target_uvhubmask) * BITSPERBYTE;
351 uvhub++) {
352 if (!bau_uvhub_isset(uvhub, distribution))
b194b120 353 continue;
b8f7fb13
CW
354 /* find a cpu for this uvhub */
355 cpu = uvhub_to_first_cpu(uvhub);
356 cpu_set(cpu, mask);
1812924b 357 }
b8f7fb13
CW
358 /* IPI all cpus; Preemption is already disabled */
359 smp_call_function_many(&mask, uv_do_reset, (void *)&reset_args, 1);
360 return;
361}
362
363static inline unsigned long
364cycles_2_us(unsigned long long cyc)
365{
366 unsigned long long ns;
367 unsigned long us;
368 ns = (cyc * per_cpu(cyc2ns, smp_processor_id()))
369 >> CYC2NS_SCALE_FACTOR;
370 us = ns / 1000;
371 return us;
1812924b
CW
372}
373
b194b120 374/*
b8f7fb13
CW
375 * wait for all cpus on this hub to finish their sends and go quiet
376 * leaves uvhub_quiesce set so that no new broadcasts are started by
377 * bau_flush_send_and_wait()
378 */
379static inline void
380quiesce_local_uvhub(struct bau_control *hmaster)
381{
382 atomic_add_short_return(1, (struct atomic_short *)
383 &hmaster->uvhub_quiesce);
384}
385
386/*
387 * mark this quiet-requestor as done
388 */
389static inline void
390end_uvhub_quiesce(struct bau_control *hmaster)
391{
392 atomic_add_short_return(-1, (struct atomic_short *)
393 &hmaster->uvhub_quiesce);
394}
395
396/*
397 * Wait for completion of a broadcast software ack message
398 * return COMPLETE, RETRY(PLUGGED or TIMEOUT) or GIVEUP
b194b120 399 */
2a919596 400static int uv1_wait_completion(struct bau_desc *bau_desc,
b8f7fb13
CW
401 unsigned long mmr_offset, int right_shift, int this_cpu,
402 struct bau_control *bcp, struct bau_control *smaster, long try)
b194b120 403{
b194b120 404 unsigned long descriptor_status;
b8f7fb13 405 cycles_t ttime;
712157aa 406 struct ptc_stats *stat = bcp->statp;
b194b120 407
b8f7fb13 408 /* spin on the status MMR, waiting for it to go idle */
b194b120
CW
409 while ((descriptor_status = (((unsigned long)
410 uv_read_local_mmr(mmr_offset) >>
411 right_shift) & UV_ACT_STATUS_MASK)) !=
412 DESC_STATUS_IDLE) {
b194b120 413 /*
2a919596
JS
414 * Our software ack messages may be blocked because
415 * there are no swack resources available. As long
416 * as none of them has timed out hardware will NACK
417 * our message and its state will stay IDLE.
b194b120 418 */
b8f7fb13
CW
419 if (descriptor_status == DESC_STATUS_SOURCE_TIMEOUT) {
420 stat->s_stimeout++;
421 return FLUSH_GIVEUP;
422 } else if (descriptor_status ==
2a919596
JS
423 DESC_STATUS_DESTINATION_TIMEOUT) {
424 stat->s_dtimeout++;
425 ttime = get_cycles();
426
427 /*
428 * Our retries may be blocked by all destination
429 * swack resources being consumed, and a timeout
430 * pending. In that case hardware returns the
431 * ERROR that looks like a destination timeout.
432 */
433 if (cycles_2_us(ttime - bcp->send_message) <
434 timeout_us) {
435 bcp->conseccompletes = 0;
436 return FLUSH_RETRY_PLUGGED;
437 }
438
439 bcp->conseccompletes = 0;
440 return FLUSH_RETRY_TIMEOUT;
441 } else {
442 /*
443 * descriptor_status is still BUSY
444 */
445 cpu_relax();
446 }
447 }
448 bcp->conseccompletes++;
449 return FLUSH_COMPLETE;
450}
451
452static int uv2_wait_completion(struct bau_desc *bau_desc,
453 unsigned long mmr_offset, int right_shift, int this_cpu,
454 struct bau_control *bcp, struct bau_control *smaster, long try)
455{
456 unsigned long descriptor_status;
457 unsigned long descriptor_status2;
458 int cpu;
459 cycles_t ttime;
460 struct ptc_stats *stat = bcp->statp;
461
462 /* UV2 has an extra bit of status */
463 cpu = bcp->uvhub_cpu;
464 /* spin on the status MMR, waiting for it to go idle */
465 descriptor_status = (((unsigned long)(uv_read_local_mmr
466 (mmr_offset)) >> right_shift) & UV_ACT_STATUS_MASK);
467 descriptor_status2 = (((unsigned long)uv_read_local_mmr
468 (UV2H_LB_BAU_SB_ACTIVATION_STATUS_2) >> cpu) & 0x1UL);
469 descriptor_status = (descriptor_status << 1) |
470 descriptor_status2;
471 while (descriptor_status != UV2H_DESC_IDLE) {
472 /*
473 * Our software ack messages may be blocked because
474 * there are no swack resources available. As long
475 * as none of them has timed out hardware will NACK
476 * our message and its state will stay IDLE.
477 */
478 if ((descriptor_status == UV2H_DESC_SOURCE_TIMEOUT) ||
479 (descriptor_status == UV2H_DESC_DEST_STRONG_NACK) ||
480 (descriptor_status == UV2H_DESC_DEST_PUT_ERR)) {
481 stat->s_stimeout++;
482 return FLUSH_GIVEUP;
483 } else if (descriptor_status == UV2H_DESC_DEST_TIMEOUT) {
b8f7fb13
CW
484 stat->s_dtimeout++;
485 ttime = get_cycles();
486
487 /*
488 * Our retries may be blocked by all destination
489 * swack resources being consumed, and a timeout
490 * pending. In that case hardware returns the
491 * ERROR that looks like a destination timeout.
492 */
12a6611f
CW
493 if (cycles_2_us(ttime - bcp->send_message) <
494 timeout_us) {
b8f7fb13
CW
495 bcp->conseccompletes = 0;
496 return FLUSH_RETRY_PLUGGED;
497 }
498
499 bcp->conseccompletes = 0;
500 return FLUSH_RETRY_TIMEOUT;
501 } else {
502 /*
503 * descriptor_status is still BUSY
504 */
505 cpu_relax();
b194b120 506 }
2a919596
JS
507 descriptor_status = (((unsigned long)(uv_read_local_mmr
508 (mmr_offset)) >> right_shift) &
509 UV_ACT_STATUS_MASK);
510 descriptor_status2 = (((unsigned long)uv_read_local_mmr
511 (UV2H_LB_BAU_SB_ACTIVATION_STATUS_2) >> cpu) &
512 0x1UL);
513 descriptor_status = (descriptor_status << 1) |
514 descriptor_status2;
b194b120 515 }
b8f7fb13 516 bcp->conseccompletes++;
b194b120
CW
517 return FLUSH_COMPLETE;
518}
519
2a919596
JS
520static int uv_wait_completion(struct bau_desc *bau_desc,
521 unsigned long mmr_offset, int right_shift, int this_cpu,
522 struct bau_control *bcp, struct bau_control *smaster, long try)
523{
524 if (is_uv1_hub())
525 return uv1_wait_completion(bau_desc, mmr_offset, right_shift,
526 this_cpu, bcp, smaster, try);
527 else
528 return uv2_wait_completion(bau_desc, mmr_offset, right_shift,
529 this_cpu, bcp, smaster, try);
530}
531
b8f7fb13
CW
532static inline cycles_t
533sec_2_cycles(unsigned long sec)
534{
535 unsigned long ns;
536 cycles_t cyc;
537
538 ns = sec * 1000000000;
539 cyc = (ns << CYC2NS_SCALE_FACTOR)/(per_cpu(cyc2ns, smp_processor_id()));
540 return cyc;
541}
542
543/*
544 * conditionally add 1 to *v, unless *v is >= u
545 * return 0 if we cannot add 1 to *v because it is >= u
546 * return 1 if we can add 1 to *v because it is < u
547 * the add is atomic
548 *
549 * This is close to atomic_add_unless(), but this allows the 'u' value
550 * to be lowered below the current 'v'. atomic_add_unless can only stop
551 * on equal.
552 */
553static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u)
554{
555 spin_lock(lock);
556 if (atomic_read(v) >= u) {
557 spin_unlock(lock);
558 return 0;
559 }
560 atomic_inc(v);
561 spin_unlock(lock);
562 return 1;
563}
564
f6d8a566
CW
565/*
566 * Our retries are blocked by all destination swack resources being
567 * in use, and a timeout is pending. In that case hardware immediately
568 * returns the ERROR that looks like a destination timeout.
569 */
570static void
571destination_plugged(struct bau_desc *bau_desc, struct bau_control *bcp,
572 struct bau_control *hmaster, struct ptc_stats *stat)
573{
574 udelay(bcp->plugged_delay);
575 bcp->plugged_tries++;
576 if (bcp->plugged_tries >= bcp->plugsb4reset) {
577 bcp->plugged_tries = 0;
578 quiesce_local_uvhub(hmaster);
579 spin_lock(&hmaster->queue_lock);
580 uv_reset_with_ipi(&bau_desc->distribution, bcp->cpu);
581 spin_unlock(&hmaster->queue_lock);
582 end_uvhub_quiesce(hmaster);
583 bcp->ipi_attempts++;
584 stat->s_resets_plug++;
585 }
586}
587
588static void
589destination_timeout(struct bau_desc *bau_desc, struct bau_control *bcp,
590 struct bau_control *hmaster, struct ptc_stats *stat)
591{
592 hmaster->max_bau_concurrent = 1;
593 bcp->timeout_tries++;
594 if (bcp->timeout_tries >= bcp->timeoutsb4reset) {
595 bcp->timeout_tries = 0;
596 quiesce_local_uvhub(hmaster);
597 spin_lock(&hmaster->queue_lock);
598 uv_reset_with_ipi(&bau_desc->distribution, bcp->cpu);
599 spin_unlock(&hmaster->queue_lock);
600 end_uvhub_quiesce(hmaster);
601 bcp->ipi_attempts++;
602 stat->s_resets_timeout++;
603 }
604}
605
50fb55ac
CW
606/*
607 * Completions are taking a very long time due to a congested numalink
608 * network.
609 */
610static void
611disable_for_congestion(struct bau_control *bcp, struct ptc_stats *stat)
612{
613 int tcpu;
614 struct bau_control *tbcp;
615
616 /* let only one cpu do this disabling */
617 spin_lock(&disable_lock);
618 if (!baudisabled && bcp->period_requests &&
619 ((bcp->period_time / bcp->period_requests) > congested_cycles)) {
620 /* it becomes this cpu's job to turn on the use of the
621 BAU again */
622 baudisabled = 1;
623 bcp->set_bau_off = 1;
624 bcp->set_bau_on_time = get_cycles() +
625 sec_2_cycles(bcp->congested_period);
626 stat->s_bau_disabled++;
627 for_each_present_cpu(tcpu) {
628 tbcp = &per_cpu(bau_control, tcpu);
629 tbcp->baudisabled = 1;
630 }
631 }
632 spin_unlock(&disable_lock);
633}
634
b194b120
CW
635/**
636 * uv_flush_send_and_wait
637 *
b8f7fb13 638 * Send a broadcast and wait for it to complete.
b194b120 639 *
f6d8a566 640 * The flush_mask contains the cpus the broadcast is to be sent to including
b8f7fb13 641 * cpus that are on the local uvhub.
b194b120 642 *
450a007e
CW
643 * Returns 0 if all flushing represented in the mask was done.
644 * Returns 1 if it gives up entirely and the original cpu mask is to be
645 * returned to the kernel.
b194b120 646 */
450a007e
CW
647int uv_flush_send_and_wait(struct bau_desc *bau_desc,
648 struct cpumask *flush_mask, struct bau_control *bcp)
b194b120 649{
b194b120 650 int right_shift;
b8f7fb13
CW
651 int completion_status = 0;
652 int seq_number = 0;
653 long try = 0;
654 int cpu = bcp->uvhub_cpu;
655 int this_cpu = bcp->cpu;
b194b120 656 unsigned long mmr_offset;
b4c286e6 657 unsigned long index;
b194b120
CW
658 cycles_t time1;
659 cycles_t time2;
e8e5e8a8 660 cycles_t elapsed;
712157aa 661 struct ptc_stats *stat = bcp->statp;
b8f7fb13
CW
662 struct bau_control *smaster = bcp->socket_master;
663 struct bau_control *hmaster = bcp->uvhub_master;
664
2a919596
JS
665 if (is_uv1_hub() &&
666 !atomic_inc_unless_ge(&hmaster->uvhub_lock,
b8f7fb13 667 &hmaster->active_descriptor_count,
e8e5e8a8 668 hmaster->max_bau_concurrent)) {
b8f7fb13
CW
669 stat->s_throttles++;
670 do {
671 cpu_relax();
672 } while (!atomic_inc_unless_ge(&hmaster->uvhub_lock,
673 &hmaster->active_descriptor_count,
e8e5e8a8 674 hmaster->max_bau_concurrent));
b8f7fb13 675 }
b8f7fb13
CW
676 while (hmaster->uvhub_quiesce)
677 cpu_relax();
b194b120
CW
678
679 if (cpu < UV_CPUS_PER_ACT_STATUS) {
680 mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
681 right_shift = cpu * UV_ACT_STATUS_SIZE;
682 } else {
683 mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1;
684 right_shift =
685 ((cpu - UV_CPUS_PER_ACT_STATUS) * UV_ACT_STATUS_SIZE);
686 }
687 time1 = get_cycles();
688 do {
b8f7fb13 689 if (try == 0) {
7fba1bcd 690 bau_desc->header.msg_type = MSG_REGULAR;
b8f7fb13
CW
691 seq_number = bcp->message_number++;
692 } else {
b8f7fb13
CW
693 bau_desc->header.msg_type = MSG_RETRY;
694 stat->s_retry_messages++;
695 }
696 bau_desc->header.sequence = seq_number;
dc163a41 697 index = (1UL << UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT) |
b8f7fb13
CW
698 bcp->uvhub_cpu;
699 bcp->send_message = get_cycles();
b194b120 700 uv_write_local_mmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
b8f7fb13 701 try++;
b194b120 702 completion_status = uv_wait_completion(bau_desc, mmr_offset,
b8f7fb13
CW
703 right_shift, this_cpu, bcp, smaster, try);
704
705 if (completion_status == FLUSH_RETRY_PLUGGED) {
f6d8a566 706 destination_plugged(bau_desc, bcp, hmaster, stat);
b8f7fb13 707 } else if (completion_status == FLUSH_RETRY_TIMEOUT) {
f6d8a566 708 destination_timeout(bau_desc, bcp, hmaster, stat);
b8f7fb13 709 }
e8e5e8a8 710 if (bcp->ipi_attempts >= bcp->ipi_reset_limit) {
b8f7fb13
CW
711 bcp->ipi_attempts = 0;
712 completion_status = FLUSH_GIVEUP;
713 break;
714 }
715 cpu_relax();
716 } while ((completion_status == FLUSH_RETRY_PLUGGED) ||
717 (completion_status == FLUSH_RETRY_TIMEOUT));
b194b120 718 time2 = get_cycles();
e8e5e8a8
CW
719 bcp->plugged_tries = 0;
720 bcp->timeout_tries = 0;
e8e5e8a8
CW
721 if ((completion_status == FLUSH_COMPLETE) &&
722 (bcp->conseccompletes > bcp->complete_threshold) &&
723 (hmaster->max_bau_concurrent <
724 hmaster->max_bau_concurrent_constant))
725 hmaster->max_bau_concurrent++;
b8f7fb13
CW
726 while (hmaster->uvhub_quiesce)
727 cpu_relax();
728 atomic_dec(&hmaster->active_descriptor_count);
e8e5e8a8
CW
729 if (time2 > time1) {
730 elapsed = time2 - time1;
731 stat->s_time += elapsed;
50fb55ac
CW
732 if ((completion_status == FLUSH_COMPLETE) && (try == 1)) {
733 bcp->period_requests++;
734 bcp->period_time += elapsed;
735 if ((elapsed > congested_cycles) &&
736 (bcp->period_requests > bcp->congested_reps)) {
737 disable_for_congestion(bcp, stat);
738 }
739 }
e8e5e8a8 740 } else
450a007e 741 stat->s_requestor--;
b8f7fb13
CW
742 if (completion_status == FLUSH_COMPLETE && try > 1)
743 stat->s_retriesok++;
744 else if (completion_status == FLUSH_GIVEUP) {
b8f7fb13 745 stat->s_giveup++;
450a007e 746 return 1;
b194b120 747 }
450a007e 748 return 0;
b194b120
CW
749}
750
1812924b
CW
751/**
752 * uv_flush_tlb_others - globally purge translation cache of a virtual
753 * address or all TLB's
bdbcdd48 754 * @cpumask: mask of all cpu's in which the address is to be removed
1812924b
CW
755 * @mm: mm_struct containing virtual address range
756 * @va: virtual address to be removed (or TLB_FLUSH_ALL for all TLB's on cpu)
bdbcdd48 757 * @cpu: the current cpu
1812924b
CW
758 *
759 * This is the entry point for initiating any UV global TLB shootdown.
760 *
761 * Purges the translation caches of all specified processors of the given
762 * virtual address, or purges all TLB's on specified processors.
763 *
bdbcdd48
TH
764 * The caller has derived the cpumask from the mm_struct. This function
765 * is called only if there are bits set in the mask. (e.g. flush_tlb_page())
1812924b 766 *
b8f7fb13
CW
767 * The cpumask is converted into a uvhubmask of the uvhubs containing
768 * those cpus.
b194b120 769 *
bdbcdd48
TH
770 * Note that this function should be called with preemption disabled.
771 *
772 * Returns NULL if all remote flushing was done.
773 * Returns pointer to cpumask if some remote flushing remains to be
774 * done. The returned pointer is valid till preemption is re-enabled.
1812924b 775 */
bdbcdd48
TH
776const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
777 struct mm_struct *mm,
778 unsigned long va, unsigned int cpu)
1812924b 779{
b194b120 780 int locals = 0;
450a007e
CW
781 int remotes = 0;
782 int hubs = 0;
77ed23f8
CW
783 int tcpu;
784 int tpnode;
dc163a41 785 struct bau_desc *bau_desc;
b8f7fb13
CW
786 struct cpumask *flush_mask;
787 struct ptc_stats *stat;
788 struct bau_control *bcp;
50fb55ac 789 struct bau_control *tbcp;
77ed23f8 790 struct hub_and_pnode *hpp;
bdbcdd48 791
e8e5e8a8 792 /* kernel was booted 'nobau' */
b8f7fb13
CW
793 if (nobau)
794 return cpumask;
bdbcdd48 795
b8f7fb13 796 bcp = &per_cpu(bau_control, cpu);
712157aa 797 stat = bcp->statp;
50fb55ac
CW
798
799 /* bau was disabled due to slow response */
800 if (bcp->baudisabled) {
801 /* the cpu that disabled it must re-enable it */
802 if (bcp->set_bau_off) {
803 if (get_cycles() >= bcp->set_bau_on_time) {
804 stat->s_bau_reenabled++;
805 baudisabled = 0;
806 for_each_present_cpu(tcpu) {
807 tbcp = &per_cpu(bau_control, tcpu);
808 tbcp->baudisabled = 0;
809 tbcp->period_requests = 0;
810 tbcp->period_time = 0;
811 }
812 }
813 }
814 return cpumask;
815 }
e8e5e8a8 816
b8f7fb13
CW
817 /*
818 * Each sending cpu has a per-cpu mask which it fills from the caller's
450a007e
CW
819 * cpu mask. All cpus are converted to uvhubs and copied to the
820 * activation descriptor.
b8f7fb13
CW
821 */
822 flush_mask = (struct cpumask *)per_cpu(uv_flush_tlb_mask, cpu);
450a007e 823 /* don't actually do a shootdown of the local cpu */
b8f7fb13
CW
824 cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu));
825 if (cpu_isset(cpu, *cpumask))
450a007e 826 stat->s_ntargself++;
1812924b 827
b8f7fb13
CW
828 bau_desc = bcp->descriptor_base;
829 bau_desc += UV_ITEMS_PER_DESCRIPTOR * bcp->uvhub_cpu;
b8f7fb13 830 bau_uvhubs_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE);
450a007e 831
b8f7fb13 832 for_each_cpu(tcpu, flush_mask) {
77ed23f8
CW
833 /*
834 * The distribution vector is a bit map of pnodes, relative
835 * to the partition base pnode (and the partition base nasid
836 * in the header).
837 * Translate cpu to pnode and hub using an array stored
838 * in local memory.
839 */
840 hpp = &bcp->socket_master->target_hub_and_pnode[tcpu];
841 tpnode = hpp->pnode - bcp->partition_base_pnode;
842 bau_uvhub_set(tpnode, &bau_desc->distribution);
843 if (hpp->uvhub == bcp->uvhub)
450a007e 844 locals++;
b194b120 845 else
450a007e 846 remotes++;
b194b120 847 }
450a007e
CW
848 if ((locals + remotes) == 0)
849 return NULL;
b8f7fb13 850 stat->s_requestor++;
450a007e
CW
851 stat->s_ntargcpu += remotes + locals;
852 stat->s_ntargremotes += remotes;
853 stat->s_ntarglocals += locals;
b8f7fb13 854 remotes = bau_uvhub_weight(&bau_desc->distribution);
450a007e
CW
855
856 /* uvhub statistics */
857 hubs = bau_uvhub_weight(&bau_desc->distribution);
858 if (locals) {
859 stat->s_ntarglocaluvhub++;
860 stat->s_ntargremoteuvhub += (hubs - 1);
861 } else
862 stat->s_ntargremoteuvhub += hubs;
863 stat->s_ntarguvhub += hubs;
864 if (hubs >= 16)
b8f7fb13 865 stat->s_ntarguvhub16++;
450a007e 866 else if (hubs >= 8)
b8f7fb13 867 stat->s_ntarguvhub8++;
450a007e 868 else if (hubs >= 4)
b8f7fb13 869 stat->s_ntarguvhub4++;
450a007e 870 else if (hubs >= 2)
b8f7fb13
CW
871 stat->s_ntarguvhub2++;
872 else
873 stat->s_ntarguvhub1++;
1812924b
CW
874
875 bau_desc->payload.address = va;
bdbcdd48 876 bau_desc->payload.sending_cpu = cpu;
1812924b 877
b8f7fb13 878 /*
450a007e
CW
879 * uv_flush_send_and_wait returns 0 if all cpu's were messaged,
880 * or 1 if it gave up and the original cpumask should be returned.
b8f7fb13 881 */
450a007e
CW
882 if (!uv_flush_send_and_wait(bau_desc, flush_mask, bcp))
883 return NULL;
884 else
885 return cpumask;
1812924b
CW
886}
887
888/*
889 * The BAU message interrupt comes here. (registered by set_intr_gate)
890 * See entry_64.S
891 *
892 * We received a broadcast assist message.
893 *
b8f7fb13 894 * Interrupts are disabled; this interrupt could represent
1812924b
CW
895 * the receipt of several messages.
896 *
b8f7fb13
CW
897 * All cores/threads on this hub get this interrupt.
898 * The last one to see it does the software ack.
1812924b 899 * (the resource will not be freed until noninterruptable cpus see this
b8f7fb13 900 * interrupt; hardware may timeout the s/w ack and reply ERROR)
1812924b 901 */
b194b120 902void uv_bau_message_interrupt(struct pt_regs *regs)
1812924b 903{
1812924b 904 int count = 0;
b8f7fb13
CW
905 cycles_t time_start;
906 struct bau_payload_queue_entry *msg;
907 struct bau_control *bcp;
908 struct ptc_stats *stat;
909 struct msg_desc msgdesc;
910
911 time_start = get_cycles();
912 bcp = &per_cpu(bau_control, smp_processor_id());
712157aa 913 stat = bcp->statp;
b8f7fb13
CW
914 msgdesc.va_queue_first = bcp->va_queue_first;
915 msgdesc.va_queue_last = bcp->va_queue_last;
916 msg = bcp->bau_msg_head;
1812924b
CW
917 while (msg->sw_ack_vector) {
918 count++;
b8f7fb13
CW
919 msgdesc.msg_slot = msg - msgdesc.va_queue_first;
920 msgdesc.sw_ack_slot = ffs(msg->sw_ack_vector) - 1;
921 msgdesc.msg = msg;
922 uv_bau_process_message(&msgdesc, bcp);
1812924b 923 msg++;
b8f7fb13
CW
924 if (msg > msgdesc.va_queue_last)
925 msg = msgdesc.va_queue_first;
926 bcp->bau_msg_head = msg;
1812924b 927 }
b8f7fb13 928 stat->d_time += (get_cycles() - time_start);
1812924b 929 if (!count)
b8f7fb13 930 stat->d_nomsg++;
1812924b 931 else if (count > 1)
b8f7fb13
CW
932 stat->d_multmsg++;
933 ack_APIC_irq();
1812924b
CW
934}
935
c4c4688f
CW
936/*
937 * uv_enable_timeouts
938 *
b8f7fb13 939 * Each target uvhub (i.e. a uvhub that has no cpu's) needs to have
c4c4688f
CW
940 * shootdown message timeouts enabled. The timeout does not cause
941 * an interrupt, but causes an error message to be returned to
942 * the sender.
943 */
77ed23f8 944static void __init uv_enable_timeouts(void)
1812924b 945{
b8f7fb13
CW
946 int uvhub;
947 int nuvhubs;
1812924b 948 int pnode;
c4c4688f 949 unsigned long mmr_image;
1812924b 950
b8f7fb13 951 nuvhubs = uv_num_possible_blades();
1812924b 952
b8f7fb13
CW
953 for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
954 if (!uv_blade_nr_possible_cpus(uvhub))
1812924b 955 continue;
c4c4688f 956
b8f7fb13 957 pnode = uv_blade_to_pnode(uvhub);
c4c4688f
CW
958 mmr_image =
959 uv_read_global_mmr64(pnode, UVH_LB_BAU_MISC_CONTROL);
960 /*
961 * Set the timeout period and then lock it in, in three
962 * steps; captures and locks in the period.
963 *
964 * To program the period, the SOFT_ACK_MODE must be off.
965 */
966 mmr_image &= ~((unsigned long)1 <<
6f4edd69 967 UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT);
c4c4688f
CW
968 uv_write_global_mmr64
969 (pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
970 /*
971 * Set the 4-bit period.
972 */
973 mmr_image &= ~((unsigned long)0xf <<
6f4edd69 974 UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT);
c4c4688f 975 mmr_image |= (UV_INTD_SOFT_ACK_TIMEOUT_PERIOD <<
6f4edd69 976 UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT);
c4c4688f
CW
977 uv_write_global_mmr64
978 (pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
979 /*
2a919596 980 * UV1:
c4c4688f
CW
981 * Subsequent reversals of the timebase bit (3) cause an
982 * immediate timeout of one or all INTD resources as
983 * indicated in bits 2:0 (7 causes all of them to timeout).
984 */
985 mmr_image |= ((unsigned long)1 <<
6f4edd69 986 UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT);
2a919596
JS
987 if (is_uv2_hub()) {
988 mmr_image |= ((unsigned long)1 << UV2_LEG_SHFT);
989 mmr_image |= ((unsigned long)1 << UV2_EXT_SHFT);
990 }
c4c4688f
CW
991 uv_write_global_mmr64
992 (pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
1812924b 993 }
1812924b
CW
994}
995
b194b120 996static void *uv_ptc_seq_start(struct seq_file *file, loff_t *offset)
1812924b
CW
997{
998 if (*offset < num_possible_cpus())
999 return offset;
1000 return NULL;
1001}
1002
b194b120 1003static void *uv_ptc_seq_next(struct seq_file *file, void *data, loff_t *offset)
1812924b
CW
1004{
1005 (*offset)++;
1006 if (*offset < num_possible_cpus())
1007 return offset;
1008 return NULL;
1009}
1010
b194b120 1011static void uv_ptc_seq_stop(struct seq_file *file, void *data)
1812924b
CW
1012{
1013}
1014
b8f7fb13 1015static inline unsigned long long
12a6611f 1016microsec_2_cycles(unsigned long microsec)
b8f7fb13
CW
1017{
1018 unsigned long ns;
1019 unsigned long long cyc;
1020
12a6611f 1021 ns = microsec * 1000;
b8f7fb13
CW
1022 cyc = (ns << CYC2NS_SCALE_FACTOR)/(per_cpu(cyc2ns, smp_processor_id()));
1023 return cyc;
1024}
1025
1812924b 1026/*
b8f7fb13
CW
1027 * Display the statistics thru /proc.
1028 * 'data' points to the cpu number
1812924b 1029 */
b194b120 1030static int uv_ptc_seq_show(struct seq_file *file, void *data)
1812924b
CW
1031{
1032 struct ptc_stats *stat;
1033 int cpu;
1034
1035 cpu = *(loff_t *)data;
1036
1037 if (!cpu) {
1038 seq_printf(file,
450a007e
CW
1039 "# cpu sent stime self locals remotes ncpus localhub ");
1040 seq_printf(file,
1041 "remotehub numuvhubs numuvhubs16 numuvhubs8 ");
1812924b 1042 seq_printf(file,
450a007e 1043 "numuvhubs4 numuvhubs2 numuvhubs1 dto ");
b8f7fb13
CW
1044 seq_printf(file,
1045 "retries rok resetp resett giveup sto bz throt ");
1046 seq_printf(file,
1047 "sw_ack recv rtime all ");
1048 seq_printf(file,
50fb55ac
CW
1049 "one mult none retry canc nocan reset rcan ");
1050 seq_printf(file,
1051 "disable enable\n");
1812924b
CW
1052 }
1053 if (cpu < num_possible_cpus() && cpu_online(cpu)) {
1054 stat = &per_cpu(ptcstats, cpu);
b8f7fb13
CW
1055 /* source side statistics */
1056 seq_printf(file,
1057 "cpu %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ",
1058 cpu, stat->s_requestor, cycles_2_us(stat->s_time),
450a007e
CW
1059 stat->s_ntargself, stat->s_ntarglocals,
1060 stat->s_ntargremotes, stat->s_ntargcpu,
1061 stat->s_ntarglocaluvhub, stat->s_ntargremoteuvhub,
1062 stat->s_ntarguvhub, stat->s_ntarguvhub16);
1063 seq_printf(file, "%ld %ld %ld %ld %ld ",
b8f7fb13
CW
1064 stat->s_ntarguvhub8, stat->s_ntarguvhub4,
1065 stat->s_ntarguvhub2, stat->s_ntarguvhub1,
450a007e 1066 stat->s_dtimeout);
b8f7fb13
CW
1067 seq_printf(file, "%ld %ld %ld %ld %ld %ld %ld %ld ",
1068 stat->s_retry_messages, stat->s_retriesok,
1069 stat->s_resets_plug, stat->s_resets_timeout,
1070 stat->s_giveup, stat->s_stimeout,
1071 stat->s_busy, stat->s_throttles);
e8e5e8a8 1072
b8f7fb13
CW
1073 /* destination side statistics */
1074 seq_printf(file,
50fb55ac 1075 "%lx %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ",
9674f35b 1076 uv_read_global_mmr64(uv_cpu_to_pnode(cpu),
1812924b 1077 UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE),
b8f7fb13
CW
1078 stat->d_requestee, cycles_2_us(stat->d_time),
1079 stat->d_alltlb, stat->d_onetlb, stat->d_multmsg,
1080 stat->d_nomsg, stat->d_retries, stat->d_canceled,
1081 stat->d_nocanceled, stat->d_resets,
1082 stat->d_rcanceled);
50fb55ac
CW
1083 seq_printf(file, "%ld %ld\n",
1084 stat->s_bau_disabled, stat->s_bau_reenabled);
1812924b
CW
1085 }
1086
1087 return 0;
1088}
1089
e8e5e8a8
CW
1090/*
1091 * Display the tunables thru debugfs
1092 */
1093static ssize_t tunables_read(struct file *file, char __user *userbuf,
1094 size_t count, loff_t *ppos)
1095{
b365a85c 1096 char *buf;
e8e5e8a8
CW
1097 int ret;
1098
b365a85c 1099 buf = kasprintf(GFP_KERNEL, "%s %s %s\n%d %d %d %d %d %d %d %d %d\n",
e8e5e8a8
CW
1100 "max_bau_concurrent plugged_delay plugsb4reset",
1101 "timeoutsb4reset ipi_reset_limit complete_threshold",
1102 "congested_response_us congested_reps congested_period",
1103 max_bau_concurrent, plugged_delay, plugsb4reset,
1104 timeoutsb4reset, ipi_reset_limit, complete_threshold,
1105 congested_response_us, congested_reps, congested_period);
1106
b365a85c
DC
1107 if (!buf)
1108 return -ENOMEM;
1109
1110 ret = simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf));
1111 kfree(buf);
1112 return ret;
e8e5e8a8
CW
1113}
1114
1812924b 1115/*
b8f7fb13 1116 * -1: resetf the statistics
1812924b 1117 * 0: display meaning of the statistics
1812924b 1118 */
b194b120 1119static ssize_t uv_ptc_proc_write(struct file *file, const char __user *user,
b4c286e6 1120 size_t count, loff_t *data)
1812924b 1121{
b8f7fb13
CW
1122 int cpu;
1123 long input_arg;
1812924b 1124 char optstr[64];
b8f7fb13 1125 struct ptc_stats *stat;
1812924b 1126
e7eb8726 1127 if (count == 0 || count > sizeof(optstr))
cef53278 1128 return -EINVAL;
1812924b
CW
1129 if (copy_from_user(optstr, user, count))
1130 return -EFAULT;
1131 optstr[count - 1] = '\0';
b8f7fb13 1132 if (strict_strtol(optstr, 10, &input_arg) < 0) {
1812924b
CW
1133 printk(KERN_DEBUG "%s is invalid\n", optstr);
1134 return -EINVAL;
1135 }
1136
b8f7fb13 1137 if (input_arg == 0) {
1812924b 1138 printk(KERN_DEBUG "# cpu: cpu number\n");
b8f7fb13
CW
1139 printk(KERN_DEBUG "Sender statistics:\n");
1140 printk(KERN_DEBUG
1141 "sent: number of shootdown messages sent\n");
1142 printk(KERN_DEBUG
1143 "stime: time spent sending messages\n");
1144 printk(KERN_DEBUG
1145 "numuvhubs: number of hubs targeted with shootdown\n");
1146 printk(KERN_DEBUG
1147 "numuvhubs16: number times 16 or more hubs targeted\n");
1148 printk(KERN_DEBUG
1149 "numuvhubs8: number times 8 or more hubs targeted\n");
1150 printk(KERN_DEBUG
1151 "numuvhubs4: number times 4 or more hubs targeted\n");
1152 printk(KERN_DEBUG
1153 "numuvhubs2: number times 2 or more hubs targeted\n");
1154 printk(KERN_DEBUG
1155 "numuvhubs1: number times 1 hub targeted\n");
1156 printk(KERN_DEBUG
1157 "numcpus: number of cpus targeted with shootdown\n");
1158 printk(KERN_DEBUG
1159 "dto: number of destination timeouts\n");
1160 printk(KERN_DEBUG
1161 "retries: destination timeout retries sent\n");
1162 printk(KERN_DEBUG
1163 "rok: : destination timeouts successfully retried\n");
1164 printk(KERN_DEBUG
1165 "resetp: ipi-style resource resets for plugs\n");
1166 printk(KERN_DEBUG
1167 "resett: ipi-style resource resets for timeouts\n");
1168 printk(KERN_DEBUG
1169 "giveup: fall-backs to ipi-style shootdowns\n");
1170 printk(KERN_DEBUG
1171 "sto: number of source timeouts\n");
1172 printk(KERN_DEBUG
1173 "bz: number of stay-busy's\n");
1174 printk(KERN_DEBUG
1175 "throt: number times spun in throttle\n");
1176 printk(KERN_DEBUG "Destination side statistics:\n");
1812924b 1177 printk(KERN_DEBUG
b8f7fb13 1178 "sw_ack: image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE\n");
1812924b 1179 printk(KERN_DEBUG
b8f7fb13 1180 "recv: shootdown messages received\n");
1812924b 1181 printk(KERN_DEBUG
b8f7fb13 1182 "rtime: time spent processing messages\n");
1812924b 1183 printk(KERN_DEBUG
b8f7fb13 1184 "all: shootdown all-tlb messages\n");
1812924b 1185 printk(KERN_DEBUG
b8f7fb13 1186 "one: shootdown one-tlb messages\n");
1812924b 1187 printk(KERN_DEBUG
b8f7fb13 1188 "mult: interrupts that found multiple messages\n");
1812924b 1189 printk(KERN_DEBUG
b8f7fb13 1190 "none: interrupts that found no messages\n");
1812924b 1191 printk(KERN_DEBUG
b8f7fb13 1192 "retry: number of retry messages processed\n");
1812924b 1193 printk(KERN_DEBUG
b8f7fb13 1194 "canc: number messages canceled by retries\n");
1812924b 1195 printk(KERN_DEBUG
b8f7fb13 1196 "nocan: number retries that found nothing to cancel\n");
1812924b 1197 printk(KERN_DEBUG
b8f7fb13
CW
1198 "reset: number of ipi-style reset requests processed\n");
1199 printk(KERN_DEBUG
1200 "rcan: number messages canceled by reset requests\n");
50fb55ac
CW
1201 printk(KERN_DEBUG
1202 "disable: number times use of the BAU was disabled\n");
1203 printk(KERN_DEBUG
1204 "enable: number times use of the BAU was re-enabled\n");
b8f7fb13
CW
1205 } else if (input_arg == -1) {
1206 for_each_present_cpu(cpu) {
1207 stat = &per_cpu(ptcstats, cpu);
1208 memset(stat, 0, sizeof(struct ptc_stats));
1209 }
e8e5e8a8
CW
1210 }
1211
1212 return count;
1213}
1214
1215static int local_atoi(const char *name)
1216{
1217 int val = 0;
1218
1219 for (;; name++) {
1220 switch (*name) {
1221 case '0' ... '9':
1222 val = 10*val+(*name-'0');
1223 break;
1224 default:
1225 return val;
b8f7fb13 1226 }
1812924b 1227 }
e8e5e8a8
CW
1228}
1229
1230/*
1231 * set the tunables
1232 * 0 values reset them to defaults
1233 */
1234static ssize_t tunables_write(struct file *file, const char __user *user,
1235 size_t count, loff_t *data)
1236{
1237 int cpu;
1238 int cnt = 0;
1239 int val;
1240 char *p;
1241 char *q;
1242 char instr[64];
1243 struct bau_control *bcp;
1812924b 1244
e8e5e8a8
CW
1245 if (count == 0 || count > sizeof(instr)-1)
1246 return -EINVAL;
1247 if (copy_from_user(instr, user, count))
1248 return -EFAULT;
1249
1250 instr[count] = '\0';
1251 /* count the fields */
1252 p = instr + strspn(instr, WHITESPACE);
1253 q = p;
1254 for (; *p; p = q + strspn(q, WHITESPACE)) {
1255 q = p + strcspn(p, WHITESPACE);
1256 cnt++;
1257 if (q == p)
1258 break;
1259 }
1260 if (cnt != 9) {
1261 printk(KERN_INFO "bau tunable error: should be 9 numbers\n");
1262 return -EINVAL;
1263 }
1264
1265 p = instr + strspn(instr, WHITESPACE);
1266 q = p;
1267 for (cnt = 0; *p; p = q + strspn(q, WHITESPACE), cnt++) {
1268 q = p + strcspn(p, WHITESPACE);
1269 val = local_atoi(p);
1270 switch (cnt) {
1271 case 0:
1272 if (val == 0) {
1273 max_bau_concurrent = MAX_BAU_CONCURRENT;
1274 max_bau_concurrent_constant =
1275 MAX_BAU_CONCURRENT;
1276 continue;
1277 }
1278 bcp = &per_cpu(bau_control, smp_processor_id());
1279 if (val < 1 || val > bcp->cpus_in_uvhub) {
1280 printk(KERN_DEBUG
1281 "Error: BAU max concurrent %d is invalid\n",
1282 val);
1283 return -EINVAL;
1284 }
1285 max_bau_concurrent = val;
1286 max_bau_concurrent_constant = val;
1287 continue;
1288 case 1:
1289 if (val == 0)
1290 plugged_delay = PLUGGED_DELAY;
1291 else
1292 plugged_delay = val;
1293 continue;
1294 case 2:
1295 if (val == 0)
1296 plugsb4reset = PLUGSB4RESET;
1297 else
1298 plugsb4reset = val;
1299 continue;
1300 case 3:
1301 if (val == 0)
1302 timeoutsb4reset = TIMEOUTSB4RESET;
1303 else
1304 timeoutsb4reset = val;
1305 continue;
1306 case 4:
1307 if (val == 0)
1308 ipi_reset_limit = IPI_RESET_LIMIT;
1309 else
1310 ipi_reset_limit = val;
1311 continue;
1312 case 5:
1313 if (val == 0)
1314 complete_threshold = COMPLETE_THRESHOLD;
1315 else
1316 complete_threshold = val;
1317 continue;
1318 case 6:
1319 if (val == 0)
1320 congested_response_us = CONGESTED_RESPONSE_US;
1321 else
1322 congested_response_us = val;
1323 continue;
1324 case 7:
1325 if (val == 0)
1326 congested_reps = CONGESTED_REPS;
1327 else
1328 congested_reps = val;
1329 continue;
1330 case 8:
1331 if (val == 0)
1332 congested_period = CONGESTED_PERIOD;
1333 else
1334 congested_period = val;
1335 continue;
1336 }
1337 if (q == p)
1338 break;
1339 }
1340 for_each_present_cpu(cpu) {
1341 bcp = &per_cpu(bau_control, cpu);
1342 bcp->max_bau_concurrent = max_bau_concurrent;
1343 bcp->max_bau_concurrent_constant = max_bau_concurrent;
1344 bcp->plugged_delay = plugged_delay;
1345 bcp->plugsb4reset = plugsb4reset;
1346 bcp->timeoutsb4reset = timeoutsb4reset;
1347 bcp->ipi_reset_limit = ipi_reset_limit;
1348 bcp->complete_threshold = complete_threshold;
1349 bcp->congested_response_us = congested_response_us;
1350 bcp->congested_reps = congested_reps;
1351 bcp->congested_period = congested_period;
1352 }
1812924b
CW
1353 return count;
1354}
1355
1356static const struct seq_operations uv_ptc_seq_ops = {
dc163a41
IM
1357 .start = uv_ptc_seq_start,
1358 .next = uv_ptc_seq_next,
1359 .stop = uv_ptc_seq_stop,
1360 .show = uv_ptc_seq_show
1812924b
CW
1361};
1362
b194b120 1363static int uv_ptc_proc_open(struct inode *inode, struct file *file)
1812924b
CW
1364{
1365 return seq_open(file, &uv_ptc_seq_ops);
1366}
1367
e8e5e8a8
CW
1368static int tunables_open(struct inode *inode, struct file *file)
1369{
1370 return 0;
1371}
1372
1812924b 1373static const struct file_operations proc_uv_ptc_operations = {
b194b120
CW
1374 .open = uv_ptc_proc_open,
1375 .read = seq_read,
1376 .write = uv_ptc_proc_write,
1377 .llseek = seq_lseek,
1378 .release = seq_release,
1812924b
CW
1379};
1380
e8e5e8a8
CW
1381static const struct file_operations tunables_fops = {
1382 .open = tunables_open,
1383 .read = tunables_read,
1384 .write = tunables_write,
6038f373 1385 .llseek = default_llseek,
e8e5e8a8
CW
1386};
1387
b194b120 1388static int __init uv_ptc_init(void)
1812924b 1389{
b194b120 1390 struct proc_dir_entry *proc_uv_ptc;
1812924b
CW
1391
1392 if (!is_uv_system())
1393 return 0;
1394
10f02d11
AD
1395 proc_uv_ptc = proc_create(UV_PTC_BASENAME, 0444, NULL,
1396 &proc_uv_ptc_operations);
1812924b
CW
1397 if (!proc_uv_ptc) {
1398 printk(KERN_ERR "unable to create %s proc entry\n",
1399 UV_PTC_BASENAME);
1400 return -EINVAL;
1401 }
e8e5e8a8
CW
1402
1403 tunables_dir = debugfs_create_dir(UV_BAU_TUNABLES_DIR, NULL);
1404 if (!tunables_dir) {
1405 printk(KERN_ERR "unable to create debugfs directory %s\n",
1406 UV_BAU_TUNABLES_DIR);
1407 return -EINVAL;
1408 }
1409 tunables_file = debugfs_create_file(UV_BAU_TUNABLES_FILE, 0600,
1410 tunables_dir, NULL, &tunables_fops);
1411 if (!tunables_file) {
1412 printk(KERN_ERR "unable to create debugfs file %s\n",
1413 UV_BAU_TUNABLES_FILE);
1414 return -EINVAL;
1415 }
1812924b
CW
1416 return 0;
1417}
1418
1812924b 1419/*
77ed23f8 1420 * Initialize the sending side's sending buffers.
1812924b 1421 */
b8f7fb13 1422static void
77ed23f8 1423uv_activation_descriptor_init(int node, int pnode, int base_pnode)
1812924b
CW
1424{
1425 int i;
b8f7fb13 1426 int cpu;
1812924b 1427 unsigned long pa;
1812924b 1428 unsigned long m;
b194b120 1429 unsigned long n;
b8f7fb13
CW
1430 struct bau_desc *bau_desc;
1431 struct bau_desc *bd2;
1432 struct bau_control *bcp;
b194b120 1433
0e2595cd
CW
1434 /*
1435 * each bau_desc is 64 bytes; there are 8 (UV_ITEMS_PER_DESCRIPTOR)
cfa60917 1436 * per cpu; and one per cpu on the uvhub (UV_ADP_SIZE)
0e2595cd 1437 */
8e5e9521
JJ
1438 bau_desc = kmalloc_node(sizeof(struct bau_desc) * UV_ADP_SIZE
1439 * UV_ITEMS_PER_DESCRIPTOR, GFP_KERNEL, node);
b8f7fb13 1440 BUG_ON(!bau_desc);
b4c286e6 1441
b8f7fb13
CW
1442 pa = uv_gpa(bau_desc); /* need the real nasid*/
1443 n = pa >> uv_nshift;
b194b120 1444 m = pa & uv_mmask;
b4c286e6 1445
77ed23f8 1446 /* the 14-bit pnode */
9c26f52b
CW
1447 uv_write_global_mmr64(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE,
1448 (n << UV_DESC_BASE_PNODE_SHIFT | m));
0e2595cd 1449 /*
77ed23f8 1450 * Initializing all 8 (UV_ITEMS_PER_DESCRIPTOR) descriptors for each
0e2595cd 1451 * cpu even though we only use the first one; one descriptor can
b8f7fb13 1452 * describe a broadcast to 256 uv hubs.
0e2595cd 1453 */
b8f7fb13
CW
1454 for (i = 0, bd2 = bau_desc; i < (UV_ADP_SIZE*UV_ITEMS_PER_DESCRIPTOR);
1455 i++, bd2++) {
1456 memset(bd2, 0, sizeof(struct bau_desc));
1457 bd2->header.sw_ack_flag = 1;
94ca8e48 1458 /*
77ed23f8
CW
1459 * The base_dest_nasid set in the message header is the nasid
1460 * of the first uvhub in the partition. The bit map will
1461 * indicate destination pnode numbers relative to that base.
1462 * They may not be consecutive if nasid striding is being used.
94ca8e48 1463 */
77ed23f8
CW
1464 bd2->header.base_dest_nasid = UV_PNODE_TO_NASID(base_pnode);
1465 bd2->header.dest_subnodeid = UV_LB_SUBNODEID;
b8f7fb13
CW
1466 bd2->header.command = UV_NET_ENDPOINT_INTD;
1467 bd2->header.int_both = 1;
b194b120
CW
1468 /*
1469 * all others need to be set to zero:
1470 * fairness chaining multilevel count replied_to
1471 */
1472 }
b8f7fb13
CW
1473 for_each_present_cpu(cpu) {
1474 if (pnode != uv_blade_to_pnode(uv_cpu_to_blade_id(cpu)))
1475 continue;
1476 bcp = &per_cpu(bau_control, cpu);
1477 bcp->descriptor_base = bau_desc;
1478 }
b194b120
CW
1479}
1480
1481/*
1482 * initialize the destination side's receiving buffers
b8f7fb13
CW
1483 * entered for each uvhub in the partition
1484 * - node is first node (kernel memory notion) on the uvhub
1485 * - pnode is the uvhub's physical identifier
b194b120 1486 */
b8f7fb13
CW
1487static void
1488uv_payload_queue_init(int node, int pnode)
b194b120 1489{
4ea3c51d 1490 int pn;
b8f7fb13 1491 int cpu;
b4c286e6 1492 char *cp;
b8f7fb13
CW
1493 unsigned long pa;
1494 struct bau_payload_queue_entry *pqp;
1495 struct bau_payload_queue_entry *pqp_malloc;
1496 struct bau_control *bcp;
1812924b 1497
8e5e9521
JJ
1498 pqp = kmalloc_node((DEST_Q_SIZE + 1)
1499 * sizeof(struct bau_payload_queue_entry),
1500 GFP_KERNEL, node);
dc163a41 1501 BUG_ON(!pqp);
b8f7fb13 1502 pqp_malloc = pqp;
b4c286e6 1503
b194b120
CW
1504 cp = (char *)pqp + 31;
1505 pqp = (struct bau_payload_queue_entry *)(((unsigned long)cp >> 5) << 5);
b8f7fb13
CW
1506
1507 for_each_present_cpu(cpu) {
1508 if (pnode != uv_cpu_to_pnode(cpu))
1509 continue;
1510 /* for every cpu on this pnode: */
1511 bcp = &per_cpu(bau_control, cpu);
1512 bcp->va_queue_first = pqp;
1513 bcp->bau_msg_head = pqp;
1514 bcp->va_queue_last = pqp + (DEST_Q_SIZE - 1);
1515 }
4ea3c51d
CW
1516 /*
1517 * need the pnode of where the memory was really allocated
1518 */
1519 pa = uv_gpa(pqp);
b8f7fb13 1520 pn = pa >> uv_nshift;
b194b120
CW
1521 uv_write_global_mmr64(pnode,
1522 UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST,
4ea3c51d 1523 ((unsigned long)pn << UV_PAYLOADQ_PNODE_SHIFT) |
b194b120
CW
1524 uv_physnodeaddr(pqp));
1525 uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL,
1526 uv_physnodeaddr(pqp));
b194b120
CW
1527 uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST,
1528 (unsigned long)
b8f7fb13
CW
1529 uv_physnodeaddr(pqp + (DEST_Q_SIZE - 1)));
1530 /* in effect, all msg_type's are set to MSG_NOOP */
dc163a41 1531 memset(pqp, 0, sizeof(struct bau_payload_queue_entry) * DEST_Q_SIZE);
b194b120 1532}
1812924b 1533
b194b120 1534/*
b8f7fb13 1535 * Initialization of each UV hub's structures
b194b120 1536 */
77ed23f8 1537static void __init uv_init_uvhub(int uvhub, int vector, int base_pnode)
b194b120 1538{
9674f35b 1539 int node;
b194b120 1540 int pnode;
b194b120 1541 unsigned long apicid;
b8f7fb13
CW
1542
1543 node = uvhub_to_first_node(uvhub);
1544 pnode = uv_blade_to_pnode(uvhub);
77ed23f8 1545 uv_activation_descriptor_init(node, pnode, base_pnode);
b8f7fb13 1546 uv_payload_queue_init(node, pnode);
b194b120 1547 /*
77ed23f8
CW
1548 * The below initialization can't be in firmware because the
1549 * messaging IRQ will be determined by the OS.
b194b120 1550 */
8191c9f6 1551 apicid = uvhub_to_first_apicid(uvhub) | uv_apicid_hibits;
e38e2af1 1552 uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG,
b8f7fb13
CW
1553 ((apicid << 32) | vector));
1554}
1555
12a6611f
CW
1556/*
1557 * We will set BAU_MISC_CONTROL with a timeout period.
1558 * But the BIOS has set UVH_AGING_PRESCALE_SEL and UVH_TRANSACTION_TIMEOUT.
1559 * So the destination timeout period has be be calculated from them.
1560 */
1561static int
1562calculate_destination_timeout(void)
1563{
1564 unsigned long mmr_image;
1565 int mult1;
1566 int mult2;
1567 int index;
1568 int base;
1569 int ret;
1570 unsigned long ts_ns;
1571
2a919596
JS
1572 if (is_uv1_hub()) {
1573 mult1 = UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD &
1574 BAU_MISC_CONTROL_MULT_MASK;
1575 mmr_image = uv_read_local_mmr(UVH_AGING_PRESCALE_SEL);
1576 index = (mmr_image >> BAU_URGENCY_7_SHIFT) & BAU_URGENCY_7_MASK;
1577 mmr_image = uv_read_local_mmr(UVH_TRANSACTION_TIMEOUT);
1578 mult2 = (mmr_image >> BAU_TRANS_SHIFT) & BAU_TRANS_MASK;
1579 base = timeout_base_ns[index];
1580 ts_ns = base * mult1 * mult2;
1581 ret = ts_ns / 1000;
1582 } else {
1583 /* 4 bits 0/1 for 10/80us, 3 bits of multiplier */
1584 mmr_image = uv_read_local_mmr(UVH_AGING_PRESCALE_SEL);
1585 mmr_image = (mmr_image & UV_SA_MASK) >> UV_SA_SHFT;
1586 if (mmr_image & ((unsigned long)1 << UV2_ACK_UNITS_SHFT))
1587 mult1 = 80;
1588 else
1589 mult1 = 10;
1590 base = mmr_image & UV2_ACK_MASK;
1591 ret = mult1 * base;
1592 }
12a6611f
CW
1593 return ret;
1594}
1595
b8f7fb13
CW
1596/*
1597 * initialize the bau_control structure for each cpu
1598 */
77ed23f8 1599static int __init uv_init_per_cpu(int nuvhubs, int base_part_pnode)
b8f7fb13 1600{
a8328ee5 1601 int i;
b8f7fb13 1602 int cpu;
77ed23f8 1603 int tcpu;
b8f7fb13
CW
1604 int pnode;
1605 int uvhub;
c4026cfd 1606 int have_hmaster;
b8f7fb13 1607 short socket = 0;
a8328ee5 1608 unsigned short socket_mask;
c4026cfd 1609 unsigned char *uvhub_mask;
b8f7fb13
CW
1610 struct bau_control *bcp;
1611 struct uvhub_desc *bdp;
1612 struct socket_desc *sdp;
1613 struct bau_control *hmaster = NULL;
1614 struct bau_control *smaster = NULL;
1615 struct socket_desc {
1616 short num_cpus;
cfa60917 1617 short cpu_number[MAX_CPUS_PER_SOCKET];
b8f7fb13
CW
1618 };
1619 struct uvhub_desc {
a8328ee5 1620 unsigned short socket_mask;
b8f7fb13
CW
1621 short num_cpus;
1622 short uvhub;
1623 short pnode;
1624 struct socket_desc socket[2];
1625 };
1626 struct uvhub_desc *uvhub_descs;
1627
12a6611f
CW
1628 timeout_us = calculate_destination_timeout();
1629
8e5e9521 1630 uvhub_descs = kmalloc(nuvhubs * sizeof(struct uvhub_desc), GFP_KERNEL);
b8f7fb13 1631 memset(uvhub_descs, 0, nuvhubs * sizeof(struct uvhub_desc));
c4026cfd 1632 uvhub_mask = kzalloc((nuvhubs+7)/8, GFP_KERNEL);
b8f7fb13
CW
1633 for_each_present_cpu(cpu) {
1634 bcp = &per_cpu(bau_control, cpu);
1635 memset(bcp, 0, sizeof(struct bau_control));
b8f7fb13 1636 pnode = uv_cpu_hub_info(cpu)->pnode;
77ed23f8
CW
1637 if ((pnode - base_part_pnode) >= UV_DISTRIBUTION_SIZE) {
1638 printk(KERN_EMERG
1639 "cpu %d pnode %d-%d beyond %d; BAU disabled\n",
1640 cpu, pnode, base_part_pnode,
1641 UV_DISTRIBUTION_SIZE);
1642 return 1;
1643 }
1644 bcp->osnode = cpu_to_node(cpu);
1645 bcp->partition_base_pnode = uv_partition_base_pnode;
b8f7fb13 1646 uvhub = uv_cpu_hub_info(cpu)->numa_blade_id;
c4026cfd 1647 *(uvhub_mask + (uvhub/8)) |= (1 << (uvhub%8));
b8f7fb13
CW
1648 bdp = &uvhub_descs[uvhub];
1649 bdp->num_cpus++;
1650 bdp->uvhub = uvhub;
1651 bdp->pnode = pnode;
a8328ee5
CW
1652 /* kludge: 'assuming' one node per socket, and assuming that
1653 disabling a socket just leaves a gap in node numbers */
77ed23f8 1654 socket = bcp->osnode & 1;
a8328ee5 1655 bdp->socket_mask |= (1 << socket);
b8f7fb13
CW
1656 sdp = &bdp->socket[socket];
1657 sdp->cpu_number[sdp->num_cpus] = cpu;
1658 sdp->num_cpus++;
cfa60917
CW
1659 if (sdp->num_cpus > MAX_CPUS_PER_SOCKET) {
1660 printk(KERN_EMERG "%d cpus per socket invalid\n", sdp->num_cpus);
1661 return 1;
1662 }
b8f7fb13 1663 }
c4026cfd
CW
1664 for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
1665 if (!(*(uvhub_mask + (uvhub/8)) & (1 << (uvhub%8))))
1666 continue;
1667 have_hmaster = 0;
b8f7fb13 1668 bdp = &uvhub_descs[uvhub];
a8328ee5
CW
1669 socket_mask = bdp->socket_mask;
1670 socket = 0;
1671 while (socket_mask) {
1672 if (!(socket_mask & 1))
1673 goto nextsocket;
1674 sdp = &bdp->socket[socket];
1675 for (i = 0; i < sdp->num_cpus; i++) {
1676 cpu = sdp->cpu_number[i];
b8f7fb13
CW
1677 bcp = &per_cpu(bau_control, cpu);
1678 bcp->cpu = cpu;
a8328ee5 1679 if (i == 0) {
b8f7fb13 1680 smaster = bcp;
c4026cfd
CW
1681 if (!have_hmaster) {
1682 have_hmaster++;
b8f7fb13 1683 hmaster = bcp;
c4026cfd 1684 }
b8f7fb13
CW
1685 }
1686 bcp->cpus_in_uvhub = bdp->num_cpus;
1687 bcp->cpus_in_socket = sdp->num_cpus;
1688 bcp->socket_master = smaster;
a8328ee5 1689 bcp->uvhub = bdp->uvhub;
b8f7fb13 1690 bcp->uvhub_master = hmaster;
a8328ee5
CW
1691 bcp->uvhub_cpu = uv_cpu_hub_info(cpu)->
1692 blade_processor_id;
cfa60917
CW
1693 if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) {
1694 printk(KERN_EMERG
1695 "%d cpus per uvhub invalid\n",
1696 bcp->uvhub_cpu);
1697 return 1;
1698 }
b8f7fb13 1699 }
a8328ee5 1700nextsocket:
b8f7fb13 1701 socket++;
a8328ee5 1702 socket_mask = (socket_mask >> 1);
77ed23f8
CW
1703 /* each socket gets a local array of pnodes/hubs */
1704 bcp = smaster;
1705 bcp->target_hub_and_pnode = kmalloc_node(
1706 sizeof(struct hub_and_pnode) *
1707 num_possible_cpus(), GFP_KERNEL, bcp->osnode);
1708 memset(bcp->target_hub_and_pnode, 0,
1709 sizeof(struct hub_and_pnode) *
1710 num_possible_cpus());
1711 for_each_present_cpu(tcpu) {
1712 bcp->target_hub_and_pnode[tcpu].pnode =
1713 uv_cpu_hub_info(tcpu)->pnode;
1714 bcp->target_hub_and_pnode[tcpu].uvhub =
1715 uv_cpu_hub_info(tcpu)->numa_blade_id;
1716 }
b8f7fb13
CW
1717 }
1718 }
1719 kfree(uvhub_descs);
c4026cfd 1720 kfree(uvhub_mask);
e8e5e8a8
CW
1721 for_each_present_cpu(cpu) {
1722 bcp = &per_cpu(bau_control, cpu);
50fb55ac 1723 bcp->baudisabled = 0;
712157aa 1724 bcp->statp = &per_cpu(ptcstats, cpu);
e8e5e8a8
CW
1725 /* time interval to catch a hardware stay-busy bug */
1726 bcp->timeout_interval = microsec_2_cycles(2*timeout_us);
1727 bcp->max_bau_concurrent = max_bau_concurrent;
1728 bcp->max_bau_concurrent_constant = max_bau_concurrent;
1729 bcp->plugged_delay = plugged_delay;
1730 bcp->plugsb4reset = plugsb4reset;
1731 bcp->timeoutsb4reset = timeoutsb4reset;
1732 bcp->ipi_reset_limit = ipi_reset_limit;
1733 bcp->complete_threshold = complete_threshold;
1734 bcp->congested_response_us = congested_response_us;
1735 bcp->congested_reps = congested_reps;
1736 bcp->congested_period = congested_period;
1737 }
cfa60917 1738 return 0;
b194b120
CW
1739}
1740
1741/*
1742 * Initialization of BAU-related structures
1743 */
1744static int __init uv_bau_init(void)
1745{
b8f7fb13
CW
1746 int uvhub;
1747 int pnode;
1748 int nuvhubs;
2c74d666 1749 int cur_cpu;
b8f7fb13
CW
1750 int vector;
1751 unsigned long mmr;
b194b120
CW
1752
1753 if (!is_uv_system())
1754 return 0;
1812924b 1755
b8f7fb13
CW
1756 if (nobau)
1757 return 0;
1758
76ba0ecd 1759 for_each_possible_cpu(cur_cpu)
eaa95840 1760 zalloc_cpumask_var_node(&per_cpu(uv_flush_tlb_mask, cur_cpu),
76ba0ecd
RR
1761 GFP_KERNEL, cpu_to_node(cur_cpu));
1762
b8f7fb13 1763 uv_nshift = uv_hub_info->m_val;
036ed8ba 1764 uv_mmask = (1UL << uv_hub_info->m_val) - 1;
b8f7fb13 1765 nuvhubs = uv_num_possible_blades();
50fb55ac
CW
1766 spin_lock_init(&disable_lock);
1767 congested_cycles = microsec_2_cycles(congested_response_us);
9674f35b 1768
94ca8e48 1769 uv_partition_base_pnode = 0x7fffffff;
77ed23f8 1770 for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
b8f7fb13
CW
1771 if (uv_blade_nr_possible_cpus(uvhub) &&
1772 (uv_blade_to_pnode(uvhub) < uv_partition_base_pnode))
1773 uv_partition_base_pnode = uv_blade_to_pnode(uvhub);
77ed23f8
CW
1774 }
1775
1776 if (uv_init_per_cpu(nuvhubs, uv_partition_base_pnode)) {
1777 nobau = 1;
1778 return 0;
1779 }
b8f7fb13
CW
1780
1781 vector = UV_BAU_MESSAGE;
1782 for_each_possible_blade(uvhub)
1783 if (uv_blade_nr_possible_cpus(uvhub))
77ed23f8 1784 uv_init_uvhub(uvhub, vector, uv_partition_base_pnode);
b8f7fb13 1785
1812924b 1786 uv_enable_timeouts();
b8f7fb13
CW
1787 alloc_intr_gate(vector, uv_bau_message_intr1);
1788
1789 for_each_possible_blade(uvhub) {
93a7ca0c
CW
1790 if (uv_blade_nr_possible_cpus(uvhub)) {
1791 pnode = uv_blade_to_pnode(uvhub);
1792 /* INIT the bau */
1793 uv_write_global_mmr64(pnode,
1794 UVH_LB_BAU_SB_ACTIVATION_CONTROL,
1795 ((unsigned long)1 << 63));
1796 mmr = 1; /* should be 1 to broadcast to both sockets */
1797 uv_write_global_mmr64(pnode, UVH_BAU_DATA_BROADCAST,
1798 mmr);
1799 }
b8f7fb13 1800 }
b4c286e6 1801
1812924b
CW
1802 return 0;
1803}
b8f7fb13 1804core_initcall(uv_bau_init);
e8e5e8a8 1805fs_initcall(uv_ptc_init);
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