Commit | Line | Data |
---|---|---|
1812924b CW |
1 | /* |
2 | * SGI UltraViolet TLB flush routines. | |
3 | * | |
f073cc8f | 4 | * (c) 2008-2011 Cliff Wickman <cpw@sgi.com>, SGI. |
1812924b CW |
5 | * |
6 | * This code is released under the GNU General Public License version 2 or | |
7 | * later. | |
8 | */ | |
aef8f5b8 | 9 | #include <linux/seq_file.h> |
1812924b | 10 | #include <linux/proc_fs.h> |
e8e5e8a8 | 11 | #include <linux/debugfs.h> |
1812924b | 12 | #include <linux/kernel.h> |
5a0e3ad6 | 13 | #include <linux/slab.h> |
ca444564 | 14 | #include <linux/delay.h> |
1812924b | 15 | |
1812924b | 16 | #include <asm/mmu_context.h> |
bdbcdd48 | 17 | #include <asm/uv/uv.h> |
1812924b | 18 | #include <asm/uv/uv_mmrs.h> |
b4c286e6 | 19 | #include <asm/uv/uv_hub.h> |
1812924b | 20 | #include <asm/uv/uv_bau.h> |
7b6aa335 | 21 | #include <asm/apic.h> |
b4c286e6 | 22 | #include <asm/idle.h> |
b194b120 | 23 | #include <asm/tsc.h> |
99dd8713 | 24 | #include <asm/irq_vectors.h> |
b8f7fb13 | 25 | #include <asm/timer.h> |
1812924b | 26 | |
12a6611f CW |
27 | /* timeouts in nanoseconds (indexed by UVH_AGING_PRESCALE_SEL urgency7 30:28) */ |
28 | static int timeout_base_ns[] = { | |
29 | 20, | |
30 | 160, | |
31 | 1280, | |
32 | 10240, | |
33 | 81920, | |
34 | 655360, | |
35 | 5242880, | |
36 | 167772160 | |
37 | }; | |
f073cc8f | 38 | |
12a6611f | 39 | static int timeout_us; |
e8e5e8a8 | 40 | static int nobau; |
50fb55ac CW |
41 | static int baudisabled; |
42 | static spinlock_t disable_lock; | |
43 | static cycles_t congested_cycles; | |
12a6611f | 44 | |
e8e5e8a8 | 45 | /* tunables: */ |
f073cc8f CW |
46 | static int max_concurr = MAX_BAU_CONCURRENT; |
47 | static int max_concurr_const = MAX_BAU_CONCURRENT; | |
48 | static int plugged_delay = PLUGGED_DELAY; | |
49 | static int plugsb4reset = PLUGSB4RESET; | |
50 | static int timeoutsb4reset = TIMEOUTSB4RESET; | |
51 | static int ipi_reset_limit = IPI_RESET_LIMIT; | |
52 | static int complete_threshold = COMPLETE_THRESHOLD; | |
53 | static int congested_respns_us = CONGESTED_RESPONSE_US; | |
54 | static int congested_reps = CONGESTED_REPS; | |
55 | static int congested_period = CONGESTED_PERIOD; | |
56 | ||
57 | static struct tunables tunables[] = { | |
58 | {&max_concurr, MAX_BAU_CONCURRENT}, /* must be [0] */ | |
59 | {&plugged_delay, PLUGGED_DELAY}, | |
60 | {&plugsb4reset, PLUGSB4RESET}, | |
61 | {&timeoutsb4reset, TIMEOUTSB4RESET}, | |
62 | {&ipi_reset_limit, IPI_RESET_LIMIT}, | |
63 | {&complete_threshold, COMPLETE_THRESHOLD}, | |
64 | {&congested_respns_us, CONGESTED_RESPONSE_US}, | |
65 | {&congested_reps, CONGESTED_REPS}, | |
66 | {&congested_period, CONGESTED_PERIOD} | |
67 | }; | |
68 | ||
e8e5e8a8 CW |
69 | static struct dentry *tunables_dir; |
70 | static struct dentry *tunables_file; | |
b4c286e6 | 71 | |
f073cc8f CW |
72 | /* these correspond to the statistics printed by ptc_seq_show() */ |
73 | static char *stat_description[] = { | |
74 | "sent: number of shootdown messages sent", | |
75 | "stime: time spent sending messages", | |
76 | "numuvhubs: number of hubs targeted with shootdown", | |
77 | "numuvhubs16: number times 16 or more hubs targeted", | |
78 | "numuvhubs8: number times 8 or more hubs targeted", | |
79 | "numuvhubs4: number times 4 or more hubs targeted", | |
80 | "numuvhubs2: number times 2 or more hubs targeted", | |
81 | "numuvhubs1: number times 1 hub targeted", | |
82 | "numcpus: number of cpus targeted with shootdown", | |
83 | "dto: number of destination timeouts", | |
84 | "retries: destination timeout retries sent", | |
85 | "rok: : destination timeouts successfully retried", | |
86 | "resetp: ipi-style resource resets for plugs", | |
87 | "resett: ipi-style resource resets for timeouts", | |
88 | "giveup: fall-backs to ipi-style shootdowns", | |
89 | "sto: number of source timeouts", | |
90 | "bz: number of stay-busy's", | |
91 | "throt: number times spun in throttle", | |
92 | "swack: image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE", | |
93 | "recv: shootdown messages received", | |
94 | "rtime: time spent processing messages", | |
95 | "all: shootdown all-tlb messages", | |
96 | "one: shootdown one-tlb messages", | |
97 | "mult: interrupts that found multiple messages", | |
98 | "none: interrupts that found no messages", | |
99 | "retry: number of retry messages processed", | |
100 | "canc: number messages canceled by retries", | |
101 | "nocan: number retries that found nothing to cancel", | |
102 | "reset: number of ipi-style reset requests processed", | |
103 | "rcan: number messages canceled by reset requests", | |
104 | "disable: number times use of the BAU was disabled", | |
105 | "enable: number times use of the BAU was re-enabled" | |
106 | }; | |
107 | ||
108 | static int __init | |
109 | setup_nobau(char *arg) | |
b8f7fb13 CW |
110 | { |
111 | nobau = 1; | |
112 | return 0; | |
113 | } | |
114 | early_param("nobau", setup_nobau); | |
b4c286e6 | 115 | |
b8f7fb13 | 116 | /* base pnode in this partition */ |
f073cc8f | 117 | static int uv_base_pnode __read_mostly; |
1812924b | 118 | |
dc163a41 IM |
119 | static DEFINE_PER_CPU(struct ptc_stats, ptcstats); |
120 | static DEFINE_PER_CPU(struct bau_control, bau_control); | |
b8f7fb13 CW |
121 | static DEFINE_PER_CPU(cpumask_var_t, uv_flush_tlb_mask); |
122 | ||
9674f35b | 123 | /* |
b8f7fb13 CW |
124 | * Determine the first node on a uvhub. 'Nodes' are used for kernel |
125 | * memory allocation. | |
9674f35b | 126 | */ |
b8f7fb13 | 127 | static int __init uvhub_to_first_node(int uvhub) |
9674f35b CW |
128 | { |
129 | int node, b; | |
130 | ||
131 | for_each_online_node(node) { | |
132 | b = uv_node_to_blade_id(node); | |
b8f7fb13 | 133 | if (uvhub == b) |
9674f35b CW |
134 | return node; |
135 | } | |
b8f7fb13 | 136 | return -1; |
9674f35b CW |
137 | } |
138 | ||
139 | /* | |
b8f7fb13 | 140 | * Determine the apicid of the first cpu on a uvhub. |
9674f35b | 141 | */ |
b8f7fb13 | 142 | static int __init uvhub_to_first_apicid(int uvhub) |
9674f35b CW |
143 | { |
144 | int cpu; | |
145 | ||
146 | for_each_present_cpu(cpu) | |
b8f7fb13 | 147 | if (uvhub == uv_cpu_to_blade_id(cpu)) |
9674f35b CW |
148 | return per_cpu(x86_cpu_to_apicid, cpu); |
149 | return -1; | |
150 | } | |
151 | ||
1812924b CW |
152 | /* |
153 | * Free a software acknowledge hardware resource by clearing its Pending | |
154 | * bit. This will return a reply to the sender. | |
155 | * If the message has timed out, a reply has already been sent by the | |
156 | * hardware but the resource has not been released. In that case our | |
157 | * clear of the Timeout bit (as well) will free the resource. No reply will | |
158 | * be sent (the hardware will only do one reply per message). | |
159 | */ | |
f073cc8f | 160 | static void reply_to_message(struct msg_desc *mdp, struct bau_control *bcp) |
1812924b | 161 | { |
b194b120 | 162 | unsigned long dw; |
f073cc8f | 163 | struct bau_pq_entry *msg; |
1812924b | 164 | |
b8f7fb13 CW |
165 | msg = mdp->msg; |
166 | if (!msg->canceled) { | |
f073cc8f CW |
167 | dw = (msg->swack_vec << UV_SW_ACK_NPENDING) | msg->swack_vec; |
168 | write_mmr_sw_ack(dw); | |
b8f7fb13 | 169 | } |
1812924b | 170 | msg->replied_to = 1; |
f073cc8f | 171 | msg->swack_vec = 0; |
1812924b CW |
172 | } |
173 | ||
174 | /* | |
b8f7fb13 | 175 | * Process the receipt of a RETRY message |
1812924b | 176 | */ |
f073cc8f CW |
177 | static void bau_process_retry_msg(struct msg_desc *mdp, |
178 | struct bau_control *bcp) | |
1812924b | 179 | { |
b8f7fb13 CW |
180 | int i; |
181 | int cancel_count = 0; | |
b8f7fb13 CW |
182 | unsigned long msg_res; |
183 | unsigned long mmr = 0; | |
f073cc8f CW |
184 | struct bau_pq_entry *msg = mdp->msg; |
185 | struct bau_pq_entry *msg2; | |
186 | struct ptc_stats *stat = bcp->statp; | |
1812924b | 187 | |
b8f7fb13 CW |
188 | stat->d_retries++; |
189 | /* | |
190 | * cancel any message from msg+1 to the retry itself | |
191 | */ | |
192 | for (msg2 = msg+1, i = 0; i < DEST_Q_SIZE; msg2++, i++) { | |
f073cc8f CW |
193 | if (msg2 > mdp->queue_last) |
194 | msg2 = mdp->queue_first; | |
b8f7fb13 CW |
195 | if (msg2 == msg) |
196 | break; | |
197 | ||
f073cc8f | 198 | /* same conditions for cancellation as do_reset */ |
b8f7fb13 | 199 | if ((msg2->replied_to == 0) && (msg2->canceled == 0) && |
f073cc8f CW |
200 | (msg2->swack_vec) && ((msg2->swack_vec & |
201 | msg->swack_vec) == 0) && | |
b8f7fb13 CW |
202 | (msg2->sending_cpu == msg->sending_cpu) && |
203 | (msg2->msg_type != MSG_NOOP)) { | |
f073cc8f CW |
204 | mmr = read_mmr_sw_ack(); |
205 | msg_res = msg2->swack_vec; | |
b8f7fb13 CW |
206 | /* |
207 | * This is a message retry; clear the resources held | |
208 | * by the previous message only if they timed out. | |
209 | * If it has not timed out we have an unexpected | |
210 | * situation to report. | |
211 | */ | |
39847e7f | 212 | if (mmr & (msg_res << UV_SW_ACK_NPENDING)) { |
f073cc8f | 213 | unsigned long mr; |
b8f7fb13 CW |
214 | /* |
215 | * is the resource timed out? | |
216 | * make everyone ignore the cancelled message. | |
217 | */ | |
218 | msg2->canceled = 1; | |
219 | stat->d_canceled++; | |
220 | cancel_count++; | |
f073cc8f CW |
221 | mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res; |
222 | write_mmr_sw_ack(mr); | |
39847e7f | 223 | } |
b8f7fb13 CW |
224 | } |
225 | } | |
226 | if (!cancel_count) | |
227 | stat->d_nocanceled++; | |
228 | } | |
1812924b | 229 | |
b8f7fb13 CW |
230 | /* |
231 | * Do all the things a cpu should do for a TLB shootdown message. | |
232 | * Other cpu's may come here at the same time for this message. | |
233 | */ | |
f073cc8f CW |
234 | static void bau_process_message(struct msg_desc *mdp, |
235 | struct bau_control *bcp) | |
b8f7fb13 | 236 | { |
b8f7fb13 | 237 | short socket_ack_count = 0; |
f073cc8f CW |
238 | short *sp; |
239 | struct atomic_short *asp; | |
240 | struct ptc_stats *stat = bcp->statp; | |
241 | struct bau_pq_entry *msg = mdp->msg; | |
b8f7fb13 | 242 | struct bau_control *smaster = bcp->socket_master; |
1812924b | 243 | |
b8f7fb13 CW |
244 | /* |
245 | * This must be a normal message, or retry of a normal message | |
246 | */ | |
1812924b CW |
247 | if (msg->address == TLB_FLUSH_ALL) { |
248 | local_flush_tlb(); | |
b8f7fb13 | 249 | stat->d_alltlb++; |
1812924b CW |
250 | } else { |
251 | __flush_tlb_one(msg->address); | |
b8f7fb13 | 252 | stat->d_onetlb++; |
1812924b | 253 | } |
b8f7fb13 CW |
254 | stat->d_requestee++; |
255 | ||
256 | /* | |
257 | * One cpu on each uvhub has the additional job on a RETRY | |
258 | * of releasing the resource held by the message that is | |
259 | * being retried. That message is identified by sending | |
260 | * cpu number. | |
261 | */ | |
262 | if (msg->msg_type == MSG_RETRY && bcp == bcp->uvhub_master) | |
f073cc8f | 263 | bau_process_retry_msg(mdp, bcp); |
1812924b | 264 | |
b8f7fb13 | 265 | /* |
f073cc8f | 266 | * This is a swack message, so we have to reply to it. |
b8f7fb13 CW |
267 | * Count each responding cpu on the socket. This avoids |
268 | * pinging the count's cache line back and forth between | |
269 | * the sockets. | |
270 | */ | |
f073cc8f CW |
271 | sp = &smaster->socket_acknowledge_count[mdp->msg_slot]; |
272 | asp = (struct atomic_short *)sp; | |
273 | socket_ack_count = atom_asr(1, asp); | |
b8f7fb13 | 274 | if (socket_ack_count == bcp->cpus_in_socket) { |
f073cc8f | 275 | int msg_ack_count; |
b8f7fb13 CW |
276 | /* |
277 | * Both sockets dump their completed count total into | |
278 | * the message's count. | |
279 | */ | |
280 | smaster->socket_acknowledge_count[mdp->msg_slot] = 0; | |
f073cc8f CW |
281 | asp = (struct atomic_short *)&msg->acknowledge_count; |
282 | msg_ack_count = atom_asr(socket_ack_count, asp); | |
b8f7fb13 CW |
283 | |
284 | if (msg_ack_count == bcp->cpus_in_uvhub) { | |
285 | /* | |
286 | * All cpus in uvhub saw it; reply | |
287 | */ | |
f073cc8f | 288 | reply_to_message(mdp, bcp); |
b8f7fb13 CW |
289 | } |
290 | } | |
1812924b | 291 | |
b8f7fb13 | 292 | return; |
1812924b CW |
293 | } |
294 | ||
295 | /* | |
485f07d3 | 296 | * Determine the first cpu on a pnode. |
b8f7fb13 | 297 | */ |
485f07d3 | 298 | static int pnode_to_first_cpu(int pnode, struct bau_control *smaster) |
b8f7fb13 CW |
299 | { |
300 | int cpu; | |
485f07d3 | 301 | struct hub_and_pnode *hpp; |
302 | ||
303 | for_each_present_cpu(cpu) { | |
304 | hpp = &smaster->thp[cpu]; | |
305 | if (pnode == hpp->pnode) | |
b8f7fb13 | 306 | return cpu; |
485f07d3 | 307 | } |
b8f7fb13 CW |
308 | return -1; |
309 | } | |
310 | ||
311 | /* | |
312 | * Last resort when we get a large number of destination timeouts is | |
313 | * to clear resources held by a given cpu. | |
314 | * Do this with IPI so that all messages in the BAU message queue | |
f073cc8f | 315 | * can be identified by their nonzero swack_vec field. |
1812924b | 316 | * |
b8f7fb13 CW |
317 | * This is entered for a single cpu on the uvhub. |
318 | * The sender want's this uvhub to free a specific message's | |
f073cc8f | 319 | * swack resources. |
1812924b | 320 | */ |
f073cc8f | 321 | static void do_reset(void *ptr) |
1812924b | 322 | { |
b4c286e6 | 323 | int i; |
f073cc8f CW |
324 | struct bau_control *bcp = &per_cpu(bau_control, smp_processor_id()); |
325 | struct reset_args *rap = (struct reset_args *)ptr; | |
326 | struct bau_pq_entry *msg; | |
327 | struct ptc_stats *stat = bcp->statp; | |
1812924b | 328 | |
b8f7fb13 | 329 | stat->d_resets++; |
b8f7fb13 CW |
330 | /* |
331 | * We're looking for the given sender, and | |
f073cc8f | 332 | * will free its swack resource. |
b8f7fb13 CW |
333 | * If all cpu's finally responded after the timeout, its |
334 | * message 'replied_to' was set. | |
335 | */ | |
f073cc8f CW |
336 | for (msg = bcp->queue_first, i = 0; i < DEST_Q_SIZE; msg++, i++) { |
337 | unsigned long msg_res; | |
338 | /* do_reset: same conditions for cancellation as | |
339 | bau_process_retry_msg() */ | |
b8f7fb13 CW |
340 | if ((msg->replied_to == 0) && |
341 | (msg->canceled == 0) && | |
342 | (msg->sending_cpu == rap->sender) && | |
f073cc8f | 343 | (msg->swack_vec) && |
b8f7fb13 | 344 | (msg->msg_type != MSG_NOOP)) { |
f073cc8f CW |
345 | unsigned long mmr; |
346 | unsigned long mr; | |
b8f7fb13 CW |
347 | /* |
348 | * make everyone else ignore this message | |
349 | */ | |
350 | msg->canceled = 1; | |
b8f7fb13 CW |
351 | /* |
352 | * only reset the resource if it is still pending | |
353 | */ | |
f073cc8f CW |
354 | mmr = read_mmr_sw_ack(); |
355 | msg_res = msg->swack_vec; | |
356 | mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res; | |
b8f7fb13 CW |
357 | if (mmr & msg_res) { |
358 | stat->d_rcanceled++; | |
f073cc8f | 359 | write_mmr_sw_ack(mr); |
dc163a41 | 360 | } |
dc163a41 IM |
361 | } |
362 | } | |
b8f7fb13 | 363 | return; |
dc163a41 IM |
364 | } |
365 | ||
366 | /* | |
b8f7fb13 CW |
367 | * Use IPI to get all target uvhubs to release resources held by |
368 | * a given sending cpu number. | |
dc163a41 | 369 | */ |
a456eaab | 370 | static void reset_with_ipi(struct pnmask *distribution, struct bau_control *bcp) |
dc163a41 | 371 | { |
485f07d3 | 372 | int pnode; |
373 | int apnode; | |
f073cc8f | 374 | int maskbits; |
485f07d3 | 375 | int sender = bcp->cpu; |
442d3924 | 376 | cpumask_t *mask = bcp->uvhub_master->cpumask; |
485f07d3 | 377 | struct bau_control *smaster = bcp->socket_master; |
b8f7fb13 | 378 | struct reset_args reset_args; |
dc163a41 | 379 | |
b8f7fb13 | 380 | reset_args.sender = sender; |
442d3924 | 381 | cpus_clear(*mask); |
b8f7fb13 | 382 | /* find a single cpu for each uvhub in this distribution mask */ |
a456eaab | 383 | maskbits = sizeof(struct pnmask) * BITSPERBYTE; |
485f07d3 | 384 | /* each bit is a pnode relative to the partition base pnode */ |
385 | for (pnode = 0; pnode < maskbits; pnode++) { | |
f073cc8f | 386 | int cpu; |
485f07d3 | 387 | if (!bau_uvhub_isset(pnode, distribution)) |
b194b120 | 388 | continue; |
485f07d3 | 389 | apnode = pnode + bcp->partition_base_pnode; |
390 | cpu = pnode_to_first_cpu(apnode, smaster); | |
442d3924 | 391 | cpu_set(cpu, *mask); |
1812924b | 392 | } |
f073cc8f CW |
393 | |
394 | /* IPI all cpus; preemption is already disabled */ | |
442d3924 | 395 | smp_call_function_many(mask, do_reset, (void *)&reset_args, 1); |
b8f7fb13 CW |
396 | return; |
397 | } | |
398 | ||
f073cc8f | 399 | static inline unsigned long cycles_2_us(unsigned long long cyc) |
b8f7fb13 CW |
400 | { |
401 | unsigned long long ns; | |
402 | unsigned long us; | |
f073cc8f CW |
403 | int cpu = smp_processor_id(); |
404 | ||
405 | ns = (cyc * per_cpu(cyc2ns, cpu)) >> CYC2NS_SCALE_FACTOR; | |
b8f7fb13 CW |
406 | us = ns / 1000; |
407 | return us; | |
1812924b CW |
408 | } |
409 | ||
b194b120 | 410 | /* |
b8f7fb13 CW |
411 | * wait for all cpus on this hub to finish their sends and go quiet |
412 | * leaves uvhub_quiesce set so that no new broadcasts are started by | |
413 | * bau_flush_send_and_wait() | |
414 | */ | |
f073cc8f | 415 | static inline void quiesce_local_uvhub(struct bau_control *hmaster) |
b8f7fb13 | 416 | { |
f073cc8f | 417 | atom_asr(1, (struct atomic_short *)&hmaster->uvhub_quiesce); |
b8f7fb13 CW |
418 | } |
419 | ||
420 | /* | |
421 | * mark this quiet-requestor as done | |
422 | */ | |
f073cc8f | 423 | static inline void end_uvhub_quiesce(struct bau_control *hmaster) |
b8f7fb13 | 424 | { |
f073cc8f CW |
425 | atom_asr(-1, (struct atomic_short *)&hmaster->uvhub_quiesce); |
426 | } | |
427 | ||
428 | static unsigned long uv1_read_status(unsigned long mmr_offset, int right_shift) | |
429 | { | |
430 | unsigned long descriptor_status; | |
431 | ||
432 | descriptor_status = uv_read_local_mmr(mmr_offset); | |
433 | descriptor_status >>= right_shift; | |
434 | descriptor_status &= UV_ACT_STATUS_MASK; | |
435 | return descriptor_status; | |
b8f7fb13 CW |
436 | } |
437 | ||
438 | /* | |
439 | * Wait for completion of a broadcast software ack message | |
440 | * return COMPLETE, RETRY(PLUGGED or TIMEOUT) or GIVEUP | |
b194b120 | 441 | */ |
2a919596 | 442 | static int uv1_wait_completion(struct bau_desc *bau_desc, |
f073cc8f CW |
443 | unsigned long mmr_offset, int right_shift, |
444 | struct bau_control *bcp, long try) | |
b194b120 | 445 | { |
b194b120 | 446 | unsigned long descriptor_status; |
f073cc8f | 447 | cycles_t ttm; |
712157aa | 448 | struct ptc_stats *stat = bcp->statp; |
b194b120 | 449 | |
f073cc8f | 450 | descriptor_status = uv1_read_status(mmr_offset, right_shift); |
b8f7fb13 | 451 | /* spin on the status MMR, waiting for it to go idle */ |
f073cc8f | 452 | while ((descriptor_status != DS_IDLE)) { |
b194b120 | 453 | /* |
2a919596 JS |
454 | * Our software ack messages may be blocked because |
455 | * there are no swack resources available. As long | |
456 | * as none of them has timed out hardware will NACK | |
457 | * our message and its state will stay IDLE. | |
b194b120 | 458 | */ |
f073cc8f | 459 | if (descriptor_status == DS_SOURCE_TIMEOUT) { |
b8f7fb13 CW |
460 | stat->s_stimeout++; |
461 | return FLUSH_GIVEUP; | |
f073cc8f | 462 | } else if (descriptor_status == DS_DESTINATION_TIMEOUT) { |
2a919596 | 463 | stat->s_dtimeout++; |
f073cc8f | 464 | ttm = get_cycles(); |
2a919596 JS |
465 | |
466 | /* | |
467 | * Our retries may be blocked by all destination | |
468 | * swack resources being consumed, and a timeout | |
469 | * pending. In that case hardware returns the | |
470 | * ERROR that looks like a destination timeout. | |
471 | */ | |
f073cc8f | 472 | if (cycles_2_us(ttm - bcp->send_message) < timeout_us) { |
2a919596 JS |
473 | bcp->conseccompletes = 0; |
474 | return FLUSH_RETRY_PLUGGED; | |
475 | } | |
476 | ||
477 | bcp->conseccompletes = 0; | |
478 | return FLUSH_RETRY_TIMEOUT; | |
479 | } else { | |
480 | /* | |
481 | * descriptor_status is still BUSY | |
482 | */ | |
483 | cpu_relax(); | |
484 | } | |
f073cc8f | 485 | descriptor_status = uv1_read_status(mmr_offset, right_shift); |
2a919596 JS |
486 | } |
487 | bcp->conseccompletes++; | |
488 | return FLUSH_COMPLETE; | |
489 | } | |
490 | ||
f073cc8f CW |
491 | /* |
492 | * UV2 has an extra bit of status in the ACTIVATION_STATUS_2 register. | |
493 | */ | |
494 | static unsigned long uv2_read_status(unsigned long offset, int rshft, int cpu) | |
2a919596 JS |
495 | { |
496 | unsigned long descriptor_status; | |
497 | unsigned long descriptor_status2; | |
f073cc8f CW |
498 | |
499 | descriptor_status = ((read_lmmr(offset) >> rshft) & UV_ACT_STATUS_MASK); | |
500 | descriptor_status2 = (read_mmr_uv2_status() >> cpu) & 0x1UL; | |
501 | descriptor_status = (descriptor_status << 1) | descriptor_status2; | |
502 | return descriptor_status; | |
503 | } | |
504 | ||
505 | static int uv2_wait_completion(struct bau_desc *bau_desc, | |
506 | unsigned long mmr_offset, int right_shift, | |
507 | struct bau_control *bcp, long try) | |
508 | { | |
509 | unsigned long descriptor_stat; | |
510 | cycles_t ttm; | |
511 | int cpu = bcp->uvhub_cpu; | |
2a919596 JS |
512 | struct ptc_stats *stat = bcp->statp; |
513 | ||
f073cc8f CW |
514 | descriptor_stat = uv2_read_status(mmr_offset, right_shift, cpu); |
515 | ||
2a919596 | 516 | /* spin on the status MMR, waiting for it to go idle */ |
f073cc8f | 517 | while (descriptor_stat != UV2H_DESC_IDLE) { |
2a919596 JS |
518 | /* |
519 | * Our software ack messages may be blocked because | |
520 | * there are no swack resources available. As long | |
521 | * as none of them has timed out hardware will NACK | |
522 | * our message and its state will stay IDLE. | |
523 | */ | |
f073cc8f CW |
524 | if ((descriptor_stat == UV2H_DESC_SOURCE_TIMEOUT) || |
525 | (descriptor_stat == UV2H_DESC_DEST_STRONG_NACK) || | |
526 | (descriptor_stat == UV2H_DESC_DEST_PUT_ERR)) { | |
2a919596 JS |
527 | stat->s_stimeout++; |
528 | return FLUSH_GIVEUP; | |
f073cc8f | 529 | } else if (descriptor_stat == UV2H_DESC_DEST_TIMEOUT) { |
b8f7fb13 | 530 | stat->s_dtimeout++; |
f073cc8f | 531 | ttm = get_cycles(); |
b8f7fb13 CW |
532 | /* |
533 | * Our retries may be blocked by all destination | |
534 | * swack resources being consumed, and a timeout | |
535 | * pending. In that case hardware returns the | |
536 | * ERROR that looks like a destination timeout. | |
537 | */ | |
f073cc8f | 538 | if (cycles_2_us(ttm - bcp->send_message) < timeout_us) { |
b8f7fb13 CW |
539 | bcp->conseccompletes = 0; |
540 | return FLUSH_RETRY_PLUGGED; | |
541 | } | |
b8f7fb13 CW |
542 | bcp->conseccompletes = 0; |
543 | return FLUSH_RETRY_TIMEOUT; | |
544 | } else { | |
545 | /* | |
f073cc8f | 546 | * descriptor_stat is still BUSY |
b8f7fb13 CW |
547 | */ |
548 | cpu_relax(); | |
b194b120 | 549 | } |
f073cc8f | 550 | descriptor_stat = uv2_read_status(mmr_offset, right_shift, cpu); |
b194b120 | 551 | } |
b8f7fb13 | 552 | bcp->conseccompletes++; |
b194b120 CW |
553 | return FLUSH_COMPLETE; |
554 | } | |
555 | ||
f073cc8f CW |
556 | /* |
557 | * There are 2 status registers; each and array[32] of 2 bits. Set up for | |
558 | * which register to read and position in that register based on cpu in | |
559 | * current hub. | |
560 | */ | |
561 | static int wait_completion(struct bau_desc *bau_desc, | |
562 | struct bau_control *bcp, long try) | |
2a919596 | 563 | { |
f073cc8f CW |
564 | int right_shift; |
565 | unsigned long mmr_offset; | |
566 | int cpu = bcp->uvhub_cpu; | |
567 | ||
568 | if (cpu < UV_CPUS_PER_AS) { | |
569 | mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0; | |
570 | right_shift = cpu * UV_ACT_STATUS_SIZE; | |
571 | } else { | |
572 | mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1; | |
573 | right_shift = ((cpu - UV_CPUS_PER_AS) * UV_ACT_STATUS_SIZE); | |
574 | } | |
575 | ||
da87c937 | 576 | if (bcp->uvhub_version == 1) |
2a919596 | 577 | return uv1_wait_completion(bau_desc, mmr_offset, right_shift, |
f073cc8f | 578 | bcp, try); |
2a919596 JS |
579 | else |
580 | return uv2_wait_completion(bau_desc, mmr_offset, right_shift, | |
f073cc8f | 581 | bcp, try); |
2a919596 JS |
582 | } |
583 | ||
f073cc8f | 584 | static inline cycles_t sec_2_cycles(unsigned long sec) |
b8f7fb13 CW |
585 | { |
586 | unsigned long ns; | |
587 | cycles_t cyc; | |
588 | ||
589 | ns = sec * 1000000000; | |
590 | cyc = (ns << CYC2NS_SCALE_FACTOR)/(per_cpu(cyc2ns, smp_processor_id())); | |
591 | return cyc; | |
592 | } | |
593 | ||
594 | /* | |
f073cc8f | 595 | * Our retries are blocked by all destination sw ack resources being |
f6d8a566 CW |
596 | * in use, and a timeout is pending. In that case hardware immediately |
597 | * returns the ERROR that looks like a destination timeout. | |
598 | */ | |
f073cc8f CW |
599 | static void destination_plugged(struct bau_desc *bau_desc, |
600 | struct bau_control *bcp, | |
f6d8a566 CW |
601 | struct bau_control *hmaster, struct ptc_stats *stat) |
602 | { | |
603 | udelay(bcp->plugged_delay); | |
604 | bcp->plugged_tries++; | |
f073cc8f | 605 | |
f6d8a566 CW |
606 | if (bcp->plugged_tries >= bcp->plugsb4reset) { |
607 | bcp->plugged_tries = 0; | |
f073cc8f | 608 | |
f6d8a566 | 609 | quiesce_local_uvhub(hmaster); |
f073cc8f | 610 | |
f6d8a566 | 611 | spin_lock(&hmaster->queue_lock); |
485f07d3 | 612 | reset_with_ipi(&bau_desc->distribution, bcp); |
f6d8a566 | 613 | spin_unlock(&hmaster->queue_lock); |
f073cc8f | 614 | |
f6d8a566 | 615 | end_uvhub_quiesce(hmaster); |
f073cc8f | 616 | |
f6d8a566 CW |
617 | bcp->ipi_attempts++; |
618 | stat->s_resets_plug++; | |
619 | } | |
620 | } | |
621 | ||
f073cc8f CW |
622 | static void destination_timeout(struct bau_desc *bau_desc, |
623 | struct bau_control *bcp, struct bau_control *hmaster, | |
624 | struct ptc_stats *stat) | |
f6d8a566 | 625 | { |
f073cc8f | 626 | hmaster->max_concurr = 1; |
f6d8a566 CW |
627 | bcp->timeout_tries++; |
628 | if (bcp->timeout_tries >= bcp->timeoutsb4reset) { | |
629 | bcp->timeout_tries = 0; | |
f073cc8f | 630 | |
f6d8a566 | 631 | quiesce_local_uvhub(hmaster); |
f073cc8f | 632 | |
f6d8a566 | 633 | spin_lock(&hmaster->queue_lock); |
485f07d3 | 634 | reset_with_ipi(&bau_desc->distribution, bcp); |
f6d8a566 | 635 | spin_unlock(&hmaster->queue_lock); |
f073cc8f | 636 | |
f6d8a566 | 637 | end_uvhub_quiesce(hmaster); |
f073cc8f | 638 | |
f6d8a566 CW |
639 | bcp->ipi_attempts++; |
640 | stat->s_resets_timeout++; | |
641 | } | |
642 | } | |
643 | ||
50fb55ac CW |
644 | /* |
645 | * Completions are taking a very long time due to a congested numalink | |
646 | * network. | |
647 | */ | |
f073cc8f CW |
648 | static void disable_for_congestion(struct bau_control *bcp, |
649 | struct ptc_stats *stat) | |
50fb55ac | 650 | { |
50fb55ac CW |
651 | /* let only one cpu do this disabling */ |
652 | spin_lock(&disable_lock); | |
f073cc8f | 653 | |
50fb55ac CW |
654 | if (!baudisabled && bcp->period_requests && |
655 | ((bcp->period_time / bcp->period_requests) > congested_cycles)) { | |
f073cc8f CW |
656 | int tcpu; |
657 | struct bau_control *tbcp; | |
50fb55ac CW |
658 | /* it becomes this cpu's job to turn on the use of the |
659 | BAU again */ | |
660 | baudisabled = 1; | |
661 | bcp->set_bau_off = 1; | |
f073cc8f CW |
662 | bcp->set_bau_on_time = get_cycles(); |
663 | bcp->set_bau_on_time += sec_2_cycles(bcp->cong_period); | |
50fb55ac CW |
664 | stat->s_bau_disabled++; |
665 | for_each_present_cpu(tcpu) { | |
666 | tbcp = &per_cpu(bau_control, tcpu); | |
f073cc8f | 667 | tbcp->baudisabled = 1; |
50fb55ac CW |
668 | } |
669 | } | |
f073cc8f | 670 | |
50fb55ac CW |
671 | spin_unlock(&disable_lock); |
672 | } | |
673 | ||
f073cc8f CW |
674 | static void count_max_concurr(int stat, struct bau_control *bcp, |
675 | struct bau_control *hmaster) | |
676 | { | |
677 | bcp->plugged_tries = 0; | |
678 | bcp->timeout_tries = 0; | |
679 | if (stat != FLUSH_COMPLETE) | |
680 | return; | |
681 | if (bcp->conseccompletes <= bcp->complete_threshold) | |
682 | return; | |
683 | if (hmaster->max_concurr >= hmaster->max_concurr_const) | |
684 | return; | |
685 | hmaster->max_concurr++; | |
686 | } | |
687 | ||
688 | static void record_send_stats(cycles_t time1, cycles_t time2, | |
689 | struct bau_control *bcp, struct ptc_stats *stat, | |
690 | int completion_status, int try) | |
691 | { | |
692 | cycles_t elapsed; | |
693 | ||
694 | if (time2 > time1) { | |
695 | elapsed = time2 - time1; | |
696 | stat->s_time += elapsed; | |
697 | ||
698 | if ((completion_status == FLUSH_COMPLETE) && (try == 1)) { | |
699 | bcp->period_requests++; | |
700 | bcp->period_time += elapsed; | |
701 | if ((elapsed > congested_cycles) && | |
702 | (bcp->period_requests > bcp->cong_reps)) | |
703 | disable_for_congestion(bcp, stat); | |
704 | } | |
705 | } else | |
706 | stat->s_requestor--; | |
707 | ||
708 | if (completion_status == FLUSH_COMPLETE && try > 1) | |
709 | stat->s_retriesok++; | |
710 | else if (completion_status == FLUSH_GIVEUP) | |
711 | stat->s_giveup++; | |
712 | } | |
713 | ||
714 | /* | |
715 | * Because of a uv1 hardware bug only a limited number of concurrent | |
716 | * requests can be made. | |
717 | */ | |
718 | static void uv1_throttle(struct bau_control *hmaster, struct ptc_stats *stat) | |
719 | { | |
720 | spinlock_t *lock = &hmaster->uvhub_lock; | |
721 | atomic_t *v; | |
722 | ||
723 | v = &hmaster->active_descriptor_count; | |
724 | if (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr)) { | |
725 | stat->s_throttles++; | |
726 | do { | |
727 | cpu_relax(); | |
728 | } while (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr)); | |
729 | } | |
730 | } | |
731 | ||
732 | /* | |
733 | * Handle the completion status of a message send. | |
734 | */ | |
735 | static void handle_cmplt(int completion_status, struct bau_desc *bau_desc, | |
736 | struct bau_control *bcp, struct bau_control *hmaster, | |
737 | struct ptc_stats *stat) | |
738 | { | |
739 | if (completion_status == FLUSH_RETRY_PLUGGED) | |
740 | destination_plugged(bau_desc, bcp, hmaster, stat); | |
741 | else if (completion_status == FLUSH_RETRY_TIMEOUT) | |
742 | destination_timeout(bau_desc, bcp, hmaster, stat); | |
743 | } | |
744 | ||
745 | /* | |
b8f7fb13 | 746 | * Send a broadcast and wait for it to complete. |
b194b120 | 747 | * |
f6d8a566 | 748 | * The flush_mask contains the cpus the broadcast is to be sent to including |
b8f7fb13 | 749 | * cpus that are on the local uvhub. |
b194b120 | 750 | * |
450a007e CW |
751 | * Returns 0 if all flushing represented in the mask was done. |
752 | * Returns 1 if it gives up entirely and the original cpu mask is to be | |
753 | * returned to the kernel. | |
b194b120 | 754 | */ |
450a007e | 755 | int uv_flush_send_and_wait(struct bau_desc *bau_desc, |
f073cc8f | 756 | struct cpumask *flush_mask, struct bau_control *bcp) |
b194b120 | 757 | { |
b8f7fb13 | 758 | int seq_number = 0; |
f073cc8f | 759 | int completion_stat = 0; |
da87c937 | 760 | int uv1 = 0; |
b8f7fb13 | 761 | long try = 0; |
b4c286e6 | 762 | unsigned long index; |
b194b120 CW |
763 | cycles_t time1; |
764 | cycles_t time2; | |
712157aa | 765 | struct ptc_stats *stat = bcp->statp; |
b8f7fb13 | 766 | struct bau_control *hmaster = bcp->uvhub_master; |
da87c937 CW |
767 | struct uv1_bau_msg_header *uv1_hdr = NULL; |
768 | struct uv2_bau_msg_header *uv2_hdr = NULL; | |
b8f7fb13 | 769 | |
da87c937 CW |
770 | if (bcp->uvhub_version == 1) { |
771 | uv1 = 1; | |
f073cc8f | 772 | uv1_throttle(hmaster, stat); |
da87c937 CW |
773 | uv1_hdr = &bau_desc->header.uv1_hdr; |
774 | } else | |
775 | uv2_hdr = &bau_desc->header.uv2_hdr; | |
f073cc8f | 776 | |
b8f7fb13 CW |
777 | while (hmaster->uvhub_quiesce) |
778 | cpu_relax(); | |
b194b120 | 779 | |
b194b120 CW |
780 | time1 = get_cycles(); |
781 | do { | |
b8f7fb13 | 782 | if (try == 0) { |
da87c937 CW |
783 | if (uv1) |
784 | uv1_hdr->msg_type = MSG_REGULAR; | |
785 | else | |
786 | uv2_hdr->msg_type = MSG_REGULAR; | |
b8f7fb13 CW |
787 | seq_number = bcp->message_number++; |
788 | } else { | |
da87c937 CW |
789 | if (uv1) |
790 | uv1_hdr->msg_type = MSG_RETRY; | |
791 | else | |
792 | uv2_hdr->msg_type = MSG_RETRY; | |
b8f7fb13 CW |
793 | stat->s_retry_messages++; |
794 | } | |
f073cc8f | 795 | |
da87c937 CW |
796 | if (uv1) |
797 | uv1_hdr->sequence = seq_number; | |
798 | else | |
799 | uv2_hdr->sequence = seq_number; | |
f073cc8f | 800 | index = (1UL << AS_PUSH_SHIFT) | bcp->uvhub_cpu; |
b8f7fb13 | 801 | bcp->send_message = get_cycles(); |
f073cc8f CW |
802 | |
803 | write_mmr_activation(index); | |
804 | ||
b8f7fb13 | 805 | try++; |
f073cc8f CW |
806 | completion_stat = wait_completion(bau_desc, bcp, try); |
807 | ||
808 | handle_cmplt(completion_stat, bau_desc, bcp, hmaster, stat); | |
b8f7fb13 | 809 | |
e8e5e8a8 | 810 | if (bcp->ipi_attempts >= bcp->ipi_reset_limit) { |
b8f7fb13 | 811 | bcp->ipi_attempts = 0; |
f073cc8f | 812 | completion_stat = FLUSH_GIVEUP; |
b8f7fb13 CW |
813 | break; |
814 | } | |
815 | cpu_relax(); | |
f073cc8f CW |
816 | } while ((completion_stat == FLUSH_RETRY_PLUGGED) || |
817 | (completion_stat == FLUSH_RETRY_TIMEOUT)); | |
818 | ||
b194b120 | 819 | time2 = get_cycles(); |
f073cc8f CW |
820 | |
821 | count_max_concurr(completion_stat, bcp, hmaster); | |
822 | ||
b8f7fb13 CW |
823 | while (hmaster->uvhub_quiesce) |
824 | cpu_relax(); | |
f073cc8f | 825 | |
b8f7fb13 | 826 | atomic_dec(&hmaster->active_descriptor_count); |
f073cc8f CW |
827 | |
828 | record_send_stats(time1, time2, bcp, stat, completion_stat, try); | |
829 | ||
830 | if (completion_stat == FLUSH_GIVEUP) | |
831 | return 1; | |
832 | return 0; | |
833 | } | |
834 | ||
835 | /* | |
836 | * The BAU is disabled. When the disabled time period has expired, the cpu | |
837 | * that disabled it must re-enable it. | |
838 | * Return 0 if it is re-enabled for all cpus. | |
839 | */ | |
840 | static int check_enable(struct bau_control *bcp, struct ptc_stats *stat) | |
841 | { | |
842 | int tcpu; | |
843 | struct bau_control *tbcp; | |
844 | ||
845 | if (bcp->set_bau_off) { | |
846 | if (get_cycles() >= bcp->set_bau_on_time) { | |
847 | stat->s_bau_reenabled++; | |
848 | baudisabled = 0; | |
849 | for_each_present_cpu(tcpu) { | |
850 | tbcp = &per_cpu(bau_control, tcpu); | |
851 | tbcp->baudisabled = 0; | |
852 | tbcp->period_requests = 0; | |
853 | tbcp->period_time = 0; | |
50fb55ac | 854 | } |
f073cc8f | 855 | return 0; |
50fb55ac | 856 | } |
f073cc8f CW |
857 | } |
858 | return -1; | |
859 | } | |
860 | ||
861 | static void record_send_statistics(struct ptc_stats *stat, int locals, int hubs, | |
862 | int remotes, struct bau_desc *bau_desc) | |
863 | { | |
864 | stat->s_requestor++; | |
865 | stat->s_ntargcpu += remotes + locals; | |
866 | stat->s_ntargremotes += remotes; | |
867 | stat->s_ntarglocals += locals; | |
868 | ||
869 | /* uvhub statistics */ | |
870 | hubs = bau_uvhub_weight(&bau_desc->distribution); | |
871 | if (locals) { | |
872 | stat->s_ntarglocaluvhub++; | |
873 | stat->s_ntargremoteuvhub += (hubs - 1); | |
e8e5e8a8 | 874 | } else |
f073cc8f CW |
875 | stat->s_ntargremoteuvhub += hubs; |
876 | ||
877 | stat->s_ntarguvhub += hubs; | |
878 | ||
879 | if (hubs >= 16) | |
880 | stat->s_ntarguvhub16++; | |
881 | else if (hubs >= 8) | |
882 | stat->s_ntarguvhub8++; | |
883 | else if (hubs >= 4) | |
884 | stat->s_ntarguvhub4++; | |
885 | else if (hubs >= 2) | |
886 | stat->s_ntarguvhub2++; | |
887 | else | |
888 | stat->s_ntarguvhub1++; | |
889 | } | |
890 | ||
891 | /* | |
892 | * Translate a cpu mask to the uvhub distribution mask in the BAU | |
893 | * activation descriptor. | |
894 | */ | |
895 | static int set_distrib_bits(struct cpumask *flush_mask, struct bau_control *bcp, | |
896 | struct bau_desc *bau_desc, int *localsp, int *remotesp) | |
897 | { | |
898 | int cpu; | |
899 | int pnode; | |
900 | int cnt = 0; | |
901 | struct hub_and_pnode *hpp; | |
902 | ||
903 | for_each_cpu(cpu, flush_mask) { | |
904 | /* | |
905 | * The distribution vector is a bit map of pnodes, relative | |
906 | * to the partition base pnode (and the partition base nasid | |
907 | * in the header). | |
908 | * Translate cpu to pnode and hub using a local memory array. | |
909 | */ | |
910 | hpp = &bcp->socket_master->thp[cpu]; | |
911 | pnode = hpp->pnode - bcp->partition_base_pnode; | |
912 | bau_uvhub_set(pnode, &bau_desc->distribution); | |
913 | cnt++; | |
914 | if (hpp->uvhub == bcp->uvhub) | |
915 | (*localsp)++; | |
916 | else | |
917 | (*remotesp)++; | |
b194b120 | 918 | } |
f073cc8f CW |
919 | if (!cnt) |
920 | return 1; | |
450a007e | 921 | return 0; |
b194b120 CW |
922 | } |
923 | ||
f073cc8f CW |
924 | /* |
925 | * globally purge translation cache of a virtual address or all TLB's | |
bdbcdd48 | 926 | * @cpumask: mask of all cpu's in which the address is to be removed |
1812924b CW |
927 | * @mm: mm_struct containing virtual address range |
928 | * @va: virtual address to be removed (or TLB_FLUSH_ALL for all TLB's on cpu) | |
bdbcdd48 | 929 | * @cpu: the current cpu |
1812924b CW |
930 | * |
931 | * This is the entry point for initiating any UV global TLB shootdown. | |
932 | * | |
933 | * Purges the translation caches of all specified processors of the given | |
934 | * virtual address, or purges all TLB's on specified processors. | |
935 | * | |
bdbcdd48 TH |
936 | * The caller has derived the cpumask from the mm_struct. This function |
937 | * is called only if there are bits set in the mask. (e.g. flush_tlb_page()) | |
1812924b | 938 | * |
b8f7fb13 CW |
939 | * The cpumask is converted into a uvhubmask of the uvhubs containing |
940 | * those cpus. | |
b194b120 | 941 | * |
bdbcdd48 TH |
942 | * Note that this function should be called with preemption disabled. |
943 | * | |
944 | * Returns NULL if all remote flushing was done. | |
945 | * Returns pointer to cpumask if some remote flushing remains to be | |
946 | * done. The returned pointer is valid till preemption is re-enabled. | |
1812924b | 947 | */ |
bdbcdd48 | 948 | const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask, |
f073cc8f CW |
949 | struct mm_struct *mm, unsigned long va, |
950 | unsigned int cpu) | |
1812924b | 951 | { |
b194b120 | 952 | int locals = 0; |
450a007e CW |
953 | int remotes = 0; |
954 | int hubs = 0; | |
dc163a41 | 955 | struct bau_desc *bau_desc; |
b8f7fb13 CW |
956 | struct cpumask *flush_mask; |
957 | struct ptc_stats *stat; | |
958 | struct bau_control *bcp; | |
bdbcdd48 | 959 | |
e8e5e8a8 | 960 | /* kernel was booted 'nobau' */ |
b8f7fb13 CW |
961 | if (nobau) |
962 | return cpumask; | |
bdbcdd48 | 963 | |
b8f7fb13 | 964 | bcp = &per_cpu(bau_control, cpu); |
712157aa | 965 | stat = bcp->statp; |
50fb55ac CW |
966 | |
967 | /* bau was disabled due to slow response */ | |
968 | if (bcp->baudisabled) { | |
f073cc8f CW |
969 | if (check_enable(bcp, stat)) |
970 | return cpumask; | |
50fb55ac | 971 | } |
e8e5e8a8 | 972 | |
b8f7fb13 CW |
973 | /* |
974 | * Each sending cpu has a per-cpu mask which it fills from the caller's | |
450a007e CW |
975 | * cpu mask. All cpus are converted to uvhubs and copied to the |
976 | * activation descriptor. | |
b8f7fb13 CW |
977 | */ |
978 | flush_mask = (struct cpumask *)per_cpu(uv_flush_tlb_mask, cpu); | |
450a007e | 979 | /* don't actually do a shootdown of the local cpu */ |
b8f7fb13 | 980 | cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu)); |
f073cc8f | 981 | |
b8f7fb13 | 982 | if (cpu_isset(cpu, *cpumask)) |
450a007e | 983 | stat->s_ntargself++; |
1812924b | 984 | |
b8f7fb13 | 985 | bau_desc = bcp->descriptor_base; |
da87c937 | 986 | bau_desc += (ITEMS_PER_DESC * bcp->uvhub_cpu); |
b8f7fb13 | 987 | bau_uvhubs_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE); |
f073cc8f | 988 | if (set_distrib_bits(flush_mask, bcp, bau_desc, &locals, &remotes)) |
450a007e | 989 | return NULL; |
450a007e | 990 | |
f073cc8f | 991 | record_send_statistics(stat, locals, hubs, remotes, bau_desc); |
1812924b CW |
992 | |
993 | bau_desc->payload.address = va; | |
bdbcdd48 | 994 | bau_desc->payload.sending_cpu = cpu; |
b8f7fb13 | 995 | /* |
450a007e CW |
996 | * uv_flush_send_and_wait returns 0 if all cpu's were messaged, |
997 | * or 1 if it gave up and the original cpumask should be returned. | |
b8f7fb13 | 998 | */ |
450a007e CW |
999 | if (!uv_flush_send_and_wait(bau_desc, flush_mask, bcp)) |
1000 | return NULL; | |
1001 | else | |
1002 | return cpumask; | |
1812924b CW |
1003 | } |
1004 | ||
1005 | /* | |
1006 | * The BAU message interrupt comes here. (registered by set_intr_gate) | |
1007 | * See entry_64.S | |
1008 | * | |
1009 | * We received a broadcast assist message. | |
1010 | * | |
b8f7fb13 | 1011 | * Interrupts are disabled; this interrupt could represent |
1812924b CW |
1012 | * the receipt of several messages. |
1013 | * | |
b8f7fb13 CW |
1014 | * All cores/threads on this hub get this interrupt. |
1015 | * The last one to see it does the software ack. | |
1812924b | 1016 | * (the resource will not be freed until noninterruptable cpus see this |
b8f7fb13 | 1017 | * interrupt; hardware may timeout the s/w ack and reply ERROR) |
1812924b | 1018 | */ |
b194b120 | 1019 | void uv_bau_message_interrupt(struct pt_regs *regs) |
1812924b | 1020 | { |
1812924b | 1021 | int count = 0; |
b8f7fb13 | 1022 | cycles_t time_start; |
f073cc8f | 1023 | struct bau_pq_entry *msg; |
b8f7fb13 CW |
1024 | struct bau_control *bcp; |
1025 | struct ptc_stats *stat; | |
1026 | struct msg_desc msgdesc; | |
1027 | ||
1028 | time_start = get_cycles(); | |
f073cc8f | 1029 | |
b8f7fb13 | 1030 | bcp = &per_cpu(bau_control, smp_processor_id()); |
712157aa | 1031 | stat = bcp->statp; |
f073cc8f CW |
1032 | |
1033 | msgdesc.queue_first = bcp->queue_first; | |
1034 | msgdesc.queue_last = bcp->queue_last; | |
1035 | ||
b8f7fb13 | 1036 | msg = bcp->bau_msg_head; |
f073cc8f | 1037 | while (msg->swack_vec) { |
1812924b | 1038 | count++; |
f073cc8f CW |
1039 | |
1040 | msgdesc.msg_slot = msg - msgdesc.queue_first; | |
1041 | msgdesc.swack_slot = ffs(msg->swack_vec) - 1; | |
b8f7fb13 | 1042 | msgdesc.msg = msg; |
f073cc8f CW |
1043 | bau_process_message(&msgdesc, bcp); |
1044 | ||
1812924b | 1045 | msg++; |
f073cc8f CW |
1046 | if (msg > msgdesc.queue_last) |
1047 | msg = msgdesc.queue_first; | |
b8f7fb13 | 1048 | bcp->bau_msg_head = msg; |
1812924b | 1049 | } |
b8f7fb13 | 1050 | stat->d_time += (get_cycles() - time_start); |
1812924b | 1051 | if (!count) |
b8f7fb13 | 1052 | stat->d_nomsg++; |
1812924b | 1053 | else if (count > 1) |
b8f7fb13 | 1054 | stat->d_multmsg++; |
f073cc8f | 1055 | |
b8f7fb13 | 1056 | ack_APIC_irq(); |
1812924b CW |
1057 | } |
1058 | ||
c4c4688f | 1059 | /* |
f073cc8f | 1060 | * Each target uvhub (i.e. a uvhub that has cpu's) needs to have |
c4c4688f CW |
1061 | * shootdown message timeouts enabled. The timeout does not cause |
1062 | * an interrupt, but causes an error message to be returned to | |
1063 | * the sender. | |
1064 | */ | |
f073cc8f | 1065 | static void __init enable_timeouts(void) |
1812924b | 1066 | { |
b8f7fb13 CW |
1067 | int uvhub; |
1068 | int nuvhubs; | |
1812924b | 1069 | int pnode; |
c4c4688f | 1070 | unsigned long mmr_image; |
1812924b | 1071 | |
b8f7fb13 | 1072 | nuvhubs = uv_num_possible_blades(); |
1812924b | 1073 | |
b8f7fb13 CW |
1074 | for (uvhub = 0; uvhub < nuvhubs; uvhub++) { |
1075 | if (!uv_blade_nr_possible_cpus(uvhub)) | |
1812924b | 1076 | continue; |
c4c4688f | 1077 | |
b8f7fb13 | 1078 | pnode = uv_blade_to_pnode(uvhub); |
f073cc8f | 1079 | mmr_image = read_mmr_misc_control(pnode); |
c4c4688f CW |
1080 | /* |
1081 | * Set the timeout period and then lock it in, in three | |
1082 | * steps; captures and locks in the period. | |
1083 | * | |
1084 | * To program the period, the SOFT_ACK_MODE must be off. | |
1085 | */ | |
f073cc8f CW |
1086 | mmr_image &= ~(1L << SOFTACK_MSHIFT); |
1087 | write_mmr_misc_control(pnode, mmr_image); | |
c4c4688f CW |
1088 | /* |
1089 | * Set the 4-bit period. | |
1090 | */ | |
f073cc8f CW |
1091 | mmr_image &= ~((unsigned long)0xf << SOFTACK_PSHIFT); |
1092 | mmr_image |= (SOFTACK_TIMEOUT_PERIOD << SOFTACK_PSHIFT); | |
1093 | write_mmr_misc_control(pnode, mmr_image); | |
c4c4688f | 1094 | /* |
2a919596 | 1095 | * UV1: |
c4c4688f CW |
1096 | * Subsequent reversals of the timebase bit (3) cause an |
1097 | * immediate timeout of one or all INTD resources as | |
1098 | * indicated in bits 2:0 (7 causes all of them to timeout). | |
1099 | */ | |
f073cc8f | 1100 | mmr_image |= (1L << SOFTACK_MSHIFT); |
2a919596 | 1101 | if (is_uv2_hub()) { |
da87c937 | 1102 | mmr_image &= ~(1L << UV2_LEG_SHFT); |
f073cc8f | 1103 | mmr_image |= (1L << UV2_EXT_SHFT); |
2a919596 | 1104 | } |
f073cc8f | 1105 | write_mmr_misc_control(pnode, mmr_image); |
1812924b | 1106 | } |
1812924b CW |
1107 | } |
1108 | ||
f073cc8f | 1109 | static void *ptc_seq_start(struct seq_file *file, loff_t *offset) |
1812924b CW |
1110 | { |
1111 | if (*offset < num_possible_cpus()) | |
1112 | return offset; | |
1113 | return NULL; | |
1114 | } | |
1115 | ||
f073cc8f | 1116 | static void *ptc_seq_next(struct seq_file *file, void *data, loff_t *offset) |
1812924b CW |
1117 | { |
1118 | (*offset)++; | |
1119 | if (*offset < num_possible_cpus()) | |
1120 | return offset; | |
1121 | return NULL; | |
1122 | } | |
1123 | ||
f073cc8f | 1124 | static void ptc_seq_stop(struct seq_file *file, void *data) |
1812924b CW |
1125 | { |
1126 | } | |
1127 | ||
f073cc8f | 1128 | static inline unsigned long long usec_2_cycles(unsigned long microsec) |
b8f7fb13 CW |
1129 | { |
1130 | unsigned long ns; | |
1131 | unsigned long long cyc; | |
1132 | ||
12a6611f | 1133 | ns = microsec * 1000; |
b8f7fb13 CW |
1134 | cyc = (ns << CYC2NS_SCALE_FACTOR)/(per_cpu(cyc2ns, smp_processor_id())); |
1135 | return cyc; | |
1136 | } | |
1137 | ||
1812924b | 1138 | /* |
f073cc8f | 1139 | * Display the statistics thru /proc/sgi_uv/ptc_statistics |
b8f7fb13 | 1140 | * 'data' points to the cpu number |
f073cc8f | 1141 | * Note: see the descriptions in stat_description[]. |
1812924b | 1142 | */ |
f073cc8f | 1143 | static int ptc_seq_show(struct seq_file *file, void *data) |
1812924b CW |
1144 | { |
1145 | struct ptc_stats *stat; | |
1146 | int cpu; | |
1147 | ||
1148 | cpu = *(loff_t *)data; | |
1812924b CW |
1149 | if (!cpu) { |
1150 | seq_printf(file, | |
450a007e CW |
1151 | "# cpu sent stime self locals remotes ncpus localhub "); |
1152 | seq_printf(file, | |
1153 | "remotehub numuvhubs numuvhubs16 numuvhubs8 "); | |
1812924b | 1154 | seq_printf(file, |
f073cc8f | 1155 | "numuvhubs4 numuvhubs2 numuvhubs1 dto retries rok "); |
b8f7fb13 | 1156 | seq_printf(file, |
f073cc8f | 1157 | "resetp resett giveup sto bz throt swack recv rtime "); |
b8f7fb13 | 1158 | seq_printf(file, |
f073cc8f | 1159 | "all one mult none retry canc nocan reset rcan "); |
50fb55ac CW |
1160 | seq_printf(file, |
1161 | "disable enable\n"); | |
1812924b CW |
1162 | } |
1163 | if (cpu < num_possible_cpus() && cpu_online(cpu)) { | |
1164 | stat = &per_cpu(ptcstats, cpu); | |
b8f7fb13 CW |
1165 | /* source side statistics */ |
1166 | seq_printf(file, | |
1167 | "cpu %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ", | |
1168 | cpu, stat->s_requestor, cycles_2_us(stat->s_time), | |
450a007e CW |
1169 | stat->s_ntargself, stat->s_ntarglocals, |
1170 | stat->s_ntargremotes, stat->s_ntargcpu, | |
1171 | stat->s_ntarglocaluvhub, stat->s_ntargremoteuvhub, | |
1172 | stat->s_ntarguvhub, stat->s_ntarguvhub16); | |
1173 | seq_printf(file, "%ld %ld %ld %ld %ld ", | |
b8f7fb13 CW |
1174 | stat->s_ntarguvhub8, stat->s_ntarguvhub4, |
1175 | stat->s_ntarguvhub2, stat->s_ntarguvhub1, | |
450a007e | 1176 | stat->s_dtimeout); |
b8f7fb13 CW |
1177 | seq_printf(file, "%ld %ld %ld %ld %ld %ld %ld %ld ", |
1178 | stat->s_retry_messages, stat->s_retriesok, | |
1179 | stat->s_resets_plug, stat->s_resets_timeout, | |
1180 | stat->s_giveup, stat->s_stimeout, | |
1181 | stat->s_busy, stat->s_throttles); | |
e8e5e8a8 | 1182 | |
b8f7fb13 CW |
1183 | /* destination side statistics */ |
1184 | seq_printf(file, | |
50fb55ac | 1185 | "%lx %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ", |
f073cc8f | 1186 | read_gmmr_sw_ack(uv_cpu_to_pnode(cpu)), |
b8f7fb13 CW |
1187 | stat->d_requestee, cycles_2_us(stat->d_time), |
1188 | stat->d_alltlb, stat->d_onetlb, stat->d_multmsg, | |
1189 | stat->d_nomsg, stat->d_retries, stat->d_canceled, | |
1190 | stat->d_nocanceled, stat->d_resets, | |
1191 | stat->d_rcanceled); | |
50fb55ac CW |
1192 | seq_printf(file, "%ld %ld\n", |
1193 | stat->s_bau_disabled, stat->s_bau_reenabled); | |
1812924b | 1194 | } |
1812924b CW |
1195 | return 0; |
1196 | } | |
1197 | ||
e8e5e8a8 CW |
1198 | /* |
1199 | * Display the tunables thru debugfs | |
1200 | */ | |
1201 | static ssize_t tunables_read(struct file *file, char __user *userbuf, | |
f073cc8f | 1202 | size_t count, loff_t *ppos) |
e8e5e8a8 | 1203 | { |
b365a85c | 1204 | char *buf; |
e8e5e8a8 CW |
1205 | int ret; |
1206 | ||
b365a85c | 1207 | buf = kasprintf(GFP_KERNEL, "%s %s %s\n%d %d %d %d %d %d %d %d %d\n", |
f073cc8f | 1208 | "max_concur plugged_delay plugsb4reset", |
e8e5e8a8 CW |
1209 | "timeoutsb4reset ipi_reset_limit complete_threshold", |
1210 | "congested_response_us congested_reps congested_period", | |
f073cc8f | 1211 | max_concurr, plugged_delay, plugsb4reset, |
e8e5e8a8 | 1212 | timeoutsb4reset, ipi_reset_limit, complete_threshold, |
f073cc8f | 1213 | congested_respns_us, congested_reps, congested_period); |
e8e5e8a8 | 1214 | |
b365a85c DC |
1215 | if (!buf) |
1216 | return -ENOMEM; | |
1217 | ||
1218 | ret = simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf)); | |
1219 | kfree(buf); | |
1220 | return ret; | |
e8e5e8a8 CW |
1221 | } |
1222 | ||
1812924b | 1223 | /* |
f073cc8f CW |
1224 | * handle a write to /proc/sgi_uv/ptc_statistics |
1225 | * -1: reset the statistics | |
1812924b | 1226 | * 0: display meaning of the statistics |
1812924b | 1227 | */ |
f073cc8f CW |
1228 | static ssize_t ptc_proc_write(struct file *file, const char __user *user, |
1229 | size_t count, loff_t *data) | |
1812924b | 1230 | { |
b8f7fb13 | 1231 | int cpu; |
f073cc8f CW |
1232 | int i; |
1233 | int elements; | |
b8f7fb13 | 1234 | long input_arg; |
1812924b | 1235 | char optstr[64]; |
b8f7fb13 | 1236 | struct ptc_stats *stat; |
1812924b | 1237 | |
e7eb8726 | 1238 | if (count == 0 || count > sizeof(optstr)) |
cef53278 | 1239 | return -EINVAL; |
1812924b CW |
1240 | if (copy_from_user(optstr, user, count)) |
1241 | return -EFAULT; | |
1242 | optstr[count - 1] = '\0'; | |
f073cc8f | 1243 | |
b8f7fb13 | 1244 | if (strict_strtol(optstr, 10, &input_arg) < 0) { |
1812924b CW |
1245 | printk(KERN_DEBUG "%s is invalid\n", optstr); |
1246 | return -EINVAL; | |
1247 | } | |
1248 | ||
b8f7fb13 | 1249 | if (input_arg == 0) { |
f073cc8f | 1250 | elements = sizeof(stat_description)/sizeof(*stat_description); |
1812924b | 1251 | printk(KERN_DEBUG "# cpu: cpu number\n"); |
b8f7fb13 | 1252 | printk(KERN_DEBUG "Sender statistics:\n"); |
f073cc8f CW |
1253 | for (i = 0; i < elements; i++) |
1254 | printk(KERN_DEBUG "%s\n", stat_description[i]); | |
b8f7fb13 CW |
1255 | } else if (input_arg == -1) { |
1256 | for_each_present_cpu(cpu) { | |
1257 | stat = &per_cpu(ptcstats, cpu); | |
1258 | memset(stat, 0, sizeof(struct ptc_stats)); | |
1259 | } | |
e8e5e8a8 CW |
1260 | } |
1261 | ||
1262 | return count; | |
1263 | } | |
1264 | ||
1265 | static int local_atoi(const char *name) | |
1266 | { | |
1267 | int val = 0; | |
1268 | ||
1269 | for (;; name++) { | |
1270 | switch (*name) { | |
1271 | case '0' ... '9': | |
1272 | val = 10*val+(*name-'0'); | |
1273 | break; | |
1274 | default: | |
1275 | return val; | |
b8f7fb13 | 1276 | } |
1812924b | 1277 | } |
e8e5e8a8 CW |
1278 | } |
1279 | ||
1280 | /* | |
f073cc8f CW |
1281 | * Parse the values written to /sys/kernel/debug/sgi_uv/bau_tunables. |
1282 | * Zero values reset them to defaults. | |
e8e5e8a8 | 1283 | */ |
f073cc8f CW |
1284 | static int parse_tunables_write(struct bau_control *bcp, char *instr, |
1285 | int count) | |
e8e5e8a8 | 1286 | { |
e8e5e8a8 CW |
1287 | char *p; |
1288 | char *q; | |
f073cc8f CW |
1289 | int cnt = 0; |
1290 | int val; | |
1291 | int e = sizeof(tunables) / sizeof(*tunables); | |
e8e5e8a8 | 1292 | |
e8e5e8a8 CW |
1293 | p = instr + strspn(instr, WHITESPACE); |
1294 | q = p; | |
1295 | for (; *p; p = q + strspn(q, WHITESPACE)) { | |
1296 | q = p + strcspn(p, WHITESPACE); | |
1297 | cnt++; | |
1298 | if (q == p) | |
1299 | break; | |
1300 | } | |
f073cc8f CW |
1301 | if (cnt != e) { |
1302 | printk(KERN_INFO "bau tunable error: should be %d values\n", e); | |
e8e5e8a8 CW |
1303 | return -EINVAL; |
1304 | } | |
1305 | ||
1306 | p = instr + strspn(instr, WHITESPACE); | |
1307 | q = p; | |
1308 | for (cnt = 0; *p; p = q + strspn(q, WHITESPACE), cnt++) { | |
1309 | q = p + strcspn(p, WHITESPACE); | |
1310 | val = local_atoi(p); | |
1311 | switch (cnt) { | |
1312 | case 0: | |
1313 | if (val == 0) { | |
f073cc8f CW |
1314 | max_concurr = MAX_BAU_CONCURRENT; |
1315 | max_concurr_const = MAX_BAU_CONCURRENT; | |
e8e5e8a8 CW |
1316 | continue; |
1317 | } | |
e8e5e8a8 CW |
1318 | if (val < 1 || val > bcp->cpus_in_uvhub) { |
1319 | printk(KERN_DEBUG | |
1320 | "Error: BAU max concurrent %d is invalid\n", | |
1321 | val); | |
1322 | return -EINVAL; | |
1323 | } | |
f073cc8f CW |
1324 | max_concurr = val; |
1325 | max_concurr_const = val; | |
e8e5e8a8 | 1326 | continue; |
f073cc8f | 1327 | default: |
e8e5e8a8 | 1328 | if (val == 0) |
f073cc8f | 1329 | *tunables[cnt].tunp = tunables[cnt].deflt; |
e8e5e8a8 | 1330 | else |
f073cc8f | 1331 | *tunables[cnt].tunp = val; |
e8e5e8a8 CW |
1332 | continue; |
1333 | } | |
1334 | if (q == p) | |
1335 | break; | |
1336 | } | |
f073cc8f CW |
1337 | return 0; |
1338 | } | |
1339 | ||
1340 | /* | |
1341 | * Handle a write to debugfs. (/sys/kernel/debug/sgi_uv/bau_tunables) | |
1342 | */ | |
1343 | static ssize_t tunables_write(struct file *file, const char __user *user, | |
1344 | size_t count, loff_t *data) | |
1345 | { | |
1346 | int cpu; | |
1347 | int ret; | |
1348 | char instr[100]; | |
1349 | struct bau_control *bcp; | |
1350 | ||
1351 | if (count == 0 || count > sizeof(instr)-1) | |
1352 | return -EINVAL; | |
1353 | if (copy_from_user(instr, user, count)) | |
1354 | return -EFAULT; | |
1355 | ||
1356 | instr[count] = '\0'; | |
1357 | ||
00b30cf0 | 1358 | cpu = get_cpu(); |
1359 | bcp = &per_cpu(bau_control, cpu); | |
f073cc8f | 1360 | ret = parse_tunables_write(bcp, instr, count); |
00b30cf0 | 1361 | put_cpu(); |
f073cc8f CW |
1362 | if (ret) |
1363 | return ret; | |
1364 | ||
e8e5e8a8 CW |
1365 | for_each_present_cpu(cpu) { |
1366 | bcp = &per_cpu(bau_control, cpu); | |
f073cc8f CW |
1367 | bcp->max_concurr = max_concurr; |
1368 | bcp->max_concurr_const = max_concurr; | |
1369 | bcp->plugged_delay = plugged_delay; | |
1370 | bcp->plugsb4reset = plugsb4reset; | |
1371 | bcp->timeoutsb4reset = timeoutsb4reset; | |
1372 | bcp->ipi_reset_limit = ipi_reset_limit; | |
1373 | bcp->complete_threshold = complete_threshold; | |
1374 | bcp->cong_response_us = congested_respns_us; | |
1375 | bcp->cong_reps = congested_reps; | |
1376 | bcp->cong_period = congested_period; | |
e8e5e8a8 | 1377 | } |
1812924b CW |
1378 | return count; |
1379 | } | |
1380 | ||
1381 | static const struct seq_operations uv_ptc_seq_ops = { | |
f073cc8f CW |
1382 | .start = ptc_seq_start, |
1383 | .next = ptc_seq_next, | |
1384 | .stop = ptc_seq_stop, | |
1385 | .show = ptc_seq_show | |
1812924b CW |
1386 | }; |
1387 | ||
f073cc8f | 1388 | static int ptc_proc_open(struct inode *inode, struct file *file) |
1812924b CW |
1389 | { |
1390 | return seq_open(file, &uv_ptc_seq_ops); | |
1391 | } | |
1392 | ||
e8e5e8a8 CW |
1393 | static int tunables_open(struct inode *inode, struct file *file) |
1394 | { | |
1395 | return 0; | |
1396 | } | |
1397 | ||
1812924b | 1398 | static const struct file_operations proc_uv_ptc_operations = { |
f073cc8f | 1399 | .open = ptc_proc_open, |
b194b120 | 1400 | .read = seq_read, |
f073cc8f | 1401 | .write = ptc_proc_write, |
b194b120 CW |
1402 | .llseek = seq_lseek, |
1403 | .release = seq_release, | |
1812924b CW |
1404 | }; |
1405 | ||
e8e5e8a8 CW |
1406 | static const struct file_operations tunables_fops = { |
1407 | .open = tunables_open, | |
1408 | .read = tunables_read, | |
1409 | .write = tunables_write, | |
6038f373 | 1410 | .llseek = default_llseek, |
e8e5e8a8 CW |
1411 | }; |
1412 | ||
b194b120 | 1413 | static int __init uv_ptc_init(void) |
1812924b | 1414 | { |
b194b120 | 1415 | struct proc_dir_entry *proc_uv_ptc; |
1812924b CW |
1416 | |
1417 | if (!is_uv_system()) | |
1418 | return 0; | |
1419 | ||
10f02d11 AD |
1420 | proc_uv_ptc = proc_create(UV_PTC_BASENAME, 0444, NULL, |
1421 | &proc_uv_ptc_operations); | |
1812924b CW |
1422 | if (!proc_uv_ptc) { |
1423 | printk(KERN_ERR "unable to create %s proc entry\n", | |
1424 | UV_PTC_BASENAME); | |
1425 | return -EINVAL; | |
1426 | } | |
e8e5e8a8 CW |
1427 | |
1428 | tunables_dir = debugfs_create_dir(UV_BAU_TUNABLES_DIR, NULL); | |
1429 | if (!tunables_dir) { | |
1430 | printk(KERN_ERR "unable to create debugfs directory %s\n", | |
1431 | UV_BAU_TUNABLES_DIR); | |
1432 | return -EINVAL; | |
1433 | } | |
1434 | tunables_file = debugfs_create_file(UV_BAU_TUNABLES_FILE, 0600, | |
f073cc8f | 1435 | tunables_dir, NULL, &tunables_fops); |
e8e5e8a8 CW |
1436 | if (!tunables_file) { |
1437 | printk(KERN_ERR "unable to create debugfs file %s\n", | |
1438 | UV_BAU_TUNABLES_FILE); | |
1439 | return -EINVAL; | |
1440 | } | |
1812924b CW |
1441 | return 0; |
1442 | } | |
1443 | ||
1812924b | 1444 | /* |
77ed23f8 | 1445 | * Initialize the sending side's sending buffers. |
1812924b | 1446 | */ |
f073cc8f | 1447 | static void activation_descriptor_init(int node, int pnode, int base_pnode) |
1812924b CW |
1448 | { |
1449 | int i; | |
b8f7fb13 | 1450 | int cpu; |
da87c937 | 1451 | int uv1 = 0; |
6a469e46 | 1452 | unsigned long gpa; |
1812924b | 1453 | unsigned long m; |
b194b120 | 1454 | unsigned long n; |
f073cc8f | 1455 | size_t dsize; |
b8f7fb13 CW |
1456 | struct bau_desc *bau_desc; |
1457 | struct bau_desc *bd2; | |
da87c937 CW |
1458 | struct uv1_bau_msg_header *uv1_hdr; |
1459 | struct uv2_bau_msg_header *uv2_hdr; | |
b8f7fb13 | 1460 | struct bau_control *bcp; |
b194b120 | 1461 | |
0e2595cd | 1462 | /* |
f073cc8f CW |
1463 | * each bau_desc is 64 bytes; there are 8 (ITEMS_PER_DESC) |
1464 | * per cpu; and one per cpu on the uvhub (ADP_SZ) | |
0e2595cd | 1465 | */ |
f073cc8f CW |
1466 | dsize = sizeof(struct bau_desc) * ADP_SZ * ITEMS_PER_DESC; |
1467 | bau_desc = kmalloc_node(dsize, GFP_KERNEL, node); | |
b8f7fb13 | 1468 | BUG_ON(!bau_desc); |
b4c286e6 | 1469 | |
6a469e46 JS |
1470 | gpa = uv_gpa(bau_desc); |
1471 | n = uv_gpa_to_gnode(gpa); | |
1472 | m = uv_gpa_to_offset(gpa); | |
da87c937 CW |
1473 | if (is_uv1_hub()) |
1474 | uv1 = 1; | |
b4c286e6 | 1475 | |
77ed23f8 | 1476 | /* the 14-bit pnode */ |
f073cc8f | 1477 | write_mmr_descriptor_base(pnode, (n << UV_DESC_PSHIFT | m)); |
0e2595cd | 1478 | /* |
f073cc8f | 1479 | * Initializing all 8 (ITEMS_PER_DESC) descriptors for each |
0e2595cd | 1480 | * cpu even though we only use the first one; one descriptor can |
b8f7fb13 | 1481 | * describe a broadcast to 256 uv hubs. |
0e2595cd | 1482 | */ |
f073cc8f | 1483 | for (i = 0, bd2 = bau_desc; i < (ADP_SZ * ITEMS_PER_DESC); i++, bd2++) { |
b8f7fb13 | 1484 | memset(bd2, 0, sizeof(struct bau_desc)); |
da87c937 CW |
1485 | if (uv1) { |
1486 | uv1_hdr = &bd2->header.uv1_hdr; | |
1487 | uv1_hdr->swack_flag = 1; | |
1488 | /* | |
1489 | * The base_dest_nasid set in the message header | |
1490 | * is the nasid of the first uvhub in the partition. | |
1491 | * The bit map will indicate destination pnode numbers | |
1492 | * relative to that base. They may not be consecutive | |
1493 | * if nasid striding is being used. | |
1494 | */ | |
1495 | uv1_hdr->base_dest_nasid = | |
1496 | UV_PNODE_TO_NASID(base_pnode); | |
1497 | uv1_hdr->dest_subnodeid = UV_LB_SUBNODEID; | |
1498 | uv1_hdr->command = UV_NET_ENDPOINT_INTD; | |
1499 | uv1_hdr->int_both = 1; | |
1500 | /* | |
1501 | * all others need to be set to zero: | |
1502 | * fairness chaining multilevel count replied_to | |
1503 | */ | |
1504 | } else { | |
1505 | uv2_hdr = &bd2->header.uv2_hdr; | |
1506 | uv2_hdr->swack_flag = 1; | |
1507 | uv2_hdr->base_dest_nasid = | |
1508 | UV_PNODE_TO_NASID(base_pnode); | |
1509 | uv2_hdr->dest_subnodeid = UV_LB_SUBNODEID; | |
1510 | uv2_hdr->command = UV_NET_ENDPOINT_INTD; | |
1511 | } | |
b194b120 | 1512 | } |
b8f7fb13 CW |
1513 | for_each_present_cpu(cpu) { |
1514 | if (pnode != uv_blade_to_pnode(uv_cpu_to_blade_id(cpu))) | |
1515 | continue; | |
1516 | bcp = &per_cpu(bau_control, cpu); | |
1517 | bcp->descriptor_base = bau_desc; | |
1518 | } | |
b194b120 CW |
1519 | } |
1520 | ||
1521 | /* | |
1522 | * initialize the destination side's receiving buffers | |
b8f7fb13 CW |
1523 | * entered for each uvhub in the partition |
1524 | * - node is first node (kernel memory notion) on the uvhub | |
1525 | * - pnode is the uvhub's physical identifier | |
b194b120 | 1526 | */ |
f073cc8f | 1527 | static void pq_init(int node, int pnode) |
b194b120 | 1528 | { |
b8f7fb13 | 1529 | int cpu; |
f073cc8f | 1530 | size_t plsize; |
b4c286e6 | 1531 | char *cp; |
f073cc8f CW |
1532 | void *vp; |
1533 | unsigned long pn; | |
1534 | unsigned long first; | |
1535 | unsigned long pn_first; | |
1536 | unsigned long last; | |
1537 | struct bau_pq_entry *pqp; | |
b8f7fb13 | 1538 | struct bau_control *bcp; |
1812924b | 1539 | |
f073cc8f CW |
1540 | plsize = (DEST_Q_SIZE + 1) * sizeof(struct bau_pq_entry); |
1541 | vp = kmalloc_node(plsize, GFP_KERNEL, node); | |
1542 | pqp = (struct bau_pq_entry *)vp; | |
dc163a41 | 1543 | BUG_ON(!pqp); |
b4c286e6 | 1544 | |
b194b120 | 1545 | cp = (char *)pqp + 31; |
f073cc8f | 1546 | pqp = (struct bau_pq_entry *)(((unsigned long)cp >> 5) << 5); |
b8f7fb13 CW |
1547 | |
1548 | for_each_present_cpu(cpu) { | |
1549 | if (pnode != uv_cpu_to_pnode(cpu)) | |
1550 | continue; | |
1551 | /* for every cpu on this pnode: */ | |
1552 | bcp = &per_cpu(bau_control, cpu); | |
f073cc8f CW |
1553 | bcp->queue_first = pqp; |
1554 | bcp->bau_msg_head = pqp; | |
1555 | bcp->queue_last = pqp + (DEST_Q_SIZE - 1); | |
b8f7fb13 | 1556 | } |
4ea3c51d | 1557 | /* |
6a469e46 | 1558 | * need the gnode of where the memory was really allocated |
4ea3c51d | 1559 | */ |
6a469e46 | 1560 | pn = uv_gpa_to_gnode(uv_gpa(pqp)); |
f073cc8f CW |
1561 | first = uv_physnodeaddr(pqp); |
1562 | pn_first = ((unsigned long)pn << UV_PAYLOADQ_PNODE_SHIFT) | first; | |
1563 | last = uv_physnodeaddr(pqp + (DEST_Q_SIZE - 1)); | |
1564 | write_mmr_payload_first(pnode, pn_first); | |
1565 | write_mmr_payload_tail(pnode, first); | |
1566 | write_mmr_payload_last(pnode, last); | |
1567 | ||
b8f7fb13 | 1568 | /* in effect, all msg_type's are set to MSG_NOOP */ |
f073cc8f | 1569 | memset(pqp, 0, sizeof(struct bau_pq_entry) * DEST_Q_SIZE); |
b194b120 | 1570 | } |
1812924b | 1571 | |
b194b120 | 1572 | /* |
b8f7fb13 | 1573 | * Initialization of each UV hub's structures |
b194b120 | 1574 | */ |
f073cc8f | 1575 | static void __init init_uvhub(int uvhub, int vector, int base_pnode) |
b194b120 | 1576 | { |
9674f35b | 1577 | int node; |
b194b120 | 1578 | int pnode; |
b194b120 | 1579 | unsigned long apicid; |
b8f7fb13 CW |
1580 | |
1581 | node = uvhub_to_first_node(uvhub); | |
1582 | pnode = uv_blade_to_pnode(uvhub); | |
f073cc8f CW |
1583 | |
1584 | activation_descriptor_init(node, pnode, base_pnode); | |
1585 | ||
1586 | pq_init(node, pnode); | |
b194b120 | 1587 | /* |
77ed23f8 CW |
1588 | * The below initialization can't be in firmware because the |
1589 | * messaging IRQ will be determined by the OS. | |
b194b120 | 1590 | */ |
8191c9f6 | 1591 | apicid = uvhub_to_first_apicid(uvhub) | uv_apicid_hibits; |
f073cc8f | 1592 | write_mmr_data_config(pnode, ((apicid << 32) | vector)); |
b8f7fb13 CW |
1593 | } |
1594 | ||
12a6611f CW |
1595 | /* |
1596 | * We will set BAU_MISC_CONTROL with a timeout period. | |
1597 | * But the BIOS has set UVH_AGING_PRESCALE_SEL and UVH_TRANSACTION_TIMEOUT. | |
f073cc8f | 1598 | * So the destination timeout period has to be calculated from them. |
12a6611f | 1599 | */ |
f073cc8f | 1600 | static int calculate_destination_timeout(void) |
12a6611f CW |
1601 | { |
1602 | unsigned long mmr_image; | |
1603 | int mult1; | |
1604 | int mult2; | |
1605 | int index; | |
1606 | int base; | |
1607 | int ret; | |
1608 | unsigned long ts_ns; | |
1609 | ||
2a919596 | 1610 | if (is_uv1_hub()) { |
f073cc8f | 1611 | mult1 = SOFTACK_TIMEOUT_PERIOD & BAU_MISC_CONTROL_MULT_MASK; |
2a919596 JS |
1612 | mmr_image = uv_read_local_mmr(UVH_AGING_PRESCALE_SEL); |
1613 | index = (mmr_image >> BAU_URGENCY_7_SHIFT) & BAU_URGENCY_7_MASK; | |
1614 | mmr_image = uv_read_local_mmr(UVH_TRANSACTION_TIMEOUT); | |
1615 | mult2 = (mmr_image >> BAU_TRANS_SHIFT) & BAU_TRANS_MASK; | |
1616 | base = timeout_base_ns[index]; | |
1617 | ts_ns = base * mult1 * mult2; | |
1618 | ret = ts_ns / 1000; | |
1619 | } else { | |
d059f9fa CW |
1620 | /* 4 bits 0/1 for 10/80us base, 3 bits of multiplier */ |
1621 | mmr_image = uv_read_local_mmr(UVH_LB_BAU_MISC_CONTROL); | |
2a919596 | 1622 | mmr_image = (mmr_image & UV_SA_MASK) >> UV_SA_SHFT; |
f073cc8f | 1623 | if (mmr_image & (1L << UV2_ACK_UNITS_SHFT)) |
d059f9fa | 1624 | base = 80; |
2a919596 | 1625 | else |
d059f9fa CW |
1626 | base = 10; |
1627 | mult1 = mmr_image & UV2_ACK_MASK; | |
2a919596 JS |
1628 | ret = mult1 * base; |
1629 | } | |
12a6611f CW |
1630 | return ret; |
1631 | } | |
1632 | ||
f073cc8f CW |
1633 | static void __init init_per_cpu_tunables(void) |
1634 | { | |
1635 | int cpu; | |
1636 | struct bau_control *bcp; | |
1637 | ||
1638 | for_each_present_cpu(cpu) { | |
1639 | bcp = &per_cpu(bau_control, cpu); | |
1640 | bcp->baudisabled = 0; | |
1641 | bcp->statp = &per_cpu(ptcstats, cpu); | |
1642 | /* time interval to catch a hardware stay-busy bug */ | |
1643 | bcp->timeout_interval = usec_2_cycles(2*timeout_us); | |
1644 | bcp->max_concurr = max_concurr; | |
1645 | bcp->max_concurr_const = max_concurr; | |
1646 | bcp->plugged_delay = plugged_delay; | |
1647 | bcp->plugsb4reset = plugsb4reset; | |
1648 | bcp->timeoutsb4reset = timeoutsb4reset; | |
1649 | bcp->ipi_reset_limit = ipi_reset_limit; | |
1650 | bcp->complete_threshold = complete_threshold; | |
1651 | bcp->cong_response_us = congested_respns_us; | |
1652 | bcp->cong_reps = congested_reps; | |
1653 | bcp->cong_period = congested_period; | |
1654 | } | |
1655 | } | |
1656 | ||
b8f7fb13 | 1657 | /* |
f073cc8f | 1658 | * Scan all cpus to collect blade and socket summaries. |
b8f7fb13 | 1659 | */ |
f073cc8f CW |
1660 | static int __init get_cpu_topology(int base_pnode, |
1661 | struct uvhub_desc *uvhub_descs, | |
1662 | unsigned char *uvhub_mask) | |
b8f7fb13 | 1663 | { |
b8f7fb13 CW |
1664 | int cpu; |
1665 | int pnode; | |
1666 | int uvhub; | |
f073cc8f | 1667 | int socket; |
b8f7fb13 CW |
1668 | struct bau_control *bcp; |
1669 | struct uvhub_desc *bdp; | |
1670 | struct socket_desc *sdp; | |
b8f7fb13 | 1671 | |
b8f7fb13 CW |
1672 | for_each_present_cpu(cpu) { |
1673 | bcp = &per_cpu(bau_control, cpu); | |
f073cc8f | 1674 | |
b8f7fb13 | 1675 | memset(bcp, 0, sizeof(struct bau_control)); |
f073cc8f | 1676 | |
b8f7fb13 | 1677 | pnode = uv_cpu_hub_info(cpu)->pnode; |
f073cc8f | 1678 | if ((pnode - base_pnode) >= UV_DISTRIBUTION_SIZE) { |
77ed23f8 CW |
1679 | printk(KERN_EMERG |
1680 | "cpu %d pnode %d-%d beyond %d; BAU disabled\n", | |
f073cc8f | 1681 | cpu, pnode, base_pnode, UV_DISTRIBUTION_SIZE); |
77ed23f8 CW |
1682 | return 1; |
1683 | } | |
f073cc8f | 1684 | |
77ed23f8 | 1685 | bcp->osnode = cpu_to_node(cpu); |
f073cc8f CW |
1686 | bcp->partition_base_pnode = base_pnode; |
1687 | ||
b8f7fb13 | 1688 | uvhub = uv_cpu_hub_info(cpu)->numa_blade_id; |
c4026cfd | 1689 | *(uvhub_mask + (uvhub/8)) |= (1 << (uvhub%8)); |
b8f7fb13 | 1690 | bdp = &uvhub_descs[uvhub]; |
f073cc8f | 1691 | |
b8f7fb13 CW |
1692 | bdp->num_cpus++; |
1693 | bdp->uvhub = uvhub; | |
1694 | bdp->pnode = pnode; | |
f073cc8f | 1695 | |
a8328ee5 CW |
1696 | /* kludge: 'assuming' one node per socket, and assuming that |
1697 | disabling a socket just leaves a gap in node numbers */ | |
77ed23f8 | 1698 | socket = bcp->osnode & 1; |
a8328ee5 | 1699 | bdp->socket_mask |= (1 << socket); |
b8f7fb13 CW |
1700 | sdp = &bdp->socket[socket]; |
1701 | sdp->cpu_number[sdp->num_cpus] = cpu; | |
1702 | sdp->num_cpus++; | |
cfa60917 | 1703 | if (sdp->num_cpus > MAX_CPUS_PER_SOCKET) { |
f073cc8f CW |
1704 | printk(KERN_EMERG "%d cpus per socket invalid\n", |
1705 | sdp->num_cpus); | |
cfa60917 CW |
1706 | return 1; |
1707 | } | |
b8f7fb13 | 1708 | } |
f073cc8f CW |
1709 | return 0; |
1710 | } | |
1711 | ||
1712 | /* | |
1713 | * Each socket is to get a local array of pnodes/hubs. | |
1714 | */ | |
1715 | static void make_per_cpu_thp(struct bau_control *smaster) | |
1716 | { | |
1717 | int cpu; | |
1718 | size_t hpsz = sizeof(struct hub_and_pnode) * num_possible_cpus(); | |
1719 | ||
1720 | smaster->thp = kmalloc_node(hpsz, GFP_KERNEL, smaster->osnode); | |
1721 | memset(smaster->thp, 0, hpsz); | |
1722 | for_each_present_cpu(cpu) { | |
1723 | smaster->thp[cpu].pnode = uv_cpu_hub_info(cpu)->pnode; | |
1724 | smaster->thp[cpu].uvhub = uv_cpu_hub_info(cpu)->numa_blade_id; | |
1725 | } | |
1726 | } | |
1727 | ||
442d3924 | 1728 | /* |
1729 | * Each uvhub is to get a local cpumask. | |
1730 | */ | |
1731 | static void make_per_hub_cpumask(struct bau_control *hmaster) | |
1732 | { | |
1733 | int sz = sizeof(cpumask_t); | |
1734 | ||
1735 | hmaster->cpumask = kzalloc_node(sz, GFP_KERNEL, hmaster->osnode); | |
1736 | } | |
1737 | ||
f073cc8f CW |
1738 | /* |
1739 | * Initialize all the per_cpu information for the cpu's on a given socket, | |
1740 | * given what has been gathered into the socket_desc struct. | |
1741 | * And reports the chosen hub and socket masters back to the caller. | |
1742 | */ | |
1743 | static int scan_sock(struct socket_desc *sdp, struct uvhub_desc *bdp, | |
1744 | struct bau_control **smasterp, | |
1745 | struct bau_control **hmasterp) | |
1746 | { | |
1747 | int i; | |
1748 | int cpu; | |
1749 | struct bau_control *bcp; | |
1750 | ||
1751 | for (i = 0; i < sdp->num_cpus; i++) { | |
1752 | cpu = sdp->cpu_number[i]; | |
1753 | bcp = &per_cpu(bau_control, cpu); | |
1754 | bcp->cpu = cpu; | |
1755 | if (i == 0) { | |
1756 | *smasterp = bcp; | |
1757 | if (!(*hmasterp)) | |
1758 | *hmasterp = bcp; | |
1759 | } | |
1760 | bcp->cpus_in_uvhub = bdp->num_cpus; | |
1761 | bcp->cpus_in_socket = sdp->num_cpus; | |
1762 | bcp->socket_master = *smasterp; | |
1763 | bcp->uvhub = bdp->uvhub; | |
da87c937 CW |
1764 | if (is_uv1_hub()) |
1765 | bcp->uvhub_version = 1; | |
1766 | else if (is_uv2_hub()) | |
1767 | bcp->uvhub_version = 2; | |
1768 | else { | |
1769 | printk(KERN_EMERG "uvhub version not 1 or 2\n"); | |
1770 | return 1; | |
1771 | } | |
f073cc8f CW |
1772 | bcp->uvhub_master = *hmasterp; |
1773 | bcp->uvhub_cpu = uv_cpu_hub_info(cpu)->blade_processor_id; | |
1774 | if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) { | |
1775 | printk(KERN_EMERG "%d cpus per uvhub invalid\n", | |
1776 | bcp->uvhub_cpu); | |
1777 | return 1; | |
1778 | } | |
1779 | } | |
1780 | return 0; | |
1781 | } | |
1782 | ||
1783 | /* | |
1784 | * Summarize the blade and socket topology into the per_cpu structures. | |
1785 | */ | |
1786 | static int __init summarize_uvhub_sockets(int nuvhubs, | |
1787 | struct uvhub_desc *uvhub_descs, | |
1788 | unsigned char *uvhub_mask) | |
1789 | { | |
1790 | int socket; | |
1791 | int uvhub; | |
1792 | unsigned short socket_mask; | |
1793 | ||
c4026cfd | 1794 | for (uvhub = 0; uvhub < nuvhubs; uvhub++) { |
f073cc8f CW |
1795 | struct uvhub_desc *bdp; |
1796 | struct bau_control *smaster = NULL; | |
1797 | struct bau_control *hmaster = NULL; | |
1798 | ||
c4026cfd CW |
1799 | if (!(*(uvhub_mask + (uvhub/8)) & (1 << (uvhub%8)))) |
1800 | continue; | |
f073cc8f | 1801 | |
b8f7fb13 | 1802 | bdp = &uvhub_descs[uvhub]; |
a8328ee5 CW |
1803 | socket_mask = bdp->socket_mask; |
1804 | socket = 0; | |
1805 | while (socket_mask) { | |
f073cc8f CW |
1806 | struct socket_desc *sdp; |
1807 | if ((socket_mask & 1)) { | |
1808 | sdp = &bdp->socket[socket]; | |
1809 | if (scan_sock(sdp, bdp, &smaster, &hmaster)) | |
cfa60917 | 1810 | return 1; |
9c9153db | 1811 | make_per_cpu_thp(smaster); |
b8f7fb13 CW |
1812 | } |
1813 | socket++; | |
a8328ee5 | 1814 | socket_mask = (socket_mask >> 1); |
b8f7fb13 | 1815 | } |
442d3924 | 1816 | make_per_hub_cpumask(hmaster); |
b8f7fb13 | 1817 | } |
f073cc8f CW |
1818 | return 0; |
1819 | } | |
1820 | ||
1821 | /* | |
1822 | * initialize the bau_control structure for each cpu | |
1823 | */ | |
1824 | static int __init init_per_cpu(int nuvhubs, int base_part_pnode) | |
1825 | { | |
1826 | unsigned char *uvhub_mask; | |
1827 | void *vp; | |
1828 | struct uvhub_desc *uvhub_descs; | |
1829 | ||
1830 | timeout_us = calculate_destination_timeout(); | |
1831 | ||
1832 | vp = kmalloc(nuvhubs * sizeof(struct uvhub_desc), GFP_KERNEL); | |
1833 | uvhub_descs = (struct uvhub_desc *)vp; | |
1834 | memset(uvhub_descs, 0, nuvhubs * sizeof(struct uvhub_desc)); | |
1835 | uvhub_mask = kzalloc((nuvhubs+7)/8, GFP_KERNEL); | |
1836 | ||
1837 | if (get_cpu_topology(base_part_pnode, uvhub_descs, uvhub_mask)) | |
bbd270e6 | 1838 | goto fail; |
f073cc8f CW |
1839 | |
1840 | if (summarize_uvhub_sockets(nuvhubs, uvhub_descs, uvhub_mask)) | |
bbd270e6 | 1841 | goto fail; |
f073cc8f | 1842 | |
b8f7fb13 | 1843 | kfree(uvhub_descs); |
c4026cfd | 1844 | kfree(uvhub_mask); |
f073cc8f | 1845 | init_per_cpu_tunables(); |
cfa60917 | 1846 | return 0; |
bbd270e6 | 1847 | |
1848 | fail: | |
1849 | kfree(uvhub_descs); | |
1850 | kfree(uvhub_mask); | |
1851 | return 1; | |
b194b120 CW |
1852 | } |
1853 | ||
1854 | /* | |
1855 | * Initialization of BAU-related structures | |
1856 | */ | |
1857 | static int __init uv_bau_init(void) | |
1858 | { | |
b8f7fb13 CW |
1859 | int uvhub; |
1860 | int pnode; | |
1861 | int nuvhubs; | |
2c74d666 | 1862 | int cur_cpu; |
f073cc8f | 1863 | int cpus; |
b8f7fb13 | 1864 | int vector; |
f073cc8f | 1865 | cpumask_var_t *mask; |
b194b120 CW |
1866 | |
1867 | if (!is_uv_system()) | |
1868 | return 0; | |
1812924b | 1869 | |
b8f7fb13 CW |
1870 | if (nobau) |
1871 | return 0; | |
1872 | ||
f073cc8f CW |
1873 | for_each_possible_cpu(cur_cpu) { |
1874 | mask = &per_cpu(uv_flush_tlb_mask, cur_cpu); | |
1875 | zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cur_cpu)); | |
1876 | } | |
76ba0ecd | 1877 | |
b8f7fb13 | 1878 | nuvhubs = uv_num_possible_blades(); |
50fb55ac | 1879 | spin_lock_init(&disable_lock); |
f073cc8f | 1880 | congested_cycles = usec_2_cycles(congested_respns_us); |
9674f35b | 1881 | |
f073cc8f | 1882 | uv_base_pnode = 0x7fffffff; |
77ed23f8 | 1883 | for (uvhub = 0; uvhub < nuvhubs; uvhub++) { |
f073cc8f CW |
1884 | cpus = uv_blade_nr_possible_cpus(uvhub); |
1885 | if (cpus && (uv_blade_to_pnode(uvhub) < uv_base_pnode)) | |
1886 | uv_base_pnode = uv_blade_to_pnode(uvhub); | |
77ed23f8 CW |
1887 | } |
1888 | ||
d059f9fa CW |
1889 | enable_timeouts(); |
1890 | ||
f073cc8f | 1891 | if (init_per_cpu(nuvhubs, uv_base_pnode)) { |
77ed23f8 CW |
1892 | nobau = 1; |
1893 | return 0; | |
1894 | } | |
b8f7fb13 CW |
1895 | |
1896 | vector = UV_BAU_MESSAGE; | |
1897 | for_each_possible_blade(uvhub) | |
1898 | if (uv_blade_nr_possible_cpus(uvhub)) | |
f073cc8f | 1899 | init_uvhub(uvhub, vector, uv_base_pnode); |
b8f7fb13 | 1900 | |
b8f7fb13 CW |
1901 | alloc_intr_gate(vector, uv_bau_message_intr1); |
1902 | ||
1903 | for_each_possible_blade(uvhub) { | |
93a7ca0c | 1904 | if (uv_blade_nr_possible_cpus(uvhub)) { |
f073cc8f CW |
1905 | unsigned long val; |
1906 | unsigned long mmr; | |
93a7ca0c CW |
1907 | pnode = uv_blade_to_pnode(uvhub); |
1908 | /* INIT the bau */ | |
f073cc8f CW |
1909 | val = 1L << 63; |
1910 | write_gmmr_activation(pnode, val); | |
93a7ca0c | 1911 | mmr = 1; /* should be 1 to broadcast to both sockets */ |
da87c937 CW |
1912 | if (!is_uv1_hub()) |
1913 | write_mmr_data_broadcast(pnode, mmr); | |
93a7ca0c | 1914 | } |
b8f7fb13 | 1915 | } |
b4c286e6 | 1916 | |
1812924b CW |
1917 | return 0; |
1918 | } | |
b8f7fb13 | 1919 | core_initcall(uv_bau_init); |
e8e5e8a8 | 1920 | fs_initcall(uv_ptc_init); |